CN108509367A - A kind of bus structures and its wiring method - Google Patents
A kind of bus structures and its wiring method Download PDFInfo
- Publication number
- CN108509367A CN108509367A CN201810276473.2A CN201810276473A CN108509367A CN 108509367 A CN108509367 A CN 108509367A CN 201810276473 A CN201810276473 A CN 201810276473A CN 108509367 A CN108509367 A CN 108509367A
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- China
- Prior art keywords
- differential pair
- spacing
- adjacent
- cabling
- differential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The invention discloses a kind of bus structures, including：At least two differential pairs, each differential pair is made of two adjacent data lines, and has the first spacing between adjacent differential pair；It is equipped with ground cabling in region corresponding to first spacing, and is arranged at intervals with multiple vias on described ground cabling.The invention also discloses a kind of wiring methods, including：Between adjacent differential pair cabling is configured in folded region；Multiple vias are arranged in interval on described ground cabling；Wherein, each differential pair is made of two adjacent data lines, and has the first spacing between adjacent differential pair, and folded region is the region corresponding to first spacing between the adjacent differential pair.By applying the present invention, the crosstalk between bus differential pair and electromagnetic interference can be effectively reduced.
Description
Technical field
The present invention relates to the anti-interference wiring technique field of data transmission bus more particularly to a kind of bus structures and its cloth
Line method.
Background technology
In nonvolatile memory (NVME, Non-Volatile Memory Express) solid state disk (SSD, Solid
State Disk) in, Peripheral Component Interconnect of new generation (PCI-E, Peripheral Component Interconnect-
Express) bus is the highest cabling of speed, and the transmission speed of PCIE 3.0 is 8GT/S, the transmission of the following PCIE 4.0 at present
Speed can reach 16GT/S.And PCI-E buses are also most to be vulnerable to electromagnetic interference and most easily produce the cabling of interference, therefore,
PCI-E difference connects up the performance for directly affecting PCI-E interface and SSD systems.The solution of the prior art is, mainly by increase
Spacing between differential pair (diff pair) reduces the mutual crosstalk of differential pair, as shown in Figure 1, showing difference in Fig. 1
Dividing to 1 and differential pair 2, each differential pair is made of two adjacent data lines, then, the prior art is by increasing differential pair
Spacing h between 1 and differential pair 2 reduces the crosstalk between differential pair 1 and differential pair 2.However, this by increasing spacing
Mode effect is simultaneously bad, and can not also reduce electromagnetic interference (EMI, Electromagnetic of the PCI-E cablings to system
Interference)。
Invention content
In view of this, a kind of bus structures of proposition of the embodiment of the present invention and its wiring method, at least to solve the prior art
Present in the above technical problem.
According to the first aspect of the invention, a kind of bus structures are provided, including：
At least two differential pairs, each differential pair are made of two adjacent data lines, and adjacent differential pair it
Between have the first spacing；
It is equipped with ground cabling in region corresponding to first spacing, and is arranged at intervals with multiple mistakes on described ground cabling
Hole.
According to one embodiment of the present invention, when at least side of the differential pair positioned at edge does not have other adjacent difference
Clock synchronization is equipped with described ground cabling in the side of other not adjacent differential pairs of the differential pair positioned at edge, and described
Ground cabling and it is described between the differential pair at edge have the second spacing.
According to one embodiment of the present invention, first spacing is more than first threshold, and second spacing is more than second
Threshold value.
According to one embodiment of the present invention, it is smaller than third threshold value between the adjacent via.
According to one embodiment of the present invention, the bus is the Peripheral Component Interconnect PCI-E buses of a new generation.
According to the second aspect of the invention, a kind of wiring method is provided, including：
Between adjacent differential pair cabling is configured in folded region；
Multiple vias are arranged in interval on described ground cabling；
Wherein, each differential pair is made of two adjacent data lines, and has first between adjacent differential pair
Spacing, folded region is the region corresponding to first spacing between the adjacent differential pair.
According to one embodiment of the present invention, the method further includes：When at least side of the differential pair positioned at edge does not have
When there are other adjacent differential pairs, institute is equipped in the side of other not adjacent differential pairs of the differential pair positioned at edge
State ground cabling, and described ground cabling and it is described between the differential pair at edge with the second spacing.
According to one embodiment of the present invention, first spacing is more than first threshold, and second spacing is more than second
Threshold value.
According to one embodiment of the present invention, it is smaller than third threshold value between the adjacent via.
According to one embodiment of the present invention, the bus is the Peripheral Component Interconnect PCI-E buses of a new generation.
The embodiment of the present invention is spaced on ground cabling and sets by being configured cabling between adjacent bus differential pair
Set multiple vias；The both sides of differential pair using two-row spacing uniform ground via formed approximate medium integrated waveguide (SIW,
Substrate Integrated Waveguide) the electric boundary of side can as increased by one of wall between two differential pairs
To effectively reduce between difference cabling crosstalk and difference cabling to the EMI of system.Also, ground cabling in the range of space allows
Spacing between via is smaller, and the anti-jamming effectiveness of the embodiment of the present invention is better.
It is to be appreciated that the teachings of the present invention does not need to realize whole advantageous effects recited above, but it is specific
Technical solution may be implemented specific technique effect, and the other embodiment of the present invention can also be realized and not mentioned above
Advantageous effect.
Description of the drawings
Detailed description below, above-mentioned and other mesh of exemplary embodiment of the invention are read by reference to attached drawing
, feature and advantage will become prone to understand.In the accompanying drawings, if showing the present invention's by way of example rather than limitation
Dry embodiment, wherein：
In the accompanying drawings, identical or corresponding label indicates identical or corresponding part.
Fig. 1 shows a kind of schematic diagram of PCI-E differential pairs cabling in the prior art；
Fig. 2 is according to a kind of bus structures schematic diagram of one aspect of the invention；
Fig. 3 shows a kind of flow diagram of wiring method according to one embodiment of the present invention.
Specific implementation mode
The principle and spirit of the invention are described below with reference to several illustrative embodiments.It should be appreciated that providing this
A little embodiments are used for the purpose of making those skilled in the art can better understand that realizing the present invention in turn, and be not with any
Mode limits the scope of the invention.On the contrary, these embodiments are provided so that the present invention is more thorough and complete, and energy
It enough will fully convey the scope of the invention to those skilled in the art.
The technical solution of the present invention is further elaborated in the following with reference to the drawings and specific embodiments.
A kind of bus structures that the embodiment of the present invention is provided, as shown in Fig. 2, including mainly：At least two differential pairs, often
A differential pair is made of two adjacent data lines, and has the first spacing between adjacent differential pair；In the first spacing, institute is right
It is equipped with ground cabling in the region answered, and is arranged at intervals with multiple vias on ground cabling.
By taking differential pair 1 shown in Fig. 2 and differential pair 2 as an example, differential pair 1 and differential pair 2 are respectively by two adjacent numbers
It is formed according to line, this two adjacent data lines can be isometric, equidistant, and differential pair is all represented per the straight line of band shade in Fig. 2
In a data line, the effect of differential pair is for carrying out differential signal transmission.Adjacent differential pair 1 and differential pair 2 it
Between there is the first spacing h, usually in the case where space allows, the value of h can select as possible greatly, adjacent because the value of h is bigger
Crosstalk between differential pair will be smaller.So, in the actual implementation process can rule of thumb or statistical result set one
First threshold, and the first spacing h can select the value more than the first threshold, to ensure the crosstalk between adjacent differential pair compared with
It is small.
Region corresponding to first spacing h is region folded between adjacent differential pair 1 and differential pair 2, the present invention
It is equipped with ground cabling in embodiment region folded between differential pair 1 and differential pair 2, and is arranged at intervals with multiple mistakes on ground cabling
Hole.As shown in Fig. 2, be equipped with ground cabling gnd2 in region folded between differential pair 1 and differential pair 2, in addition, in differential pair 1 and
Ground cabling gnd1 is equipped between the adjacent differential pair (not shown) in its left side in folded region, it is right with it in differential pair 2
Ground cabling gnd3 is equipped between the adjacent differential pair (not shown) in side in folded region；Also, in gnd1, gnd2 and
What is be respectively separated on gnd3 is provided with multiple vias, and the spacing between adjacent via is D.By taking differential pair 2 as an example, with left side
Gnd2 between spacing be denoted as s1, the spacing between the gnd3 on right side is denoted as s2.
In a specific embodiment, when at least side of the differential pair positioned at edge does not have other adjacent differential pairs
When, it is equipped with described ground cabling in the side of other not adjacent differential pairs of the differential pair positioned at edge, and described
Cabling and it is described between the differential pair at edge have the second spacing.It is assumed that the differential pair 1 in Fig. 2 is in leftmost side side
The differential pair of edge, there is no differential pairs adjacent thereto to the left, then can also be equipped with ground cabling in the left side of differential pair 1
Gnd1, and there are second distance s 3 between gnd1 and differential pair 1.
It should be noted that in specific implementation process, the value of s1, s2 and s3 can be all identical, can also be according to reality
Border needs setting is different from or part is identical.The value of s1, s2 and s3 can as possible take partially in the range of space allows
Big value, because the value of s1, s2 and s3 are too small to influence line impedence, or in computing impedance, needs gnd cabling shadows
Sound is taken into account.In the actual implementation process can rule of thumb or statistical result set a second threshold, and differential pair with
Its adjacent spacing walked between ground wire can select the value more than the second threshold, to ensure to cabling impedance influences compared with
It is small.
In addition, the spacing walked between the via on ground wire can select all equidistantly, can also select not equidistantly, this can
With flexibly selection according to actual needs.But the spacing between adjacent via is small as possible, such that the embodiment of the present invention
The effect for reducing the crosstalk and electromagnetic interference between differential pair is more preferable.
Specifically, the bus described in the embodiment of the present invention can be PCI-E buses, certainly, the embodiment of the present invention and not only
It is limited to be useful in PCI-E buses, other are any there are the data transmission bus of crosstalk and electromagnetic interference, are also suitable for the present invention
The bus structures and wire laying mode of embodiment.
In conjunction with Fig. 2, and as shown in figure 3, the embodiment of the present invention additionally provides a kind of wiring method, this method includes mainly：
Step 301, it is configured cabling in region folded between adjacent differential pair；
Step 302, multiple vias are arranged in interval on described ground cabling.
Wherein, each differential pair is made of two adjacent data lines, and has first between adjacent differential pair
Spacing, folded region is the region corresponding to first spacing between the adjacent differential pair.
By taking differential pair 1 shown in Fig. 2 and differential pair 2 as an example, differential pair 1 and differential pair 2 are respectively by two adjacent numbers
It is formed according to line, this two adjacent data lines can be isometric, equidistant, and differential pair is all represented per the straight line of band shade in Fig. 2
In a data line, the effect of differential pair is for carrying out differential signal transmission.Adjacent differential pair 1 and differential pair 2 it
Between there is the first spacing h, usually in the case where space allows, the value of h can select as possible greatly, adjacent because the value of h is bigger
Crosstalk between differential pair will be smaller.So, in the actual implementation process can rule of thumb or statistical result set one
First threshold, and the first spacing h can select the value more than the first threshold, to ensure the crosstalk between adjacent differential pair compared with
It is small.
Region corresponding to first spacing h is region folded between adjacent differential pair 1 and differential pair 2, the present invention
It is equipped with ground cabling in embodiment region folded between differential pair 1 and differential pair 2, and is arranged at intervals with multiple mistakes on ground cabling
Hole.As shown in Fig. 2, be equipped with ground cabling gnd2 in region folded between differential pair 1 and differential pair 2, in addition, in differential pair 1 and
Ground cabling gnd1 is equipped between the adjacent differential pair (not shown) in its left side in folded region, it is right with it in differential pair 2
Ground cabling gnd3 is equipped between the adjacent differential pair (not shown) in side in folded region；Also, in gnd1, gnd2 and
What is be respectively separated on gnd3 is provided with multiple vias, and the spacing between adjacent via is D.By taking differential pair 2 as an example, with left side
Gnd2 between spacing be denoted as s1, the spacing between the gnd3 on right side is denoted as s2.
In a specific embodiment, when at least side of the differential pair positioned at edge does not have other adjacent differential pairs
When, it is equipped with described ground cabling in the side of other not adjacent differential pairs of the differential pair positioned at edge, and described
Cabling and it is described between the differential pair at edge have the second spacing.It is assumed that the differential pair 1 in Fig. 2 is in leftmost side side
The differential pair of edge, there is no differential pairs adjacent thereto to the left, then can also be equipped with ground cabling in the left side of differential pair 1
Gnd1, and there are second distance s 3 between gnd1 and differential pair 1.
It should be noted that in specific implementation process, the value of s1, s2 and s3 can be all identical, can also be according to reality
Border needs setting is different from or part is identical.The value of s1, s2 and s3 can as possible take partially in the range of space allows
Big value, because the value of s1, s2 and s3 are too small to influence line impedence, or in computing impedance, needs gnd cabling shadows
Sound is taken into account.In the actual implementation process can rule of thumb or statistical result set a second threshold, and differential pair with
Its adjacent spacing walked between ground wire can select the value more than the second threshold, to ensure to cabling impedance influences compared with
It is small.
In addition, the spacing walked between the via on ground wire can select all equidistantly, can also select not equidistantly, this can
With flexibly selection according to actual needs.But the spacing between adjacent via is small as possible, such that the embodiment of the present invention
The effect for reducing the crosstalk and electromagnetic interference between differential pair is more preferable.
Specifically, the bus described in the embodiment of the present invention can be PCI-E buses, certainly, the embodiment of the present invention and not only
It is limited to be useful in PCI-E buses, other are any there are the data transmission bus of crosstalk and electromagnetic interference, are also suitable for the present invention
The bus structures and wire laying mode of embodiment.
The embodiment of the present invention is spaced on ground cabling and sets by being configured cabling between adjacent bus differential pair
Set multiple vias；The electricity of approximate medium integrated waveguide side is formed using two-row spacing uniform ground via in the both sides of differential pair
Boundary can effectively reduce crosstalk and difference cabling pair between difference cabling as increased by one of wall between two differential pairs
The EMI of system.Also, in the range of space allows spacing between cabling via it is smaller, the embodiment of the present invention it is anti-dry
It is better to disturb effect.
It need to be noted that be：The description of above example is similar with the description of above method embodiment, has
The similar advantageous effect with embodiment of the method, therefore do not repeat.For undisclosed technical detail in the embodiment of the present invention, ask
Understand with reference to the description of the method for the present invention embodiment, to save length, therefore repeats no more.
It should be noted that herein, the terms "include", "comprise" or its any other variant are intended to non-row
His property includes, so that process, method, article or device including a series of elements include not only those elements, and
And further include other elements that are not explicitly listed, or further include for this process, method, article or device institute it is intrinsic
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including this
There is also other identical elements in the process of element, method, article or device.
In several embodiments provided herein, it should be understood that disclosed device and method can pass through it
Its mode is realized.Apparatus embodiments described above are merely indicative, for example, the division of the unit, only
A kind of division of logic function, formula that in actual implementation, there may be another division manner, such as：Multiple units or component can combine, or
It is desirably integrated into another system, or some features can be ignored or not executed.In addition, shown or discussed each composition portion
It can be the INDIRECT COUPLING by some interfaces, equipment or unit to divide mutual coupling or direct-coupling or communication connection
Or communication connection, can be electrical, mechanical or other forms.
The above-mentioned unit illustrated as separating component can be or may not be and be physically separated, aobvious as unit
The component shown can be or may not be physical unit；Both it can be located at a place, may be distributed over multiple network lists
In member；Some or all of wherein unit can be selected according to the actual needs to achieve the purpose of the solution of this embodiment.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of bus structures, which is characterized in that including：
At least two differential pairs, each differential pair is made of two adjacent data lines, and is had between adjacent differential pair
There is the first spacing；
It is equipped with ground cabling in region corresponding to first spacing, and is arranged at intervals with multiple vias on described ground cabling.
2. bus structures according to claim 1, which is characterized in that when at least side of the differential pair positioned at edge does not have
When other adjacent differential pairs, it is equipped in the side of other not adjacent differential pairs of the differential pair positioned at edge described
Ground cabling, and described ground cabling and it is described between the differential pair at edge have the second spacing.
3. bus structures according to claim 2, which is characterized in that first spacing is more than first threshold, and described the
Two spacing are more than second threshold.
4. bus structures according to claim 1, which is characterized in that be smaller than third between the adjacent via
Threshold value.
5. bus structures according to any one of claims 1 to 4, which is characterized in that the bus is the peripheral hardware of a new generation
Component connection PCI-E buses.
6. a kind of wiring method, which is characterized in that the method includes：
Between adjacent differential pair cabling is configured in folded region；
Multiple vias are arranged in interval on described ground cabling；
Wherein, each differential pair is made of two adjacent data lines, and has the first spacing between adjacent differential pair,
Folded region is the region corresponding to first spacing between the adjacent differential pair.
7. wiring method according to claim 6, which is characterized in that the method further includes：
When at least side of the differential pair positioned at edge does not have other adjacent differential pairs, in the differential pair positioned at edge
The sides of other not adjacent differential pairs be equipped with described ground cabling, and described ground cabling and the differential pair positioned at edge
Between have the second spacing.
8. wiring method according to claim 7, which is characterized in that first spacing is more than first threshold, and described the
Two spacing are more than second threshold.
9. wiring method according to claim 6, which is characterized in that be smaller than third between the adjacent via
Threshold value.
10. according to claim 6 to 9 any one of them wiring method, which is characterized in that the bus is the peripheral hardware of a new generation
Component connection PCI-E buses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810276473.2A CN108509367A (en) | 2018-03-30 | 2018-03-30 | A kind of bus structures and its wiring method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810276473.2A CN108509367A (en) | 2018-03-30 | 2018-03-30 | A kind of bus structures and its wiring method |
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| Publication Number | Publication Date |
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| CN108509367A true CN108509367A (en) | 2018-09-07 |
Family
ID=63379304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810276473.2A Pending CN108509367A (en) | 2018-03-30 | 2018-03-30 | A kind of bus structures and its wiring method |
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| CN206541551U (en) * | 2017-02-24 | 2017-10-03 | 厦门天马微电子有限公司 | Display panel |
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2018
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| US20060067023A1 (en) * | 2004-09-29 | 2006-03-30 | Sony Corporation | Method and system for ESD protection of balanced circuit board lines |
| CN103366023A (en) * | 2012-03-26 | 2013-10-23 | 鸿富锦精密工业（深圳）有限公司 | Differential signal routing line distributing system and differential signal routing line distributing method |
| CN104936373A (en) * | 2014-03-21 | 2015-09-23 | 华为技术有限公司 | Circuit board, distribution method of surface-layer difference lines and communication equipment |
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