CN108490705A - array substrate, liquid crystal display panel and display device - Google Patents
array substrate, liquid crystal display panel and display device Download PDFInfo
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- CN108490705A CN108490705A CN201810328914.9A CN201810328914A CN108490705A CN 108490705 A CN108490705 A CN 108490705A CN 201810328914 A CN201810328914 A CN 201810328914A CN 108490705 A CN108490705 A CN 108490705A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
Abstract
The present invention provides a kind of array substrate, liquid crystal display panel and display device, the array substrate includes multiple sub-pixel groups, each sub-pixel group includes being disposed adjacent its first sub-pixel and the second sub-pixel along row to arrangement, the first area of first sub-pixel is disposed adjacent with the second area of second sub-pixel and along capable to arrangement, the second area of first sub-pixel is disposed adjacent with the first area of second sub-pixel and along capable to arrangement, wherein, the number of strip shaped electric poles is more than the number of strip shaped electric poles in second area in first area, each sub-pixel carries out open region using the excess room of adjacent subpixels and compensates so that more the lower strip shaped electric poles that can be placed in its subregion, improve the space availability ratio of each sub-pixel, to increase the penetrance of liquid crystal display panel and display device as far as possible.
Description
Technical field
The present invention relates to a kind of display technology field more particularly to array substrate, liquid crystal display panel and display devices.
Background technology
Liquid crystal display panel be typically by a color membrane substrates (ColorFilterSubstrate, CF Substrate),
One thin-film transistor array base-plate (ThinFilmTransistorArraySubstrate, TFT ArraySubstrate) and
One liquid crystal layer (LiquidCrystalLayer) being configured between two substrates is constituted, and operation principle is by two sheet glass
Apply driving voltage on substrate to control the rotation of the liquid crystal molecule of liquid crystal layer, the light refraction of backlight module is out generated into picture
Face.According to the aligned difference of liquid crystal, liquid crystal display panel can be divided into following several types：TN (twisted-nematic) pattern,
VA (vertical orientation) pattern, IPS (in-plane changes) pattern, FFS (fringing field switching) pattern etc..
IPS, FFS mode are the mainstream implementation patterns of current liquid crystal display panel at present, IPS patterns, FFS mode LCD
Dot structure it is as follows：It is formed with pixel electrode and public electrode on the same substrate.In the LCD of IPS patterns, public electrode and
Pixel electrode is formed as comb teeth shape, and is formed on same insulating film.FFS mode is to improve the display mode of IPS patterns,
It is opposite across insulating film with public electrode to be wherein formed as pixel electrode.The pixel electrode of the LCD of FFS mode is for example with formation
There is the structure of multiple slits, and utilizes electric field (edge of the edge (fringe) for being formed in pixel electrode between public electrode
Electric field) control liquid crystal molecule orientation, thus compared with the LCD of IPS patterns, the LCD of FFS mode has wide viewing angle and high transmission
These features of rate.In order to promote penetrance, the quantity of strip shaped electric poles can be increased as possible, but with the increase of display resolution,
The area in each pixel openings area is smaller and smaller, it is contemplated that exposure limit, the pixel of a fixed size can only place limited
Strip shaped electric poles quantity, therefore, how to improve penetrance in the pixel openings area of limited areal becomes urgent problem to be solved.
Invention content
A kind of array substrate of present invention offer, liquid crystal panel and display device, can improve array substrate, liquid crystal face
The penetrance of plate and display device improves display effect.
In a first aspect, the present invention provides a kind of array substrate, including：Underlay substrate；Grid line and data line, are successively set on
On the underlay substrate, the grid line is along row to extending and along row to arrangement, and the data line is along arranging to extending and along row to row
Row, the grid line and the data line, which intersect, limits multiple sub-pixels, each sub-pixel include along arrange to arrangement first
Region and second area, the first area along row to width be more than the second area along line direction width；And the
One electrode, including multiple strip shaped electric poles disposed in parallel；The first electrode is located at the partial electrode packet in the first area
M strip shaped electric poles are included, it includes N number of strip shaped electric poles that the first electrode, which is located at the partial electrode in second area, wherein M>N, and
M is the integer more than or equal to 2, and N is the integer more than or equal to 1；The multiple sub-pixel includes multiple sub-pixel groups, per height picture
Element group includes being disposed adjacent its first sub-pixel and the second sub-pixel along row to arrangement, the first area of first sub-pixel
Be disposed adjacent with the second area of second sub-pixel and along row to arrangement, the second area of first sub-pixel with it is described
The first area of second sub-pixel is disposed adjacent and along capable to arrangement；The data line includes the first data line, is located at the first son
Between pixel and the second sub-pixel, first data line correspond to each sub-pixel part include the first branch line, second
Line, and the connecting line between first branch line and second branch line, first branch line are parallel to described second
Branch line, straight line where the connecting line relative to row to gradient be more than first branch line where straight line relative to row to
Gradient.
Second aspect, a kind of liquid crystal display panel provided by the invention, including the color membrane substrates and array base that are correspondingly arranged
Plate, the array substrate use above-mentioned array substrate.
The third aspect, a kind of display device provided by the invention, including above-mentioned liquid crystal display panel.
Array substrate, liquid crystal display panel and display device provided in an embodiment of the present invention, including multiple sub-pixels, each
Sub-pixel includes that edge is arranged to the first area of arrangement and second area, and the first electrode is located at the part in the first area
Electrode includes M strip shaped electric poles, and it includes N number of strip shaped electric poles that the first electrode, which is located at the partial electrode in second area, wherein
M>N, and M is the integer more than or equal to 2, N is the integer more than or equal to 1；The multiple sub-pixel includes multiple sub-pixel groups, often
A sub- pixel groups include being disposed adjacent its first sub-pixel and the second sub-pixel along row to arrangement, and the of first sub-pixel
One region is disposed adjacent with the second area of second sub-pixel and along capable to arrangement, the second area of first sub-pixel
It is disposed adjacent with the first area of second sub-pixel and along row to arrangement, each sub-pixel can be made to utilize adjacent sub- picture
The excess room of element makes more the lower strip shaped electric poles that can be placed in its subregion, improves the space profit of each sub-pixel
With rate, display panel penetrance can be increased as far as possible.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to do one simply to introduce, it should be apparent that, the accompanying drawings in the following description is this hair
Some bright embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is a kind of structural schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 2 is the dot structure schematic diagram in array substrate shown in Fig. 1；
Fig. 3 is the sectional view in the directions A1-A2 along Fig. 2；
Fig. 4 is the dot structure schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 5 is the dot structure schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 6 is the sectional view in the directions B1-B2 along Fig. 5；
Fig. 7 is the dot structure schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 8 is the dot structure schematic diagram of another array substrate provided in an embodiment of the present invention.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, hereinafter with reference to the attached drawing of the embodiment of the present invention,
Technical scheme of the present invention is clearly and completely described by embodiment, it is clear that described embodiment is a part of the invention
Embodiment, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making wound
The every other embodiment obtained under the premise of the property made labour, shall fall within the protection scope of the present invention.
The present invention relates to a kind of array substrate and the liquid crystal display panel being made of the array substrate, display devices, including
Underlay substrate and the thin film transistor (TFT) formed on underlay substrate, public electrode, pixel electrode, grid line and data line etc., wherein
Switch element of the thin film transistor (TFT) as display panel sub-pixel.The grid line of the grid connection array substrate of thin film transistor (TFT),
It is connected to gate driving circuit via grid line, the source electrode of thin film transistor (TFT) connects data line, and being connected to data via data line drives
Dynamic circuit, the drain electrode of thin film transistor (TFT) are connected to pixel electrode, pass through data line on-load voltage to pixel electrode so that pixel electricity
Horizontal component of electric field is formed between pole and public electrode, and then the image of realization liquid crystal display panel, display device is shown.
With reference to shown in figure 1,2,3, Fig. 1 is a kind of structural schematic diagram of array substrate provided in an embodiment of the present invention, and Fig. 2 is
Dot structure schematic diagram in array substrate shown in Fig. 1, Fig. 3 are the sectional view in the directions A1-A2 along Fig. 2.The present invention is real first
It applies example and a kind of array substrate 10 is provided, including underlay substrate 101 and the first electrode 14, a plurality of that is formed on underlay substrate 101
Data line 11 and a plurality of grid line 12, multiple data lines 11 are along row to extending and along capable to arrangement, and a plurality of grid line 12 is along capable to extension
And it is formed to arrangement, multiple data lines 11 and the multiple sub-pixel P being arranged in array of definition arranged in a crossed manner of a plurality of grid line 12 along row
Pel array, in above-mentioned pel array, each sub-pixel P includes at least a switch element 13.
Each switch element 13 for example can be thin film transistor (TFT), including grid, with the semiconductor channel of gate overlap, set
Set gate insulation layer between grid and semiconductor channel and the source electrode being electrically connected respectively with semiconductor channel both sides and leakage
Pole.The grid of switch element 13 in the sub-pixel P of same a line is connected to same grid line 12, is located at the sub- picture of same row
The source electrode of switch element 13 in plain P is connected to a data line 11.In the present embodiment, first electrode 14 is pixel electricity
Pole, there are one first electrode 14, each first electrode 14 is electrically connected the interior settings of each sub-pixel P with the drain electrode of switch element T.
In the present embodiment, the grid of switch element 13 is optionally formed by same film layer with grid line 12；Switch element 13
Source electrode, drain electrode and data line 11 are optionally formed by same film layer.However, the present invention is not limited thereto, at other
In embodiment, the film layer relationship between film layer relationship and/or source-drain electrode and data line between grid and grid line is visually actual
It is appropriately designed that demand does other.The material of first electrode for example can be indium tin oxide, indium-zinc oxide, aluminium tin-oxide,
The transparent conductive materials such as aluminium zinc oxide, indium germanium zinc oxide.
Wherein, each sub-pixel P includes first area PH1 and second area PH2, first area PH1 and second area PH2
Be interconnected and form the open region of each sub-pixel P, wherein first area PH1 along row to width be more than the edges second area PH2
The width of line direction.
Multiple sub-pixel P being arranged in array include the first sub-pixel P1 and the second sub-pixel P2, first sub-pixel
P1 and setting adjacent thereto simultaneously forms a sub- pixel groups, multiple sub-pixel group weights along row to the second sub-pixel P2 of arrangement
Multiple arrangement form pel array.Wherein, the second area PH2 of the first area PH1 of the first sub-pixel P1 and the second sub-pixel P2
It is disposed adjacent and along row to arrangement, the second area PH2 of the first sub-pixel P1 is adjacent with the first area PH1 of the second sub-pixel P2
It is arranged and along capable to arrangement.
Specifically, in each sub-pixel group, data line 11 includes the first data line 111 and the second data line 112, first
For data line 111 between the first sub-pixel P1 and the second sub-pixel P2, the second data line 112 is located at the two of each sub-pixel group
Side, i.e., each sub-pixel group include first data line 111 and two the second data lines 112, and two the second data lines 112 divide
Not Wei Yu above-mentioned first sub-pixel P1 far from the second sides sub-pixel P2 and the second sub-pixel P2 far from the first sub-pixel P1's
Side.First data line 111 includes the first branch line 111a, the second branch line 111b, and is located at the first branch line 111a and second
Connecting line 111c between line 111b, wherein the first branch line 111a is located at of first area PH1 and second of the first sub-pixel P1
Between the second area PH2 of pixel P2, the second branch line 111b is located at the second area PH2 and the second sub-pixel of the first sub-pixel P1
Between the first area PH1 of P2, the first branch line 111a is arranged in parallel with the second branch line 111b, the straight line where connecting line 111c with
Angle theta 1 of the row between is less than the angle theta 2 of straight line and row where the first branch line 111a between, in other words connecting line 111c
Relative to row to gradient be more than the first branch line 111a, the second branch line 111b relative to row to gradient, it might even be possible to be：
First branch line 111a and the second branch line 111b is along arranging to extension, and only connecting line 111c is relative to row to certain inclination
Degree.In this way, compared with the prior art, it can be by being compensated close to the outs open area of the first branch line 111a in the second sub-pixel P2
It is mended to the first sub-pixel P1 adjacent thereto, while by the outs open area of the close second branch line 111b in the first sub-pixel P1
Repay the first area PH1 that the first sub-pixel P1 is formed to the second sub-pixel P2 adjacent thereto and second area PH2, the second son
The first area PH1 and second area PH2 of pixel P2.
In each sub-pixel P, first electrode 14 includes multiple strip shaped electric poles disposed in parallel, which for example may be used
To be formed by the slit that closure is arranged in first electrode 14, the end of multiple strip shaped electric poles is connected, and is connected to same
The first branch line 111a, the second branch line 111b of the drain electrode of a corresponding switch element 13, the strip shaped electric poles and the first data line 111
Be arranged in parallel, and the first branch line 111a of the first data line 111, the second branch line 111b be mutually parallel and with the second data line 112
It is arranged in parallel.As shown in Fig. 2, in an embodiment of the present invention, first electrode 14 is enabled to be located at the partial electrode in the PH1 of first area
Including M strip shaped electric poles, it includes N number of strip shaped electric poles that first electrode 14, which is located at the partial electrode in second area PH2, wherein M>
N, and M is the integer more than or equal to 2, N is the integer more than or equal to 1.For example, in the present embodiment, in each sub-pixel P,
Each first electrode 14 includes two the first strip shaped electric poles 141 and second strip shaped electric poles 142, wherein two the first strips
Electrode 141 extends to the separate first area of second area PH2 from one end of the separate second area PH2 of first area PH1
One end of PH1；Second strip shaped electric poles 142 include main electrode 14a and connection electrode 142b, and main electrode 14a passes through connection electrode
142b is connected on the first strip shaped electric poles 141 adjacent thereto, specifically, being connected to close the first of the first strip shaped electric poles 141
The boundary of region PH1 and second area PH2 so that there are three strip shaped electric poles for tool in the first area PH1 of each sub-pixel P
(being respectively two the first strip shaped electric poles 141 and second strip shaped electric poles 142), and in the second area PH2 of each sub-pixel P
Interior only two the first strip shaped electric poles 141.Certainly, only there are three strip shaped electric poles as showing for setting using in each sub-pixel by Fig. 2
Example carries out exemplary introduction to the realization method of the embodiment of the present invention, and the present invention is not limited thereto, the electricity in each sub-pixel
As long as pole item number meets following setting：It includes M strip to enable the partial electrode that first electrode 14 is located in the PH1 of first area
Electrode, it includes N number of strip shaped electric poles that first electrode 14, which is located at the partial electrode in second area PH2, wherein M>N, and M be more than
Integer equal to 2, N are the integer more than or equal to 1.
With the raising that people require display device clarity, PPI (the pixels per of liquid crystal display panel
Inch, the number of pixels that per inch is possessed) it is higher and higher, cause the area of the open region of each sub-pixel smaller and smaller, examines
Consider the exposure limit in array substrate manufacturing process, the sub-pixel of a fixed size can only place limited strip shaped electric poles number
Amount, the area of the open region of sub-pixel become smaller, and the item number for the pixel electrode that can be housed in each sub-pixel is caused just to receive
Limitation, but in order to meet the low-power consumption of display device, the requirement of high contrast, high brightness, it is necessary to improve LCD display
The penetrance of plate, and the reduction of strip shaped electric poles quantity necessarily leads to the reduction of liquid crystal display panel penetrance in array substrate.This
Inventive embodiments are in the case where the gross area of the open region of each sub-pixel is substantially constant, by adjusting two adjacent subpixels
Between data line extending direction and structure so that two adjacent subpixels form the relationship that open region compensates mutually so that
Greater number of strip shaped electric poles can be placed in the subregion of each sub-pixel, improve its penetrance.Especially due to exposure
Under the limitation of the limit, when placing N number of strip shaped electric poles in each sub-pixel, space is relatively more more than needed and places N without sufficient space
When+1 strip shaped electric poles, the mode that can be provided through the embodiment of the present invention makes each sub-pixel utilize the richness of adjacent subpixels
Complementary space makes the lower N+1 strip shaped electric poles that can be placed in its subregion, improves the space availability ratio of each sub-pixel, can
To increase display panel penetrance as far as possible, wherein N is the integer more than or equal to 1.
For example, being limited by exposure limit in processing procedure, when the width of each sub-pixel open region is about 25um, fit
Two strip shaped electric poles are preferably placed, when the width of each sub-pixel open region is about 31um, suitable for placing three strip shaped electric poles,
When the width of each sub-pixel open region is between 25-31um, due to being more than exposure limit, in each sub-pixel at most also only
Two strip shaped electric poles can be placed, such words light efficiency, which is not achieved, most preferably has certain penetrance loss.In the present embodiment,
It is set as：Each sub-pixel group along row to width can be for example 56um, the phase passed through between two adjacent subpixels is complementary
Repay design so that the first area PH1 of each sub-pixel along row to width be 25um, in the PH1 of first area there are two settings
Strip shaped electric poles, and the second area PH2 of each sub-pixel along row to width be 31um, in the PH1 of first area there are two settings
Strip shaped electric poles, namely：Enable M=3, N=2.Each sub-pixel can be made to make its portion using the excess room of adjacent subpixels
The lower N+1 strip shaped electric poles that can be placed in subregion, improve the space availability ratio of each sub-pixel, can increase as far as possible aobvious
Show panel penetrance, wherein N is the integer more than or equal to 1.
Further, in the present embodiment, the main electrode 14a of the second strip shaped electric poles 142 is parallel to the first strip shaped electric poles
141, connection electrode 142b are parallel to the connecting line 111c of the first data line 111.
Further, in the present embodiment, the connecting line 111c of the first data line 111 is located in each sub-pixel group
Between, the central point of the connecting line 111c of the first data line 111 is overlapped with the central point of each sub-pixel group so that the first sub-pixel
The open region area equation of P1 and the second sub-pixel P2 ensure the display area equation of two sub-pixels, to improve liquid crystal display
The show uniformity of panel.
In the present embodiment, first electrode 14 is pixel electrode, and array substrate 10 further includes second electrode 15, second electrode
15 for example can be whole face formula, and a public voltage signal is provided to it by external drive unit, that is, in the present embodiment,
Second electrode 15 is public electrode, forms a current potential between pixel electrode and public electrode according to the signal from data line
Difference.About the film layer structure of array substrate 10, specifically, for example can be：A underlay substrate 101 is provided, in underlay substrate 101
Upper formation the first metal layer, to its graphical grid for forming grid line and switch element；It forms gate insulating layer 102 and covers grid line
The first metal layer with where grid, then forms active layer on gate insulating layer, is overlapped with grid part；Form the
Two metal layers, it is graphically formed data line with the source electrode of switch element, drain electrode, the source electrode of switch element, drain electrode respectively with
The both ends of active layer are in electrical contact, and the raceway groove of switching element is formed between source electrode, drain electrode；Planarization layer 103 is formed, data are covered
Second metal layer where line, source electrode, drain electrode, while playing the role of planarization and insulation；Form public electrode；Form insulation
Layer 104 covers public electrode；Pixel electrode layer is formed, to its graphical formation first electrode 14, public electrode and first electrode
14 can for example form for transparent conductive material, such as ITO metal oxide transparent materials.In the present embodiment, switch member
Part is amorphous silicon film transistor, and certainly, which may be low-temperature polysilicon film transistor or metal oxidation
Object thin film transistor (TFT), the embodiment of the present invention are not limited this.
Fig. 4 is the dot structure schematic diagram of another array substrate provided in an embodiment of the present invention, battle array provided by the embodiment
Row board structure is similar with the structure of Fig. 1-3 array substrates provided：Each sub-pixel group include a first sub-pixel P1 and
One setting adjacent thereto is simultaneously sub to the second sub-pixel P2, the first area PH1 of the first sub-pixel P1 of arrangement and second along row
The second area PH2 of pixel P2 is disposed adjacent and along capable to arrangement, the second area PH2 and the second sub-pixel of the first sub-pixel P1
The first area PH1 of P2 is disposed adjacent and along row to arrangement, and the partial electrode that first electrode 14 is located in the PH1 of first area includes
M strip shaped electric poles, it includes N number of strip shaped electric poles that first electrode 14, which is located at the partial electrode in second area PH2, wherein M>N, and M
For the integer more than or equal to 2, N is the integer more than or equal to 1.First data line 111 is located at the first sub-pixel P1 and the second sub- picture
Between plain P2, the second data line 112 is located at the both sides of each sub-pixel group.First data line 111 includes the first branch line 111a, the
Two branch line 111b, and connecting line 111c, the first branch line 111a between the first branch line 111a and the second branch line 111b,
Two branch line 111b are mutually parallel, connecting line 111c relative to row to gradient be more than the first branch line 111a, the second branch line 111b
Relative to row to gradient.
Further, in the present embodiment, each strip shaped electric poles include main electrode 14a with positioned at the ends each main electrode 14a
The termination electrode 14f at end, wherein main electrode 14a and the first branch line 111a of the first data line 111 are arranged in parallel, termination electrode 14f with
The connecting line 111c of first data line 111 is arranged in parallel, in other words the angle theta of the straight line where connecting line 111c and row between
1, equal to the angle β 1 of straight line and row between where each termination electrode 14f, can further increase array substrate place
Liquid crystal display panel light transmittance.For example, could be provided as：Straight line and the capable angle between where connecting line 111c are
35 °~45 °, 35 °~45 ° of the angle of straight line and row between where each termination electrode 14f, and the numbers of termination electrode 14f and first
It is mutually parallel according to the connecting line 111c of line 111.End described herein can be the separate switch element of each strip shaped electric poles
One end, naturally it is also possible to refer to the both ends of the close upper and lower grid line of each strip shaped electric poles, comparison of the embodiment of the present invention does not limit
System.
Fig. 5 is the dot structure schematic diagram of another array substrate provided in an embodiment of the present invention, and Fig. 6 is the B1- along Fig. 5
The sectional view in the directions B2, array base-plate structure provided by the embodiment are similar with the structure of Fig. 1-3 array substrates provided：Per height
Pixel groups include a first sub-pixel P1 and a setting adjacent thereto and the second sub-pixel P2 along row to arrangement, the first son
The first area PH1 of pixel P1 is disposed adjacent with the second area PH2 of the second sub-pixel P2 and along capable to arrangement, the first sub-pixel
The second area PH2 of P1 is disposed adjacent with the first area PH1 of the second sub-pixel P2 and along row to arrangement, and first electrode 14 is logical
The strip shaped electric poles of slit formation are crossed, and the partial electrode of first electrode 14 being located in the PH1 of first area includes M strip electricity
Pole, it includes N number of strip shaped electric poles that first electrode 14, which is located at the partial electrode in second area PH2, wherein M>N, and M be more than etc.
In 2 integer, N is the integer more than or equal to 1.First data line 111 between the first sub-pixel P1 and the second sub-pixel P2,
Second data line 112 is located at the both sides of each sub-pixel group.First data line 111 includes the first branch line 111a, the second branch line
111b, and the connecting line 111c between the first branch line 111a and the second branch line 111b, the first branch line 111a, the second branch line
111b is mutually parallel, connecting line 111c relative to row to gradient be more than the first branch line 111a, the second branch line 111b relative to
Arrange to gradient.The difference is that in the present embodiment, first electrode 14 is public electrode, passes through external drive unit
Give it to provide a public voltage signal, such as external drive unit can be connected to by common signal line, can also between prolong
It extends to the non-display area of array substrate and is connected to external drive unit.
Further, in the present embodiment, first electrode 14 further includes bucking electrode 143, covers data line 11.Shielding electricity
Pole 143 is electrically connected to each other with each strip shaped electric poles, can shield the electric field that current signal generates in data line 11, such as by including
In the liquid crystal display panel of the array substrate, influence of the current signal to liquid crystal molecule in data line 11 can be shielded, improves liquid
The display effect of LCD panel.
Array substrate further includes multiple second electrodes 15, and in the present embodiment, second electrode 15 is pixel electrode, per height
The drain electrode of the corresponding switch element of pixel electrode connection of pixel.About the film layer structure of the array substrate, specifically, for example can be with
For：One underlay substrate 101 is provided, the first metal layer is formed on underlay substrate 101, to its graphical formation grid line and switch member
The grid of part；It forms gate insulating layer 102 and covers grid line and the first metal layer where grid, then the shape on gate insulating layer
At active layer, overlapped with grid part；Second metal layer is formed, the source with switch element is graphically formed data line to it
Pole, drain electrode, the source electrode of switch element, drain electrode are in electrical contact with the both ends of active layer respectively, and member of opening the light is formed between source electrode, drain electrode
The raceway groove of part；Planarization layer 103, the second metal layer where covering data line, source electrode, drain electrode are formed, while playing planarization
With the effect of insulation；Pixel electrode is formed, in each sub-pixel, which can be that strip shaped electric poles may be planar
Electrode；It forms insulating layer 104 and covers pixel electrode；Common electrode layer is formed, to its graphical formation public electrode, in every height
In pixel, public electrode includes multiple strip shaped electric poles and bucking electrode, and bucking electrode is a part for public electrode.Pixel electrode
It can for example be formed for transparent conductive material with public electrode, such as ITO metal oxide transparent materials.In the present embodiment
In, switch element is amorphous silicon film transistor, and certainly, which may be low-temperature polysilicon film transistor, or
Person's metal oxide thin-film transistor, the embodiment of the present invention are not limited this.
In the present embodiment, it could be provided as：In each sub-pixel P, the strip shaped electric poles of each first electrode 14 include
First strip electricity and the second strip shaped electric poles, wherein the first strip shaped electric poles from the separate second area PH2 of first area PH1 one
End extends to one end of the separate first area PH1 of second area PH2；Second strip shaped electric poles include main electrode and connect electricity
Pole, main electrode is connected to by connection electrode on the first strip shaped electric poles adjacent thereto, specifically, being connected to the first strip shaped electric poles
Close first area PH1 and second area PH2 boundary so that the strip in the first area PH1 of each sub-pixel
The number of electrode is more than the number of the strip shaped electric poles in the second area PH2 of each sub-pixel.It can make each sub-pixel profit
The lower N+1 strip shaped electric poles for place in its subregion with the excess room of adjacent subpixels are improved per height picture
The space availability ratio of element, can increase display panel penetrance as far as possible.
Further, in the present embodiment, it may be arranged as：Each strip shaped electric poles include main electrode and are located at each main
The termination electrode of electrode end, wherein main electrode and the first branch line 111a of the first data line 111 are arranged in parallel, termination electrode and
The connecting line 111c of one data line 111 is arranged in parallel, in other words the angle etc. of the straight line where connecting line 111c and row between
In the angle of straight line and row between where each termination electrode, the display surface where the array substrate can be further increased
The light transmittance of plate.For example, could be provided as：The angle of straight line and row between where connecting line 111c is 35 °~45 °, often
35 °~45 ° of the angle of straight line and row between where a termination electrode, and the connecting line of termination electrode and the first data line 111
111c is mutually parallel.End described herein can be one end of the separate switching element of each strip shaped electric poles, naturally it is also possible to
Refer to the both ends of the close upper and lower grid line of each strip shaped electric poles, comparison of the embodiment of the present invention is not limited.
Fig. 7 is the dot structure schematic diagram of another array substrate provided in an embodiment of the present invention, battle array provided by the embodiment
Row board structure is similar with the structure of array substrate that Fig. 5,6 provide：First electrode 14 is public electrode, and first electrode 14 is also wrapped
Bucking electrode 143 is included, data line 11 is covered.Bucking electrode 143 is electrically connected to each other with each strip shaped electric poles.
The difference is that in the present embodiment, in each sub-pixel P, the strip shaped electric poles of each first electrode 14 include
First strip shaped electric poles 141 and the second strip shaped electric poles 142, wherein the first strip shaped electric poles 141 are from first area PH1 far from second
One end of region PH2 extends to one end of the separate first area PH1 of second area PH2；Second strip shaped electric poles 142 are connected to
On bucking electrode 143 between two sub-pixels, the bucking electrode 143 between two sub-pixels covers the first data line
111, and extend along the extending direction of the first data line 111, specifically, being connected to the bucking electrode between two sub-pixels
The part of the 143 connecting line 111c corresponding to the first data line 111 can further promote display panel where array substrate
Penetrance.
Further, in the present embodiment, it may be arranged as：Each strip shaped electric poles include main electrode and are located at each main
The termination electrode of electrode end, wherein main electrode and the first branch line 111a of the first data line 111 are arranged in parallel, termination electrode and
The connecting line 111c of one data line 111 is arranged in parallel, in other words the angle etc. of the straight line where connecting line 111c and row between
In the angle of straight line and row between where each termination electrode, the display surface where the array substrate can be further increased
The light transmittance of plate.
Fig. 8 is the dot structure schematic diagram of another array substrate provided in an embodiment of the present invention, provided in this embodiment
The structure of the structure array substrate as shown in fig. 4 of array substrate is similar.Further, in the present embodiment, pel array packet
It includes along row to the grid line 12 of extension, along the first data line 111, the second data line 112 and multiple sub-pixels arranged to extension
Group, each sub-pixel group include the first sub-pixel P1 and setting adjacent thereto and the second sub-pixel P2 along row to arrangement, and first
It includes M strip shaped electric poles that electrode 14, which is located at the partial electrode in the PH1 of first area, and first electrode 14 is located in second area PH2
Partial electrode include N number of strip shaped electric poles, wherein M>N, and M is the integer more than or equal to 2, N is the integer more than or equal to 1.The
One data line 111 include the first branch line 111a, the second branch line 111b, and positioned at the first branch line 111a and the second branch line 111b it
Between connecting line 111c, the first branch line 111a, the second branch line 111b, the second data line 112 be mutually parallel and relative to row to inclining
Tiltedly setting, has between the first branch line 111a, the second branch line 111b, the second data line 112 and the extending direction of grid line 12 in other words
There are one being also not equal to 90 ° of angle not equal to 0 °, connecting line 111c relative to row to gradient be more than the first branch line 111a,
Second branch line 111b relative to row to gradient, multiple strip shaped electric poles of first electrode 14 are mutually parallel and are parallel to the second number
According to the extending direction of line.
Further, above-mentioned multiple sub-pixel groups include sub to the first sub-pixel group P10 being disposed adjacent and second along arranging
Pixel groups P20, the second data line 112 are located at the both sides of the first sub-pixel group P10 and the second sub-pixel group P20, the first son
The first sub-pixel P1 in the first sub-pixel P1 and the second sub-pixel group P20 in pixel groups P10 is connected on the left of it
The second data line of same 112, second in the second sub-pixel P2 and the second sub-pixel group P20 in the first sub-pixel group P10
Sub-pixel P2 is connected to the second data line of same 112 on the right side of it.Second data line 112 be entirety along row to
The broken line of extension, wherein the second data line 112 is corresponding in the second sub-pixel group corresponding to the part of the first sub-pixel group P10
The part of P20 is symmetrical arranged relative to grid line 12, in other words relative to row to being symmetrical arranged, so that the first sub-pixel group
In P10 in the extending direction of first electrode 14 and the second sub-pixel group P20 the extending direction of first electrode 14 relative to grid line 12
It is symmetrical arranged, the first data line 111 is corresponding in the second sub-pixel group P20's corresponding to the part of the first sub-pixel group P10
Part is symmetrical arranged also relative to grid line 12, is formed pseudo- double domain structures, can be further increased the transmitance of array substrate.
Further, in the present embodiment, it may be arranged as：Each strip shaped electric poles include main electrode and are located at each main
The termination electrode of electrode end, wherein main electrode and the first branch line 111a of the first data line 111 are arranged in parallel, termination electrode and
The connecting line 111c of one data line 111 is arranged in parallel, in other words the angle etc. of the straight line where connecting line 111c and row between
In the angle of straight line and row between where each termination electrode, the display surface where the array substrate can be further increased
The light transmittance of plate.
The present invention also provides a kind of liquid crystal display panels, including array substrate, color membrane substrates and the aid being oppositely arranged in
Layer of liquid crystal molecule between the two.
The present invention also provides a kind of display devices, including above-mentioned liquid crystal display panel and shell, wherein shell is formed
Accommodating space, for accommodating display panel, shell can be hard, can also be flexible, the present invention does not make this specifically
Limitation.It is understood that display device provided in an embodiment of the present invention, can be computer, TV, display device for mounting on vehicle etc. its
There is the display device of display function, the present invention to be not specifically limited to this for he.
Note that above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiments described here, can carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out to the present invention by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
May include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (14)
1. a kind of array substrate, which is characterized in that including：
Underlay substrate；
Grid line and data line are successively set on the underlay substrate, and the grid line edge is gone to extension and along row to arrangement, described
Data line is along arranging to extending and along row to arrangement, and the grid line intersects with the data line and limits multiple sub-pixels, each
Sub-pixel include along arranging to the first area of arrangement and second area, the first area along row to width be more than described second
Width of the region along line direction；
And first electrode, including multiple strip shaped electric poles disposed in parallel；
The partial electrode that the first electrode is located in the first area includes M strip shaped electric poles, and the first electrode is located at
Partial electrode in second area includes N number of strip shaped electric poles, wherein M>N, and M is integer more than or equal to 2, N be more than or equal to
1 integer；
The multiple sub-pixel includes multiple sub-pixel groups, and each sub-pixel group includes being disposed adjacent it along capable to the first of arrangement
Sub-pixel and the second sub-pixel, the first area of first sub-pixel are disposed adjacent with the second area of second sub-pixel
And along row to arrangement, the second area of first sub-pixel is disposed adjacent and with the first area of second sub-pixel along row
To arrangement；
The data line includes the first data line, between the first sub-pixel and the second sub-pixel, first data line pair
Should include the first branch line, the second branch line in the part of each sub-pixel, and positioned at first branch line and second branch line
Between connecting line, first branch line is parallel to second branch line, the straight line where the connecting line relative to row to
Gradient be more than first branch line where straight line relative to row to gradient.
2. array substrate according to claim 1, which is characterized in that the first electrode is pixel electrode, the array
Substrate further includes public electrode, and the public electrode is between the pixel electrode and the underlay substrate.
3. array substrate according to claim 1, which is characterized in that the first electrode is public electrode, the array
Substrate further includes pixel electrode, and the pixel electrode is between the public electrode and the underlay substrate.
4. array substrate according to claim 3, which is characterized in that the public electrode further includes bucking electrode, described
Bucking electrode covers the data line.
5. array substrate according to claim 4, which is characterized in that in each sub-pixel, the strip shaped electric poles include
First strip shaped electric poles and the second strip shaped electric poles, first strip shaped electric poles are from the first area far from the second area
One end extends to one end far from the first area of the second area, and second strip shaped electric poles are located at firstth area
In domain；
The initiating terminal of second strip shaped electric poles is connected to the part corresponding to the connecting line of the bucking electrode, and described
The end of two strip shaped electric poles is located at one end far from the second area of the first area.
6. array substrate according to claim 1, which is characterized in that the central point of the connecting line of first data line with
The central point of each sub-pixel group overlaps, the open region area equation of first sub-pixel and second sub-pixel.
7. array substrate according to claim 1, which is characterized in that the first area along row to width be 25um,
The second area along row to width be 31um, wherein M=3, N=2.
8. array substrate according to claim 1, which is characterized in that the data line further includes at least two and is arranged in parallel
The second data line, be located at the both sides of each sub-pixel group, the first branch line of first data line is counted with described second
It is arranged in parallel according to line, the strip shaped electric poles are arranged in parallel with first branch line.
9. array substrate according to claim 8, which is characterized in that in each sub-pixel, the strip shaped electric poles include
With positioned at the termination electrode of the main electrode end, the main electrode is parallel with first branch line of the first data line to be set main electrode
It sets, the connecting line of the termination electrode and first data line is arranged in parallel.
10. array substrate according to claim 9, which is characterized in that the connecting line of first data line and grid line
Angle is 35 °~45 °.
11. array substrate according to claim 9, which is characterized in that in each sub-pixel, the strip shaped electric poles include
First strip shaped electric poles and the second strip shaped electric poles, first strip shaped electric poles are from the first area far from the second area
One end extends to one end far from the first area of the second area, and second strip shaped electric poles are located at firstth area
In domain；
Second strip shaped electric poles include main electrode and connection electrode, and the main electrode is connected to described by the connection electrode
First strip shaped electric poles, the main electrode are parallel to first strip shaped electric poles, and the connection electrode is parallel to described first
The connecting line of data line.
12. array substrate according to claim 8, which is characterized in that second data line is set relative to grid line inclination
It sets；
The multiple sub-pixel group includes that edge is arranged to the first sub-pixel group being disposed adjacent and the second sub-pixel group, second number
According to line correspond to the first sub-pixel group part it is corresponding in the part of the second sub-pixel group relative to grid line pair
Claim setting.
13. a kind of liquid crystal display panel, which is characterized in that including such as claim 1-12 any one of them array substrate.
14. a kind of display device, which is characterized in that including liquid crystal display panel as claimed in claim 13.
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