CN108475659A - Pinboard and its manufacturing method with big depth-to-width ratio embedded metal line - Google Patents
Pinboard and its manufacturing method with big depth-to-width ratio embedded metal line Download PDFInfo
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- CN108475659A CN108475659A CN201680058415.1A CN201680058415A CN108475659A CN 108475659 A CN108475659 A CN 108475659A CN 201680058415 A CN201680058415 A CN 201680058415A CN 108475659 A CN108475659 A CN 108475659A
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- 239000002184 metal Substances 0.000 title claims abstract description 258
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 258
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 99
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 238000003780 insertion Methods 0.000 claims description 22
- 230000037431 insertion Effects 0.000 claims description 22
- 238000000034 method Methods 0.000 abstract description 33
- 230000003071 parasitic effect Effects 0.000 abstract description 29
- 230000005540 biological transmission Effects 0.000 abstract description 5
- 230000008054 signal transmission Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 21
- 239000010703 silicon Substances 0.000 description 21
- 238000009826 distribution Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 230000000694 effects Effects 0.000 description 10
- 238000001259 photo etching Methods 0.000 description 9
- 239000011810 insulating material Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 239000000203 mixture Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- 238000000708 deep reactive-ion etching Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000000992 sputter etching Methods 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 3
- 125000002915 carbonyl group Chemical group [*:2]C([*:1])=O 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005323 electroforming Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Abstract
A kind of pinboard and its manufacturing method with big depth-to-width ratio embedded metal line, in substrate (710), the depth of metal wire and the ratio of width are not less than 1 for the embedded setting of metal wire (722,724) of the pinboard (700).The manufacturing method of pinboard includes carrying out single side etching to the substrate (1301) of pinboard, then the hole of first etching filling metallic conductor etches the slot (1317) in the hole (1316) and metal wire of filling metallic conductor simultaneously again.The metal wire of embedded big depth-to-width ratio in pinboard substrate, under conditions of not increasing metal line-width, keep high metal line wire density, reduce the dead resistance and parasitic inductance of metal wire, improve the power transmission efficiency and signal transmission bandwidth of pinboard, big depth-to-width ratio embedded metal line and through-hole, simple process and low cost are manufactured with single-sided process method.
Description
Pinboard and its manufacturing method technical field with big depth-to-width ratio embedded metal line
[0001] the present invention relates to a kind of integrated circuit and its manufacturing method, the pinboards and its manufacturing method of especially a kind of integrated circuit.
Background technique
[0002] as the development of ic manufacturing technology, the characteristic size (feature size) of transistor are constantly reduced, Jian closes speed and is continuously increased.Therefore, (interconnection) is interconnected between IC chip to be also continuously improved therewith with the requirement for encapsulating (p ackage).Firstly, encapsulation allows for providing highdensity metal line (layout), the transmission of data, signal and power provides enough channels between different IC chips.Secondly, encapsulation needs reduce the parasitic parameter (parasitic parameters) introduced due to interconnection, transmission data, the efficiency (efficiency) and bandwidth (bandwidth) of signal and power between IC chip are improved.
[0003] silicon pinboard (silicon interposer) partially solves the problems, such as wiring density and parasitic parameter.Firstly, production technology and equipment record based on silicon materials, the metal line width (line width) of very little may be implemented in last part technology (back end of line, BEOL).These mature techniques are processed to the silicon pinboard metal redistribution layer (redistribution layer, RDL) of (fabricate) fine (fine pitch), to improve wiring density.On the other hand, the IC chip of interconnection usually passes through flip-chip (flip-chip) and directly connects with silicon pinboard, and silicon pinboard is connect by through silicon via (through-silicon- via, TSV) with other package substrates (package substrate).The parasitic parameter introduced due to eliminating lead frame (lead frame) and bonding line (bonding wire), improves the bandwidth of signal transmission.
[0004] although silicon pinboard eliminates the parasitic parameter that lead frame and bonding line bow I enter, the metal redistribution layer on silicon pinboard introduces new parasitic parameter.The parasitic parameter of silicon pinboard introducing can be reduced using broader metal interconnection wire, but the wiring density for improving metal layer but requires to use narrower thinner metal wire.Therefore, the silicon pinboard of the prior art can not reduce parasitic parameter with inch and improve the wiring density of metal layer.
[0005] as shown in Figure 1, a pinboard 100 of the prior art includes the back metal interconnection layer 130 of substrate (substrate) 110, the front metal interconnection layer 120 of substrate and substrate.Substrate 110 is semiconductor material such as silicon, glass or ceramics.Substrate 110 includes multiple conductive through holes 111.Conductive through hole 111 is filled out in the hole by substrate 110
Insulating layer 113 outside the metal 112 and metal filled forms.Conductive through hole 111 realizes being electrically connected for front metal interconnection layer (plain conductor) 120 and back metal interconnection layer 130.Front metal interconnection layer 120 is by insulating materials 121, the metal carbonyl conducting layer 122,124 being distributed in insulating materials, and the conductive hole 123 between electrical connection different metal conductor layer forms.Conductive hole is the metal wire in insulating materials.With double layer of metal conducting wire for explaining the prior art in Fig. 1, the number of plies of plain conductor can increase or decrease with the need in actual use.Front metal interconnection layer 120 is usually also comprising the welding material (soldering material) 126 for 125 upper end of convex block (bump) 125 and convex block (bump) connecting with upper layer plain conductor; it is welded for realizing the flip-chip of pinboard 100 and other integrated circuits; if not needing welding material 126 using direct joining technique (Direct Bonding).The spacing of convex block 125 is usually smaller, can realize and be electrically connected with the intensive port of integrated circuit surface.Back metal interconnection layer 130 is made of the soldered ball 133 of 132 bottom of metal carbonyl conducting layer 132 and metal carbonyl conducting layer in insulating layer 131, insulating layer 131.Pinboard 100 is welded on other package substrates by soldered ball 133.The spacing of bottom soldered ball 133 is usually larger, convenient for being reliably electrically connected with the biggish package substrate realization of line width.
As shown in Fig. 2, another pinboard 200 of the prior art includes the back metal interconnection layer 230 of substrate 210, the front metal interconnection layer 220 of substrate and substrate.With the difference of the prior art construction of public affairs Jian in Fig. 1 are as follows: the front metal interconnection layer 220 of pinboard 200 includes the shallow slot (shallow trench) 221 for being formed in 210 surface of substrate, and metal wire 223 is formed in shallow slot 221.(isolate) is isolated with substrate 210 by insulating layer 222 for metal wire 223, is electrically connected by conductive hole 224 with other metal wires 225 formation in front metal interconnection layer 220.The depth very little of shallow slot 221 carries out photoetching to guarantee in the still smooth enough spin coating that can carry out photoresist of rear surface for forming shallow slot 221 to process the figure of through-hole 212.In addition to this, the shallow slot 221 in documents 1 and conductive through hole 211 share copper plating and flatening process, to reach the technical effect of simplified manufacturing process.
In 1 Application of Silicon Interposer for 3D-Integration silicon pinboard of documents in the application in three-dimensionally integrated, the 5-9 pages, in October, 2011 (SEMICON Europa, Messe Dresden, Germany), guarantee to form the still smooth enough spin coating processing via hole image that can carry out photoresist of groove rear surface using shallow trench.Another advantage of the structure is that shallow slot and through-hole share copper plating and flatening process, to simplify manufacturing process.But shallow slot limits its depth-to-width ratio, can not improve and achieve the purpose that reduce metal line impedence.
[0008] in 2 US7932179B2 of documents, groove is formed in substrate back and is filled up by insulating materials, and metal wire is formed on the insulating materials in groove.
[0009] in 3 US7812461 of documents, include in groove (trench) column (stud), and the column is prominent (protruding) from channel bottom.On the other hand, the metal in groove is only covered on flute surfaces rather than by trench fill.
[0010] in 4 US20090152743A1 of documents, groove is located in the dielectric layer of substrate surface.
[0011] requirement with IC chip to pinboard front metal interconnection layer wiring density is higher and higher, and the width of metal wire can be more and more narrow.The metal wire 122,124 no matter being formed in insulating layer 121, the metal wire 223 being also formed in substrate surface shallow slot 221, the dead resistance and parasitic inductance that they are introduced will all be significantly increased with the reduction of metal line-width.Dead resistance is bigger, and the efficiency by metal interconnection layer transimission power is lower, can also lead to mains ripple because of the resistive pressure drop (IR voltage drop) in dead resistance；And parasitic inductance is bigger, the bandwidth for transmitting signal by metal interconnection layer is lower.
Technical problem
[0012] the object of the present invention is to provide a kind of pinboard and its manufacturing method with big depth-to-width ratio embedded metal line, technical problems to be solved are the wiring densities that same inch reduces the parasitic parameter of metal wire and raising metal layer on pinboard.
Solution to the problem
Technical solution
[0013] the invention adopts the following technical scheme: a kind of pinboard with big depth-to-width ratio embedded metal line, metal wire is equipped on the substrate of pinboard, the metal wire insertion is arranged in substrate, and the depth of metal wire and the ratio of width of the insertion setting are not less than 1.
[0014] ratio of the depth of the metal wire of insertion setting of the invention and width are as follows: ratio≤20 of 2≤depth and width
[0015] ratio of the depth of the metal wire of insertion setting of the invention and width are as follows: ratio > 3 of depth and width.
[0016] ratio of the depth of the metal wire of insertion setting of the invention and width are as follows: ratio≤10 of 5≤depth and width.
[0017] depth of metal wire of insertion setting of the invention and the ratio of width are 10.
[0018] metal wire of the invention insertion is arranged in the first surface of substrate.
[0019] metal wire that insertion of the invention is arranged in the first surface of substrate is realized through third through-hole and is electrically connected with the second surface of substrate, and the through-hole is the electric conductor that metal is filled in hole.
[0020] metal wire of the invention insertion is arranged in the second surface of substrate.
[0021] metal wire that insertion of the invention is arranged in the second surface of substrate is realized through fourth hole and fifth hole and is electrically connected with the first surface of substrate, and the through-hole is the electric conductor that metal is filled in hole.
[0022] a kind of manufacturing method of the pinboard with big depth-to-width ratio embedded metal line, the substrate of pinboard is performed etching to be formed filling metallic conductor hole and insertion be arranged in substrate metal wire slot, then metal filling is carried out, the etching is carried out in the single side of substrate, the hole of first etching filling metallic conductor, depth is the depth that the depth in the hole of filling metallic conductor subtracts the slot of filling metal wire, then the hole of filling metallic conductor and the slot of metal wire are etched with inch again, depth is the depth of embedded metal line.
Advantageous effect of the invention
Beneficial effect
[0023] present invention compared with prior art, by the metal wire for being embedded in big depth-to-width ratio in pinboard substrate, under conditions of not increasing metal line-width, keep high metal line wire density, the dead resistance and parasitic inductance for reducing metal wire, improve the power transmission efficiency and signal transmission bandwidth of pinboard, manufacture big depth-to-width ratio embedded metal line and through-hole using single-sided process method, simple process and low cost.
To the brief description of accompanying drawing
Detailed description of the invention
[0024] Fig. 1 is the adapter plate structure schematic diagram (one) of the prior art.
[0025] Fig. 2 is the adapter plate structure schematic diagram (two) of the prior art.
[0026] Fig. 3-1 is that the metal wire setting of pinboard substrate illustrates schematic diagram.
[0027] Fig. 3-2 is the graph of relation of embedded metal line depth-to-width ratio Yu dead resistance and parasitic inductance.
[0028] Fig. 4-1 is application circuit of the pinboard as distribution network.
[0029] Fig. 4-2 is the equivalent parasitic resistance and parasitic inductance circuit diagram of distribution network metal wire.
[0030] Fig. 5 is the logarithmic plot of distribution network impedance and frequency relation.
[0031] Fig. 6 is the structural schematic diagram of the embodiment of the present invention 1.
[0032] Fig. 7 is the A- A cross-sectional view of Fig. 6.
[0033] Fig. 8 is the structural schematic diagram of the embodiment of the present invention 2.
[0034] Fig. 9 is the B-B cross-sectional view of Fig. 8.
[0035] Figure 10 is application connection schematic diagram of the invention.
[0036] Figure 11 is the structural schematic diagram of the embodiment of the present invention 3.
[0037] Figure 12 is the C-C cross-sectional view of Figure 11.
[0038] Figure 13-1 is the schematic diagram of the method for the present invention step 1.
[0039] Figure 13-2 is the schematic diagram of the method for the present invention step 2.
[0040] Figure 13-3 is the schematic diagram of the method for the present invention step 3.
[0041] Figure 13-4 is the schematic diagram of the method for the present invention step 4.
[0042] Figure 13-5 is the schematic diagram of the method for the present invention step 5.
[0043] Figure 13-6 is the schematic diagram of the method for the present invention step 6.
[0044] Figure 13-7 is the schematic diagram of the method for the present invention step 7.
[0045] Figure 13-7 is the schematic diagram of the method for the present invention step 8.
Preferred forms of the invention
[0046] comparative example, using the silicon pinboard of 10mm X 10mm, with a thickness of Ι Ο Ο μ η ι, first surface includes metal wire (metal interconnection wire), the chip being connected on pinboard by flip-chip.Wherein a metal line is used to power to chip, length 5mm.Due to other for signal and non-powered metal wire occupies many areas of pinboard first surface, the width of the power supply metal wire is only capable of reaching 5um.Using the on piece copper metal line or shallow trench copper metal line of the prior art, with a thickness of 2.5um, depth-to-width ratio 0.5.Metal wire D.C. resistance is up to 6.8 Ω in this way, helps Buddhist nun, A Practical Guide to by John Ardizzoni John's Alday
Guide page 3 of High-Speed Printed-Circuit-Board Layout high-speed printed circuit board utilitarian design, in September, 2005, (Analog Dialogue, 39-09, bibliography [1]) in provide formula 2 calculate, parasitic inductance be 7.7 nH.
[0047] in embodiment 1, using the silicon pinboard of 10mm X 10mm, with a thickness of 100 μ η ι.As comparative example, first surface is covered with metal interconnection wire, and the metal line-width powered for chip is caused there was only 5 μ η ι.In embodiment 1, using the big depth-to-width ratio embedded metal line with 10, the depth of embedded metal line is 50 μ η ι, is the half of silicon switching plate thickness, influences on the mechanical strength of silicon pinboard itself little.It is equally the metal interconnection wire of 5mm long after big depth-to-width ratio embedded metal line, D.C. resistance is reduced to 340 η ι Ω, reduces 95%
, 5.7 nH are reduced to according to the parasitic inductance that bibliography [1] calculates, reduce 26%.
[0048] embodiment 2 increases the through-hole of connection pinboard first surface and second surface on the basis of embodiment 1, and the embedded metal line with big depth-to-width ratio is electrically connected with other connected circuits of first surface or second surface such as power supply realization.The D.C. resistance of metal line portions is reduced to 340 η ι Ω, reduces 95%, is reduced to 5.7 η Η according to the parasitic inductance that bibliography [1] calculates, reduces 26%.
[0049] embodiment 3 increases the big depth-to-width ratio embedded metal line in pinboard second surface on the basis of embodiment 2.The embedded metal line can be used alone the resistance and parasitic inductance for reducing embedded metal line.The function of first surface embedded metal line can also be assisted and supplemented in the insufficient situation of the big depth-to-width ratio embedded metal line number amount of first surface.The D.C. resistance of metal line portions is reduced to 340 η ι Ω, reduces 95%, is reduced to 5.7 η Η according to the parasitic inductance that bibliography [1] calculates, reduces 26%.
Embodiments of the present invention
[0050] invention is further described in detail with reference to the accompanying drawings and examples.As shown in figure 3-1, pinboard is equipped with substrate 310,310 front of substrate is equipped with front insulating layer 320, front metal line 321 is equipped in front insulating layer 320, the metal wire 322 in the shallow slot of front being arranged in 310 front of substrate, the big depth-to-width ratio metal wire (big depth-to-width ratio embedded metal layer, big depth-to-width ratio embedded metal line) 312 being embedded in substrate face is equipped with insulating layer 313 between big depth-to-width ratio metal wire 312 and substrate 310.The width ν for reducing front metal line 321, the metal wire 322 in the shallow slot of front and big depth-to-width ratio metal wire 312, can be improved wiring density of the metal wire in substrate 310.Conventionally, as different reasons, the thickness of the metal wire 32 2 in front metal line 321 and front shallow slot is usually less than or close to its width ν.
[0051] the limited reason of 321 thickness of front metal line is divided into two kinds according to the difference of manufacturing process:
[0052] (1) is based on Damascus technics (damascene process) and manufactures obtained front metal line
[0053] front insulating layer 320 itself is very thin, and usually only several microns to more than ten microns, and the thickness of front metal line 321 is no more than the thickness of front insulating layer 320；Therefore in the prior art, the thickness of front metal line 321 generally all only has several microns.On the other hand, front insulating layer 320 is usually silica or other dielectrics, and the lithographic method for being formed on its surface larger depth-to-width ratio (/ ν ν) groove is at high cost and do not popularize.So the thickness of front metal line 321 be generally smaller than or close to front metal line width ν.
[0054] (2) are based on photoetching electroforming process (LIGA process) and manufacture obtained front metal line
[0055] photoetching electroforming process (LIGA process) includes three photoetching, plating and mold (molding) basic steps.Patterned photoresist is used as the mould (mold) of plating by the technique.Since the mechanical strength (mechanical strength) of photoresist itself is much worse than silicon or silica, to limit the depth-to-width ratio of plating metal line.In addition, forming thicker front metal line in substrate surface also can bring difficulty to flatening process.
[0056] required etching, plating and flatening process can be shared with part through silicon via formation process in 322 process of metal wire in the shallow slot of front, its technical effect is that forming the metal wire 322 in the front shallow slot that one layer is similar to traditional front metal line 321 with lower cost.So the design parameter including thickness is all reference with front metal line 321.On the other hand, the processing technology of public affairs Jian requires to be initially formed the shallow slot for accommodating the metal wire 322 in the shallow slot of front in documents 1, then passes through the means of gluing and photoetching, forms the figure of through silicon via.According to gluing, requirement of the technological means to substrate surface flatness of photoetching, but also the shallow slot for accommodating the category line 322 in the shallow slot of Nintaus face cannot be too deep.
[0057] present invention has the pinboard of big depth-to-width ratio embedded metal line, the embedded big depth-to-width ratio metal wire 312 being arranged in substrate using insertion, under the premise of not increasing by 312 width w of metal wire, using the thickness of pinboard substrate material, depth/z of big depth-to-width ratio metal wire 312 is made significantly to be greater than the width v of metal wire.I.e. metal wire has big depth-to-width ratio (A/ v).Realize high density, low resistance, low inductance metal line wire.
[0058] by taking copper metal line as an example, the calculation formula of dead resistance are as follows:
(1)
[0060] calculation formula of parasitic inductance:
(2)
[0062] in formula (1) and formula (2), 7 be dead resistance, and unit is ohm (Ω), and L is parasitic inductance, and unit is nanohenry
(η Η), d, v and/^It is length, width and the depth of metal wire respectively, unit is micron (μ η ι).For example, being 5 mm for length d, width v is the metal wire of 5 μ η ι, and as shown in figure 3-2, as depth-to-width ratio (h/w) increases, the dead resistance and parasitic inductance of metal wire are substantially reduced.Compare the metal wire that depth-to-width ratio is 0.5
Embedded (in the insertion substrate) metal wire for being 10 with depth-to-width ratio, under conditions of keeping line width w is 5 μ η ι, the embedded metal line dead resistance that depth-to-width ratio is 10 reduces 20 times, and parasitic inductance reduces 26% in (in figure indicated with arrows the corresponding axiss of ordinates of two curves).
[0063] pinboard of the invention uses big depth-to-width ratio embedded metal line (metal layer) structure, the resistance and inductance of metal wire are reduced with inch, that is the impedance (impedance) of line, reduce the parasitic parameter of pinboard, the wiring density for improving metal layer, improves interacted system performance between IC chip.
[0064] below to illustrate to reduce technical effect brought by distribution network inductance for processor distribution network (Power Distribution Network, PDN).
[0065] as processor includes that the reduction of transistor line width used in on-site programmable gate array FPGA and working frequency improve, the operating voltage of processor is reduced continuous to reduce the loss of the pass the Jian of transistor charge and discharge inch.When the line width of transistor narrows down to 40 nm inch from 130 nm, the operating voltages of processor chips is from 1.5
V is reduced to 0.9 V.However, the operating current of processor is usually larger, several amperes to tens amperes, and change quickly, if the impedance of distribution network is too big, the fluctuation of processor load voltage will be caused.So a target impedance (target impedance) is normally set up to processor, the upper limit as the impedance that can tolerate (tolerate).
[0066] pinboard is bonded to the supported chip 412 of power supply chip 411 and processor as a kind of application scenarios of distribution network as shown in Fig. 4-1 on pinboard 400,
Metal connecting line 421 on pinboard is used as distribution network, and power supply chip 411 is the power supply of supported chip 412.As shown in the Fig. 4-2, the metal wire of distribution network includes dead resistance 431 and parasitic inductance 432, has codetermined the impedance of distribution network.
[0067] as shown in figure 5, the relationship of distribution network impedance and frequency, pays attention to the longitudinal axis for indicating impedance and indicate that the horizontal axis of frequency all employs logarithmic coordinates (log scale).The curve of the connection composition of solid line 511 and 512 represents the impedance frequency characteristic (charact eristic of impedance and frequency) of distribution network in the pinboard without using the prior art of big depth-to-width ratio embedded metal layer.At a lower frequency, the impedance of distribution network determines (solid line 511) by dead resistance.With the increase of frequency, the impedance of parasitic inductance is increasing, and is more than the impedance of dead resistance, and curve is caused to rise (solid line 512).If the usable area of pinboard is insufficient, cause distribution network metal wire narrow, will result in total impedance leads to the upper excessive voltage fluctuation of load more than the target impedance 530 of supported chip.On the contrary, the pinboard using big depth-to-width ratio embedded metal layer can significantly reduce
The impedance of distribution network.Low-frequency impedance represented by solid line 521 significantly reduces.Same inch, due to the reduction of parasitic inductance, high-frequency resistance represented by solid line 522 is also reduced by.Its resultant effect is exactly the requirement that can meet distribution network impedance in the larger frequency range and be less than target impedance 530.
[0068] embodiment 1
[0069] as shown in fig. 6, the pinboard (pinboard) 600 with big depth-to-width ratio embedded metal line of the invention, includes substrate 610, the surface on substrate 610 is first surface 611, and the surface under substrate 610 is second surface 6 12.
[0070] it is formed with metal wire 621,623 on first surface 611, the embedded metal line 622,624 inside substrate 610 is extended into from first surface 611.The ratio (depth-to-width ratio) of the depth/z and width w of embedded metal line 622,624 are more than or equal to 1:
[0071] hl w > \
[0072] under the conditions of being not less than 1, the impedance of big depth-to-width ratio embedded metal line is less than the impedance of existing pinboard metal interconnection wire.Further, depth-to-width ratio be greater than v > 3 W) inch, using big depth-to-width ratio embedded metal line reduce metal interconnection line impedence technical effect it is more significant.Although Α/ν value is bigger, drop that low-impedance technical effect is more significant, // ν value is also limited to the thickness of silicon pinboard and the manufacturing process of embedded metal line.If A/v value is excessive, 20 are greater than, then being difficult to produce the embedded metal line entirely without empty (void-free), the impedance for instead resulting in embedded metal line increases.Therefore, the preferable range of embedded metal line depth-to-width ratio is:
[0073] 2≤h/ w <20
[0074] preferably range is:
[0075] 5≤h/ w≤l0
[0076] metal wire 621,623 being formed on 610 first surface 611 of substrate, big depth-to-width ratio embedded metal line 622,624 can be electrically connected by the first convex block (bump) 631 being arranged thereon or the first soldered ball (solder ball) 632 with other chips realization on pinboard 600.
[0077] as shown in fig. 7, the substrate 710 (610) of pinboard 700 (600) has first surface 711 (611) and second surface 712 (612).The prior art can be used on first surface 711 and form second insulating layer 742 and the metal wire 721 (621) in second insulating layer 742,723 (623), to merely illustrate one layer of metal wire in simplification figure 7, multilayer interconnection metal wire actually may include.Embedded metal line 722 (622), 724 (624) from
First surface 711 extends into inside substrate 710, full with conductive material filling, is realized and is insulated with substrate 710 by the first insulating layer 741, and realized and planarize with first surface 711.Metal wire 721,723 and embedded metal line 722,724 can be electrically connected by the first convex block 631 or the first soldered ball 732 (632) with other chips realization on pinboard 700.The substrate for being higher than 1000 Ω ^ η ι HR-Si substrate person insulating materials (such as glass) composition for resistivity can not use the first insulating layer 741, second insulating layer 742.
[0078] embodiment 2
[0079] as shown in Figure 8, pinboard 800 (600) with big depth-to-width ratio embedded metal line of the invention, it include substrate 810 (610), first surface 811 (611), second surface 812 (612).
[0080] it is formed with metal wire 821 (621), 823 (623) on first surface 811, extends into embedded metal line 822 (622) inside substrate 810,824 (624) from first surface 811.Ratio (depth-to-width ratio) Α/ν >=1 of the depth/ζ and width w of embedded metal line 822,8 24.After comprehensively considering the factor of technical effect and manufacture difficulty, the preferable range of embedded metal line depth-to-width ratio is: 2≤/ ^≤20 ^.
[0081] pinboard 800 also includes first through hole (through substrate via, TSV) the 813, second through-hole 814 and third through-hole 815.First through hole 813 and the second through-hole 814 realize being electrically connected for metal wire 821 on first surface 811 and second surface 812.The realization embedded metal line 824 of third through-hole 815 is electrically connected with second surface 812.Through-hole is the electric conductor that metal is filled in hole.
[0082] metal wire 821,823 being formed on 810 first surface 811 of substrate, it can be electrically connected by the first convex block (bump) 831 (631) being arranged thereon or 832 (632) the first soldered ball (solder ball) with other chips realization on pinboard 800 with big depth-to-width ratio embedded metal line 82 2,824.
[0083] as shown in figure 9, the substrate 910 (610) of pinboard 900 (600) has first surface 911 (611) and second surface 912 (612).The prior art can be used on first surface 911 and form second insulating layer 942 (742) and the metal wire 921 (621) in second insulating layer 742,923 (623).Embedded metal line 922 (6 22), 924 (624) extend into substrate 910 (610) inside from first surface 911 (611), it is full with conductive material filling, it is realized and is insulated by the first insulating layer 941 (741) and substrate 910, and realized and planarize with first surface 911.Second through-hole 914 (814) is electrically connected metal wire 921 and second surface 912 (612), and third through-hole 915 (815) is electrically connected the bottom and second surface 912 of embedded metal line 924 (624).Second surface 912 is externally provided with third insulating layer 943 and conductive gasket (pad) 916, and the second soldered ball or the second convex block 951 are formed on conductive gasket 916.Other circuit devcies can pass through 916 He of conductive gasket of second surface
Second soldered ball or the second convex block 951 are electrically connected with the realization of pinboard 900.The substrate of HR-Si substrate or insulating materials (such as glass) composition for resistivity higher than 1000 Ω ^ η ι can not use the first insulating layer 941 (74 1), second insulating layer 942 (742) and third insulating layer 943.
[0084] as shown in Figure 10, with the pinboard application inch of big depth-to-width ratio embedded metal line, the substrate 1010 of pinboard includes big the first embedded metal of depth-to-width ratio line 1021, the second embedded metal line 1022.The width direction of embedded metal line in Figure 10 is the direction perpendicular to paper.First chip 1030 and the second chip 1040 are by flip-chip welding (flip-chip bond) on pinboard.First embedded metal line 1021 connects the different port in a chip, i.e. two port (port) first ports 1031 and second port 1032 in the first chip 1030.Second embedded metal line 1022 then connects two ports in different chips, the i.e. first port 1041 of the third port 1033 of the first chip 103 0 and the second chip 1040.When the first chip 1030 is supported chip, second chip 1040 is power management chip or voltage-stablizer (voltage regulator) inch, it can use the low-impedance characteristic of big the second embedded metal of depth-to-width ratio line 1022, to 1030 transimission power of supported chip.And for only transmission signal, the port (such as second port 1042 of the second chip 1040) without transimission power can be then electrically connected by the metal wire 1023 on surface with other ports.
[0085] embodiment 3
[0086] as shown in figure 11, pinboard 1100 (600) with big depth-to-width ratio embedded metal line of the invention, it include substrate 1110 (610), first surface 1111 (611), second surface 1112 (612).
[0087] it is formed with metal wire 1121 (621), 1123 (623) on first surface 1111, the embedded metal line 1122 (622) inside substrate 1110 is extended into from first surface 1111.Ratio (depth-to-width ratio) h/ of the depth/z and width v of embedded metal line 1122W≥ l.After comprehensively considering the factor of technical effect and manufacture difficulty, the preferable range of embedded metal line depth-to-width ratio is: 2≤/ ^≤20 ^.
[0088] pinboard 1100 is equipped with another embedded metal line 11 24 extended into inside substrate 1110 from second surface 1112.Ratio (depth-to-width ratio)/z/ vv >=l of the depth A and width w of another embedded metal line 1124.After comprehensively considering the factor of technical effect and manufacture difficulty, the preferable range of embedded metal line depth-to-width ratio is: w≤20 2≤h I.Another embedded metal line 1124 is electrically connected by fourth hole 1115 and fifth hole 1116 with the realization of the first surface 1111 of lining 1110.
[0089] first through hole (the through substrate via that pinboard 1100 is equipped with, TSV being electrically connected for metal wire 1121 and the second surface 1112 on first surface 1111 is realized in) 1113 (813), the second through-hole 1114 (814)
[0090] metal wire 1121,1123 on first surface 1111, big depth-to-width ratio embedded metal line 1122, fourth hole 1115 can pass through the first convex block (bump) 1131 (631) or the first soldered ball (solder
Ball) 1132 (632) are electrically connected with other chips realization on pinboard.
[0091] as shown in figure 12, the substrate 1210 (610) of pinboard 1200 (600) has first surface 1211 (611) and second surface 1212 (612).The prior art can be used on first surface 1211 and form second insulating layer 12 42 (742) and the metal wire 1221 (621) in second insulating layer 1242,1223 (623).It is internal that embedded metal line 1222 (622) and another embedded metal line 1224 (1124) extend into substrate 1210 (610) from first surface 1211 (611) and second surface 1212 (612) respectively, it is full with conductive material filling, it is realized and is insulated by the first insulating layer 1241 (741) and substrate 1210 (610).Embedded metal line 122 2 and first surface 1211, which are realized, to be planarized.Second through-hole 1214 (814) is electrically connected metal wire 1221 and second surface 1212 (612), and fourth hole 1215 (1115) is electrically connected upper end and the first surface 1211 of another embedded metal line 1224 (1124).Second surface 1212 is externally provided with third insulating layer 1243 (943) and conductive gasket (pad) 1216 (916), and the second soldered ball or the second convex block 1251 (951) are formed on conductive gasket 1216.Other circuit devcies can be electrically connected by the conductive gasket 1216 of second surface and the second soldered ball or the second convex block 1251 with the realization of pinboard 1200.The substrate of HR-Si substrate or insulating materials (such as glass) composition for resistivity higher than 1000 Ω ^ η ι can not use the first insulating layer 1241 (741), second insulating layer 1242 (742) and third insulating layer 1243.
[0092] manufacturing method of the pinboard with big depth-to-width ratio embedded metal line of the invention, the following steps are included:
[0093] one, as shown in Figure 13-1, the first etching mask (etching mask) layer 1311 is formed by the prior art on substrate 1301.First etch mask layer is silicon oxide or silicon nitride dielectric material, can also have the metal material compared with high selectivity ratio, such as aluminium using to deep reaction ion etching.The thickness of first etch mask layer 1311 however be less than (being greater than) form big depth-to-width ratio embedded metal line depth ^ in the substrate needed for mask layer thickness.Such as depth/^ of embedded metal line is 60 microns, and substrate and the first etch mask layer select to compare as 100:1 in etching technics, then the thickness of the first etch mask layer needs to be not less than 0.6 micron of (being greater than).
[0094] two, as shown in Figure 13-2, by prior art spin coating photoresist (spin coating) and photoetching in the first etch mask layer, patterned photoresist 1312 is formed.The figure of photoresist 1312 is corresponding with the figure of embedded metal line and through-hole.
[0095] three, as shown in Figure 13-3, the first etch mask layer is etched by the prior art, forms patterned first etch mask layer 1313.Photoresist 1312 is removed later.Since the thickness of patterned first etch mask layer 1313 is usually smaller, so substrate face surface still maintains substantially flat.
[0096] four, as shown in Figure 13-4, patterned second etch mask layer 1314 is formed by the prior art, figure is corresponding with the figure of through-hole.Preferably the second etch mask layer 1314 uses the graphical photoresist of spin coating and photoetching and development.Second etch mask layer 1314 also can be used silica, silicon nitride or have the metal material compared with high selectivity ratio, such as aluminium to deep reaction ion etching, and is patterned by photoetching and etching.The material of second etch mask layer 1314 must be different from the material of the first etch mask layer 1311.Its thickness however be less than (being greater than) in the substrate formed depth/^-/^ needed for mask thickness, i.e. via depth/^ and embedded metal line depth/^ difference.Such as depth/^ of through-hole is 100 microns, embedded metal line depth is 60 microns, and substrate and the second etch mask layer 1314 select to compare as 50:1 in etching technics, then the thickness of the second etch mask layer 1314 was needed not less than 0.8 micron of (being greater than).
[0097] five, as shown in Figure 13-5, substrate is performed etching with the second etch mask layer 1314, deep reaction ion etching (Deep Reactive Ion Etching, DRIE) can be used, with the C of 60 sccm4F 8Make passivation layer deposition, uses the SF of 150 sccm6Mix the 0 of 15 sccm2And 10 sccm C4F 8
It is respectively 15 seconds and 10 seconds etchings and passivation step with the period between the radio-frequency power of 500W alternately inch, gradually etching groove to the depth needed, forms depth as A as etching gas2/ ^, shape first groove 1315 corresponding with through-hole.^ is the depth of embedded metal line, and/^ is the depth of through-hole, the i.e. thickness of pinboard substrate.
[0098] six, as shown in Figure 13-6, the second etch mask layer, the first etch mask layer of exposure are removed by the prior art.Since the second etch mask layer is different from the material that the first etch mask layer uses, it is possible to readily remove thickness of second etch mask layer 1314 without consuming the first etch mask layer excessively using dry or wet etch.For example, Oxygen plasma ashing (0 can be used when the second etch mask layer is photoresist and the first etch mask layer is silica inch2Plasma ashing) photoresist is removed without damaging silica.
[0099] seven, as shown in Figure 13-7, continue to perform etching substrate with the first etch mask layer, deep reaction ion etching (Deep Reactive Ion Etching, DRIE) can be used, with the C of 60 sccm4F 8Make passivation layer deposition, uses the SF of 150 sccm6Mix the 0 of 15 sccm2And 10 sccm C4F 8
It is respectively the etching of 15 seconds and 10 seconds with the period between the radio-frequency power of 500W alternately inch as etching gas
And passivation step, gradually the depth of etching groove to needs, etching depth are.Etching depth reaches A at first groove 1315 after the step2, through-hole 1316 is formed, the depth at embedded metal line 1317 reaches h, form second groove 1317.
[0100] eight, as shown in Figure 13-8, insulating layer 1318 is formed in 1316 side wall of through-hole, 1317 side wall of second groove and substrate surface, forms the silica of 0.1-4um using chemical vapor deposition, physical vapour deposition (PVD) or thermal oxide.Art methods are pressed later, such as are electroplated, with filling hole with metal 1316 and second groove 1317.Form the electric conductor (through-hole) and big depth-to-width ratio embedded metal line for being filled with metal in through-holes.
[0101] pinboard of the invention includes big depth-to-width ratio embedded metal line and through-hole with inch, use single side (single side) technique, it performs etching in the single side of substrate, metal filling and processing technology relevant to etching and metal filling, it realizes the big depth-to-width ratio embedded metal line of low cost manufacturing and through-hole, it is difficult to gluing (photoresist coating) and light last of the twelve Earthly Branches lj (photolithography) bring to avoid the big aspect ratio trench of substrate.
Industrial applicibility
[0102] pinboard in embodiment 1-3, in the region that first surface or second surface are not occupied by big depth-to-width ratio embedded metal line, it may include other active devices (active components) in semiconductor substrate, passive device (passive components), or the combination of active device and passive device, such as integrated circuit.
Claims (1)
- ClaimsA kind of pinboard with big depth-to-width ratio embedded metal line is equipped with metal wire on the substrate of pinboard, it is characterised in that: the metal wire insertion is arranged in substrate, and the depth of metal wire and the ratio of width of the insertion setting are not less than 1.Pinboard according to claim 1 with big depth-to-width ratio embedded metal line, it is characterised in that: the depth of the metal wire of the insertion setting and the ratio of width are as follows: ratio≤20 of 2≤depth and width.Pinboard according to claim 2 with big depth-to-width ratio embedded metal line, it is characterised in that: the depth of the metal wire of the insertion setting and the ratio of width are as follows: ratio > 3 of depth and width.Pinboard according to claim 3 with big depth-to-width ratio embedded metal line, it is characterised in that: the depth of the metal wire of the insertion setting and the ratio of width are as follows: ratio≤10 of 5≤depth and width.Pinboard according to claim 4 with big depth-to-width ratio embedded metal line, it is characterised in that: the depth of metal wire and the ratio of width of the insertion setting are 10.Pinboard according to claim 1 with big depth-to-width ratio embedded metal line, it is characterised in that: the metal wire insertion is arranged in the first surface of substrate.Pinboard according to claim 6 with big depth-to-width ratio embedded metal line, it is characterized by: the metal wire being arranged in the first surface of substrate that is embedded in is electrically connected through third through-hole realization with the second surface of substrate, the through-hole is the electric conductor that metal is filled in hole.Pinboard according to claim 1 with big depth-to-width ratio embedded metal line, it is characterised in that: the metal wire insertion is arranged in the second surface of substrate.Pinboard according to claim 7 with big depth-to-width ratio embedded metal line, it is characterized by: the metal wire being arranged in the second surface of substrate that is embedded in is electrically connected through fourth hole and fifth hole realization with the first surface of substrate, the through-hole is the electric conductor that metal is filled in hole.A kind of manufacturing method of the pinboard with big depth-to-width ratio embedded metal line, the substrate of pinboard is performed etching to be formed filling metallic conductor hole and insertion be arranged in substrate metal wire slot Then metal filling is carried out, it is characterized by: the etching is carried out in the single side of substrate, the hole of first etching filling metallic conductor, depth is the depth that the depth in the hole of filling metallic conductor subtracts the slot of filling metal wire, then the hole of filling metallic conductor and the slot of metal wire are etched with inch again, depth is the depth of embedded metal line.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2016/079122 WO2017177388A1 (en) | 2016-04-13 | 2016-04-13 | Interposer having embedded metal wires with high depth-to-width ratio and method for manufacturing same |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574337A (en) * | 2003-06-10 | 2005-02-02 | 株式会社东芝 | Semiconductor device and method of manufacturing the same |
| CN101578928A (en) * | 2007-02-28 | 2009-11-11 | 丰田自动车株式会社 | Circuit board and method for manufacturing the same |
| CN102856278A (en) * | 2012-09-17 | 2013-01-02 | 中国科学院微电子研究所 | Adapter plate structure and manufacturing method thereof |
| CN103681390A (en) * | 2013-12-20 | 2014-03-26 | 中国电子科技集团公司第五十八研究所 | TSV (Through Silicon Via) technology based preparation method for wafer level silicon substrate |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002217195A (en) * | 2001-01-17 | 2002-08-02 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| CN103367285B (en) * | 2013-07-26 | 2015-10-14 | 华进半导体封装先导技术研发中心有限公司 | A kind of through-hole structure and preparation method thereof |
-
2016
- 2016-04-13 WO PCT/CN2016/079122 patent/WO2017177388A1/en active Application Filing
- 2016-04-13 CN CN201680058415.1A patent/CN108475659A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574337A (en) * | 2003-06-10 | 2005-02-02 | 株式会社东芝 | Semiconductor device and method of manufacturing the same |
| CN101578928A (en) * | 2007-02-28 | 2009-11-11 | 丰田自动车株式会社 | Circuit board and method for manufacturing the same |
| CN102856278A (en) * | 2012-09-17 | 2013-01-02 | 中国科学院微电子研究所 | Adapter plate structure and manufacturing method thereof |
| CN103681390A (en) * | 2013-12-20 | 2014-03-26 | 中国电子科技集团公司第五十八研究所 | TSV (Through Silicon Via) technology based preparation method for wafer level silicon substrate |
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