CN108475231B

CN108475231B - Memory access method, device and system architecture

Info

Publication number: CN108475231B
Application number: CN201680070340.9A
Authority: CN
Inventors: 陈少杰; 杨伟; 赵俊峰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-01-27
Filing date: 2016-01-27
Publication date: 2021-01-05
Anticipated expiration: 2036-01-27
Also published as: WO2017128103A1; CN108475231A

Abstract

A memory access method, a device and a system architecture are provided, the memory access method comprises: receiving an access request of a target processing unit, wherein the access request carries a target identifier of a target memory unit to be accessed by the target processing unit; establishing a first wireless link between a first wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identifier; and controlling the target processing unit to utilize the first wireless link to receive and transmit the memory access request data with the target memory unit. The embodiment of the invention can realize the reconfigurable wireless link between the processing unit and the memory unit and reduce the routing complexity.

Description

Memory access method, device and system architecture

Technical Field

The present invention relates to the field of storage technologies, and in particular, to a method, an apparatus, and a system architecture for accessing a memory.

Background

In communication technologies, in order to facilitate data processing, a processing unit and a memory unit are integrated separately, for example, an on-chip architecture for large data high-speed concurrent application is to integrate the processing unit and the memory unit separately, the on-chip architecture is developed to an architecture of a micro many-core + shared memory 3D stack, and when each processor core runs a thread application, corresponding data is read from a corresponding memory block of the memory stack layer. A conventional 3D stacking architecture adopts a wired interconnection manner, as shown in fig. 1, the architecture includes a many-core Layer2, an exchange Layer1, and a memory stack Layer0, the many-core Layer includes a plurality of processor cores, the memory stack Layer includes a plurality of memory blocks, access data messages between the processor cores and the memory blocks are transmitted to corresponding layers through TSVs/TSIs in a vertical direction, and then transmitted to corresponding memory blocks or processor cores through 2D routing paths of the layers, the 2D routing paths are implemented by multi-hop node routing, wherein multi-port switch in a routing module of each hop node is switched to implement packet switching. The wired interconnection mode is fixed and can not be reconstructed, and the routing complexity is high.

Disclosure of Invention

Embodiments of the present invention provide a memory access method, apparatus, and system architecture, which can implement a reconfigurable wireless link between a processing unit and a memory unit, and reduce routing complexity.

A first aspect of the present invention provides a memory access method, including:

receiving an access request of a target processing unit, wherein the access request carries a target identifier of a target memory unit to be accessed by the target processing unit;

establishing a first wireless link between a first wireless transceiving antenna of a target processing unit and a second wireless transceiving antenna of a target memory unit identified by a target identification;

and controlling the target processing unit to transmit the access request data between the first wireless link and the target memory unit. In this way, each processing unit and each memory unit communicate with each other by establishing a wireless link, so that reconfiguration is possible, and communication between different processing units and memory units can be realized by establishing different wireless links, so that routing complexity is low.

Based on the first aspect, in a first possible implementation manner of the first aspect, before establishing the first wireless link between the first wireless transceiving antenna of the target processing unit and the second wireless transceiving antenna of the target memory unit identified by the target identifier, the method further includes:

judging whether the second wireless transceiving antenna is in the current radiation angle range of the first wireless transceiving antenna;

and if the second wireless transceiving antenna is not in the current radiation angle range of the first wireless transceiving antenna, adjusting the radiation direction of the first wireless transceiving antenna so that the second wireless transceiving antenna is in the radiation angle range of the first wireless transceiving antenna.

And if the second wireless transceiving antenna is in the current radiation angle range of the first wireless transceiving antenna, directly establishing a first wireless link between the first wireless transceiving antenna of the target processing unit and the second wireless transceiving antenna of the target memory unit identified by the target identifier. When the second wireless transceiving antenna of the target memory unit is not in the coverage range of the first wireless transceiving antenna of the target processing unit, the establishment of the first wireless link can be realized by inquiring the antenna beam angle and adjusting the radiation direction of the first wireless transceiving antenna of the target processing unit, so that the range of the memory unit which can be accessed by the target processing unit is enlarged.

Based on the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, before establishing a first wireless link between a first wireless transceiver antenna of the target processing unit and a second wireless transceiver antenna of the target memory unit identified by the target identifier, the method further includes:

selecting a first wireless transceiving antenna for the target processing unit from the at least two wireless transceiving antennas, and establishing connection between the first wireless transceiving antenna and the target processing unit.

Optionally, a first wireless transceiving antenna is selected for the target processing unit from at least two wireless transceiving antennas sharing an antenna pool, in this way, all processing units share one antenna pool, and when a certain target processing unit needs to transmit memory data, the first wireless transceiving antenna can be selected from the antenna pool, so that the purpose of improving the resource utilization rate is achieved by sharing resources.

Based on the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, selecting a first wtru from at least two wtrus includes:

acquiring the load of each wireless transceiving antenna in at least two wireless transceiving antennas in an antenna pool;

selecting the wireless transceiving antenna with the minimum load from the at least two wireless transceiving antennas as the first wireless transceiving antenna. By selecting the wireless transceiving antenna with the minimum load from the antenna pool as the first wireless transceiving antenna, the wireless transceiving antenna resource with the smaller load can be fully utilized, and the utilization rate of the antenna resource is improved.

Optionally, when the first wireless link between the first wireless transceiving antenna and the second wireless transceiving antenna is established, the first wireless link may be established between the first wireless transceiving antenna and the second wireless transceiving antenna in the target time slot by using a time division multiplexing method.

Based on the first aspect, or the first possible implementation manner of the first aspect, or the second possible implementation manner of the first aspect, or the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, if the load of the first wireless transceiving antenna is greater than a preset first threshold, the method further includes:

selecting a third wireless transceiving antenna for the target processing unit from the at least two wireless transceiving antennas, and establishing the connection between the target processing unit and the third wireless transceiving antenna;

establishing a second wireless link between a third wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identifier;

and controlling the target processing unit to transmit the access request data between the second wireless link and the target memory unit. In this way, when the load of the first wireless transceiving antenna is greater than the preset first threshold, the third wireless transceiving antenna is selected from the antenna pool for the target processing unit, and the second wireless link between the third wireless transceiving antenna and the second wireless transceiving antenna is established, so that the target processing unit can receive and transmit access request data between the first wireless link and the target memory unit through the second wireless link and the target memory unit, the overload phenomenon of the first wireless transceiving antenna is reduced, the packet loss rate is reduced, the utilization rate of idle antennas is improved, and the bandwidth of each wireless transceiving antenna is balanced.

Optionally, the determining whether the load of the first wireless transceiving antenna is greater than a preset first threshold includes:

acquiring the load data volume of each historical time slice in at least one historical time slice nearest to the current moment of the first wireless transceiving antenna;

judging whether the load data volume of the first wireless transceiving antenna of each historical time slice exceeds a preset first threshold value; or, judging whether the load data amount of each historical time slice in the historical time slices with the number exceeding the preset number is larger than a preset first threshold value or not;

if yes, determining that the load of the first wireless transceiving antenna is larger than a preset first threshold value. The method predicts the load of the first wireless transceiving antenna at the current moment by counting the load data amount of the first wireless transceiving antenna in at least one historical time slice, thereby determining whether to allocate a third wireless transceiving antenna for the target processing unit, and the prediction method is accurate.

Based on the first aspect or the first possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, the processing unit corresponds to the wireless transceiving antennas one to one, and if a load of the first wireless transceiving antenna is greater than a preset first threshold, the method further includes:

establishing a connection relation between the target processing unit and the auxiliary processing unit, and establishing a third wireless link between a fourth wireless transceiving antenna and a second wireless transceiving antenna of the auxiliary processing unit;

and the control target processing unit utilizes the third wireless link to transmit the access request data with the target memory unit. In this way, it is further limited that in a scenario where the processing unit and the wireless transceiving antennas are in one-to-one correspondence, if the load of the first wireless transceiving antenna is greater than a preset first threshold, the target processing unit establishes a third wireless link with the second wireless transceiving antenna by using a fourth wireless transceiving antenna of the auxiliary processing unit, so as to reduce the load of the first wireless transceiving antenna and balance the load data amount of each wireless transceiving antenna.

Optionally, the selecting manner of the auxiliary processing unit may include:

acquiring the loads of all processing units, and taking the processing unit with the minimum load as an auxiliary processing unit; alternatively, the first and second electrodes may be,

and acquiring the antenna loads of all the processing units, and taking the processing unit with the minimum antenna load as an auxiliary processing unit.

A second aspect of the present invention provides a memory access device, including:

the receiving module is used for receiving an access request of the target processing unit, wherein the access request carries a target identifier of a target memory unit to be accessed by the target processing unit;

the system comprises an establishing module, a first wireless link, a second wireless transceiving module and a first wireless link, wherein the establishing module is used for establishing a first wireless link between a first wireless transceiving antenna of a target processing unit and a second wireless transceiving antenna of a target memory unit identified by a target identifier;

and the control module is used for controlling the target processing unit to transmit the access request data between the first wireless link and the target memory unit. In this way, each processing unit and each memory unit communicate with each other by establishing a wireless link, so that reconfiguration is possible, and communication between different processing units and memory units can be realized by establishing different wireless links, so that routing complexity is low.

In a first possible implementation manner of the second aspect, based on the second aspect, the apparatus further includes:

the judging module is used for judging whether the second wireless transceiving antenna is in the current radiation angle range of the first wireless transceiving antenna;

and the adjusting module is used for adjusting the radiation direction of the first wireless transceiving antenna if the second wireless transceiving antenna is not in the current radiation angle range of the first wireless transceiving antenna, so that the second wireless transceiving antenna is in the radiation angle range of the first wireless transceiving antenna.

In a second possible implementation manner of the second aspect, based on the second aspect or the first possible implementation manner of the second aspect, the apparatus further includes:

the first selecting module is used for selecting a first wireless transceiving antenna for the target processing unit from the at least two wireless transceiving antennas and establishing the connection between the first wireless transceiving antenna and the target processing unit.

Based on the second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the first selecting module is specifically configured to obtain a load of each of at least two wireless transceiving antennas in an antenna pool; and selecting the wireless transceiving antenna with the minimum load from the at least two wireless transceiving antennas as the first wireless transceiving antenna. In the mode, the wireless transceiving antenna with the minimum load is selected from the antenna pool as the first wireless transceiving antenna, so that the wireless transceiving antenna resource with the smaller load can be fully utilized, and the utilization rate of the antenna resource is improved.

Based on the second aspect, or the first possible implementation manner of the second aspect, or the second possible implementation manner of the second aspect, or the third possible implementation manner of the second aspect, in a fourth possible implementation manner of the second aspect, if the load of the first transceiver antenna is greater than a preset first threshold, the apparatus further includes:

the second selection module is used for selecting a third wireless transceiving antenna for the target processing unit from the at least two wireless transceiving antennas;

the establishing module is further configured to establish a connection between the target processing unit and the third wireless transceiver antenna, and establish a second wireless link between the third wireless transceiver antenna of the target processing unit and a second wireless transceiver antenna of the target memory unit identified by the target identifier;

the control module is also used for controlling the target processing unit to transmit the access request data between the second wireless link and the target memory unit. In this way, when the load of the first wireless transceiving antenna is greater than the preset first threshold, the third wireless transceiving antenna is selected from the antenna pool for the target processing unit, and the second wireless link between the third wireless transceiving antenna and the second wireless transceiving antenna is established, so that the target processing unit can receive and transmit access request data between the first wireless link and the target memory unit through the second wireless link and the target memory unit, the overload phenomenon of the first wireless transceiving antenna is reduced, the packet loss rate is reduced, the utilization rate of idle antennas is improved, and the bandwidth of each wireless transceiving antenna is balanced.

Based on the second aspect or the first possible implementation manner of the second aspect, in a fifth possible implementation manner of the second aspect, the processing units correspond to the transceivers one to one, and if the load of the first transceiver is greater than a preset first threshold, the apparatus further includes,

the establishing module is further used for establishing a connection relationship between the target processing unit and the auxiliary processing unit and establishing a third wireless link between a fourth wireless transceiving antenna and a second wireless transceiving antenna of the auxiliary processing unit;

the control module is also used for controlling the target processing unit to transmit the access request data between the third wireless link and the target memory unit. In this way, it is further limited that in a scenario where the processing unit and the wireless transceiving antennas are in one-to-one correspondence, if the load of the first wireless transceiving antenna is greater than a preset first threshold, the target processing unit establishes a third wireless link with the second wireless transceiving antenna by using a fourth wireless transceiving antenna of the auxiliary processing unit, so as to reduce the load of the first wireless transceiving antenna and balance the load data amount of each wireless transceiving antenna.

Optionally, the selecting manner of the auxiliary processing unit may include:

A third aspect of the present invention provides a memory access system architecture, where the system architecture includes a many-core layer and a memory stack layer, where the many-core layer and the memory stack layer communicate with each other through a wireless signal, the many-core layer includes at least two processing units and a global memory controller, and the memory stack layer includes at least two memory units;

the global memory controller receives an access request of a target processing unit, wherein the access request carries a target identifier of a target memory unit to be accessed by the target processing unit;

the global memory controller establishes a wireless link between the wireless transceiving antenna of the target processing unit and the wireless transceiving antenna of the target memory unit identified by the target identification;

the global memory controller controls the target processing unit to transmit the memory access request data between the wireless link and the target memory unit. In this way, each processing unit and each memory unit communicate with each other by establishing a wireless link, so that reconfiguration is possible, and communication between different processing units and memory units can be realized by establishing different wireless links, so that routing complexity is low.

A fourth aspect of the present invention provides a readable medium, which includes an execution instruction, and when the execution instruction is executed by a memory controller, the memory controller may perform any one of the possible embodiments of the first aspect.

A fifth aspect of the present invention provides a memory controller, comprising a processor, a memory, and a bus;

the memory is used for storing execution instructions, and the processor is connected with the memory through a bus, and when the memory controller runs, the processor executes the execution instructions stored in the memory, so that the memory controller executes any one of the possible implementation manners of the first aspect.

In the embodiment of the invention, an access request of a target processing unit is received, the access request carries a target identifier of a target memory unit to be accessed by the target processing unit, a first wireless link between a first wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identifier is established, and the target processing unit is controlled to transmit access request data between the first wireless link and the target memory unit.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a diagram illustrating an on-chip architecture according to the prior art according to an embodiment of the present invention;

fig. 2 is a schematic flowchart of a memory access method according to an embodiment of the present invention;

fig. 3 is a schematic flowchart of another memory access method according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a reconfigurable on-chip architecture according to an embodiment of the present invention;

fig. 5 is a schematic diagram illustrating an establishment of a wireless link between a processing unit and a wireless transceiver antenna of a memory unit according to an embodiment of the present invention;

fig. 6 is a schematic diagram illustrating an establishment of a wireless link between a processing unit and a wireless transceiver antenna of a memory unit according to another embodiment of the present invention;

fig. 7 is a schematic diagram of an internal structure of an on-chip architecture according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a memory access density according to an embodiment of the present invention;

fig. 9 is a schematic diagram illustrating sparse memory access according to an embodiment of the present invention;

FIG. 10 is a diagram illustrating a comparison of four memory accesses provided by the present invention;

fig. 11 is a schematic structural diagram of a memory access device according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of another memory controller according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention.

The wireless transceiving antennas (e.g., the first wireless transceiving antenna, the second wireless transceiving antenna, the third wireless transceiving antenna, and the fourth wireless transceiving antenna) in the embodiments of the present invention may be one antenna or an antenna array.

In an embodiment of the present invention, in an optional implementation manner, the wireless transceiving antennas of the processing unit may exist in an antenna pool, that is, a plurality of wireless transceiving antennas in the antenna pool are shared by all processing units, and when the target processing unit needs to access the target memory unit, the first wireless transceiving antenna is selected from the shared antenna pool to perform communication. In another optional implementation, the processing units and the wireless transceiving antennas may be in a one-to-one correspondence relationship, that is, one processing unit is provided with one wireless transceiving antenna, and when the target processing unit needs to access the target memory unit, the first wireless transceiving antenna of the target processing unit is used for communication.

Optionally, the memory access method according to the embodiment of the present invention may be applied to a many-core-shared memory 3D integrated on-chip architecture, where the on-chip architecture includes a many-core layer and a memory stack layer, the many-core layer includes a plurality of processing units (e.g., a processor core) and a global memory controller, the memory stack layer includes a plurality of memory units (e.g., a memory block RAM Cluster), and the many-core layer and the memory stack layer communicate with each other through a wireless signal. The global memory controller is mainly used for scheduling the establishment and deletion of wireless links between the wireless transceiving antennas of each processing unit and the wireless transceiving antennas of each memory unit, so that the transceiving of access data between any processing unit and any memory unit can be realized through the wireless links, the reconfigurability is strong, the routing complexity is low, and the point-to-point data transmission is realized, so the time delay is small.

Optionally, the memory access method according to the embodiment of the present invention may also be applied to a single board machine frame, where the single board machine frame includes a rack, an upper frame of the rack includes multiple processing units (e.g., processors or processor cores), a lower frame of the rack includes multiple memory units (e.g., memory banks), and a wireless link between a wireless transceiver antenna of each processing unit and a wireless transceiver antenna of each memory unit is established through the wireless transceiver antenna of each processing unit, so as to implement transceiving of access data between each processing unit and a corresponding memory unit through the wireless link.

It should be noted that the applicable scenarios of the memory access method of the present embodiment include, but are not limited to, the two scenarios described above, which are only examples.

Referring to fig. 2, a schematic flow chart of a memory access method according to an embodiment of the present invention is shown, where the memory access method according to the present embodiment includes steps S200 to S202;

s200, receiving an access request of a target processing unit, wherein the access request carries a target identifier of a target memory unit to be accessed by the target processing unit;

in this embodiment of the present invention, the target Processing Unit may be a processor or a processor core, and the processor may include a Central Processing Unit (CPU), an image processor, and the like, which are not limited herein. The present invention is not limited to the existence form of the target processing unit. The target processing unit may run various applications and various threads, and the target processing unit may read data from or store data to any one of the target memory units in the memory stack layer. The target memory unit may be a memory block or a memory bank of a memory stack layer, which is not limited herein.

In this embodiment, the target processing unit is provided with a wireless transceiving antenna and a wireless transceiving circuit, and the target memory unit is also provided with a wireless transceiving antenna and a wireless transceiving circuit, as shown in fig. 5, which is an enlarged view of the target processing unit and the target memory unit provided in the embodiment of the present invention. For each memory block, firstly, a signal sent by a target processor core through a wireless transceiving antenna of the memory block is received, then the received signal is demodulated through a demodulation circuit, so that memory access request data of the target processor core are obtained, finally, corresponding response data are returned for the memory access data, and the return of the response data is also sent through the wireless transceiving antenna of the memory block.

It should be noted that, as shown in fig. 5, the transmission of the access request data between each processor core and each memory block is based on a wireless link established between the processor core and the memory block, and when the target processor core needs to access the target memory block, a first wireless link between the target processor core and the target memory block needs to be established in advance. And transmitting the memory access request data based on the first wireless link, so that each processor core can establish a wireless link with any memory block to realize point-to-point communication.

As shown in fig. 6, an enlarged view of another target processing unit and a target memory unit provided in the embodiment of the present invention is different from fig. 5 in that each processor core in fig. 6 does not correspond to a wireless transceiving antenna one by one, but all processor cores share one antenna pool, the shared antenna pool is connected to the processor cores through a switching network, and any processor core can transmit access request data between any wireless transceiving antenna in the antenna pool and the memory unit. Note that the circuit configuration of each radio transmitting/receiving antenna in the antenna pool is the same as that in fig. 5.

In this embodiment, when the target processing unit accesses the target memory unit in advance, an access request is sent to the global memory controller, where the access request carries a target identifier of the target memory unit, and the global memory controller establishes and schedules a wireless link according to the access request. As shown in fig. 4, which is a memory access system architecture diagram provided in an embodiment of the present invention, a global memory controller performs a wireless link configuration, and any processing unit (processor core) in a many-core layer can access any memory block in a memory stack layer, and when the global memory controller receives an access request from a target processor core, the global memory controller establishes and schedules a wireless link according to a target identifier of the target memory block in the access request.

S201, establishing a first wireless link between a first wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identifier;

in the embodiment of the invention, the processing units of each layer in the memory access system architecture are integrated with the wireless transceiving antennas and circuits, the memory units of each layer are also integrated with the wireless transceiving antennas and circuits, interlayer communication is carried out in a wireless mode through the antenna array, and the direction of a link is changed through wave speed scanning of the antenna array to form a reconfigurable wireless link, so that each processing unit can directly access a plurality of adjacent memory units, and the routing complexity is greatly simplified.

The global memory controller establishes a first wireless link between a first wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identifier, and it should be noted that, generally, the current radiation angle range of the first wireless transceiving antenna of the target processing unit is limited, so it is necessary to further determine whether the second wireless transceiving antenna of the target memory unit is within the current radiation angle range of the first wireless transceiving antenna of the target processing unit.

Therefore, before establishing the first wireless link between the first wireless transceiving antenna of the target processing unit and the second wireless transceiving antenna of the target memory unit, steps S20-S21 may be further included;

s20, judging whether the second wireless transceiving antenna is in the current radiation angle range of the first wireless transceiving antenna;

in an embodiment of the present invention, a current radiation angle range of the first wireless transceiving antenna of the target processing unit may include a plurality of memory units, and the plurality of memory units may be all memory units of the system architecture or may be some memory units of all memory units of the system architecture. The wireless link may be established only when the wireless transceiving antenna of the memory unit is within the current radiation angle range of the processing unit, and therefore, a determination is required before establishing the first wireless link between the first wireless transceiving antenna and the second wireless transceiving antenna.

Specifically, optionally, the determining manner may be that the global memory controller queries whether the second wireless transceiving antenna of the target memory unit identified by the target identifier is within the current radiation angle range of the first wireless transceiving antenna of the target processing unit, and the memory units of the wireless transceiving antennas of each processing unit within various radiation angle ranges are stored in the system architecture.

S21, if the second wireless transceiving antenna is not within the current radiation angle range of the first wireless transceiving antenna, adjusting the radiation direction of the first wireless transceiving antenna so that the second wireless transceiving antenna is within the radiation angle range of the first wireless transceiving antenna.

In this embodiment of the present invention, if the second wireless transceiving antenna of the target memory unit identified by the target identifier is not within the current radiation angle range of the first wireless transceiving antenna of the target processing unit, it indicates that the target processing unit cannot directly access the target memory unit, and queries the antenna beam angle and the transmission power between the first wireless transceiving antenna of the target processing unit and the second wireless transceiving antenna of the target memory unit.

The global memory controller informs the antenna array beam forming unit to adjust the radiation direction of the first wireless transceiving antenna of the target processing unit and adjusts the radiation direction to the inquired antenna beam angle, so that the second wireless transceiving antenna is in the radiation angle range of the first wireless transceiving antenna, and simultaneously, the global memory controller informs the transmitter to adjust the transmission power of the first wireless transceiving antenna of the target processing unit, and a first wireless link between the first wireless transceiving antenna of the target processing unit and the second wireless transceiving antenna of the target memory unit is established by using the adjusted first wireless transceiving antenna of the target processing unit.

Optionally, if the second wireless transceiving antenna of the target memory unit identified by the target identifier is within the current radiation angle range of the first wireless transceiving antenna of the target processing unit, the first wireless link between the first wireless transceiving antenna of the target processing unit and the second wireless transceiving antenna of the target memory unit may be directly established.

S202, controlling the target processing unit to utilize the first wireless link to transmit the access request data with the target memory unit.

In the embodiment of the invention, the global memory controller controls the target processing unit to transmit the access data between the target memory unit and the established first wireless link. It should be noted that, before the target processing unit and the target memory unit perform access request data transmission, the global memory controller starts the wireless memory initialization training, and after the training is completed, the channel is successfully established. The global memory controller controls the target processing unit to send access request data to the target memory unit through the first wireless link, and the target memory unit executes the access request and returns data or response which needs to be read by the target processing unit. Furthermore, the global memory controller judges whether the first wireless link needs to be closed according to the access frequency of the target memory unit in the historical time slice, so that the energy consumption is reduced.

Optionally, if the load of the first wtru is greater than the preset first threshold, in order to balance the bandwidths of the wtrus, the method may further include the following steps S203-S205, or the method may further include the following steps S206-S207; steps S203 to S205 are proposed balancing strategies for the scenario of sharing the antenna pool shown in fig. 6, and steps S206 to S207 are proposed balancing strategies for the scenario of one-to-one correspondence between the processing units and the wireless transceiving antennas shown in fig. 5.

It should be noted that the method for determining whether the load of the first wireless transceiving antenna is greater than the preset first threshold may include the following steps:

step one, acquiring the load data volume of each historical time slice of at least one historical time slice nearest to the current time of the first wireless transceiving antenna;

in the embodiment of the present invention, the load data amount of the first wireless transceiving antenna is a data amount of the memory access request data transmission between the first wireless transceiving antenna and the memory unit. The global memory controller obtains the load data volume of the first wireless transceiving antenna in each historical time slice in at least one historical time slice nearest to the current time. Optionally, the load data amount of each wireless transceiving antenna may be monitored by a third party, and the global memory controller may directly obtain the load data amount of each historical time slice of the first wireless transceiving antenna in the at least one historical time slice from the third party. Fig. 8 is a statistical chart of load data amounts of the wtrus 1 to 4 in the historical time slices T1 to T6, which are obtained by the global local memory controller according to the embodiment of the present invention. The first transceiver antenna may be any one of the transceiver antennas 1 to 4.

Step two, judging whether the load data volume of the first wireless transceiving antenna in each historical time slice exceeds a first preset threshold value; or the load data amount of each historical time slice in the historical time slices of which the number exceeds the preset number in the at least one historical time slice by the first wireless transceiving antenna is larger than a preset first threshold value.

In the embodiment of the present invention, the global memory controller determines whether the load data amount of the first wireless transceiving antenna in each counted historical time slice exceeds a preset first threshold, and as shown in fig. 8, the load data amount of the first wireless transceiving antenna in the four historical time slices T3 to T6 may be selected to be counted for determination. As shown in the figure, if the first wtru is the second wtru or the third wtru, the load data amount of the first wtru in the historical time slices T3-T6 is greater than the preset first threshold.

It should be noted that, in the determination process, it is not necessary that the load data amount of the first wtru antenna of each historical time slice in all the historical time slices is greater than the preset first threshold, for example, as long as the load data amount of the first wtru antenna of each historical time slice in the historical time slices exceeding the preset number is greater than the preset first threshold, for example, counting 4 historical time slices, it is possible to determine that the load of the first wtru antenna is greater than the preset first threshold as long as the load data amount of the first wtru antenna of 3 historical time slices is greater than the preset first threshold.

It should be understood that the manner of determining whether the load of the first wtru is greater than the preset first threshold is various, and the embodiment of the present invention is not limited thereto.

In an alternative embodiment, steps S203-S205 are included;

s203, selecting a third wireless transceiving antenna from the at least two wireless transceiving antennas for the target processing unit, and establishing the connection between the target processing unit and the third wireless transceiving antenna;

in the embodiment of the present invention, if the load of the first wireless transceiving antenna of the target processing unit is greater than the preset first threshold, in order to reduce the bandwidth of the first wtru of the target processing unit and balance the bandwidth of each wtru, the global memory controller schedules all wtrus, selects a third wtru from at least two wtrus in the antenna pool for the target processing unit, as shown in fig. 6, for example, the processing unit is taken as a processor core, all the processor cores share a wireless transceiving antenna in an antenna pool, when the load of the first wireless transceiving antenna of the target processing unit is larger than a preset first threshold value, the global memory controller selects a third wireless transceiving antenna for the target processing unit from the shared antenna pool, and establishing connection between the third wireless transceiving antenna and the target memory unit through a switching network.

It should be noted that the criteria for selecting the third wtru may include a plurality of criteria, for example, an idle antenna may be selected from the shared antenna pool as the third wtru, an antenna with less access request data sent or received in a plurality of recent historical time slices may be selected, or an antenna with less current load may be selected as the third wtru, and the like, which is not limited herein.

S204, establishing a second wireless link between a third wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identifier;

in the embodiment of the present invention, the global memory controller establishes the second wireless link between the third wireless transceiving antenna and the second wireless transceiving antenna of the target memory unit, it should be noted that, when establishing the second wireless link between the third wireless transceiving antenna and the second wireless transceiving antenna of the target memory unit, it is also necessary to determine whether the second wireless transceiving antenna is within the current radiation angle range of the third wireless transceiving antenna, so as to adopt different wireless link establishment manners, and the specific establishment manner may refer to the establishment manner of the first wireless link between the first wireless transceiving antenna of the target processing unit and the second wireless transceiving antenna of the target memory unit, which is not described herein again.

S205, controlling the target processing unit to transmit the access request data between the second wireless link and the target memory unit.

In the embodiment of the invention, the global memory controller controls the target processing unit to transmit the access request data between the second wireless link and the target memory unit. It should be noted that, the memory access request data may be transmitted between the first wireless link and the second wireless link and the target memory unit in a frequency division multiplexing manner, and the second wireless transceiver antenna of the target memory unit is an omnidirectional antenna, so that the memory access request data of each wireless link may be received at the same time. And finally acquiring the memory access request data by a second wireless transceiving antenna of the target memory unit in a Frequency Division Multiplexing (FDM) mode.

In another alternative embodiment, steps S206-S207 are included;

s206, establishing a connection relation between the target processing unit and the auxiliary processing unit, and establishing a third wireless link between a fourth wireless transceiving antenna of the auxiliary processing unit and the second wireless transceiving antenna;

in the embodiment of the present invention, the processing units and the wireless transceiving antennas are in one-to-one correspondence, as shown in fig. 5, that is, in a scenario where the processing units and the wireless transceiving antennas are in one-to-one correspondence. When the load of the first wireless transceiving antenna of the target processing unit is greater than the preset first threshold, the auxiliary processing unit needs to be selected, and a connection relationship between the target processing unit and the auxiliary processing unit is established. For example, the processing unit with the minimum load among all the processing units may be selected as the auxiliary processing unit, or the processing unit with the minimum load of the wireless transmitting and receiving antenna among all the processing units may be obtained first, and the processing unit with the minimum load of the wireless transmitting and receiving antenna may be used as the auxiliary processing unit. The processing unit and the auxiliary processing unit can communicate with each other to complete the routing of the access request data.

Further, a third wireless link between a fourth wireless transceiving antenna and a second wireless transceiving antenna of the auxiliary processing unit is established, and specifically, optionally, as shown in fig. 7, which is a architecture diagram of a many-core-shared memory 3D integrated system provided in the embodiment of the present invention, as shown in the figure, the processing unit is a processor core, the memory unit is a memory block, and the diagram includes eight processor cores and eight memory blocks, as shown in the figure, a routing path also exists between the processor cores, and a connection relationship can be established, the global memory controller implements dynamic scheduling of wireless link bandwidth resources, memory access data of each processor core is scheduled to different channels after being processed by an address decoder, a data queue and a request queue of the global memory controller, and one channel corresponds to a wireless transceiving antenna of one processor core, as shown in the figure, assuming that the processor core3 is a target processing unit, the memory block 1 is a target memory unit, and the load of the wireless transceiving antennas of the processor core3 in recent historical time slices is greater than a preset first threshold, the processor core1 and the processor core2 can be selected as auxiliary processor cores, the wireless transceiving antennas of the processor core1 and the processor core2 are used as a fourth wireless transceiving antenna, and a third wireless link between the fourth wireless transceiving antenna and the memory block 1 is established, that is, the high bandwidth requirement is met through channel combination.

And S207, controlling the target processing unit to transmit the access request data between the third wireless link and the target memory unit.

In the embodiment of the present invention, the control target processing unit utilizes the third wireless link to transmit the memory access request data to the target memory unit, and it should be noted that the memory access request data may be transmitted between the first wireless link and the third wireless link in a frequency division multiplexing manner.

Further optionally, the embodiment of the present invention may further achieve the purpose of improving the low bandwidth utilization rate by splitting a single channel of the wireless transceiving antenna, for example, if some memory units have sparse access, one wireless transceiving antenna may be split into channels. Specifically, optionally, taking the target memory unit as an example for description, the global memory controller determines whether the access frequency of each of the several recent historical time slices of the target memory unit is lower than a preset threshold, where the preset threshold may be set according to an actual situation, as shown in fig. 9, the access frequency of each of the historical time slices of the memory block 2 and the memory block 3 is relatively small, and the access is relatively sparse. If the target memory unit is the memory block 2 or the memory block 3, the target memory unit belongs to a memory unit with sparse access, and further, a spare memory unit which is adjacent to the target memory unit and has sparse access is selected.

Specifically, as shown in fig. 7, assuming that the target processing unit is a processor core7, the target memory unit is a memory block 6, and the number of accesses of the memory block 6 in the latest historical time slice is relatively small, in order to improve the bandwidth utilization rate of the wireless transceiver antenna of the processor core7, in this embodiment, the memory blocks 5 and 7 that are adjacent to the memory block 6 and have relatively sparse accesses are selected as the candidate memory blocks.

In the embodiment of the present invention, the single-channel splitting of the first wireless transceiving antenna of the target processing unit is performed to improve the low bandwidth utilization rate, and the specific splitting manner may be that transmission of access request data is performed between different independent time slots and different memory units through transmission beam scanning of the wireless transceiving antenna of the target processing unit, and a first wireless link between the first wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit is established in the target time slot. Specifically, optionally, as shown in fig. 7, the wireless transceiving antenna of the processor core7 performs transmission of the access request data with the memory blocks 5 to 7 in different time slots, respectively, where in one time slot, a wireless link is established between the wireless transceiving antenna of the processor core7 and one memory block for communication.

The first wireless transceiving antenna of the target processing unit may also communicate with different memory units by splitting the antenna array (each sub-antenna array disperses the directivity).

Referring to fig. 3, a schematic flow chart of another memory access method according to an embodiment of the present invention is shown, where the memory access method according to the embodiment includes:

s300, receiving an access request of a target processing unit, wherein the access request carries a target identifier of a target memory unit to be accessed by the target processing unit;

step S300 according to the embodiment of the present invention please refer to step S200 according to the embodiment of fig. 2, which is not described herein again.

S301, selecting the first wireless transceiving antenna from at least two wireless transceiving antennas for the target processing unit, and establishing a connection between the first wireless transceiving antenna and the target processing unit.

In the embodiment of the present invention, all processing units share an antenna pool, the antenna pool includes a plurality of wireless transceiving antennas, and when a target processing unit needs to access a target memory unit, a first wireless transceiving antenna is selected for the target processing unit from at least two wireless transceiving antennas in the shared antenna pool, and a connection between the first wireless transceiving antenna and the target processing unit is established. It should be noted that, there may be various selection manners for selecting the first wtru from the shared antenna pool, for example, a free antenna may be selected from the shared antenna pool as the first wtru, or an antenna with the smallest load may be selected from the shared antenna pool as the first wtru, or one wtru may be randomly selected from a plurality of wtrus with loads lower than a certain threshold as the first wtru, and the selection manner is not limited herein.

Optionally, the selecting the first wireless transceiving antenna for the target processing unit from the at least two wireless transceiving antennas includes the following two steps:

the method comprises the following steps that firstly, the load of each wireless transceiving antenna in at least two wireless transceiving antennas is obtained;

and step two, selecting the first wireless transceiving antenna with the minimum load from the at least two wireless transceiving antennas.

In a specific embodiment, an antenna with the smallest load is selected from a plurality of wireless transceiving antennas of an antenna pool as a first wireless transceiving antenna, the first wireless transceiving antenna carries transmission of other access request data, and simultaneously carries transmission of the access request data between a target memory unit and the target processing unit, and the other access request data may be access request data of the other processing unit to the target memory unit or access request data of the other processing unit to the target memory unit. If the other processing unit does not send the access request data of the target memory unit, the embodiment may route the access request data of the other processing unit to the target processing unit, and control the first wireless transceiving antenna of the target processing unit to transmit different access request data with different memory units in a time division multiplexing manner.

S302, establishing a first wireless link between a first wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identifier;

and S303, controlling the target processing unit to transmit the access request data between the first wireless link and the target memory unit.

Referring to steps S201 to S202 of fig. 2, steps S302 to S303 of the embodiment of the present invention are not described herein again.

Referring to fig. 11, a schematic structural diagram of a memory access device according to an embodiment of the present invention is shown, where the memory access device according to the embodiment of the present invention includes:

a receiving module 100, configured to receive an access request of a target processing unit, where the access request carries a target identifier of a target memory unit to be accessed by the target processing unit;

an establishing module 101, configured to establish a first wireless link between a first wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identifier;

a control module 102, configured to control the target processing unit to perform transmission of access request data between the target memory unit and the first wireless link.

Optionally, the apparatus may further include a determining module 103 and an adjusting module 104;

a judging module 103, configured to judge whether the second wireless transceiving antenna is within a current radiation angle range of the first wireless transceiving antenna;

an adjusting module 104, configured to adjust a radiation direction of the first wireless transceiving antenna if the second wireless transceiving antenna is not within the current radiation angle range of the first wireless transceiving antenna, so that the second wireless transceiving antenna is within the radiation angle range of the first wireless transceiving antenna.

Optionally, the apparatus may further include a first selecting module 105;

a first selecting module 105, configured to select the first wireless transceiving antenna for the target processing unit from at least two wireless transceiving antennas, and establish a connection between the first wireless transceiving antenna and the target processing unit.

Specifically, optionally, the first selecting module 105 is specifically configured to obtain a load of each of at least two wireless transceiving antennas; and selecting the first wireless transceiving antenna with the minimum load from the at least two wireless transceiving antennas.

Optionally, all the processing units share an antenna pool, where the antenna pool includes at least two wireless transceiving antennas, and if the load of the first wireless transceiving antenna is greater than a preset first threshold, the apparatus further includes a second selecting module 106;

a second selecting module 106, configured to select a third wtru from the at least two wtrus;

the establishing module 101 is further configured to establish a connection between the target processing unit and the third wireless transceiver antenna, and establish a second wireless link between the third wireless transceiver antenna of the target processing unit and the second wireless transceiver antenna of the target memory unit identified by the target identifier;

the control module 102 is further configured to control the target processing unit to perform transmission of access request data with the target memory unit by using the second wireless link.

Optionally, if the processing unit corresponds to the wireless transceiving antennas one to one, if the load of the first wireless transceiving antenna is greater than a preset first threshold, the establishing module 101 is further configured to establish a connection relationship between the target processing unit and the auxiliary processing unit, and establish a third wireless link between a fourth wireless transceiving antenna of the auxiliary processing unit and the second wireless transceiving antenna;

the control module 102 is further configured to control the target processing unit to perform transmission of access request data with the target memory unit by using the third wireless link.

It is to be understood that, the specific implementation manner of each module and unit in the memory access device may further refer to the related description in the method embodiment.

Referring to fig. 12, which is a schematic structural diagram of a memory controller according to an embodiment of the present invention, as shown in the figure, the memory controller 40 includes a processor 401, a memory 402 and a bus 403, the processor 401 and the memory 402 are both connected to the bus 403, the memory is used for storing an execution instruction, and the processor 401 calls the execution instruction stored in the memory 402:

a processor 401, configured to receive an access request of a target processing unit, where the access request carries a target identifier of a target memory unit to be accessed by the target processing unit;

the processor 401 is further configured to establish a first wireless link between a first wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identifier;

the processor 401 is further configured to control the target processing unit to perform transmission of access request data with the target memory unit by using the first wireless link.

Optionally, before the first wireless link between the first wireless transceiving antenna of the target processing unit and the second wireless transceiving antenna of the target memory unit identified by the target identifier is established;

the processor 401 is further configured to determine whether the second wtru is within the current radiation angle range of the first wtru;

if the second wireless transceiving antenna is not in the current radiation angle range of the first wireless transceiving antenna, adjusting the radiation direction of the first wireless transceiving antenna so as to enable the second wireless transceiving antenna to be in the radiation angle range of the first wireless transceiving antenna.

The processor 401 is further configured to select the first wireless transceiving antenna from the at least two wireless transceiving antennas for the target processing unit, and establish a connection between the first wireless transceiving antenna and the target processing unit.

Optionally, the selecting the first wireless transceiving antenna for the target processing unit from the at least two wireless transceiving antennas includes:

the processor 401 is further configured to obtain a load of each of the at least two wireless transceiving antennas;

the processor 401 is further configured to select the first wtru with the smallest load from the at least two wtrus.

If the load of the first wireless transceiving antenna is larger than a preset first threshold value;

the processor 401 is further configured to select a third wireless transceiving antenna for the target processing unit from the at least two wireless transceiving antennas, and establish a connection between the target processing unit and the third wireless transceiving antenna;

processor 401 is further configured to establish a second wireless link between a third wireless transceiver antenna of the target processing unit and a second wireless transceiver antenna of the target memory unit identified by the target identifier;

the processor 401 is further configured to control the target processing unit to perform transmission of access request data with the target memory unit by using the second wireless link.

If the processing unit is in one-to-one correspondence with the wireless transceiving antenna, the load of the first wireless transceiving antenna is greater than a preset first threshold value;

the processor 401 is further configured to establish a connection relationship between the target processing unit and the auxiliary processing unit, and establish a third wireless link between a fourth wireless transceiving antenna of the auxiliary processing unit and the second wireless transceiving antenna;

the processor 401 is further configured to control the target processing unit to perform transmission of access request data with the target memory unit by using the third wireless link.

Referring to fig. 4, a memory access system architecture diagram provided for an embodiment of the present invention is shown in the figure, where the system architecture includes a many-core layer and a memory stack layer, the many-core layer includes a plurality of processor cores and a global memory controller, the memory stack layer includes a plurality of memory blocks, the many-core layer and the memory stack layer communicate with each other through wireless signals, the global memory controller configures a wireless link between the processor cores and the memory blocks, so as to establish a wireless link between each processor core and a different memory block, and the processor cores and the memory blocks can transmit access data through the wireless link, as shown in the figure, if the memory blocks include 8, any processor core in the many-core layer can access any memory block in the 8 memory blocks through configuring the wireless link. The following takes an example of the target processor core pre-accessing the target memory block as an example.

The global memory controller receives an access request of a target processor core, wherein the access request carries a target identifier of a target memory block pre-accessed by the target processor core;

the global memory controller establishes a wireless link between a wireless transceiving antenna of the target processor core and a wireless transceiving antenna of the target memory block identified by the target identifier;

and the global memory controller controls the target processor core to transmit the memory access request data between the wireless link and the target memory block.

Optionally, if a memory intensive access with high locality occurs in the system architecture, that is, as shown in the top left corner of fig. 10, that is, only the memory block (core5 MEM DIE) of the processor core5 among all the memory blocks is intensive in access, the wireless transceiver antenna of the target processor core wirelessly communicates with the core5 MEM DIE by transmitting frequency division multiplexing with other idle antennas, and the wireless transceiver antenna of the core5 MEM DIE acquires corresponding access request data by frequency division multiplexing.

Optionally, if discrete sparse memory access occurs in the system architecture, that is, as shown in the top right corner of fig. 10, that is, only the memory block (core4 MEM DIE) of the processor core4, the memory block (core6 MEM DIE) of the processor core6, and the memory block (core7 MEM DIE) of the processor core7 in all the memory blocks are sparse accessed, establishing wireless link communication with different memory blocks at different independent time slices may be implemented in a beam scanning (time division multiplexing) manner.

Optionally, if spatially discrete memory intensive access occurs in the system architecture, as shown in the lower left diagram of fig. 10, that is, multiple memory blocks in all the memory blocks are intensively accessed, the transmit frequency division needs to be performed by grouping, for example, the wireless transceiver antennas of the processor core1, the processor core2 and the processor core3 are divided into a group to perform transmit frequency division multiplexing access core2 MEM DIE; the wireless transceiving antennas of the processor core2, the processor core3 and the processor core4 are grouped to transmit a frequency division multiplexing access core3 MEM DIE.

Optionally, if the memory in the system architecture is concurrently accessed in a spatially discrete manner, as shown in the lower right diagram of fig. 10, that is, multiple memory blocks in all the memory blocks are sparsely accessed, and the multiple memory blocks cannot be grouped into one group due to reasons such as non-adjacent spaces, the memory blocks need to be grouped by the memory blocks first, and then the memory blocks in the group need to be accessed by using the wireless transceiving antenna of one processor core, as shown in the figure, core1 MEM DIE, core2 MEM DIE, and core3 MEM DIE are grouped into one group, the memory blocks are accessed by using the wireless transceiving antenna of processor core1 to perform beam scanning, the core4 MEM DIE, the core6 MEM DIE, and the core7 DIE are grouped into one group, and the memory blocks are accessed by using the wireless transceiving antenna of processor core7 to perform beam scanning.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs.

The modules in the memory access device of the embodiment of the invention can be merged, divided and deleted according to actual needs.

The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.

Claims

1. A memory access method, comprising:

establishing a first wireless link between a first wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identifier in a target time slot;

and controlling the target processing unit to transmit the access request data between the first wireless link and the target memory unit, wherein the access request data is transmitted between different time slots and different memory units through the transmission beam scanning of the first wireless transceiving antenna.

2. The method of claim 1, wherein prior to establishing the first wireless link in the target time slot between the first wireless transceiver antenna of the target processing unit and the second wireless transceiver antenna of the target memory unit identified by the target identifier, the method further comprises:

3. The method of claim 1 or 2, wherein before establishing the first radio link between the first radio transceiver antenna of the target processing unit and the second radio transceiver antenna of the target memory unit identified by the target identifier in the target timeslot, the method further comprises:

and selecting the first wireless transceiving antenna for the target processing unit from at least two wireless transceiving antennas, and establishing the connection between the first wireless transceiving antenna and the target processing unit.

4. The method of claim 3, wherein said selecting the first wtru from among at least two wtrus comprises:

acquiring the load of each wireless transceiving antenna in the at least two wireless transceiving antennas;

and selecting the first wireless transceiving antenna with the minimum load from the at least two wireless transceiving antennas.

5. The method of claim 1, wherein if the load of the first wireless transceiving antenna is greater than a preset first threshold, the method further comprises:

selecting a third wireless transceiving antenna from at least two wireless transceiving antennas for the target processing unit, and establishing the connection between the target processing unit and the third wireless transceiving antenna;

and controlling the target processing unit to utilize the second wireless link to transmit the memory access request data with the target memory unit.

6. The method according to claim 1 or 2, wherein the processing units are in one-to-one correspondence with the wireless transceiving antennas, and if the load of the first wireless transceiving antenna is greater than a preset first threshold, the method further comprises:

establishing a connection relation between the target processing unit and an auxiliary processing unit, and establishing a third wireless link between a fourth wireless transceiving antenna of the auxiliary processing unit and the second wireless transceiving antenna;

and controlling the target processing unit to utilize the third wireless link to transmit the memory access request data with the target memory unit.

7. A memory access device, comprising:

a receiving module, configured to receive an access request of a target processing unit, where the access request carries a target identifier of a target memory unit to be accessed by the target processing unit;

an establishing module, configured to establish a first wireless link between a first wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identifier in a target time slot;

and the control module is used for controlling the target processing unit to transmit the memory access request data between the first wireless link and the target memory unit, wherein the memory access request data is transmitted between different time slots and different memory units through the transmission beam scanning of the first wireless transceiving antenna.

8. The apparatus of claim 7, wherein the apparatus further comprises:

9. The apparatus of claim 7 or 8, wherein the apparatus further comprises:

the first selecting module is used for selecting the first wireless transceiving antenna from at least two wireless transceiving antennas for the target processing unit and establishing the connection between the first wireless transceiving antenna and the target processing unit.

10. The apparatus of claim 9, wherein the first selecting module is specifically configured to obtain a load of each of the at least two wtrus, and select the first wtru with a minimum load from the at least two wtrus.

11. The apparatus of claim 7, wherein if the load of the first wireless transceiving antenna is greater than a predetermined first threshold, the apparatus further comprises:

a second selecting module, configured to select a third wireless transceiving antenna for the target processing unit from the at least two wireless transceiving antennas;

the establishing module is further configured to establish a connection between the target processing unit and the third wireless transceiver antenna, and establish a second wireless link between the third wireless transceiver antenna of the target processing unit and the second wireless transceiver antenna of the target memory unit identified by the target identifier;

the control module is further configured to control the target processing unit to transmit the memory access request data with the target memory unit by using the second wireless link.

12. The apparatus according to claim 7 or 8, wherein the processing units are in one-to-one correspondence with the wireless transceiving antennas, and if the load of the first wireless transceiving antenna is greater than a preset first threshold, the establishing module is further configured to establish a connection relationship between the target processing unit and the auxiliary processing unit, and establish a third wireless link between a fourth wireless transceiving antenna of the auxiliary processing unit and the second wireless transceiving antenna;

the control module is further configured to control the target processing unit to transmit the memory access request data with the target memory unit by using the third wireless link.

13. A memory access system architecture is characterized in that the system architecture comprises a many-core layer and a memory stack layer, wherein the many-core layer and the memory stack layer are communicated through wireless signals, the many-core layer comprises at least two processing units and a global memory controller, and the memory stack layer comprises at least two memory units;

the global memory controller establishes a wireless link between a first wireless transceiving antenna of the target processing unit and a second wireless transceiving antenna of the target memory unit identified by the target identification in a target time slot;

the global memory controller controls the target processing unit to transmit the memory access request data between the wireless link and the target memory unit, wherein the memory access request data are transmitted between different memory units and different time slots through the transmission beam scanning of the first wireless transceiving antenna.

14. A readable medium comprising execution instructions that, when executed by a memory controller, cause the memory controller to perform the method of any of claims 1-6.

15. A memory controller, comprising: a processor, a memory, and a bus;

the memory is used for storing execution instructions, the processor is connected with the memory through the bus, and when the memory controller runs, the processor executes the execution instructions stored in the memory so as to enable the memory controller to execute the method of any one of claims 1-6.