CN108461476A - A kind of electric fuse device and its manufacturing method - Google Patents
A kind of electric fuse device and its manufacturing method Download PDFInfo
- Publication number
- CN108461476A CN108461476A CN201710087199.XA CN201710087199A CN108461476A CN 108461476 A CN108461476 A CN 108461476A CN 201710087199 A CN201710087199 A CN 201710087199A CN 108461476 A CN108461476 A CN 108461476A
- Authority
- CN
- China
- Prior art keywords
- layer
- polysilicon
- electric fuse
- polysilicon layer
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
A kind of electric fuse device of present invention offer and its manufacturing method, the device include：Semiconductor substrate is formed with well region in the semiconductor substrate, isolation structure is formed in the well region；The conductive layer formed on the semiconductor substrate, the conductive layer includes the fuse part for the electric fuse device for covering the isolation structure, and the cathode and anode for the electric fuse device being electrically connected respectively with the well region of the isolation structure both sides, the fuse part is between the cathode and anode.Electric fuse device according to the present invention has at least two current channels, so that the resistance of the electric fuse device in programming fusing process, has fixed resistance value after fusing, and resistance value after its fusing is controllable.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of electric fuse device and its manufacturing method.
Background technology
Efuse (electrically programmable fuse) belongs to the memory of one time programming, and programming mechanism is difficult to single electric current
Or voltage is explained, but can be regarded as：In the case where keeping voltage stabilization, blows conductor connection resistance with transient high-current or make its resistance
It significantly increases.Wherein, the polysilicon fuse (Poly Fuse) that high current is blown is one of common fuse, is widely used in
In 0.25 μm~28nmCMOS technologies.
Silicon oxide layer is formed frequently in substrate surface in the prior art, the polysilicon of doping is formed on silicon oxide layer surface
Layer forms silicided polysilicon fuse by fuse-wires structure of the polysilicon layer of doping.Silicided polysilicon fuse is before fusing
Resistance be 50 to 100 ohm between, after fusing, polyfuse resistance value is more than 3000 ohm, have have a greater change
Range.
The present invention provides resistance value after a kind of fusing controllable electric fuse devices and its manufacturing method.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
The present invention provides the manufacturing method of a kind of electric fuse device and electric fuse device, the device includes：
Semiconductor substrate is formed with well region in the semiconductor substrate, isolation structure is formed in the well region；With
The conductive layer formed on the semiconductor substrate, the conductive layer include the institute that part covers the isolation structure
The fuse part of electric fuse device is stated, and the electric fuse device being electrically connected respectively with the well region of the isolation structure both sides
Cathode and anode, the fuse part is between the cathode and anode.
Illustratively, the conductive layer is polysilicon layer.
Illustratively, the polysilicon layer is polysilicon connecting layer.
Illustratively, further include the metal silicide layer formed on the polysilicon layer.
Illustratively, it is formed with the heavy doping being electrically connected with the cathode and anode in the well region of the isolation structure both sides
Active area.
A kind of electric fuse device, the device include：
Semiconductor substrate is formed with isolation structure in the semiconductor substrate；With
Lamination on the isolation structure, the lamination include that the first conductive layer stacked gradually from top to bottom and second are led
Electric layer, first conductive layer have different resistance from the conductive layer more than second；
Wherein, the lamination includes being formed in first conductive layer and the electric fuse more than second in conductive layer
The cathode and anode of device, and the electric fuse device between the cathode and anode fuse part.
Illustratively, first conductive layer is the first polysilicon layer, and second conductive layer is the second polysilicon layer.
Illustratively, second polysilicon layer is polysilicon connecting layer.
Illustratively, first polysilicon layer is polycrystalline silicon gate layer.
Illustratively, first polysilicon layer is big compared with the second polysilicon layer resistance.
Illustratively, further include the metal silicide layer formed on second polysilicon layer.
A kind of manufacturing method of electric fuse device, the method includes：
Semiconductor substrate is provided, well region is formed in the semiconductor substrate, isolation structure is formed in the well region；
Form conductive layer on the semiconductor substrate, pattern the conductive layer with formed respectively with the isolation structure
The cathode and anode of the electric fuse device of the well region electrical connection of both sides, and the fusing between the cathode and anode
Portion.
Illustratively, the conductive layer is polysilicon layer.
Illustratively, the polysilicon layer is polysilicon connecting layer.
Illustratively, further include forming metal silicide layer on the polysilicon layer.
Illustratively, be formed in the well region of the isolation structure both sides be electrically connected with the cathode and anode it is highly doped
Active area.
A kind of manufacturing method of electric fuse device, the method includes：
Semiconductor substrate is provided, isolation structure is formed in the semiconductor substrate；
Lamination is formed on the isolation structure, the lamination includes the first conductive layer stacked gradually from top to bottom and
Two conductive layers pattern first conductive layer and second conductive layer to form the cathode and sun of the electric fuse device
Pole, and the fuse part between the cathode and anode, wherein first conductive layer and second conductive layer pattern
There is different resistance after change.
Illustratively, first conductive layer is the first polysilicon layer, and second conductive layer is the second polysilicon layer.
Illustratively, second polysilicon layer is polysilicon connecting layer.
Illustratively, first polysilicon layer is polycrystalline silicon gate layer.
Illustratively, after patterning, first polysilicon layer is big compared with the second polysilicon layer resistance.
Illustratively, further include forming metal silicide layer on second polysilicon layer.
In conclusion electric fuse device according to the present invention has at least two current channels, to the electric fuse device
The resistance of part has fixed resistance value, and the resistance value after its fusing is controllable in programming fusing process after fusing.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is the schematic flow chart of the manufacturing method of electric fuse device involved in the prior art；
Fig. 2A~2B is the structure sectional view and floor map of electric fuse device in the prior art；
Fig. 3 is the schematic flow chart of the manufacturing method for the electric fuse device that one embodiment of the present of invention proposes；
Fig. 4 A~4F are the device of the formation in the manufacturing process for the electric fuse device that one embodiment of the present of invention proposes
Structure sectional view, floor map and interlock circuit schematic diagram；
Fig. 5 A~5F are the device of the formation in the manufacturing process for the electric fuse device that an alternative embodiment of the invention proposes
Structure sectional view, floor map and the interlock circuit schematic diagram of part；
Fig. 6 is the schematic flow chart of the manufacturing method for the electric fuse device that an alternative embodiment of the invention proposes.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present inventionization
Learn mechanical grinding method.Obviously, execution of the invention is not limited to the specific details that the technical staff of semiconductor applications is familiar with.
Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can also have other realities
Apply mode.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or combination thereof.
Now, exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated
Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted.
To be below embodiment to principle according to the present invention using the forming process of electric fuse in the forming process of mos gate pole
It is specifically described, it is to be understood that the present invention is said using forming electric fuse in the forming process of mos gate pole as embodiment
It is bright to be merely exemplary that ground, any manufacturing process for forming electric fuse structure according to the present invention are suitable for the present invention.
It is handled in the prior art frequently with the formation process in the forming process of mos gate pole, being carried out at the same time electric fuse device.One
A typical manufacturing process is as shown in Figure 1, first, execute step S101：Semiconductor substrate is provided, in the semiconductor substrate
Form isolation structure；Then, step S102 is executed：Gate dielectric is formed on the semiconductor substrate；Then, step is executed
S103：Polysilicon layer is formed on the gate dielectric, and patterns the gate dielectric and polysilicon layer, forms grid
Structure and electric fuse device structure；Finally, contact electrode is formed in the electric fuse device structure, to connect the electric fuse
Cathode and anode.
Referring to Fig. 2A and Fig. 2 B, the sectional view and floor map of the electric fuse device formed in the prior art are shown,
Wherein Fig. 2A is the cross-sectional view in the directions A-A along Fig. 2 B.It is formed with isolation structure 201 in semiconductor substrate 200, described half
It is formed with gate structure (not shown) on conductor substrate, polysilicon layer 202 and described more is formed on the isolation structure 201
Doping is formed with silicide layer 203 on crystal silicon layer 202.Referring to Fig. 2 B, polysilicon layer 202 is located at 201 top of isolation structure, described
Polysilicon layer 202 includes constituting 2021 layers of electric fuse device fuse part and respectively constituting electric fuse device cathode and anode
2022 and 2023.With continued reference to Fig. 2A, the electric fuse device can further include the electricity constituted in the polysilicon layer
The contact electrode 204 and 205 being respectively formed on the cathode 2022 of fuse and anode 2023, the contact electrode 204 and 205 are distinguished
It is made of conductive through hole 206 and top-level metallic 207.
In this configuration, polysilicon fuse device is integrally located above isolation structure, during device programming, electric current
Channel carries out the fusing of electric fuse by the fuse part 2021 of polysilicon electric fuse device.Resistance before fusing is fused by it
The resistance of portion 2021 and the metal silicide layer being positioned above determines, between being 50 to 100 ohm；After fusing, polysilicon
Fuse part form open circuit, resistance value is more than 3000 ohm, and the front and back phase resistance range that fuses is larger.
For this purpose, the present invention provides one kind having at least two current channels, there is fixed resistance value, and it is molten after fusing
The controllable electric fuse device of resistance value of having no progeny and its manufacturing method.
Embodiment one
A kind of manufacture of electric fuse device of one embodiment of the present of invention proposition is described with reference to figure 3 and Fig. 4 A~4F
Journey, wherein Fig. 3 is the schematic flow chart of the manufacturing method for the electric fuse device that one embodiment of the present of invention proposes, Fig. 4 A
The structure sectional view of the device formed in the manufacturing process for the electric fuse device that~4F proposes for one embodiment of the present of invention,
Floor map and interlock circuit schematic diagram.
First, step S301 is executed：Semiconductor substrate is provided, well region is formed in the semiconductor substrate, in the trap
Isolation structure is formed in area.
As shown in Figure 4 A, semiconductor substrate 400 is provided, isolation structure 401, institute are formed in the semiconductor substrate 400
It states and is formed with ion trap 403 below isolation structure.The constituent material of semiconductor substrate 400 can be undoped monocrystalline silicon, mix
There are monocrystalline silicon, the silicon-on-insulator (SOI) etc. of impurity.Illustratively, the side of isolation structure is formed on the semiconductor substrate
Method uses：First, patterned semiconductor substrate forms groove；Then, isolated material is filled in the trench, and the isolated material can
Think the oxide material of any insulation such as silica；Then, the oxide material outside chemical mechanical grinding removal groove is executed.
Illustratively, 401 both sides of the isolation structure, which are also formed with, is heavily doped with source region 402, in the semiconductor substrate
Be heavily doped with source region be N-type heavily doped region or p-type heavily doped region, doping concentration ranging from 1 × 1017~1 × 1020e/cm3,
The ion trap is p-type ion trap corresponding with the active area or N-type ion trap.It is described be heavily doped with source region can guarantee after
Cathode and anode and the ion trap of the continuous electric fuse device formed have preferable electrical contact, reduce cathode and anode and ion
The contact resistance of trap.In one example, mos gate pole structure, mos gate pole structure are also formed in the semiconductor substrate
Positioned at the active area.Mos gate pole structure can be polysilicon gate, can also be the pseudo- grid before forming metal gates
Pole structure.Illustratively, the ion implanted region is formed in after the gate structure.Formed on the semiconductor substrate every
From structure, gate structure, the technique that the isostructural technique of ion implanted region is well known to those skilled in the art is no longer superfluous herein
It states.
In addition, as an example, being formed with side wall construction in the both sides of grid knot, wherein side wall construction includes at least oxidation
Nitride layer and/or nitride layer.The method for forming side wall construction is known to those skilled in the art, is not repeated here herein.
It is formed with source/drain region in the semiconductor substrate of side wall construction both sides, is being distinguished in the source/drain region in NMOS area and the areas PMOS
It is formed with embedded carbon silicon layer and embedded germanium silicon layer.The technical process for forming embedded carbon silicon layer and embedded germanium silicon layer is this
Field technology personnel are familiar with, and are not repeated here herein.It is formed at the top of embedded carbon silicon layer and embedded germanium silicon layer
Self-aligned silicide, to put it more simply, being omitted in diagram.
It is to be appreciated that the present invention is with mos gate pole structure, gate lateral wall structure and the source in NMOS area and the areas PMOS/
Embedded carbon silicon layer and embedded germanium Si layer structure in drain region illustrate for example to be not intended to limit the invention,
It is any that there is ion trap, the semiconductor substrate of isolation structure to be suitable for the present invention.
Then, step S302 is executed：Conductive layer is formed on the semiconductor substrate, patterns the conductive layer to be formed
The cathode and anode for the electric fuse device being electrically connected respectively with the well region of the isolation structure both sides, and it is located at described the moon
Fuse part between pole and anode.
Referring to 4B and 4C, the sectional view and floor map of the electric fuse device formed according to the present embodiment are shown,
Middle Fig. 4 B are the cross-sectional view in the directions B-B along Fig. 4 C.Conductive layer 404 is formed in semiconductor substrate 400, described in patterning
Conductive layer 404 forms the cathode for the electric fuse device being connect respectively with the well region of the both sides of the isolation structure 401 403
4042 and anode 4043, and the molten of the isolation structure 401 is partly covered between the cathode 4042 and anode 4043
Disconnected portion 4041.The cathode and anode of the electric fuse device are connected with the well region of the isolation structure both sides, will be located at isolation junction
Ion trap below structure is connected in parallel to the conductive layer by active area；To which electric fuse device has two fuse part, wherein institute
The first fuse part for stating electric fuse device includes the polysilicon layer of the top of the isolation structure 401, and the of the electric fuse device
Two fuse part include the ion trap 403 being located at below the isolation structure, the cathode and anode packet of the electric fuse device
Include the conductive layer positioned at the active region.
Illustratively, the conductive layer 404 is polysilicon layer.Illustratively, the method packet of the polysilicon layer 404 is formed
Include following steps：Conformal deposited polysilicon layer 404, to cover the surface of the semiconductor substrate 400；Recycle photoetching process shape
At patterned photoresist layer；Using patterned photoresist layer as mask, the polysilicon layer is etched, to pattern the polycrystalline
Silicon layer only forms polysilicon layer 404 on the predetermined region for forming electric fuse fuse part.
Illustratively, the polysilicon layer can be that arbitrarily can be formed and be electrically connected with the active area including element silicon
The semi-conducting material connect, such as Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP etc..Illustratively, the polysilicon layer material
Polysilicon connecting layer is can be used as, the polysilicon connecting layer is with polysilicon layer in general sense (e.g., as the more of grid material
Crystal silicon layer) it is different, the polysilicon connecting layer has preferable Ohmic contact with the active area so that with connecing for the active area
Touching has smaller resistance.In the present embodiment, the polysilicon layer uses Si.It is to be appreciated that the polysilicon layer is as more
When crystal silicon connecting layer, polysilicon connecting layer forming method in the prior art and step can be applied to realize the manufacturing process of the present invention,
To greatly simplify the technological design and implementation of the present invention.
The routine techniques of such as the methods of chemical vapor deposition can be utilized to form polysilicon layer, illustratively, polysilicon
Forming method can be selected low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions for forming the polysilicon include：Reaction
Gas is silane (SiH4), the range of flow of the silane can be 100~200 cc/mins (sccm), such as 150sccm；
Temperature range can be 700~750 degrees Celsius in reaction chamber；It can be 250~350 millimetress of mercury (mTorr) to react cavity pressure, such as
300mTorr；May also include buffer gas in the reaction gas, the buffer gas can be helium or nitrogen, the helium and
The range of flow of nitrogen can be 5~20 liters/min (slm), such as 8slm, 10slm or 15slm.
The electric fuse device formed by the method, fuse part include semiconductor substrate 400 and are located on isolation structure
The first fuse part that the polysilicon layer 4041 of side is constituted and the second fuse part being made of the ion trap 403 below isolation structure,
Its cathode and anode include the polysilicon layer 4042 and 4043 positioned at the active region.It is described more comprising active region
The cathode and anode of the electric fuse device of crystal silicon layer 4042 and 4043 come into full contact with the semiconductor active region so that formation
There are two current channels in the case of circuit turn-on for electric fuse device：One is by the polycrystalline above isolation structure
The current channel that the electric fuse fuse part that silicon layer 4041 is constituted is formed, one is formed by the ion trap 403 of isolation structure bottom
Current channel.
Fig. 4 D show that the equivalent circuit diagram that electric fuse device is constituted, wherein R1 is indicated by including polysilicon layer 4041
Equivalent resistance in the current channel that first fuse part is formed, R2 marks are by the comprising the ion trap 403 below isolation structure
Equivalent resistance in the current channel that two fuse part are formed, the two exist in the form of in parallel in circuit.Thus, electric fuse device
The resistance value of part is made of two parts, the equivalent resistance in the current channel formed by the first fuse part that polysilicon layer 4041 is constituted
R1, the equivalent resistance R2 in the current channel formed by the ion trap 403 of isolation structure bottom, as electric fuse fusing part
Semiconductor contact layer blow before, the resistance value of the electric fuse device is determined by the polysilicon layer；After blowing, electric fuse device
The resistance value of part is determined by the ion trap below the isolation structure.Further, described as electric fuse device
After the polysilicon layer of one fuse part is blown, the resistance value of electric fuse device by the ion trap below the isolation structure width
It determines.Illustratively, by controlling with the ion trap width on the perpendicular direction of the fuse part extending direction to control
State resistance value of the electric fuse device after semiconductor contact layer is blown.
Illustratively, it is also formed with metal silicide layer on the polysilicon layer.With continued reference to 4B and 4C, in polysilicon layer
It is also formed with metal silicide layer 405 on 404, in Fig. 4 C, the polysilicon layer 404 is located under the metal silicide layer 405
Side, is covered by the metal silicide layer 405.The metal silicide layer 405 includes the cathode 4052 of the electric fuse device
With the fuse part 4051 of anode 4053, and the electric fuse device between the cathode 4052 and anode 4053.Institute
On the one hand first polysilicon layer can be reduced as the resistance of electric fuse fuse part and fusing reliability, a side by stating silicide layer
Face reduces the contact resistance of follow-up fuse electrodes and the electric fuse device cathode and anode.Illustratively, the planning is formed
Method use in the semiconductor contact layer enterprising row metal doping.Illustratively, metallic silicon is formed using silicide process
Compound layer.Illustratively, the thickness of metal silicide layer is 20~50nm.
In one example, according to the present embodiment, top is formed with the electric fuse device of metal silicide, is fusing
Before, the resistance of electric fuse device is determined by the metal silicide at the top of polysilicon, about 100 ohm；After polysilicon fusing,
Resistance is determined by the ion trap below isolation structure, and the resistance value after fusing, ion can be controlled by controlling ion trap width
Well resistance control is about 400~1000 ohm/nm2。
Illustratively, executing step S302 further includes later：Contact electrode, the contact electricity are formed on the conductive layer
Pole connects the cathode and anode of electric fuse device.
Referring to Fig. 4 D and Fig. 4 F, sectional view and the plane signal of the electric fuse device formed according to the present embodiment are shown
Figure, wherein Fig. 4 D are the cross-sectional view in the directions C-C along Fig. 4 F.As shown in Figure 4 D, contact electricity is formed on conductive layer 404
Pole 406 and 407 connects the cathode and anode of the electric fuse device.The contact electrode 406 and 407 is respectively by contact through hole
408 and top-level metallic 409 form.The cathode and anode of the electric fuse device are connected to by the contact electrode 406 and 407
External circuit, external circuit supply electric current in the case of, form the Burnout circuit of logic circuit, to the electric fuse device into
The processing of row one time programming.
The method for forming the contact through hole 408 may be used：First, interlayer dielectric layer is formed on a semiconductor substrate；
Then, it patterns the interlayer dielectric layer and forms through-hole；Then, metal is filled in the through-hole, and is executed chemical machinery and ground
Mill is to expose the interlayer dielectric layer.Include in the step of forming top-level metallic 409 on the contact hole：First, it is being formed with
Interlayer dielectric layer is formed in the semiconductor substrate of the through-hole；Then, it patterns the interlayer dielectric layer and forms pre-formed top layer
The groove of metal；Then, metal is filled in the trench, and executes chemical mechanical grinding to expose the interlayer dielectric layer.
The technique that the technique of the through-hole and the top-level metallic is well known to those skilled in the art is formed, details are not described herein.
Fig. 4 E show the floor map for being formed by electric fuse device according to an embodiment of the invention, semiconductor substrate
The active area 402 of ion trap 403 (dotted line is shown), isolation structure 401 and isolation structure both sides is formed on 400.It is described every
It is formed with polysilicon layer 404, the polysilicon layer and the active region contact from 402 top of structure, the polysilicon layer 404 pushes up
Portion is formed with metal silicide layer 405.The polysilicon layer 404, which is formed on the isolation structure 401 and extends to, described to be had
Source region 402 comes into full contact with the active area 402.The polysilicon layer 404 includes 4042 He of cathode of the electric fuse device
Anode 4043, and the electric fuse device between the cathode 4042 and anode 4043 fuse part 4041.It is described
406 He of contact electrode being made of with 409 (not shown) of top-level metallic contact through hole 408 is formed on semiconductor contact layer 404
407 (not shown).
Embodiment two
A kind of manufacture of electric fuse device of an alternative embodiment of the invention proposition is described with reference to figure 5A~5F and Fig. 6
Process, wherein Fig. 5 A~5F are the formation in the manufacturing process for the electric fuse device that an alternative embodiment of the invention proposes
Structure sectional view, floor map and the interlock circuit schematic diagram of device, Fig. 6 are what an alternative embodiment of the invention proposed
The schematic flow chart of the manufacturing method of electric fuse device.
First, step S601 is executed：Semiconductor substrate is provided, isolation structure is formed in the semiconductor substrate.
As shown in Figure 5A, semiconductor substrate 500 is provided, isolation structure 501 is formed in the semiconductor substrate 500, half
The constituent material of conductor substrate 500 can be undoped monocrystalline silicon, the monocrystalline silicon mixed with impurity, silicon-on-insulator (SOI) etc..
Illustratively, the method for forming isolation structure on the semiconductor substrate uses：First, patterned semiconductor substrate forms ditch
Slot；Then, isolated material is filled in the trench, and the isolated material can be the oxide material of any insulation such as silica；
Then, the oxide material outside chemical mechanical grinding removal groove is executed.
Illustratively, it is also formed with ion trap in the semiconductor substrate and is heavily doped with source region, it is described highly doped active
Area is N-doped zone or P-doped zone, doping concentration ranging from 1 × 1017~1 × 1020e/cm3, the ion trap for institute
State the corresponding p-type ion trap of active area or N-type ion trap.In one example, it is also formed with MOS in the semiconductor substrate
Gate structure, mos gate pole structure are located at the active area.Mos gate pole structure can be polysilicon gate, can also
It is the dummy gate structure before forming metal gates.Illustratively, the ion implanted region is formed in after the gate structure.
Ion trap is formed on the semiconductor substrate, and isolation structure, gate structure, the isostructural technique of ion implanted region is this field
Technique known to technical staff, details are not described herein.
In addition, as an example, being formed with side wall construction in the both sides of grid knot, wherein side wall construction includes at least oxidation
Nitride layer and/or nitride layer.The method for forming side wall construction is known to those skilled in the art, is not repeated here herein.
It is formed with source/drain region in the semiconductor substrate of side wall construction both sides, is being distinguished in the source/drain region in NMOS area and the areas PMOS
It is formed with embedded carbon silicon layer and embedded germanium silicon layer.The technical process for forming embedded carbon silicon layer and embedded germanium silicon layer is this
Field technology personnel are familiar with, and are not repeated here herein.It is formed at the top of embedded carbon silicon layer and embedded germanium silicon layer
Self-aligned silicide, to put it more simply, being omitted in diagram.
It is to be appreciated that the present embodiment is to form active area, ion trap, mos gate pole structure, grid in semiconductor substrate
Embedded carbon silicon layer and embedded germanium Si layer structure in the source/drain region in side wall construction and NMOS area and the areas PMOS be example into
Row explanation is not intended to limit the invention, any that there is isolation structure semiconductor substrate to be suitable for the present invention.
Then, step S602 is executed：Formed on the isolation structure the first conductive layer for stacking gradually from top to bottom and
Second conductive layer patterns first conductive layer and second conductive layer to form the cathode and sun of the electric fuse device
Pole, and the fuse part between the cathode and anode, wherein first conductive layer and second conductive layer pattern
There is different resistance after change.
Referring to Fig. 5 B and Fig. 5 C, sectional view and the plane signal of the electric fuse device formed according to the present embodiment are shown
Figure, wherein Fig. 5 B are the cross-sectional view in the directions D-D along Fig. 5 C.Layer successively from top to bottom is formed on the isolation structure
Folded the first conductive layer and the second conductive layer is simultaneously formed by device sectional view and floor map after being patterned.Partly leading
The first conductive layer 502 and the second conductive layer 503 stacked gradually is formed in body substrate 500.Second conductive layer 503 includes electricity
The cathode 5032 and anode 5033 and the first fuse part 5031 of fuse-wire device；First conductive layer 502 constitutes the electric fuse device
Second fuse part of part is covered above the isolation structure 501 by second conductive layer 503.
The step of the first conductive layer stacked gradually described in formation and the second conductive layer includes：First in the semiconductor substrate
The isolation structure on form the first conductive layer；Then, the second conductive layer is formed in the semiconductor substrate, described in covering
First conductive layer.
Illustratively, first conductive layer is the first polysilicon layer, and second conductive layer is the second polysilicon layer.From
And electric fuse forming step is incorporated in the step of needing to form polysilicon in fabrication of semiconductor device in the prior art.
Illustratively, first, the first polysilicon layer is formed on a semiconductor substrate.With continued reference to 5B, first in isolation junction
The first polysilicon layer 502 is formed on structure 501.First polysilicon layer can be formed in after the source-drain area formation, also may be used
To be formed in before the source-drain area is formed in the structure-forming process of mos gate pole.Illustratively, in the formation of mos gate pole structure
First polysilicon layer is formed in the process, and specific forming process is：Form gate dielectric on a semiconductor substrate first,
Then, gate material layers are formed on the gate dielectric, i.e., described first polysilicon layer；Then, described first is patterned
Polysilicon layer forms the first polysilicon layer on the gate structure and the isolation structure.The step of the patterned polysilicon layer
Rapid use forms photoresist layer on first polysilicon layer, patterns the photoresist layer, and execute plasma etching
Technique forms the polysilicon layer on polysilicon gate construction layer and the isolation structure.It is to be appreciated that the polysilicon layer
Forming process and material using mos gate pole forming process as embodiment carry out example, be not intended to limit the invention, appoint
The process what can form first polysilicon layer is suitable for the present invention.
Then, the second polysilicon layer is formed on the semiconductor substrate.With continued reference to 5B, the shape on isolation structure 501
At the first polysilicon layer 502 on form the second polysilicon layer 503.Second polysilicon layer 503 is located on the first polysilicon layer 502
Side covers first polysilicon layer.
Illustratively, the method for forming 503 and second polysilicon layer 502 of the first polysilicon layer includes the following steps：
Mask layer is formed in described be formed in the semiconductor substrate of the second polysilicon layer, the mask layer can be as masking material
Any mask material for removing polycrystalline silicon material is expected, illustratively, using photoresist, in favor of going for subsequent masks material
It removes；Then, the mask layer is patterned using photoetching process；Then, using patterned mask material layer as mask, described in etching
First polysilicon layer and the second polysilicon layer, to pattern first polysilicon layer and the second polysilicon layer, only described pre-
It is shaped as forming first polysilicon layer, 502 and second polysilicon layer 503 on the region of electric fuse fuse part, namely is being isolated
501 surface certain area of structure forms the first polysilicon layer and the second polysilicon layer.It is to be appreciated that described form more than first
The method of crystal silicon layer and the second polysilicon layer lamination is only exemplary, any method for forming the polysilicon laminate,
Such as, the structure of first polysilicon layer is first formed in grid forming process, after during forming the second polysilicon layer
Only etch the connection between the cathode and anode and the cathode and anode of the second polysilicon layer formation electric fuse device
Portion is suitable for the present invention.
Illustratively, first polysilicon layer from after second polysilicon layer pattern have different resistance.Institute
State the first polysilicon layer has different resistance from second polysilicon layer, to make finally formed electric fuse device have
At least two different current channels form the electric fuse fuse part of successively fusing in fusing process.First polysilicon
The layer resistance different from second polysilicon layer can pass through the shape of control the first polysilicon layer and the second polysilicon layer, ruler
Very little, resistivity is realized.
Illustratively, the second polysilicon layer resistance is small compared with the first polysilicon layer resistance.Illustratively, more than described second
Crystal silicon layer uses polysilicon connecting layer, and first polysilicon layer uses polycrystalline silicon gate layer, to make full use of the prior art
The formation process of middle polysilicon gate and polysilicon connecting layer forms the electric fuse device of the present invention, to simplify technological design and reality
Step is applied, production cost is reduced.Second polysilicon layer is to have preferable Europe with the active area as polysilicon connecting layer
Nurse contacts, and has good semiconductor interface (such as the polysilicon layer as grid material) relative to polysilicon layer in general sense
Performance is touched, the contact resistance with active region contact can be reduced, thus with polysilicon layer more in general sense (as being used as grid
The polysilicon layer of material) there is smaller resistivity, and then first polysilicon layer formed in same patterning process
There is different resistance with second polysilicon layer.
Illustratively, the material of first polysilicon layer as connecting layer can be the polysilicon material suitably adulterated
Material, such as SiB, SiGe, SiC, SiP, SiGeB, SiCP etc., in the present embodiment, the preferably material of first polysilicon layer 505
Material includes SiP.
The routine techniques of such as the methods of chemical vapor deposition can be utilized to form polysilicon layer, illustratively, doping is more
Low-pressure chemical vapor phase deposition (LPCVD) technique can be selected in the forming method of crystal silicon.The process conditions for forming the polysilicon include：
Reaction gas is silane (SiH4) and PH3 mixed gas, the range of flow of the silane can be 100~200 cubic centimetres/point
Clock (sccm), such as 150sccm；The range of flow of the PH3 can be 100~300 cc/mins (sccm), such as
150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；It can be 250~350 millimetress of mercury to react cavity pressure
(mTorr), such as 300mTorr；May also include buffer gas in the reaction gas, the buffer gas can be helium or nitrogen,
The range of flow of the helium and nitrogen can be 5~20 liters/min (slm), such as 8slm, 10slm or 15slm.
It should be noted that first polysilicon layer uses polysilicon connecting layer, second polysilicon layer is using more
When polysilicon gate layer, the formation process of the electric fuse device of the present invention is incorporated to normal gate formation process and polysilicon connecting layer
In formation process, the transformation in this technique does not need to be modified technique in the prior art, utilizes the prior art
Material and processing step ingenious can realize technique manufacturing method of the invention, can greatly reduce the production of electric fuse device and set
Count cost.And first polysilicon layer uses polysilicon connecting layer, second polysilicon layer is using polycrystalline silicon gate layer
Method is only exemplary, and the method for any polysilicon layer for forming the different stacking of resistance can be applied to the present invention.
With continued reference to Fig. 5 B and 5C, the formation electric fuse device includes the electric smelting wire cathode 5032 and anode
5033 and the electric fuse device the first fuse part 5031 the second polysilicon layer 503；First polysilicon layer 502 is constituted
Second fuse part of the electric fuse device, this makes the electric fuse device to be formed, and there are two electric currents in the case of circuit turn-on
Channel：One be located at isolation structure above the first fuse part 5031 formed by the second polysilicon layer；One be located at every
The second fuse part 504 being made of the first polysilicon layer from superstructure.Fig. 5 D show the equivalent electricity that electric fuse device is constituted
In the current channel that the first fuse part of electric fuse device that Lu Tu, wherein R1 mark are made of the second polysilicon layer 5031 is formed
Equivalent resistance, in the current channel that the second fuse part of electric fuse device that R2 marks are made of the first polysilicon layer 502 is formed
Equivalent resistance, the two exists in the form of in parallel in circuit.Thus, the resistance value of electric fuse device is made of two parts, by
Equivalent resistance R1 in the current channel that first fuse part of the electric fuse device that the second polysilicon layer 5031 is constituted is formed, by the
Equivalent resistance R2 in the current channel that second fuse part of the electric fuse device that one polysilicon layer 502 is constituted is formed.The electricity
The circuit that fuse-wire device is formed has three kinds of resistance states during the work time, in more than first as electric fuse device fuse part
Crystal silicon layer and the second polysilicon layer are not blown, and the resistance value of the electric fuse device is codetermined by the two-layer polysilicon layer,
Specifically, can be determined by less resistive in two-layer polysilicon；After the polysilicon layer for having less resistive is blown, electric fuse device
The resistance value of part is determined by remaining crystal silicon layer；After two-layer polysilicon layer is blown, resistance value will be greater than 3000 Europe.Further, may be used
Resistance value of the electric fuse device after previous polycrystalline crystal silicon layer is blown is controlled by the polysilicon layer resistance blown after control.
Illustratively, it is also formed with metal silicide layer on second polysilicon layer.The silicide layer on the one hand can
Second polysilicon layer is reduced as the resistance of electric fuse fuse part and fusing reliability, on the one hand reduces follow-up fuse electrodes
With the contact resistance of the electric smelting wire cathode and anode.Illustratively, the method for forming the planning is used more than described second
Crystal silicon enterprising row metal doping layer by layer.Illustratively, metal silicide layer is formed using silicide process.Illustratively, metal
The thickness of silicide layer is 20~50nm.
In one example, according to the present embodiment, the second polysilicon layer top is formed with the electric fuse of metal silicide
Device, before the fusing of the second polysilicon layer, the resistance of electric fuse device is determined by the metal silicide at the top of polysilicon, about
100 ohm；After the fusing of second polysilicon, resistance is determined by the first polysilicon layer below the second polysilicon layer, generally
1000 or 2000 Europe；After the fusing of the first polysilicon layer, resistance is more than 3000 Europe.
Illustratively, the method further includes executing step S302 to execute later：On first polysilicon layer
Contact electrode is formed, the contact electrode connects the cathode and anode of the electric fuse device.
Referring to Fig. 5 E and Fig. 5 F, sectional view and the plane signal of the electric fuse device formed according to the present embodiment are shown
Figure, wherein Fig. 5 E be along Fig. 5 F the directions E-E cross-sectional view as shown in fig. 5e, formed and connect on the first polysilicon layer 503
Touched electrode 504 and 505, to connect the cathode and anode of the electric fuse device.The contact electrode 504 and 505 is respectively by connecing
It touches through-hole 506 and top-level metallic 507 forms.The cathode and anode of the electric fuse device pass through the contact electrode 504 and 505
It is connected to external circuit, in the case where external circuit supplies electric current, the Burnout circuit of logic circuit is formed, to the electric fuse
Device carries out one time programming processing.
The method for forming the contact through hole 506 may be used：First, interlayer dielectric layer is formed on a semiconductor substrate；
Then, it patterns the interlayer dielectric layer and forms through-hole；Then, metal is filled in the through-hole, and is executed chemical machinery and ground
Mill is to expose the interlayer dielectric layer.Include in the step of forming top-level metallic 507 on the contact hole 506：First, it is being formed
Interlayer dielectric layer is formed in the semiconductor substrate for having the through-hole；Then, it patterns the interlayer dielectric layer and forms pre-formed top
The groove of layer metal；Then, metal is filled in the trench, and executes chemical mechanical grinding to expose the inter-level dielectric
Layer.The technique that the technique of the through-hole and the top-level metallic is well known to those skilled in the art is formed, details are not described herein.
Fig. 5 F show the floor map for being formed by electric fuse device according to an embodiment of the invention, semiconductor substrate
Isolation structure 501 is formed on 500.First polysilicon layer 503 is located on the isolation structure, below the polysilicon layer
It is formed with the second polysilicon layer 502, first polysilicon layer 503 partly or entirely covers second polysilicon layer 502, institute
State the cathode, anode and the first fuse part that the first polysilicon layer includes the electric fuse device, 502 structure of the second polysilicon layer
At second fuse part.Silicide layer (not shown), the semiconductor can also be formed on the semiconductor contact layer 503
The contact electrode 506 and 507 constituted by contact through hole 506 with 507 (not shown) of top-level metallic is formed on contact layer (not show
Go out).
Embodiment three
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes：Semiconductor substrate, the semiconductor
It is formed with well region in substrate, isolation structure is formed in the well region；With
The conductive layer formed on the isolation structure, the conductive layer include the electric smelting for covering the isolation structure
The cathode and anode of silk device, and the electric fuse device between the cathode and anode fuse part.
Electric fuse device provided by the invention is further described referring to Fig. 4 B, 4C, 4D, referring to Fig. 4 B, the electricity
Fuse-wire device includes semiconductor substrate 400 and the conductive layer 404 in the semiconductor substrate；The semiconductor substrate 400
Including isolation structure 401 and ion trap 403.Illustratively, 401 both sides of the isolation structure, which are also formed with, is heavily doped with source region
402, the doping concentration for being heavily doped with source region 402 ranging from 1 × 1017~1 × 1020e/cm3, the ion trap be with it is described
The corresponding N-type ion trap of active area or p-type ion trap.The source region that is heavily doped with can guarantee the electric fuse device being subsequently formed
The cathode and anode of part have preferable electrical contact with the ion trap, reduce the contact resistance of cathode and anode and ion trap.Institute
It states conductive layer 404 to be located on the isolation structure 401, extends to the active area.
Referring to Fig. 4 C, the anode and cathode of the electric fuse device includes being heavily doped with leading in source region 402 positioned at described
Electric layer 4042 and 4043；The fuse part of the electric fuse device includes being located at the conductive silicon layer of 401 top of the isolation structure
The second fuse part that 4041 the first fuse part constituted and the ion trap 403 below the isolation structure 401 are constituted.It is described
The cathode and anode of electric fuse device come into full contact with the semiconductor active region so that the electric fuse device of formation is led in circuit
There are two current channels in the case of logical：One is the electric fuse being made of the conductive layer 4041 above isolation structure
The current channel that the first fuse part of device is formed, one is the electric fuse device being made of the ion trap 403 of isolation structure bottom
The current channel that second fuse part is formed.
Fig. 4 D show that the equivalent circuit diagram that electric fuse device is constituted, wherein R1 is indicated by 4041 structure of semiconductor contact layer
At the first fuse part of electric fuse device formed current channel in equivalent resistance, R2 indicate by isolation structure bottom ion
Equivalent resistance in the current channel that the second fuse part of electric fuse device that trap 403 is constituted is formed, the two is in circuit with parallel connection
Form exist.Thus, the resistance value of electric fuse device is made of two parts, the electric fuse fuse part shape being made of conductive layer 4041
At current channel in equivalent resistance R1, the equivalent electricity in the current channel formed by the ion trap 403 of isolation structure bottom
R2 is hindered, before being blown as the conductive layer of the first fuse part of electric fuse, the resistance value of the electric fuse device is determined by the conductive layer
It is fixed；After blowing, the resistance value of electric fuse device is determined by the ion trap below the isolation structure.Further, in institute
It states after being blown as the semiconductor contact layer of electric fuse fusing part, the resistance value of electric fuse device is by being located under the isolation structure
The width of the ion trap of side determines.So as to control the electric fuse device in semiconductor contact by controlling ion trap width
Layer blow after resistance value.
Illustratively, the conductive layer is polysilicon layer.Illustratively, it is formed with metal silicide on the polysilicon layer
Layer.As shown in Figure 4 B, metal silicide layer 405 is also formed on semiconductor contact layer 404.The silicide layer on the one hand can
The semiconductor contact layer is reduced as the resistance of electric fuse fuse part and fusing reliability, on the one hand reduces follow-up fuse electrodes
With the contact resistance of the electric smelting wire cathode and anode.Illustratively, the method for forming the planning is used in the semiconductor
The enterprising row metal doping of contact layer.Illustratively, metal silicide layer is formed using silicide process.Illustratively, metallic silicon
The thickness of compound layer is 20~50nm.
In one example, according to the present embodiment, top is formed with the electric fuse device of metal silicide, is fusing
Before, the resistance of electric fuse device is determined by the metal silicide at the top of polysilicon, about 100 ohm；After polysilicon fusing,
Resistance is determined by the ion trap below isolation structure, and the resistance value after fusing, ion can be controlled by controlling ion trap width
Well resistance control is about 400~1000 ohm/nm2。
Illustratively, the electric fuse device further comprises the contact electrode being formed in the anode and cathode, institute
It includes the conductive through hole being formed on the cathode and the anode and the top that is formed on the conductive through hole to state contact electrode
Layer metal.As shown in Fig. 4 E and 4F, the electric fuse device further comprises being formed on the anode 4042 and cathode 4043
Contact electrode 406 and 407, the contact electrode 406 and 407 respectively includes being formed in the anode 4042 and the cathode
Conductive through hole 408 and top-level metallic 409 on 4043 are constituted.On the through-hole and the through-hole by semiconductor contact layer
Top-level metallic composition contact electrode constitute cathode and anode can be connected to external circuit, external circuit supply electric current the case where
Under, the Burnout circuit of logic circuit is formed, to carry out one time programming processing to the electric fuse.
Example IV
The present invention also provides a kind of electric fuse device, the device includes：Semiconductor substrate, in the semiconductor substrate
It is formed with isolation structure；With
Lamination on the isolation structure, the lamination include that the first conductive layer stacked gradually from top to bottom and second are led
Electric layer, first conductive layer have different resistance from second conductive layer；
Wherein, the lamination includes the electric fuse device being formed in first conductive layer and second conductive layer
The cathode and anode of part, and the electric fuse device between the cathode and anode fuse part.
Another electric fuse device provided by the invention is further described referring to Fig. 5 B~Fig. 5 F.Referring to Fig. 5 B,
The electric fuse device includes semiconductor substrate 500, and the semiconductor substrate 500 includes isolation structure 501；It is described be located at it is described
The first conductive layer 503 and the second conductive layer 502 that isolation structure 501 stacks gradually from top to bottom.Referring to Fig. 5 C, it is described be located at every
From the cathode and anode that the first conductive layer 5032 and 5033 of superstructure constitutes the electric fuse device；The electric fuse device
Fuse part include the first fuse part for being made of the first conductive layer 5051 and by the second conductive layer constitute 502 constitute second
Fuse part.
Second fusing constituted comprising the first fuse part being made of the first conductive layer 5031 and the second conductive layer 502
The electric fuse device that portion is formed so that the electric fuse device of formation is in the case of circuit turn-on so that the electric fuse device formed
There are two current channels in the case of circuit turn-on：One is the formed by the first conductive layer above being located at isolation structure
One fuse part 5031；One is the second fuse part 502 being made of the second conductive layer above being located at isolation structure.Fig. 5 D are shown
The equivalent circuit diagram that electric fuse device is constituted, the electric fuse device first that wherein R1 marks are made of the first conductive layer 5031 fuse
Equivalent resistance in the current channel that portion is formed, the second fusing of the electric fuse device that R2 marks are made of the second conductive layer 502
Equivalent resistance in the current channel that portion is formed, the two exist in the form of in parallel in circuit.Thus, the resistance of electric fuse device
Value is made of two parts, in the current channel that the first fuse part of the electric fuse device being made of the first conductive layer 5031 is formed
Equivalent resistance R1, it is equivalent in the current channel that the second fuse part of the electric fuse device being made of the second conductive layer 502 is formed
Resistance R2.The circuit that the electric fuse device is formed has three kinds of resistance states during the work time, as electric fuse device
The first conductive layer and the second conductive layer of fuse part are not blown, and the resistance value of the electric fuse device is total to by the two conductive layers
With decision, specifically, can be determined by less resistive in two conductive layers；After the conductive layer for having less resistive is blown, electricity
The resistance value of fuse-wire device is determined by remaining conductive layer；After two conductive layers are blown, resistance value will be greater than 3000 Europe.More into one
Step, can control resistance of the electric fuse device after previous polycrystalline crystal silicon layer is blown by the resistance conductive layer blown after control
Value.
Illustratively, first conductive layer is the first polysilicon layer, and second conductive layer is the second polysilicon layer.Institute
State the first polysilicon layer has different conductivity from second polysilicon layer.Further, illustratively, first polycrystalline
Silicon layer or second polysilicon layer are polysilicon connecting layer.Illustratively, first polysilicon layer is as in polysilicon
The even polysilicon layer of layer.The polysilicon connecting layer has preferable Ohmic contact with the active area, relative in general sense
Polysilicon layer there is good semiconductor contact performance, can reduce the contact resistance with active area, thus with relatively general meaning
Polysilicon layer in justice has smaller resistivity (such as the polysilicon layer as grid material).It is described as connecting layer first
The material of polysilicon layer can be the semi-conducting material moderately adulterated, such as SiB, SiGe, SiC, SiP, SiGeB, SiCP etc., sheet
In embodiment, preferably the material of first polysilicon layer 502 includes SiP.Illustratively, first polysilicon layer is compared with
There is larger resistance after two poly-silicon patterns.Illustratively, second polysilicon layer is polycrystalline silicon gate layer.
Illustratively, it is also formed with metal silicide layer on first polysilicon layer.The silicide layer on the one hand can
Reduce by first polysilicon layer as fuse failure portion resistance and fusing reliability, on the one hand reduce follow-up fuse electrodes with
The contact resistance of the fuse connection structure.Illustratively, the method for forming the planning is used in first polysilicon layer
Enterprising row metal doping.Illustratively, metal silicide layer is formed using silicide process.Illustratively, metal silicide layer
Thickness be 20~50nm.
In one example, according to the present embodiment, the first polysilicon layer top is formed with the electric fuse of metal silicide
Device, before the fusing of the first polysilicon layer, the resistance of electric fuse device is determined by the metal silicide at the top of polysilicon, about
100 ohm；After the fusing of first polysilicon, resistance is determined by the second polysilicon layer below the first polysilicon layer, generally
1000 or 2000 Europe；After the fusing of the second polysilicon layer, resistance is more than 3000 Europe.
Illustratively, the electric fuse device further comprises the contact electrode being formed in the anode and cathode, institute
It includes the conductive through hole being formed on the cathode and the anode and the top that is formed on the conductive through hole to state contact electrode
Layer metal.As shown in Fig. 5 E and 5F, the electric fuse device further comprises being formed on the anode 5032 and cathode 5033
Contact electrode 504 and 505, the contact electrode 504 and 505 respectively includes being formed in the anode 5032 and the cathode
Conductive through hole 506 and top-level metallic 507 on 5033 are constituted.On the through-hole and the through-hole by semiconductor contact layer
Top-level metallic composition contact electrode constitute cathode and anode can be connected to external circuit, external circuit supply electric current the case where
Under, the Burnout circuit of logic circuit is formed, to carry out one time programming processing to the electric fuse.
It should be understood that this specification only provides illustrative implementation, what embodiment three and example IV provided
Semiconductor devices, although forming two kinds of semiconductor devices in the form of expression, it is substantially to have same operation principle
Semiconductor devices, i.e., its be substantially have more current channels (current channel of more than one), and for the first time fuse after electricity
Hinder two different embodiments of controllable electric fuse device.
In conclusion electric fuse device according to the present invention has at least two current channels, to the electric fuse device
The resistance of part has fixed resistance value, and the resistance value after its fusing is controllable in programming fusing process after fusing.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (22)
1. a kind of electric fuse device, which is characterized in that the device includes：
Semiconductor substrate is formed with well region in the semiconductor substrate, isolation structure is formed in the well region；With
The conductive layer formed on the semiconductor substrate, the conductive layer include the electric fuse for covering the isolation structure
The fuse part of device, and the cathode and sun of the electric fuse device that are electrically connected respectively with the well region of the isolation structure both sides
Pole, the fuse part is between the cathode and anode.
2. device as described in claim 1, which is characterized in that the conductive layer is polysilicon layer.
3. device as claimed in claim 2, which is characterized in that the polysilicon layer is polysilicon connecting layer.
4. device as claimed in claim 2, which is characterized in that further include the metal silicide formed on the polysilicon layer
Layer.
5. device as described in claim 1, which is characterized in that be formed in the well region of the isolation structure both sides and described the moon
What pole and anode were electrically connected is heavily doped with source region.
6. a kind of electric fuse device, which is characterized in that the device includes：
Semiconductor substrate is formed with isolation structure in the semiconductor substrate；With
Lamination on the isolation structure, the lamination include that the first conductive layer stacked gradually from top to bottom and second are conductive
Layer, first conductive layer have different resistance from second conductive layer；
Wherein, the lamination includes the cathode for the electric fuse device being formed in first conductive layer and the second conductive layer
And anode, and the electric fuse device between the cathode and anode fuse part.
7. device as claimed in claim 6, which is characterized in that first conductive layer be the first polysilicon layer, described second
Conductive layer is the second polysilicon layer.
8. device as claimed in claim 7, which is characterized in that second polysilicon layer is polysilicon connecting layer.
9. device as claimed in claim 7, which is characterized in that first polysilicon layer is polycrystalline silicon gate layer.
10. device as claimed in claim 7, which is characterized in that the first polysilicon layer the second polysilicon layer electricity
Resistance is big.
11. device as claimed in claim 7, which is characterized in that further include the metal formed on second polysilicon layer
Silicide layer.
12. a kind of manufacturing method of electric fuse device, which is characterized in that the method includes：
Semiconductor substrate is provided, well region is formed in the semiconductor substrate, isolation structure is formed in the well region；
Form conductive layer on the semiconductor substrate, pattern the conductive layer with formed respectively with the isolation structure both sides
Well region electrical connection the electric fuse device cathode and anode, and the fuse part between the cathode and anode.
13. method as claimed in claim 12, which is characterized in that the conductive layer is polysilicon layer.
14. method as claimed in claim 13, which is characterized in that the polysilicon layer is polysilicon connecting layer.
15. method as claimed in claim 13, which is characterized in that further include forming metal silicide on the polysilicon layer
Layer.
16. method as claimed in claim 12, which is characterized in that be formed in the well region of the isolation structure both sides with it is described
What cathode and anode were electrically connected is heavily doped with source region.
17. a kind of manufacturing method of electric fuse device, which is characterized in that the method includes：
Semiconductor substrate is provided, isolation structure is formed in the semiconductor substrate；
Lamination is formed on the isolation structure, the lamination includes that the first conductive layer stacked gradually from top to bottom and second are led
Electric layer, patterns first conductive layer and second conductive layer to form the cathode and anode of the electric fuse device, with
And the fuse part between the cathode and anode, wherein after first conductive layer and second conductive layer pattern
With different resistance.
18. method as claimed in claim 17, which is characterized in that first conductive layer is the first polysilicon layer, described the
Two conductive layers are the second polysilicon layer.
19. method as claimed in claim 18, which is characterized in that second polysilicon layer is polysilicon connecting layer.
20. method as claimed in claim 18, which is characterized in that first polysilicon layer is polycrystalline silicon gate layer.
21. method as claimed in claim 18, which is characterized in that after patterning, first polysilicon layer more described second
Polysilicon layer resistance is big.
22. method as claimed in claim 18, which is characterized in that further include forming metallic silicon on second polysilicon layer
Compound layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710087199.XA CN108461476B (en) | 2017-02-17 | 2017-02-17 | Electric fuse device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710087199.XA CN108461476B (en) | 2017-02-17 | 2017-02-17 | Electric fuse device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108461476A true CN108461476A (en) | 2018-08-28 |
| CN108461476B CN108461476B (en) | 2020-02-11 |
Family
ID=63228777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710087199.XA Active CN108461476B (en) | 2017-02-17 | 2017-02-17 | Electric fuse device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108461476B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645434A (en) * | 2009-06-24 | 2010-02-10 | 上海宏力半导体制造有限公司 | Electric fuse device and manufacturing method thereof |
| US20100148915A1 (en) * | 2008-12-15 | 2010-06-17 | Chien-Li Kuo | Electrical fuse structure and method for fabricating the same |
| CN104701295A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse structure and production method thereof |
-
2017
- 2017-02-17 CN CN201710087199.XA patent/CN108461476B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100148915A1 (en) * | 2008-12-15 | 2010-06-17 | Chien-Li Kuo | Electrical fuse structure and method for fabricating the same |
| CN101645434A (en) * | 2009-06-24 | 2010-02-10 | 上海宏力半导体制造有限公司 | Electric fuse device and manufacturing method thereof |
| CN104701295A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse structure and production method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108461476B (en) | 2020-02-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106711042B (en) | Method and structure for semiconductor middle section processing procedure (MEOL) technique | |
| CN100483715C (en) | CMOS compatible shallow-trench e-fuse structure and method of manufacturing the same | |
| CN103426771B (en) | The method of insulated gate semiconductor device of the manufacture with shield electrode structure | |
| KR101201489B1 (en) | Method for fabricating soi device | |
| CN102339855B (en) | Internal connection-wire structure and preparation method thereof | |
| US20060292754A1 (en) | Antifuse element and method of manufacture | |
| US20060102964A1 (en) | Passive device and method for forming the same | |
| KR20110107852A (en) | Spacer and gate dielectric structure for programmable high-k/metal gate memory transistors integrated with logic transistors and method of forming the same | |
| CN203242629U (en) | Electrode contact structure | |
| CN106098768B (en) | Staggered tunneling field effect transistor | |
| CN108257944A (en) | Semiconductor devices and its manufacturing method | |
| US7575967B2 (en) | Semiconductor integrated circuit device and a manufacturing method for the same | |
| CN101772839B (en) | Circuit structure with metal gate and high-K dielectric | |
| US6677194B2 (en) | Method of manufacturing a semiconductor integrated circuit device | |
| TWI409948B (en) | Structure and method for making high density mosfet circuits with different height contact lines | |
| JP2002368225A (en) | Semiconductor device and manufacturing method therefor | |
| US20150303117A1 (en) | Methods for fabricating integrated circutis and components thereof | |
| KR100966008B1 (en) | Room Temperature-operating Single-Electron Device and the Fabrication Method thereof | |
| CN109638010A (en) | RF switching device with and preparation method thereof | |
| CN104347589A (en) | Antifuse structure | |
| KR101867697B1 (en) | Semiconductor and method | |
| CN104064548B (en) | A kind of electrically programmable fuse device architecture and preparation method thereof | |
| CN108461476A (en) | A kind of electric fuse device and its manufacturing method | |
| CN108305894A (en) | Semiconductor devices and its manufacturing method | |
| US10923575B2 (en) | Low resistance contact for transistors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |