CN108447910A - A kind of 3D mos field effect transistor and its manufacturing method - Google Patents

A kind of 3D mos field effect transistor and its manufacturing method Download PDF

Info

Publication number
CN108447910A
CN108447910A CN201810187224.6A CN201810187224A CN108447910A CN 108447910 A CN108447910 A CN 108447910A CN 201810187224 A CN201810187224 A CN 201810187224A CN 108447910 A CN108447910 A CN 108447910A
Authority
CN
China
Prior art keywords
guide post
layer
guide
guide card
glass layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810187224.6A
Other languages
Chinese (zh)
Inventor
陈邦明
王本艳
景蔚亮
黄添益
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Xinchu Integrated Circuit Co Ltd
Original Assignee
Shanghai Xinchu Integrated Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Xinchu Integrated Circuit Co Ltd filed Critical Shanghai Xinchu Integrated Circuit Co Ltd
Priority to CN201810187224.6A priority Critical patent/CN108447910A/en
Publication of CN108447910A publication Critical patent/CN108447910A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a kind of 3D mos field effect transistor and its manufacturing methods, belong to the technology of field of transistors, including：Borophosphosilicate glass layer, the borophosphosilicate glass layer are set to above the epitaxial layer；Drain electrode, grid, source electrode and substrate pole are equipped in the well region successively；The grid includes：First guide card, first guide card are set to the borophosphosilicate glass layer upper surface；First guide post, first guide post are arranged in the borophosphosilicate glass layer；Polysilicon body, the polysilicon body cross section are V-shaped, and the tip of the polysilicon body is embedded in the epitaxial layer；First guide post both ends are connected with first guide card and the polysilicon body respectively.The advantageous effect of the technical solution is：The present invention increases conducting channel, enhances the effect of the control of grid, reduces leakage current and power consumption, reduces production cost.

Description

A kind of 3D mos field effect transistor and its manufacturing method
Technical field
The present invention relates to a kind of technology of field of transistors, specifically a kind of 3D metal oxide semiconductor field-effects Transistor and its manufacturing method.
Background technology
MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal oxide half Conductor field-effect transistor) it is a kind of current most widely used semiconductor devices.
Typical MOSFET element structure is made of PMOSFET and NMOSFET, each MOSFET sources (Source, S), drain (Drain, D), grid (Gate, G), four end of substrate (Bulk, B).
By taking NMOSFET as an example, its working principle is that, when its grid adds positive voltage, electric current can flow to source electrode from drain electrode, Can define its state at this time is " 1 "；When its grid is not added with voltage, electric current can not flow to source electrode from drain electrode, can define it at this time State is " 0 ".The operation principle of PMOSFET is similar with NMOSFET, and when its grid adds positive voltage, electric current can not be flowed from drain electrode To source electrode, can define its state at this time is " 0 "；When its grid is not added with voltage, electric current can flow to source electrode from drain electrode, at this time may be used It is " 1 " to define its state.In this way, a MOSFET can store two different states, i.e., " 1 " in computer.
Currently, as soon as a piece ic core on piece can integrate billions of a MOSFET, billions of " 0 " and " 1 " are represented, The source electrode of this billions of a MOSFET, drain electrode 5 and grid are chained up with plain conductor again, electronic signal is billions of at this Circulation finally obtains user and thinks various purposes to be achieved with regard to carrying out operation between a " 0 " and " 1 ".
Requirement with people to integrated circuit is higher and higher, and the manufacturing process of integrated circuit is constantly progressive.Manufacturing process Progress the promotion of performance, the reduction of power consumption, cost can be brought to also bring along the rapidly aggravation of design, manufacture view difficulty. With the continuous diminution of manufacturing process, especially after 20nm, drain electrode is too short at a distance from conducting channel between source electrode, and having can Electric leakage can be generated, at the same time, electric current between original drain electrode and source electrode can by whether controlled by grid, and grid The length smaller and smaller contact area caused between grid and conducting channel in pole is also smaller and smaller, cause grid to drain electrode with source electrode it Between electric current control force it is also smaller and smaller, this can extreme influence circuit performance and reliability.In this case, respective new skill Art is come into being, wherein most representative two are exactly (Fin Field-Effect Transistor, the fin field FINFET Effect transistor) and FD-SOI (Fully Depleted Silicon On Insulator, fully- depleted silicon-on-insulator).
Invention content
The present invention is directed to deficiencies of the prior art, proposes a kind of 3D metal oxide semiconductor field effect transistors Pipe and its manufacturing method.
The present invention is achieved by the following technical solutions：
The present invention relates to a kind of 3D mos field effect transistor manufacturing method, a previously prepared substrate Layer, and an epitaxial layer is prepared in the upper surface of the substrate layer, it is further comprising the steps of：
Step S1 carries out deep trench isolation in predeterminated position, etches isolation deep trouth and as gate location；
The well region of the well region and the second conduction type of the first conduction type is arranged in the epitaxial layer by step S2；
Step S3, both sides and bottom are initially formed separation layer in the isolation deep trouth, are then filled out in the isolation deep trouth Fill polysilicon body；
Step S4 forms titanium suicide layer at the drain electrode, source electrode, substrate pole and the grid in the well region；
Step S5 carries out boron-phosphorosilicate glass deposit to form borophosphosilicate glass layer, and is set in the borophosphosilicate glass layer Set form the drain electrode, the source electrode, the grid and the substrate pole guide post and guide card.
Preferably, the 3D mos field effect transistor manufacturing methods, the step S3 specifically include with Lower step：
Step S31, in the outer layer growth silicon dioxide insulating layer；
Step S32 carries out polycrystalline silicon deposit so that form the polysilicon body in the isolation deep trouth, then aoxidize institute State polysilicon body surface；
Step S33, carries out the deposit of silicon nitride, then etches away the silicon nitride of horizontal plane, in the polysilicon body both sides Form isolation side walls.
Preferably, the 3D mos field effect transistor manufacturing methods, the step S5 specifically include with Lower step：
Step S51 after deposit forms the borophosphosilicate glass layer, carries out CMP polishings；
Step S52 etches the first guide post of receiving, the second guide post, third guide post and the 4th in the boron-phosphorosilicate glass and leads The contact hole of column deposits out first guide post, second guide post, the third guide post and the described 4th in the contact hole Guide post；
Step S53 carries out Metal deposition and etching in the boron-phosphorosilicate glass layer surface, is formed and the first guide post phase The first guide card even, the second guide card being connected with second guide post, the third guide card that is connected with the third guide post and with The 4th connected guide card of 4th guide post.
Preferably, the 3D mos field effect transistor manufacturing methods, the substrate layer are highly doped half Conductor, the epitaxial layer are low-doped semiconductor.
Preferably, 3D mos field effect transistor manufacturing methods, before step S1, described outer The surface for prolonging layer carries out shallow-trench isolation, and to form several isolation shallow slots, the position of the deep trench isolation is the isolation shallow slot Place.
Preferably, the 3D mos field effect transistor manufacturing methods, the cross section of the isolation deep trouth For V-shaped.
Preferably, the 3D mos field effect transistor manufacturing methods, first guide post, described second Guide post, the third guide post and the 4th guide post are tungsten metal.
Preferably, the 3D mos field effect transistor manufacturing methods, first guide card, described second Guide card, the third guide card and the 4th guide card are tungsten metal.
The present invention relates to a kind of 3D mos field effect transistor, wherein including：
Substrate layer is formed by the semiconductor material with the first conduction type；
Epitaxial layer, the epitaxial layer are set to above the substrate layer, the conduction type of the epitaxial layer and the substrate The conduction type of layer is identical, the well region of well region and the second conduction type equipped with the first conduction type in the epitaxial layer；
Borophosphosilicate glass layer, the borophosphosilicate glass layer are set to above the epitaxial layer；
Drain electrode, grid, source electrode and substrate pole are equipped in the well region successively；
The grid includes：
First guide card, first guide card are set to the borophosphosilicate glass layer upper surface；
First guide post, first guide post are arranged in the borophosphosilicate glass layer；
Polysilicon body, the polysilicon body cross section are V-shaped, and the tip of the polysilicon body is embedded at the epitaxial layer In.
Preferably, 3D mos field effect transistor, wherein the drain electrode includes：
Second guide card, second guide card are set to the boron-phosphorosilicate glass layer surface；
Second guide post, second guide post are arranged in the borophosphosilicate glass layer, second guide post both ends respectively with Second guide card is connected with the epitaxial layer；
The source electrode includes：
Third guide card, the third guide card are set to the boron-phosphorosilicate glass layer surface；
Third guide post, the third guide post are arranged in the borophosphosilicate glass layer, third guide post both ends respectively with The third guide card is connected with the epitaxial layer；
The substrate pole includes：
4th guide card, the 4th guide card are set to the boron-phosphorosilicate glass layer surface；
4th guide post, the 4th guide post are arranged in the borophosphosilicate glass layer, the 4th guide post both ends respectively with 4th guide card is connected with the epitaxial layer.
The advantageous effect of above-mentioned technical proposal is：The present invention increases conducting channel, enhances the effect of the control of grid, Leakage current and power consumption are reduced, production cost is reduced.
Description of the drawings
Fig. 1 is in the preferred embodiment of the present invention, and a kind of 3D MOSFET structures show It is intended to；
Fig. 2 is 3D NMOSFET output characteristic curves in the preferred embodiment of the present invention；
Fig. 3 is 3D NMOSFET transfer characteristic curves in the preferred embodiment of the present invention；
Fig. 4 is 3D PMOSFET output characteristic curves in the preferred embodiment of the present invention；
Fig. 5 is 3D PMOSFET transfer characteristic curves in the preferred embodiment of the present invention；
Fig. 6 is a kind of 3D mos field effect transistor manufacturer in the preferred embodiment of the present invention Method flow diagram；
Fig. 7 is step S3 specific steps flow diagrams in the preferred embodiment of the present invention；
Fig. 8 is step S5 specific steps flow diagrams in the preferred embodiment of the present invention；
Fig. 9 is to deposit silica schematic diagram in the preferred embodiment of the present invention；
Figure 10 is deep trench isolation schematic diagram in the preferred embodiment of the present invention；
Figure 11 is the well region position of the well region of the first conduction type and the second conduction type in the preferred embodiment of the present invention Set schematic diagram；
Figure 12 is silicon dioxide insulating layer position view in the preferred embodiment of the present invention；
Figure 13 is polysilicon body position view in the preferred embodiment of the present invention；
Figure 14 is isolation side walls position view in the preferred embodiment of the present invention；
Figure 15 is the first conductivity type regions and the signal of the second conductivity type regions in the preferred embodiment of the present invention Figure；
Figure 16 is titanium suicide layer position view in the preferred embodiment of the present invention；
Figure 17 is borophosphosilicate glass layer position view in the preferred embodiment of the present invention；
Figure 18 is guide post position view in the preferred embodiment of the present invention；
Figure 19 is 3D mos field effect transistor finished products signal in the preferred embodiment of the present invention Figure；
In figure：1 substrate layer, 2 epitaxial layers, 3 borophosphosilicate glass layers, 4 grids, 5 drain electrodes, 6 source electrodes, 7 substrate poles, 8 titanium dioxides Silicon insulating layer, 9 titanium suicide layers, the well region of 10 first conduction types, the well region of 11 second conduction types, 12 first conduction types Region, 13 second conductivity type regions, 14 isolation deep trouths, 15 isolation shallow slots, 16 isolation side walls, 401 first guide cards, 402 first Guide post, 403 polysilicon bodies, 501 second guide cards, 502 second guide posts, 601 third guide cards, 602 third guide posts, 701 the 4th guide cards, 702 the 4th guide posts.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of not making creative work it is all its His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase Mutually combination.
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
The first conduction type p-type in the present embodiment, the second conduction type are N-type.
As shown in Figure 1, the present embodiment is related to a kind of 3D mos field effect transistor (Metal-Oxide- Semiconductor Field Effect Transistor, MOSFET), including：Substrate layer 1, by having the first conduction type Semiconductor material formed；Epitaxial layer 2, epitaxial layer 2 are set to 1 top of substrate layer, conduction type and the substrate layer 1 of epitaxial layer 2 Conduction type it is identical, the well region 11 of well region 10 and the second conduction type equipped with the first conduction type in epitaxial layer 2；Boron phosphorus silicon Glassy layer 3, borophosphosilicate glass layer 3 are set to 2 top of epitaxial layer；Drain electrode 5, grid 4, source electrode 6 and substrate are equipped in well region successively Pole 7.Substrate layer 1 is high doping semiconductor, and epitaxial layer 2 is low-doped semiconductor.It is equipped between polysilicon body 403 and epitaxial layer 2 Silicon dioxide insulating layer 8.The doping concentration of high doping semiconductor be more than low-doped semiconductor concentration, corresponding doping concentration compared with High semiconductor is high doping semiconductor, and doping concentration is relatively low for low-mix semiconductor.
It is 3D NMOSFET, position that drain electrode 5, grid 4, source electrode 6 and substrate pole 7, which are set to the well region 10 of the first conduction type, In the well region 11 of the second conduction type be 3D PMOSFET.
Grid 4 includes：First guide card 401, the first guide card 401 are set to 3 upper surface of borophosphosilicate glass layer；First guide post 402, the first guide post 402 is arranged in borophosphosilicate glass layer 3；Polysilicon body 403,403 cross section of polysilicon body is V-shaped, more The tip of crystal silicon body 403 is embedded in epitaxial layer 2；First guide post, 402 both ends respectively with the first guide card 401 and polysilicon body 403 It is connected.
Drain electrode 5 includes：Second guide card 501, the second guide card 501 are set to 3 surface of borophosphosilicate glass layer；Second guide post 502, Second guide post 502 is arranged in borophosphosilicate glass layer 3,502 both ends of the second guide post respectively with 2 phase of the second guide card 501 and epitaxial layer Even.
Source electrode 6 includes：Third guide card 601, third guide card 601 are set to 3 surface of borophosphosilicate glass layer；Third guide post 602, Third guide post 602 is arranged in borophosphosilicate glass layer 3,602 both ends of third guide post respectively with 2 phase of third guide card 601 and epitaxial layer.
Substrate pole 7 includes：4th guide card 701, the 4th guide card 701 are set to 3 surface of borophosphosilicate glass layer；4th guide post 702, the 4th guide post 702 is arranged in borophosphosilicate glass layer 3,702 both ends of the 4th guide post respectively with the 4th guide card 701 and epitaxial layer 2 are connected.
It is equipped with titanium suicide layer 9 between second guide post 502 and epitaxial layer 2, is equipped between the first guide post 402 and epitaxial layer 2 Titanium suicide layer 9 is equipped with titanium suicide layer 9, between the 4th guide post 702 and epitaxial layer 2 between third guide post 602 and epitaxial layer 2 Equipped with titanium suicide layer 9.
In the well region 10 of the first conduction type, region corresponding with drain electrode 5 and source electrode 6 is second conductive in epitaxial layer 2 Type area 13, corresponding substrate pole 7 is then the first conductivity type regions 12.In the well region 11 of the second conduction type, extension Region corresponding with drain electrode 5 and source electrode 6 is the first conductivity type regions 12 in layer 2, and corresponding substrate pole 7 is then the second conductive-type Type region 13.
As shown in figures 2-3, the 3D MOSFET for being in the well region 10 of the first conduction type are 3D NMOSFET, are in grid When 4 voltage Vgs=0,3D NMOSFET are in by state, and the electric current Ids=0 of source electrode 6 is arrived in drain electrode 5.When 0<Vgs<When Vth, Start to generate conducting channel between the drain electrode 5 and source electrode 6 of 3D NMOSFET, it is threshold voltage that Ids, which is almost 0, Vth, at this time.When Vgs>When Vth, the conducting channel between drain electrode 5 and source electrode 6 is formed, and electric current can be generated.Work as Vgs>Vth, drain 5 voltage Vds> When 0, Ids starts to increase rapidly, and works as Vgs-Vth>When Vds, 3D NMOSFET are in variable resistance area, at this time as Vds increases, Ids linearly increases.Work as Vgs-Vth<When Vds, 3D NMOSFET are in saturation region, and at this time as Vds increases, Ids slowly increases Greatly.When Vds is more than the breakdown voltage of 3D NMOSFET, 3D NMOSFET are breakdown, and Ids rises rapidly, may burn out at this time Device.
As shown in Figures 4 and 5, when source electrode 6, drain electrode 5, grid 4 and substrate pole 7 are in the well region 11 of the second conduction type, 3D MOSFET is 3D PMOSFET.When 4 voltage Vgs=Vbs of grid, 3D PMOSFET are in by state, drain electrode 5 to source electrode 6 Electric current Ids=0.When 0>Vgs>When Vth, start to generate conducting channel between 3D PMOSFET drain electrodes 5 and source electrode 6, Ids is several at this time It is 0.Work as Vgs<When Vth, the conducting channel between drain electrode 5 and source electrode 6 is formed, and electric current can be generated.Work as Vgs<Vth, drain-source Voltage Vds<When 0, Ids starts to increase rapidly, and works as Vgs-Vth<When Vds, 3D PMOSFET are in variable resistance area, at this time with Vds reduces, and Ids linearly increases.Work as Vgs-Vth>When Vds, 3D PMOSFET are in saturation region, at this time as Vds reduces, Ids slowly increases；When Vds is less than the breakdown voltage of 3D PMOSFET, 3D PMOSFET are breakdown, and Ids rises rapidly, at this time Device may be burnt out.
As shown in fig. 6, the present invention relates to a kind of 3D mos field effect transistor manufacturing methods, including with Lower step：
As shown in figure 9, shallow-trench isolation is carried out on the surface of epitaxial layer 2, to form several isolation shallow slots 15.
Silica membrane and deposit silicon nitride are formed in 2 surface thermal oxide of epitaxial layer, and carries out shallow-trench isolation, is etched Silica is deposited after isolation shallow slot 15.Select substrate layer 1 for highly doped silicon, epitaxial layer 2 is low-doped silicon.In 1 table of substrate layer Face thermal oxide forms SiO2Film deposits Si3N4, 15 position of isolation shallow slot is defined using photoresist, is being ready for shallow-trench isolation Place etches away SiO2And Si3N4, then carry out isolation shallow slot 15 and etch, after removing photoresist, deposit SiO2。
Step S1 carries out deep trench isolation in predeterminated position, etches isolation deep trouth and as gate location.
As shown in Figure 10, deep trench isolation is carried out in predeterminated position, etches isolation deep trouth 14.It is defined using photoresist deep Trench isolations position carries out isolation deep trouth 14 in the position for originally carrying out shallow-trench isolation and etches, used after removing photoresist again Chemically mechanical polishing grinds off the oxide layer on surface, recycles dry etching, removes Si3N4, that is, complete shallow-trench isolation and deep trench Isolation.
The well region 11 of the well region 10 and the second conduction type of the first conduction type is arranged in epitaxial layer 2 by step S2.
As shown in figure 11, the well region 10 for the first conduction type being arranged in epitaxial layer 2 is the trap of p-well region and the second conduction type Area 11 is N well regions.It injects to form local N well regions using high energy phosphonium ion, for manufacturing 3D PMOSFET, using high energy boron ion Injection forms local p-well region, for manufacturing 3D NMOSFET, finally removes photoresist, anneals, complete N well regions and p-well Area.
Step S3, both sides and bottom are initially formed separation layer in deep trouth 14 is isolated, and are then filled in deep trouth 14 is isolated more Crystal silicon body 43.
As shown in fig. 7, step S3 specifically includes following steps：
Step S31 grows silicon dioxide insulating layer 8 in epitaxial layer 2.
As shown in figure 12, sacrificial oxide layer is grown, 1 surface defect of substrate layer is captured, then grows silicon dioxide insulating layer 8；
Step S32 carries out polycrystalline silicon deposit as shown in figure 13 so that polysilicon body 403 is formed in isolation deep trouth 14, and 403 surface of oxidation polysilicon body afterwards.
Step S33, carries out the deposit of silicon nitride, then etches away the silicon nitride of horizontal plane, in 403 both sides shape of polysilicon body At isolation side walls 16.
As shown in figure 14, the deposit of silicon nitride is carried out, and etches away the silicon nitride of horizontal surface, in 403 liang of polysilicon body Side forms isolation side walls 16.Low energy, shallow depth, low-doped arsenic ion are carried out to 3D NMOSFET and 3D PMOSFET respectively And BF2 +Ion implanting, the hot carrier's effect for weakening 4 corresponding region of grid remove photoresist, then carry out Si again3N4 Deposit, and etch away the Si of horizontal surface3N4, it is isolation side walls 16 to leave part, right for being accurately positioned transistor source 6 Answer the ion implanting in region.
Step S4 forms titanium suicide layer 9 at the drain electrode 5, source electrode 6, substrate pole 7 and grid 4 in well region.
As shown in figure 15, the drain electrode 5 in well region, source electrode 6, grid 4 and 7 corresponding position of substrate pole carry out ion implanting.First The corresponding region of source electrode 6, drain electrode 5 and substrate pole 7 is defined with photoresist.Carry out shallow depth, the arsenic ion of heavy doping injects, shape At p type island region domain.Carry out shallow depth, heavy doping BF2 +Ion implanting forms n-type region in epitaxial layer 2, finally removes photoetching Glue is simultaneously annealed.
As shown in figure 16, titanium is first deposited, then carries out titanium etching, retains titanium disilicide and forms titanium suicide layer 9, as ohm Contact.
Step S5 carries out boron-phosphorosilicate glass deposit to form borophosphosilicate glass layer 3, and is arranged in borophosphosilicate glass layer 3 Form the guide post and guide card of drain 5, source electrode 6, grid 4 and substrate pole 7.
As shown in figure 8, step S5 specifically includes following steps：
Step S51 carries out boron-phosphorosilicate glass deposit to form borophosphosilicate glass layer 3, and carry out CMP as shown in figure 17 (Chemical Mechanical Polishing, chemically mechanical polishing) polishing.
Step S52 goes out to accommodate the first guide post 402, the second guide post in 3 surface etch of borophosphosilicate glass layer as shown in figure 18 502, the contact hole of third guide post 602 and the 4th guide post 702 carries out tungsten deposit in contact hole, deposits out the first guide post 402, the Two guide posts 502, third guide post 602 and the 4th guide post 702.
Step S53 carries out Metal deposition and etching on 3 surface of borophosphosilicate glass layer, forms the first guide card as shown in figure 19 401, the second guide card 501, third guide card 601 and the 4th guide card 701.Obtain complete 3D a NMOSFET and 3D PMOSFET。
Compared with prior art, the present invention increases conducting channel, enhances the effect of the control of grid, reduces electric leakage Stream and power consumption, reduce production cost.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.

Claims (10)

1. a kind of 3D mos field effect transistor manufacturing method, which is characterized in that a previously prepared substrate layer, And an epitaxial layer is prepared in the upper surface of the substrate layer, it is further comprising the steps of：
Step S1 carries out deep trench isolation in predeterminated position, etches isolation deep trouth and as gate location；
The well region of the well region and the second conduction type of the first conduction type is arranged in the epitaxial layer by step S2；
Step S3, both sides and bottom are initially formed separation layer in the isolation deep trouth, are then filled in the isolation deep trouth more Crystal silicon body；
Step S4 forms titanium suicide layer at the drain electrode, source electrode, substrate pole and the grid in the well region；
Step S5 carries out boron-phosphorosilicate glass deposit to form borophosphosilicate glass layer, and the setting group in the borophosphosilicate glass layer At the drain electrode, the guide post and guide card of the source electrode, the grid and the substrate pole.
2. 3D mos field effect transistor manufacturing method according to claim 1, characterized in that described Step S3 specifically includes following steps：
Step S31, in the outer layer growth silicon dioxide insulating layer；
Step S32 carries out polycrystalline silicon deposit so that form the polysilicon body in the isolation deep trouth, then aoxidize described more Crystal silicon body surface face；
Step S33, carries out the deposit of silicon nitride, then etches away the silicon nitride of horizontal plane, is formed in the polysilicon body both sides Isolation side walls.
3. 3D mos field effect transistor manufacturing method according to claim 1, characterized in that described Step S5 specifically includes following steps：
Step S51 after deposit forms the borophosphosilicate glass layer, carries out CMP polishings；
Step S52 is etched in the boron-phosphorosilicate glass and is accommodated the first guide post, the second guide post, third guide post and the 4th guide post Contact hole deposits out first guide post, second guide post, the third guide post and the described 4th in the contact hole and leads Column；
Step S53 carries out Metal deposition and etching in the boron-phosphorosilicate glass layer surface, what formation was connected with first guide post First guide card, the second guide card being connected with second guide post, the third guide card being connected with the third guide post and with it is described The 4th connected guide card of 4th guide post.
4. 3D mos field effect transistor manufacturing method according to claim 1, characterized in that described Substrate layer is high doping semiconductor, and the epitaxial layer is low-doped semiconductor.
5. 3D mos field effect transistor manufacturing method according to claim 1, characterized in that in step Before rapid S1, shallow-trench isolation is carried out on the surface of the epitaxial layer, to form several isolation shallow slots, the position of the deep trench isolation It is set at the isolation shallow slot.
6. 3D mos field effect transistor manufacturing method according to claim 1, characterized in that described The cross section that deep trouth is isolated is V-shaped.
7. 3D mos field effect transistor manufacturing method according to claim 3, characterized in that described First guide post, second guide post, the third guide post and the 4th guide post are tungsten metal.
8. 3D mos field effect transistor manufacturing method according to claim 3, characterized in that described First guide card, second guide card, the third guide card and the 4th guide card are tungsten metal.
9. a kind of 3D mos field effect transistor, which is characterized in that including：
Substrate layer is formed by the semiconductor material with the first conduction type；
Epitaxial layer, the epitaxial layer are set to above the substrate layer, the conduction type of the epitaxial layer and the substrate layer Conduction type is identical, the well region of well region and the second conduction type equipped with the first conduction type in the epitaxial layer；
Borophosphosilicate glass layer, the borophosphosilicate glass layer are set to above the epitaxial layer；
Drain electrode, grid, source electrode and substrate pole are equipped in the well region successively；
The grid includes：
First guide card, first guide card are set to the borophosphosilicate glass layer upper surface；
First guide post, first guide post are arranged in the borophosphosilicate glass layer；
Polysilicon body, the polysilicon body cross section are V-shaped, and the tip of the polysilicon body is embedded in the epitaxial layer.
10. 3D mos field effect transistor according to claim 7, characterized in that the drain electrode packet It includes：
Second guide card, second guide card are set to the boron-phosphorosilicate glass layer surface；
Second guide post, second guide post are arranged in the borophosphosilicate glass layer, second guide post both ends respectively with it is described Second guide card is connected with the epitaxial layer；
The source electrode includes：
Third guide card, the third guide card are set to the boron-phosphorosilicate glass layer surface；
Third guide post, the third guide post are arranged in the borophosphosilicate glass layer, third guide post both ends respectively with it is described Third guide card is connected with the epitaxial layer；
The substrate pole includes：
4th guide card, the 4th guide card are set to the boron-phosphorosilicate glass layer surface；
4th guide post, the 4th guide post are arranged in the borophosphosilicate glass layer, the 4th guide post both ends respectively with it is described 4th guide card is connected with the epitaxial layer.
CN201810187224.6A 2018-03-07 2018-03-07 A kind of 3D mos field effect transistor and its manufacturing method Pending CN108447910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810187224.6A CN108447910A (en) 2018-03-07 2018-03-07 A kind of 3D mos field effect transistor and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810187224.6A CN108447910A (en) 2018-03-07 2018-03-07 A kind of 3D mos field effect transistor and its manufacturing method

Publications (1)

Publication Number Publication Date
CN108447910A true CN108447910A (en) 2018-08-24

Family

ID=63193546

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810187224.6A Pending CN108447910A (en) 2018-03-07 2018-03-07 A kind of 3D mos field effect transistor and its manufacturing method

Country Status (1)

Country Link
CN (1) CN108447910A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040119091A1 (en) * 2002-12-18 2004-06-24 Denso Corporation Semiconductor device and method of manufacturing the same
US20170323970A1 (en) * 2016-05-06 2017-11-09 Silicet, LLC Devices and methods for a power transistor having a schottky or schottky-like contact
CN107425048A (en) * 2016-05-24 2017-12-01 台湾积体电路制造股份有限公司 Transistor and its manufacture method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040119091A1 (en) * 2002-12-18 2004-06-24 Denso Corporation Semiconductor device and method of manufacturing the same
US20170323970A1 (en) * 2016-05-06 2017-11-09 Silicet, LLC Devices and methods for a power transistor having a schottky or schottky-like contact
CN107425048A (en) * 2016-05-24 2017-12-01 台湾积体电路制造股份有限公司 Transistor and its manufacture method

Similar Documents

Publication Publication Date Title
CN205282482U (en) Integrated circuit transistor device and integrated circuit
JP6492068B2 (en) Vertical trench MOSFET devices in integrated power technology
CN101183683B (en) Method and structure for reducing floating body effects in mosfet devices
CN104752492B (en) The method and semiconductor devices being used for producing the semiconductor devices
CN104733531A (en) Dual oxide trench gate power mosfet using oxide filled trench
CN106571394B (en) Power device and its manufacture method
CN102891087A (en) Semiconductor device structure insulated from a bulk silicon substrate and method of forming the same
CN101346819B (en) Semiconductor device with field plate and method
CN103855222A (en) Semiconductor Device and Method of Manufacturing Semiconductor Device
CN110223919A (en) A kind of shield grid groove power MOSFET structure and preparation method thereof reducing conducting resistance
CN113611750A (en) SOI transverse shimming high-voltage power semiconductor device and manufacturing method and application thereof
CN102779843B (en) Transistor and forming method thereof
CN111403472A (en) Trench gate trench field plate vertical MOSFET
CN104253050B (en) A kind of manufacture method of grooved lateral MOSFET device
CN107924915A (en) Embedded SiGe techniques for multi thresholds PMOS transistor
CN108447910A (en) A kind of 3D mos field effect transistor and its manufacturing method
CN106601795B (en) A kind of trench field effect transistor and its manufacturing method
US8530967B2 (en) Lateral insulated-gate bipolar transistor and manufacturing method thereof
KR100439189B1 (en) Vertical type transistor and fabrication method thereof
CN103779416B (en) The power MOSFET device of a kind of low VF and manufacture method thereof
CN105378933B (en) Semiconductor device
CN102956704A (en) Quasi-vertical power MOSFET and methods of forming the same
CN110021658A (en) Deep oxidation groove landscape insulation bar double-pole-type transistor and preparation method thereof with anode in short circuit NPN pipe structure
CN111244154A (en) PMOS device and manufacturing method thereof
CN105336612A (en) Planar VDMOS device and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180824

WD01 Invention patent application deemed withdrawn after publication