CN108447862B - Reconfigurable on-chip integrated transformer and method for adjusting inductance value of signal line thereof - Google Patents
Reconfigurable on-chip integrated transformer and method for adjusting inductance value of signal line thereof Download PDFInfo
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- CN108447862B CN108447862B CN201810164198.5A CN201810164198A CN108447862B CN 108447862 B CN108447862 B CN 108447862B CN 201810164198 A CN201810164198 A CN 201810164198A CN 108447862 B CN108447862 B CN 108447862B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The invention discloses a reconfigurable on-chip integrated transformer and a regulating method thereof, wherein the reconfigurable on-chip integrated transformer comprises two half-turn spiral primary side inductors and two half-turn spiral secondary side inductors, six metal strips which are positioned below the primary side inductors and composed of bottom layer metals and respectively form primary side metal strip assemblies and secondary side metal strip assemblies, two grounding plates which are symmetrically distributed on the outer sides of the bottom layer metal strip assemblies and composed of bottom layer metals, and electromagnetic side walls which are symmetrically distributed on the outer sides of the grounding plates and composed of top layer metals and bottom layer metals through via holes, wherein the primary side metal strip assemblies and the secondary side metal strip assemblies which are distributed below signal lines are connected into two half-turn spiral metal strips through four CMOS switches and are connected to the grounding plates through eight CMOS switches. According to the invention, the on-off state of the CMOS switch is changed by changing the direct-current voltage loaded on the CMOS switch, so that the connection state of the bottom layer metal strip and the grounding plate is changed, and the inductance value of the inductor is changed.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an on-chip integrated transformer, in particular to a reconfigurable on-chip integrated transformer and a regulating method thereof.
Background
In recent years, with the rapid development of wireless communication technology, on-chip integrated transformers are increasingly applied to various radio frequency integrated circuit designs, and the on-chip transformers have become research hotspots as important components of circuits such as matching networks, power synthesizers and on-chip baluns.
With the reduction of the CMOS process size, the mechanism of the millimeter wave on-chip integrated transformer becomes more complex, and meanwhile, the on-chip integrated transformer occupies most of the area of a radio frequency integrated circuit layout, which seriously affects the performance of the whole system. Therefore, the present inventors propose a technical improvement of the present application.
Disclosure of Invention
The first purpose of the invention is to provide a reconfigurable on-chip integrated transformer, which can adjust the inductance value by reconfiguring the structure of the on-chip integrated transformer after being applied to a flow sheet in a radio frequency integrated circuit, thereby having better use value.
The second purpose of the invention is to provide a method for adjusting the inductance value of the signal line of the reconfigurable on-chip integrated transformer based on the structure.
In order to achieve the first object of the present invention, the technical solution of the present invention includes a plurality of metal layers distributed from top to bottom, wherein the metal layer located at the uppermost layer is a top metal layer, and the metal layer located at the lowermost layer is a bottom metal layer, and the present invention is characterized in that:
two signal lines are arranged on the top metal layer, and the two signal lines are a half-turn primary side inductor and a half-turn secondary side inductor which are formed by part of top metal on the top metal layer;
a primary side bottom layer metal strip assembly and a secondary side bottom layer metal strip assembly which are respectively right corresponding to the positions right below the two signal lines are arranged on the bottom layer metal layer, and the primary side bottom layer metal strip assembly and the secondary side bottom layer metal strip assembly respectively comprise a left side bottom layer metal strip, a middle bottom layer metal strip and a right side bottom layer metal strip which are formed by bottom layer metal;
the primary side grounding plate and the secondary side grounding plate which are respectively corresponding to the outer sides of the primary side bottom layer metal strip assembly and the secondary side bottom layer metal strip assembly and are formed by bottom layer metal are also arranged on the bottom layer metal layer, and the primary side grounding plate and the secondary side grounding plate are symmetrically arranged;
four metal side walls formed by connecting top-layer metal to bottom-layer metal through via holes are arranged at four corners of the reconfigurable on-chip integrated transformer, and each two metal side walls are respectively and symmetrically connected to the left side and the right side of the primary side grounding plate or the secondary side grounding plate;
the left bottom layer metal strip, the middle bottom layer metal strip and the right bottom layer metal strip in the primary side bottom layer metal strip assembly are sequentially connected through CMOS switches, and the left bottom layer metal strip, the middle bottom layer metal strip and the right bottom layer metal strip in the secondary side bottom layer metal strip assembly are sequentially connected through CMOS switches;
the left end and the right end of the left bottom metal strip in the primary bottom metal strip assembly are respectively connected with the corresponding positions of the primary grounding plate through a CMOS switch, the right end of the middle bottom metal strip in the primary bottom metal strip assembly is connected with the corresponding positions of the primary grounding plate through a CMOS switch, and the right end of the right bottom metal strip in the primary bottom metal strip assembly is connected with the corresponding positions of the primary grounding plate through a CMOS switch;
the left end and the right end of a left bottom metal strip in the secondary bottom metal strip assembly are connected with corresponding positions of the secondary ground plate through a CMOS switch respectively, the right end of a middle bottom metal strip in the secondary bottom metal strip assembly is connected with corresponding positions of the secondary ground plate through a CMOS switch, and the right end of a right bottom metal strip in the secondary bottom metal strip assembly is connected with corresponding positions of the secondary ground plate through a CMOS switch.
The primary side inductor and the secondary side inductor are further arranged to be half-turn spiral inductors.
The metal layer has six layers, and the through holes of two adjacent metal layers have 5 layers from top to bottom.
The second invention of the present invention is to provide a method for adjusting the inductance of the signal line of the on-chip integrated transformer based on the CMOS switch, which controls the on-off state of the two terminals of the CMOS switch by controlling the external voltage of the control terminal of the CMOS switch, and further changes the on-off state between each bottom layer metal strip in the primary bottom layer metal strip assembly and the secondary bottom layer metal strip assembly and the primary ground plate and/or the secondary ground plate, and further changes the inductance of the two signal lines.
The structure of the CMOS switch is to change the (gate) control voltage of the CMOS switch to open or close the switch (drain and source), thereby connecting and disconnecting the bottom metal strips under the signal line or the ground plate.
The invention has the advantages that: the invention provides an on-chip integrated transformer comprising on-chip CMOS switches, the inductance value of the transformer is changed by changing the control voltage of the on-chip CMOS switches, and the inductance value is continuously varied in a plurality of equal intervals. Therefore, when the on-chip integrated transformer is applied to a radio frequency integrated circuit, the inductance value can still be conveniently adjusted by reconfiguring the structure of the on-chip integrated transformer after the chip is processed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a metal layer and a via in an embodiment of the invention;
FIG. 2 is a top view of an on-chip integrated transformer including CMOS switches according to an embodiment of the present invention;
FIG. 3 is a top view of the bottom metal layer of an on-chip integrated transformer including CMOS switches according to an embodiment of the present invention;
fig. 4 is a perspective view of an on-chip integrated transformer including CMOS switches according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
The terms of direction and position of the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "top", "bottom", "side", etc., refer to the direction and position of the attached drawings. Accordingly, the use of directional and positional terms is intended to illustrate and understand the present invention and is not intended to limit the scope of the present invention.
In the embodiment of the present invention, as shown in fig. 1, the on-chip integrated transformer of the present embodiment has six metal structures from top to bottom, where 6 in fig. 1 corresponds to a top metal layer, 5 corresponds to a fifth metal layer, 4 corresponds to a fourth metal layer, 3 corresponds to a third metal layer, 2 corresponds to a second metal layer, and 1 corresponds to a bottom metal layer. The two adjacent metal layers are connected by metal via holes, and 5 layers of via holes are formed from top to bottom, namely e, d, c, b and a in the graph 1; the thickness of each metal layer and the via hole is different according to different CMOS processes; the present invention should not be limited to the number of metal layers, the thickness of each metal layer, the number of via holes, and the thickness of each via hole shown in the embodiment and the drawings.
As shown in fig. 2, the signal lines 14 and 20 are two signal lines formed by the topmost metal, which are half-turn spiral primary and secondary inductors, respectively, as shown.
As shown in fig. 3, the ground plate of this embodiment includes a primary side bottom layer metal block 9 and a secondary side bottom layer metal block 30, which are symmetrically distributed on two sides of two signal lines, in this embodiment, corresponding to the claims, the primary side bottom layer metal block 9 is also referred to as a primary side ground plate, and the secondary side bottom layer metal block 30 is also referred to as a secondary side ground plate.
As shown in fig. 3, the multilayer metal strips 7, 8, 31, 32 of this embodiment are metal sidewalls, and are connected from the top metal layer to the bottom metal layer through vias between the layers, and are symmetrically connected to both sides of the primary bottom metal block 9 and the secondary bottom metal block 30.
As shown in fig. 3, the primary side bottom layer metal strip assembly includes a left side bottom layer metal strip 15, a middle bottom layer metal strip 17, and a right side bottom layer metal strip 19, the secondary side bottom layer metal strip assembly includes a left side bottom layer metal strip 22, a middle bottom layer metal strip 24, and a right side bottom layer metal strip 26, and the primary side bottom layer metal strip assembly and the secondary side bottom layer metal strip assembly are respectively located right below the two signal lines 14 and 20.
As shown in fig. 2 and 3, a left bottom metal strip 15 in the primary side bottom metal strip assembly is connected to a primary side bottom metal block 9 through two CMOS switches 10 and 11, a middle bottom metal strip 17 in the primary side bottom metal strip assembly is connected to a left bottom metal strip 15 and a right bottom metal strip 19 in the primary side bottom metal strip assembly through two CMOS switches 16 and 18, respectively, and is connected to the primary side bottom metal strip 9 through an upper right CMOS switch 12, and the right bottom metal strip 19 is connected to the primary side bottom metal block 9 through a right CMOS switch 13; the left bottom metal strip 22 in the secondary bottom metal strip assembly is connected with a secondary bottom metal block 30 through CMOS switches 21 and 28 at two ends, the middle bottom metal strip 24 is respectively connected with the left bottom metal strip 22 and the right bottom metal strip 26 through left and right CMOS switches 23 and 25, and is connected with the secondary bottom metal strip 30 through a right lower CMOS switch 29, the right bottom metal strip 26 is connected with the secondary bottom metal strip 30 through a right upper CMOS switch 27, and direct current voltages loaded on the CMOS switches 10, 11, 12, 13, 16, 18, 21, 23, 25, 27, 28 and 29 are controlled to change the switch states, so that the connection states among the left bottom metal strip 15, the middle bottom metal strip 17 and the right bottom metal strip 19 in the primary bottom metal strip assembly and the primary bottom metal block 9 are changed, and the connection states among the left bottom metal strip 22, the right bottom metal strip 19 in the secondary bottom metal strip assembly, The connection between the middle bottom layer metal strip 24 and the right bottom layer metal strip 26 and the secondary side bottom layer metal block 30.
Each switch symbol in fig. 2 and 3 represents a CMOS switch, and the present invention should not be limited to the structure of the CMOS switch of this embodiment, but may include various CMOS switch circuits. The invention should not be limited to the connection of the wires, the specific metal layer, of this embodiment.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.
Claims (3)
1. The utility model provides a reconfigurable on-chip integrated transformer, is including the multilayer metal layer that from top to bottom distributes the setting, and wherein the metal layer that is located the superiors is the top layer metal layer, and the metal layer that is located the bottommost layer is bottom metal layer, its characterized in that: two signal lines are arranged on the top metal layer, and the two signal lines are both primary side inductors and secondary side inductors which are formed by partial top metal on the top metal layer; a primary side bottom layer metal strip assembly and a secondary side bottom layer metal strip assembly which are respectively right corresponding to the positions right below the two signal lines are arranged on the bottom layer metal layer, and the primary side bottom layer metal strip assembly and the secondary side bottom layer metal strip assembly respectively comprise a left side bottom layer metal strip, a middle bottom layer metal strip and a right side bottom layer metal strip which are formed by bottom layer metal; the primary side grounding plate and the secondary side grounding plate which are respectively corresponding to the outer sides of the primary side bottom layer metal strip assembly and the secondary side bottom layer metal strip assembly and are formed by bottom layer metal are also arranged on the bottom layer metal layer, and the primary side grounding plate and the secondary side grounding plate are symmetrically arranged; four metal side walls formed by connecting top-layer metal to bottom-layer metal through via holes are arranged at four corners of the reconfigurable on-chip integrated transformer, the left side and the right side of the primary grounding plate and the left side and the right side of the secondary grounding plate are both connected with the metal side walls, and the two metal side walls connected to the same grounding plate are symmetrically arranged; the left bottom layer metal strip, the middle bottom layer metal strip and the right bottom layer metal strip in the primary side bottom layer metal strip assembly are sequentially connected through CMOS switches, and the left bottom layer metal strip, the middle bottom layer metal strip and the right bottom layer metal strip in the secondary side bottom layer metal strip assembly are sequentially connected through CMOS switches; the left end and the right end of the left bottom metal strip in the primary bottom metal strip assembly are respectively connected with the corresponding positions of the primary grounding plate through a CMOS switch, the right end of the middle bottom metal strip in the primary bottom metal strip assembly is connected with the corresponding positions of the primary grounding plate through a CMOS switch, and the right end of the right bottom metal strip in the primary bottom metal strip assembly is connected with the corresponding positions of the primary grounding plate through a CMOS switch; the left end and the right end of a left bottom metal strip in the secondary bottom metal strip assembly are connected with corresponding positions of the secondary ground plate through a CMOS switch respectively, the right end of a middle bottom metal strip in the secondary bottom metal strip assembly is connected with corresponding positions of the secondary ground plate through a CMOS switch, and the right end of a right bottom metal strip in the secondary bottom metal strip assembly is connected with corresponding positions of the secondary ground plate through a CMOS switch.
2. The reconfigurable on-chip integrated transformer of claim 1, wherein: the primary side inductor and the secondary side inductor are half-turn spiral inductors.
3. A method of adjusting an inductance value of a signal line of the on-chip integrated transformer of claim 1 based on a CMOS switch, characterized in that: the on-off states of the two wiring electrodes of the CMOS switch are controlled by controlling the external voltage of the CMOS switch control electrode, so that the on-off states of the bottom metal strips of the primary bottom metal strip assembly and the primary grounding plate are changed, the on-off states of the bottom metal strips of the secondary bottom metal strip assembly and the secondary grounding plate are changed, and the inductance values of the two signal wires are changed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810164198.5A CN108447862B (en) | 2018-02-27 | 2018-02-27 | Reconfigurable on-chip integrated transformer and method for adjusting inductance value of signal line thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810164198.5A CN108447862B (en) | 2018-02-27 | 2018-02-27 | Reconfigurable on-chip integrated transformer and method for adjusting inductance value of signal line thereof |
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| Publication Number | Publication Date |
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| CN108447862A CN108447862A (en) | 2018-08-24 |
| CN108447862B true CN108447862B (en) | 2020-01-14 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6870456B2 (en) * | 1999-11-23 | 2005-03-22 | Intel Corporation | Integrated transformer |
| US6801114B2 (en) * | 2002-01-23 | 2004-10-05 | Broadcom Corp. | Integrated radio having on-chip transformer balun |
| CN101615892B (en) * | 2009-07-24 | 2011-07-13 | 中国科学院微电子研究所 | Radiofrequency power amplifier |
| CN102176453B (en) * | 2011-03-17 | 2013-04-24 | 杭州电子科技大学 | Vertical-structure on-chip integrated transformer |
| CN104637920B (en) * | 2015-01-15 | 2017-08-15 | 温州大学 | A kind of upper integrated single-ended inductor of adjustable of inductance value |
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Application publication date: 20180824 Assignee: Intelligent lock Research Institute of Wenzhou University Assignor: Wenzhou University Contract record no.: X2020330000086 Denomination of invention: Reconfigurable chip integrated transformer and its signal line inductance adjustment method Granted publication date: 20200114 License type: Common License Record date: 20201030 |