CN108429540B - Digital phase generator with low power consumption and high resolution - Google Patents
Digital phase generator with low power consumption and high resolution Download PDFInfo
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- CN108429540B CN108429540B CN201810151422.7A CN201810151422A CN108429540B CN 108429540 B CN108429540 B CN 108429540B CN 201810151422 A CN201810151422 A CN 201810151422A CN 108429540 B CN108429540 B CN 108429540B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00286—Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
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Abstract
The invention discloses a digital phase generator with low power consumption and high resolution, which comprises a signal injection circuit and a four-stage ring oscillator; the four-stage ring oscillator comprises a first delay unit, a second delay unit, a third delay unit and a fourth delay unit, the signal injection circuit comprises a first NMOS tube and a second NMOS tube, the grid electrode of the first NMOS tube is connected with the inverting end of an input signal, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is connected with the in-phase end of the input signal, and the source electrode is grounded; the drain electrode of the first NMOS tube is connected with the positive output end of the first delay unit, and the drain electrode of the second NMOS tube is connected with the negative output end of the first delay unit. The structure is realized based on an injection locking technology, the high-resolution phase interpolation function can be realized only by adjusting the frequency of the free oscillator of the ring oscillator, and the power consumption is very low.
Description
Technical Field
The invention belongs to the technical field of digital modulation, and particularly relates to a low-power-consumption high-resolution digital phase generator.
Background
The digital phase generator, also called digital time converter or digital delay line, generates a clock signal with a different delay or a different phase by changing the digital control signal. Digital phase generators have found wide application in clock recovery circuits, phase-locked loop feedback loops, direct frequency synthesizers, and polar modulation. The digital phase generator operates at a frequency close to the reference frequency in the phase locked loop, whereas in polar modulation systems and clock recovery circuits, the digital phase generator needs to operate at a frequency close to gigahertz.
The traditional digital phase generator based on the inverter delay chain has good linearity, but the gain of the traditional digital phase generator is seriously influenced by the process and the change of the power supply voltage, and the power consumption is very large, so that the application of the traditional digital phase generator is limited to a great extent. The phase generator based on phase interpolation has fixed gain, but the linearity is poor, and the power consumption cannot be reduced to be low even at high frequency. Therefore, how to design a digital phase generator with low power consumption and high resolution is an urgent research topic to be solved.
Disclosure of Invention
The invention aims to provide a low-power-consumption high-resolution digital phase generator which is realized based on an injection locking technology, can realize a high-resolution phase interpolation function only by adjusting the frequency of a free oscillator of a ring oscillator and has very low power consumption.
In order to achieve the above purpose, the solution of the invention is:
a digital phase generator with low power consumption and high resolution comprises a signal injection circuit and a four-stage ring oscillator, wherein the output end of the signal injection circuit is connected with the four-stage ring oscillator.
The four-stage ring oscillator comprises a first delay unit, a second delay unit, a third delay unit and a fourth delay unit, wherein the positive output end of the first delay unit is connected with the negative input end of the second delay unit, and the negative output end of the first delay unit is connected with the positive input end of the second delay unit; the positive output end of the second delay unit is connected with the negative input end of the third delay unit, and the negative output end of the second delay unit is connected with the positive input end of the third delay unit; the positive output end of the third delay unit is connected with the negative input end of the fourth delay unit, and the negative output end of the third delay unit is connected with the positive input end of the fourth delay unit; the positive output end of the fourth delay unit is connected with the positive input end of the first delay unit, and the negative output end of the fourth delay unit is connected with the negative input end of the first delay unit; the output end of the signal injection circuit is connected with the output end of the first delay unit.
The signal injection circuit comprises a first NMOS tube and a second NMOS tube, wherein the grid electrode of the first NMOS tube is connected with the inverting end of an input signal, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is connected with the in-phase end of the input signal, and the source electrode is grounded; the drain electrode of the first NMOS tube is connected with the positive output end of the first delay unit, and the drain electrode of the second NMOS tube is connected with the negative output end of the first delay unit.
The first delay unit, the second delay unit, the third delay unit and the fourth delay unit have the same structure and respectively comprise a first reference current source, a third NMOS tube, a fourth NMOS tube, a first resistor, a second resistor, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a first switch capacitor array, wherein the positive end of the first reference current source is connected with the source electrodes of the third NMOS tube and the fourth NMOS tube, and the negative end of the first reference current source is grounded; the drain electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the third NMOS tube is connected with the positive input end; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the grid electrode of the fourth NMOS tube is connected with the input negative end; one end of the first resistor is connected with the positive input end, and the other end of the first resistor is connected with the negative output end; one end of the second resistor is connected with the input negative end, and the other end of the second resistor is connected with the output positive end; the source electrode of the first PMOS tube is connected with a power supply, the grid electrode of the first PMOS tube is connected with the positive input end, and the drain electrode of the first PMOS tube is connected with the negative output end; the source electrode of the second PMOS tube is connected with a power supply, the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube; the source electrode of the fourth PMOS tube is connected with the power supply, the grid electrode of the fourth PMOS tube is connected with the negative input end, and the drain electrode of the fourth PMOS tube is connected with the positive output end; the source electrode of the third PMOS tube is connected with a power supply, the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube; one end of the switch capacitor array is connected with the output negative end, and the other end of the switch capacitor array is connected with the output positive end.
The switch capacitor array comprises fifth to twentieth PMOS tubes, wherein the grid electrode of the fifth PMOS tube is connected with the output positive end, and the source electrode and the drain electrode of the fifth PMOS tube are connected with the first control signal; the channel width of the sixth PMOS tube is twice that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the second control signal; the channel width of the seventh PMOS tube is four times that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the third control signal; the width of the channel of the eighth PMOS tube is eight times that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the fourth control signal; the channel width of the ninth PMOS tube is sixteen times of that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the fifth control signal; the channel width of the tenth PMOS tube is thirty-two times of that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the sixth control signal; the channel width of the eleventh PMOS tube is sixty-four times that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the seventh control signal; the channel width of the twelfth PMOS tube is one hundred twenty eight times of that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the eighth control signal; the size of the thirteenth PMOS tube is the same as that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the first control signal; the channel width of the fourteenth PMOS tube is twice that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the second control signal; the channel width of the fifteenth PMOS tube is four times that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the third control signal; the width of a channel of the sixteenth PMOS tube is eight times that of the channel of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the fourth control signal; the channel width of the seventeenth PMOS tube is sixteen times of that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the fifth control signal; the channel width of the eighteenth PMOS tube is thirty-two times of that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the sixth control signal; the channel width of the nineteenth PMOS tube is sixty-four times that of the fifth PMOS tube, the grid electrode is connected with the negative output end, and the source electrode and the drain electrode are connected with the seventh control signal; the channel width of the twentieth PMOS tube is one hundred twenty eight times of that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the eighth control signal.
After the scheme is adopted, the invention has the following improvements:
(1) in the ring oscillation circuit, four-stage differential delay units oscillate near working frequency to generate 8 paths of outputs with phase difference of 45 degrees, and the delay time of each stage of delay unit is controlled by an 8-bit switch capacitor array;
(2) increasing resistance between input and output signals increases rise and fall times without decreasing oscillation frequency to increase the range of injection locking;
(3) the signal injection is injected through the grids of two NMOS tubes with the same size, and the working frequency of the ring oscillator is locked to the input frequency by changing the impedance of one group of differential outputs to the ground;
(4) the adjustment of the free oscillation frequency of the ring oscillator is realized by controlling the switched capacitor array, so that a fixed phase difference is generated according to the difference value of the injection frequency, and a high-resolution phase generation circuit is realized.
The low-power-consumption high-resolution digital phase generator provided by the invention realizes 10-bit phase resolution under 800MHz frequency by using the injection locking ring oscillator, the power consumption is only 0.5mW, and the integral nonlinearity is less than 2 ps.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a differential non-linear schematic of the digital phase generator of the present invention;
fig. 3 is a schematic diagram of the integral non-linearity of the digital phase generator of the present invention.
Detailed Description
The technical solution and the advantages of the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides a low power consumption high resolution digital phase generator, comprising a four-stage ring oscillator and a signal injection circuit, wherein each stage of delay unit in the ring oscillator is composed of current mode inverters, and cross-coupled PMOS pairs provide extra delay so that even number stage delay oscillation units satisfy the start-up condition; the resistance is added between the input and the output of each stage of delay unit, the rising and falling time of the output of the oscillator is increased under the condition of not reducing the oscillation frequency, the locking range of the injection locking oscillator is enlarged, the injection signal is input at the output end of the first delay unit D1 through a symmetrical NMOS differential pair, and the generated phase is controlled by the switched capacitor array in each stage of delay unit.
As shown in fig. 1, the signal injection circuit includes a first NMOS transistor NM1 and a second NMOS transistor NM2, the gate of the first NMOS transistor NM1 is connected to the input signal inverting terminal Inn, and the source is grounded; the gate of the second NMOS transistor NM2 is connected to the in-phase terminal Inp of the input signal, and the source is grounded.
The ring oscillator comprises a first delay unit D1, a second delay unit D2, a third delay unit D3 and a fourth delay unit D4, wherein the positive output end of the first delay unit D1 is connected with the negative input end of the second delay unit D2, and the negative output end of the first delay unit D1 is connected with the positive input end of the second delay unit D2; the positive output terminal of the second delay unit D2 is connected to the negative input terminal of the third delay unit D3, and the negative output terminal of the second delay unit D2 is connected to the positive input terminal of the third delay unit D3; the positive output terminal of the third delay unit D3 is connected to the negative input terminal of the fourth delay unit D4, and the negative output terminal of the third delay unit D3 is connected to the positive input terminal of the fourth delay unit D4; the positive output terminal of the fourth delay unit D4 is connected to the positive input terminal of the first delay unit D1, and the negative output terminal of the fourth delay unit D4 is connected to the negative input terminal of the first delay unit D1; the positive output terminal of the first delay unit D1 is further connected to the drain of the first NMOS transistor NM1, and the negative output terminal of the first delay unit D1 is further connected to the drain of the second NMOS transistor NM 2.
The first delay unit D1, the second delay unit D2, the third delay unit D3 and the fourth delay unit D4 are identical in structure and comprise all the same elements; the circuit comprises a first reference current source I1, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first resistor R1, a second resistor R2, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4 and a first switch capacitor array Cap Bank; the positive end of the first reference current source I1 is connected with the sources of the third NMOS transistor NM3 and the fourth NMOS transistor NM4, and the negative end is grounded; the drain of the third NMOS tube NM3 is connected with the drain of the first PMOS tube PM1, and the gate is connected with the input positive end In +; the drain of the fourth NMOS transistor NM4 is connected to the drain of the fourth PMOS transistor PM2, and the gate is connected to the input negative terminal In-; one end of the first resistor R1 is connected with an input positive terminal In +, and the other end is connected with an output negative terminal Out-; one end of the second resistor R2 is connected with the input negative terminal In-, and the other end is connected with the output positive terminal Out-; the source electrode of the first PMOS pipe PM1 is connected with a power supply, the grid electrode is connected with an input positive terminal In +, and the drain electrode is connected with an output negative terminal Out-; the source electrode of the second PMOS tube PM2 is connected with a power supply, the grid electrode of the second PMOS tube PM2 is connected with the drain electrode of the third PMOS tube PM3, and the drain electrode of the second PMOS tube PM2 is connected with the drain electrode of the first PMOS tube PM 1; the source electrode of the fourth PMOS tube PM4 is connected with the power supply, the grid electrode is connected with the input negative terminal In-, and the drain electrode is connected with the output positive terminal Out +; the source electrode of the third PMOS tube PM3 is connected with a power supply, the grid electrode of the third PMOS tube PM3 is connected with the drain electrode of the second PMOS tube PM2, and the drain electrode of the third PMOS tube PM3 is connected with the drain electrode of the fourth PMOS tube PM 4; one end of the switch capacitor array is connected with the output negative terminal Out, and the other end is connected with the output positive terminal Out +.
The switch capacitor array comprises a fifth PMOS tube PM5, a sixth PMOS tube PM6, a seventh PMOS tube PM7, an eighth PMOS tube PM8, a ninth PMOS tube PM9, a tenth PMOS tube PM10, an eleventh PMOS tube PM11, a twelfth PMOS tube PM12, a thirteenth PMOS tube PM13, a fourteenth PMOS tube PM14, a fifteenth PMOS tube PM15, a sixteenth PMOS tube PM16, a seventeenth PMOS tube PM17, an eighteenth PMOS tube PM18, a nineteenth PMOS tube PM19 and a twentieth PMOS tube PM 20; wherein, the grid of the fifth PMOS pipe PM5 is connected with the output positive terminal, and the source and the drain are connected with the control signal C0; the channel width of the sixth PMOS tube PM6 is twice that of the fifth PMOS tube PM5, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the control signal C1; the channel width of the seventh PMOS tube PM7 is four times of that of the fifth PMOS tube PM5, the grid is connected with the output positive end, and the source and the drain are connected with the control signal C2; the channel width of the eighth PMOS tube PM8 is eight times of that of the fifth PMOS tube PM5, the grid is connected with the output positive end, and the source and the drain are connected with the control signal C3; the channel width of the ninth PMOS tube PM9 is sixteen times of that of the fifth PMOS tube PM5, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the control signal C4; the channel width of the tenth PMOS transistor PM10 is thirty-two times that of the fifth PMOS transistor PM5, the grid is connected with the output positive terminal, and the source and the drain are connected with the control signal C5; the channel width of the eleventh PMOS tube PM11 is sixty-four times that of the fifth PMOS tube PM5, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the control signal C6; the channel width of the twelfth PMOS tube PM12 is one hundred twenty eight times of that of the fifth PMOS tube PM5, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the control signal C7; the size of the thirteenth PMOS transistor PM13 is the same as that of the fifth PMOS transistor, the grid is connected with the output negative terminal, and the source and the drain are connected with the control signal C0; the channel width of the fourteenth PMOS tube PM14 is twice that of the fifth PMOS tube PM5, the grid is connected with the output negative terminal, and the source and the drain are connected with the control signal C1; the channel width of the fifteenth PMOS tube PM15 is four times of that of the fifth PMOS tube PM5, the grid is connected with the output negative terminal, and the source and the drain are connected with the control signal C2; the channel width of the sixteenth PMOS transistor PM16 is eight times of that of the fifth PMOS transistor PM5, the grid is connected with the output negative terminal, and the source and the drain are connected with the control signal C3; the channel width of the seventeenth PMOS transistor PM17 is sixteen times of that of the fifth PMOS transistor PM5, the grid is connected with the output negative terminal, and the source and the drain are connected with the control signal C4; the channel width of the eighteenth PMOS transistor PM18 is thirty-two times that of the fifth PMOS transistor PM5, the grid is connected with the output negative terminal, and the source and the drain are connected with the control signal C5; the nineteenth PMOS transistor PM11 has channel width sixty-four times that of the fifth PMOS transistor PM5, gate connected to the negative output terminal, source and drain connected to the control signal C6; the channel width of the twentieth PMOS transistor PM20 is one hundred twenty eight times that of the fifth PMOS transistor PM5, the gate is connected to the output negative terminal, and the source and the drain are connected to the control signal C [7 ].
Fig. 2 is a schematic diagram of the differential nonlinearity of the low power high resolution digital phase generator according to the present invention, with the abscissa representing the digital input code and the ordinate representing the differential nonlinearity in seconds. Under the working frequency of 800MHz, the resolution of the digital phase generator provided by the invention can reach 1.22 picoseconds, and the differential nonlinear absolute value is less than 6 picoseconds. Fig. 3 shows the integral non-linearity of the proposed digital phase generator with the abscissa of the digital input code and the ordinate of the integral non-linearity in seconds, with absolute values less than 6 picoseconds over the whole range.
In summary, the digital phase generator with low power consumption and high resolution of the present invention has the following characteristics:
(1) adjusting the phase of the output signal by adjusting the free oscillation frequency of the oscillator by utilizing the phase relation between the output signal and the injection signal in the injection locking technology;
(2) the multistage ring oscillator realizes coarse adjustment and ensures the linearity of the phase generator in each self-interval;
(3) and a PMOS tube is used as a switched capacitor array to adjust the free oscillation frequency of the ring oscillator so as to realize high-resolution phase interpolation.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention.
Claims (2)
1. A low power high resolution digital phase generator, characterized by: the four-stage ring oscillator is connected with the output end of the signal injection circuit;
the four-stage ring oscillator comprises a first delay unit, a second delay unit, a third delay unit and a fourth delay unit, wherein the positive output end of the first delay unit is connected with the negative input end of the second delay unit, and the negative output end of the first delay unit is connected with the positive input end of the second delay unit; the positive output end of the second delay unit is connected with the negative input end of the third delay unit, and the negative output end of the second delay unit is connected with the positive input end of the third delay unit; the positive output end of the third delay unit is connected with the negative input end of the fourth delay unit, and the negative output end of the third delay unit is connected with the positive input end of the fourth delay unit; the positive output end of the fourth delay unit is connected with the positive input end of the first delay unit, and the negative output end of the fourth delay unit is connected with the negative input end of the first delay unit; the output end of the signal injection circuit is connected with the output end of the first delay unit;
the first delay unit, the second delay unit, the third delay unit and the fourth delay unit have the same structure and respectively comprise a first reference current source, a third NMOS tube, a fourth NMOS tube, a first resistor, a second resistor, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a first switch capacitor array, wherein the positive end of the first reference current source is connected with the source electrodes of the third NMOS tube and the fourth NMOS tube, and the negative end of the first reference current source is grounded; the drain electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the third NMOS tube is connected with the positive input end; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the grid electrode of the fourth NMOS tube is connected with the input negative end; one end of the first resistor is connected with the positive input end, and the other end of the first resistor is connected with the negative output end; one end of the second resistor is connected with the input negative end, and the other end of the second resistor is connected with the output positive end; the source electrode of the first PMOS tube is connected with a power supply, the grid electrode of the first PMOS tube is connected with the positive input end, and the drain electrode of the first PMOS tube is connected with the negative output end; the source electrode of the second PMOS tube is connected with a power supply, the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube; the source electrode of the fourth PMOS tube is connected with the power supply, the grid electrode of the fourth PMOS tube is connected with the negative input end, and the drain electrode of the fourth PMOS tube is connected with the positive output end; the source electrode of the third PMOS tube is connected with a power supply, the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube; one end of the switch capacitor array is connected with the output negative end, and the other end of the switch capacitor array is connected with the output positive end;
the switch capacitor array comprises fifth to twentieth PMOS tubes, wherein the grid electrode of the fifth PMOS tube is connected with the output positive end, and the source electrode and the drain electrode of the fifth PMOS tube are connected with the first control signal; the channel width of the sixth PMOS tube is twice that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the second control signal; the channel width of the seventh PMOS tube is four times that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the third control signal; the width of the channel of the eighth PMOS tube is eight times that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the fourth control signal; the channel width of the ninth PMOS tube is sixteen times of that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the fifth control signal; the channel width of the tenth PMOS tube is thirty-two times of that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the sixth control signal; the channel width of the eleventh PMOS tube is sixty-four times that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the seventh control signal; the channel width of the twelfth PMOS tube is one hundred twenty eight times of that of the fifth PMOS tube, the grid electrode is connected with the output positive end, and the source electrode and the drain electrode are connected with the eighth control signal; the size of the thirteenth PMOS tube is the same as that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the first control signal; the channel width of the fourteenth PMOS tube is twice that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the second control signal; the channel width of the fifteenth PMOS tube is four times that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the third control signal; the width of a channel of the sixteenth PMOS tube is eight times that of the channel of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the fourth control signal; the channel width of the seventeenth PMOS tube is sixteen times of that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the fifth control signal; the channel width of the eighteenth PMOS tube is thirty-two times of that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the sixth control signal; the channel width of the nineteenth PMOS tube is sixty-four times that of the fifth PMOS tube, the grid electrode is connected with the negative output end, and the source electrode and the drain electrode are connected with the seventh control signal; the channel width of the twentieth PMOS tube is one hundred twenty eight times of that of the fifth PMOS tube, the grid electrode is connected with the output negative end, and the source electrode and the drain electrode are connected with the eighth control signal.
2. A low power consumption high resolution digital phase generator according to claim 1, wherein: the signal injection circuit comprises a first NMOS tube and a second NMOS tube, wherein the grid electrode of the first NMOS tube is connected with the inverting end of an input signal, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is connected with the in-phase end of the input signal, and the source electrode is grounded; the drain electrode of the first NMOS tube is connected with the positive output end of the first delay unit, and the drain electrode of the second NMOS tube is connected with the negative output end of the first delay unit.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1497849A (en) * | 2002-10-10 | 2004-05-19 | 威盛电子股份有限公司 | Method for multi-phase division with frequency-doubled phase interpolation |
| US6944070B1 (en) * | 2002-09-20 | 2005-09-13 | Integrated Device Technology, Inc. | Integrated circuit devices having high precision digital delay lines therein |
| CN101796730A (en) * | 2007-07-03 | 2010-08-04 | 爱萨有限公司 | Programmable analog-to-digital converter for low-power DC-DC SMPS |
| US8081038B2 (en) * | 2008-12-22 | 2011-12-20 | Electronics And Telecommunications Research Institute | Ring oscillator having wide frequency range |
| CN102983862A (en) * | 2006-10-27 | 2013-03-20 | 英飞凌科技股份公司 | Delay stage, ring oscillator, PLL-circuit and method |
| CN103516332A (en) * | 2012-06-19 | 2014-01-15 | 英飞凌科技股份有限公司 | System and method for boosted switches |
| CN104202042A (en) * | 2014-08-27 | 2014-12-10 | 杭州电子科技大学 | Signal source based on phase lock and phase injection synchronization and power synthesis technology |
| US9083349B1 (en) * | 2014-01-21 | 2015-07-14 | Pmc-Sierra Us, Inc. | Voltage controlled oscillator with common mode adjustment start-up |
| CN105207670A (en) * | 2015-09-10 | 2015-12-30 | 重庆西南集成电路设计有限责任公司 | Segmented low-voltage control gain ring oscillator and tuning slope switching circuit |
| CN105247787A (en) * | 2013-10-03 | 2016-01-13 | 华为技术有限公司 | Reconfigurable multi-path injection locked oscillator |
| CN105827220A (en) * | 2016-03-23 | 2016-08-03 | 成都集思科技有限公司 | Six-bit digital delay line |
| CN106209028A (en) * | 2016-06-23 | 2016-12-07 | 东南大学 | A kind of annular voltage controlled oscillator being applicable to low supply voltage |
-
2018
- 2018-02-11 CN CN201810151422.7A patent/CN108429540B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6944070B1 (en) * | 2002-09-20 | 2005-09-13 | Integrated Device Technology, Inc. | Integrated circuit devices having high precision digital delay lines therein |
| CN1497849A (en) * | 2002-10-10 | 2004-05-19 | 威盛电子股份有限公司 | Method for multi-phase division with frequency-doubled phase interpolation |
| CN102983862A (en) * | 2006-10-27 | 2013-03-20 | 英飞凌科技股份公司 | Delay stage, ring oscillator, PLL-circuit and method |
| CN101796730A (en) * | 2007-07-03 | 2010-08-04 | 爱萨有限公司 | Programmable analog-to-digital converter for low-power DC-DC SMPS |
| US8081038B2 (en) * | 2008-12-22 | 2011-12-20 | Electronics And Telecommunications Research Institute | Ring oscillator having wide frequency range |
| CN103516332A (en) * | 2012-06-19 | 2014-01-15 | 英飞凌科技股份有限公司 | System and method for boosted switches |
| CN105247787A (en) * | 2013-10-03 | 2016-01-13 | 华为技术有限公司 | Reconfigurable multi-path injection locked oscillator |
| US9083349B1 (en) * | 2014-01-21 | 2015-07-14 | Pmc-Sierra Us, Inc. | Voltage controlled oscillator with common mode adjustment start-up |
| CN104202042A (en) * | 2014-08-27 | 2014-12-10 | 杭州电子科技大学 | Signal source based on phase lock and phase injection synchronization and power synthesis technology |
| CN105207670A (en) * | 2015-09-10 | 2015-12-30 | 重庆西南集成电路设计有限责任公司 | Segmented low-voltage control gain ring oscillator and tuning slope switching circuit |
| CN105827220A (en) * | 2016-03-23 | 2016-08-03 | 成都集思科技有限公司 | Six-bit digital delay line |
| CN106209028A (en) * | 2016-06-23 | 2016-12-07 | 东南大学 | A kind of annular voltage controlled oscillator being applicable to low supply voltage |
Non-Patent Citations (2)
| Title |
|---|
| "A Multiple-Crystal Interface PLL With VCO Realignment to Reduce Phase Noise";Sheng Ye等;《A Multiple-Crystal Interface PLL With VCO Realignment to Reduce Phase Noise》;20021231;第37卷(第12期);1795-1803 * |
| "A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer》;Willem Laflere等;《IEEE JOURNAL OF SOLID-STATE CIRCUITS》;20080229;第43卷(第2期);460-467 * |
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