CN108428747A - 一种探测基板及其制备方法、x射线探测器 - Google Patents

一种探测基板及其制备方法、x射线探测器 Download PDF

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CN108428747A
CN108428747A CN201810241361.3A CN201810241361A CN108428747A CN 108428747 A CN108428747 A CN 108428747A CN 201810241361 A CN201810241361 A CN 201810241361A CN 108428747 A CN108428747 A CN 108428747A
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黄睿
吴慧利
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BOE Technology Group Co Ltd
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Abstract

本发明公开了一种探测基板，包括：基板；形成于所述基板上的PIN器件，所述PIN器件包括P型半导体层、本征半导体层和N型半导体层；刻蚀保护层，其形成于所述PIN器件的侧壁处并覆盖所述PIN器件的本征半导体层的侧壁。本发明同时公开了制备探测基板的方法以及X射线探测器。通过本发明的方案，优化了探测基板的器件结构，能够有效地改善探测基板的性能。

Description

一种探测基板及其制备方法、X射线探测器
技术领域
本发明涉及光电技术领域，尤其涉及一种探测基板及其制备方法以及包括该探测基板的X射线探测器。
背景技术
目前，X射线探测大规模应用于医疗、安全、无损检测等领域，并日益发挥着重要作用。其中较为普遍应用的是X射线数字照相检测技术(Digital Radiography,DR)，分为直接转换(Direct DR)与间接转换(Indirect DR)两种类型。间接转换型X射线探测器由于开发成熟，成本相对低，器件稳定性好等优势得到了广泛的开发与应用。
X射线探测器包括阵列基板，阵列基板中包括薄膜晶体管(Thin FilmTransistor,TFT)与光电二极管。在X射线的照射下，X射线探测器的闪烁体层与荧光体层将X射线光子转换为可见光，然后在光电二极管的作用下将该可见光转换为电信号，由薄膜晶体管读取该电信号并输出得到显示图像。其中，光电二极管是间接转换型X射线探测器阵列基板的关键组成元件，其转换效率对于X射线剂量、X射线成像的分辨率、图像的响应速度等关键指标有很大影响。
发明内容
本发明实施例提出了一种能够有效改善提高X射线探测性能的探测基板及其制备方法，以及包括该探测基板的X射线探测器。
为此，本发明实施例提出了一种探测基板，包括：基板；形成于所述基板上的PIN器件，所述PIN器件包括P型半导体层、本征半导体层和N型半导体层；刻蚀保护层，其形成于所述PIN器件的侧壁处并覆盖所述PIN器件的本征半导体层的侧壁。
可选地，所述探测基板还包括：刻蚀修复层，其形成于所述本征半导体层与所述刻蚀保护层之间。
可选地，所述刻蚀保护层由透光的绝缘材料形成。
可选地，所述本征半导体层的折射率高于所述刻蚀保护层的折射率。
所为优选，所述探测基板还包括：覆盖所述PIN器件的封装层，所述刻蚀保护层的折射率高于所述封装层的折射率。
本发明实施例还提出了一种X射线探测器，其包括上述任一种探测基板。
本发明实施例还提出了一种制备探测基板的方法，包括：在基板上形成第一掺杂半导体薄膜；在所述基板上形成刻蚀保护薄膜，并刻蚀去除待形成PIN器件的本征半导体层的区域处的部分刻蚀保护薄膜；在所述区域处以及刻蚀后的所述刻蚀保护薄膜上形成本征半导体薄膜；在所述本征半导体薄膜上形成第二掺杂半导体薄膜，第一掺杂半导体薄膜和第二掺杂半导体薄膜中的一个为P型半导体薄膜，另一个为N型半导体薄膜；对所述刻蚀保护薄膜、所述本征半导体薄膜和第二掺杂半导体薄膜进行刻蚀，形成包括第一掺杂半导体层、本征半导体层以及第二掺杂半导体层的PIN器件，以及覆盖所述本征半导体层的侧壁的刻蚀保护层。
可选地，所述方法还包括：在刻蚀去除所述区域处的部分刻蚀保护薄膜后，在所述刻蚀保护薄膜的被刻蚀表面形成刻蚀修复层。
可选地，所述方法还包括：在刻蚀去除所述区域处的部分刻蚀保护薄膜时，基于所述本征半导体层的折射率与所述刻蚀保护薄膜的折射率来调整所述刻蚀保护薄膜的在所述区域处的刻蚀表面的倾角。
可选地，所述方法还包括：在进行刻蚀以形成所述PIN器件时，基于待在所述PIN器件上形成的封装层的折射率和所述刻蚀保护薄膜的折射率来调整所述刻蚀保护层的外侧壁的倾角。
本发明实施例的方案通过为PIN器件的本征半导体层增加侧壁刻蚀保护层，减少了本征半导体层的侧壁刻蚀面积，降低了侧壁漏电流，提高了探测基板的信噪比。
附图说明
图1为本发明的探测基板的一个实施例的示意性结构图；
图2为本发明的探测基板的另一实施例的示意性结构图；
图3为本发明的探测基板的再一实施例的示意性结构图；
图4为本发明的制备探测基板的方法的一个实施例的示意性流程图；
图5-图10为本发明的制备探测基板的方法的另一个实施例的各工序示意性结构图。
具体实施方式
下面结合附图对本发明实施例进行详细说明。本发明实施例以示例的方式给出，并不作为对本发明的限定。
图1为本发明的探测基板的一个实施例的示意性结构图。本发明实施例的探测基板为包括TFT器件(薄膜晶体管)和PIN器件的阵列基板，因本发明所作改进主要在于PIN器件的结构，为清楚地描述本发明的发明构思，图1中着重示出了其中的PIN器件部分，薄膜晶体管部分可参见图8。
本发明实施例的探测基板包括基板1(参见图8)、形成于基板上的PIN器件和刻蚀保护层8，在PIN器件和刻蚀保护层外侧形成有钝化层13。
PIN器件为PIN光电二极管，包括从基板侧起依次层叠形成的下部电极6、第一掺杂半导体层7、本征半导体层10、第二掺杂半导体层11和上部电极12，其中，当第一掺杂半导体层7是N型半导体层时，第二掺杂半导体层是P型半导体层；当第一掺杂半导体层7是P型半导体层时第二掺杂半导体层是N型半导体层。本征半导体层10用于在吸收入射光后产生大量的电子-空穴对，从而PIN器件能够将光信号转换为电信号。本征半导体层10例如可以是本征非晶硅层或本征锗层等。
刻蚀保护层8形成于PIN器件的侧壁处并覆盖本征半导体层10的侧壁，用于在刻蚀形成单个PIN器件时保护本征半导体层10的侧壁。
如图1所示，本发明实施例的探测基板中的PIN器件除了吸收实线表示的入射光之外，如虚线所示的入射光也可在穿过刻蚀保护层8后入射到本征半导体层10内，因此，相比于通常吸收图1中实线所示入射光的现有探测基板的PIN器件，本发明实施例的探测基板的PIN器件能够吸收更多的入射光。
当入射光向基板垂直入射时，为增大入射率，刻蚀保护层8的外侧壁可以形成为截头棱锥状，其截面如图1所示。但本发明不限于此，根据入射光向基板入射的角度，刻蚀保护层8的外侧壁可以相应地调整。
本发明实施例通过在探测基板中PIN器件的本征半导体层10侧壁设置刻蚀保护层8，使得本征半导体层10的侧壁免受刻蚀或减少被刻蚀的面积，能够有效地降低本征半导体层10侧壁处因晶体材料表面缺陷形成的漏电流，同时提高本征半导体层10吸收的入射光量，从而提高了探测基板的信噪比。
在本发明实施例中，刻蚀保护层8可以由透光的绝缘材料形成，例如氧化硅、氮化硅等，以增大入射效率并避免影响光电转换。
图2为本发明的探测基板的另一实施例的示意性结构图。
如如图2所示，本发明实施例的探测基板在图1所示实施例的基础上还包括刻蚀修复层9，其形成于本征半导体层10与刻蚀保护层8之间，用于对刻蚀保护层8的内侧壁的刻蚀表面进行修复。刻蚀修复层9也可以由透光的绝缘材料形成，例如氧化硅或氮化硅等，刻蚀修复层9与刻蚀保护层8可以是同一种材料形成，或者也可以由不同材料形成。
本发明实施例中，通过在探测基板中PIN器件的本征半导体层10侧壁处设置刻蚀保护层8并在刻蚀保护层8与本征半导体层10的侧壁之间设置刻蚀修复层9，能够进一步提高本征半导体层10侧壁表面的平滑度，有效地降低本征半导体层10侧壁处的漏电流。通过本发明实施例的探测基板，能够将PIN器件中的暗电流(包括表面漏电流和本征暗电流)减少两个数量级，有效地改善探测基板的信噪比。
图3为本发明的探测基板的再一实施例的示意性结构图。
如图3所示，本发明实施例的探测基板在图2所示实施例的基础上，刻蚀修复层9除了包括形成在本征半导体层10和刻蚀保护层8之间的部分外，还包括形成在本征半导体层10和第一掺杂半导体层7之间的部分。
在本发明实施例中，在刻蚀保护层8的内侧壁沉积形成刻蚀修复层9时，刻蚀修复层9同时也会沉积到第一掺杂半导体层7上，但由于遂穿效应的存在，刻蚀修复层9的形成在本征半导体层10和第一掺杂半导体层7之间的部分不会影响PIN器件内载流子的传输，因此可以保留刻蚀修复层9的该部分以简化制备工艺。
在本发明实施例中，由于第一掺杂半导体层7通常由透光材料形成，使得入射刻蚀保护层8后未直接进入本征半导体层10的入射光可以经由第一掺杂半导体层7的透射以及下部电极6的反射而入射到本征半导体层10中，如图3所示。通过本发明实施例，能够进一步提高本征半导体层10吸收的入射光量，提高探测基板的信噪比。
在本发明一个实施例中，本征半导体层10的折射率可以高于刻蚀保护层8的折射率，使得从刻蚀保护层8进入本征半导体层10的入射光能够以所需的角度折射并尽可能多地由本征半导体层10吸收。
在本发明一个实施例中，探测基板还包括覆盖PIN器件的第一封装层14(参见图9)，且刻蚀保护层8的折射率高于第一封装层14的折射率，使得从第一封装层14进入刻蚀保护层8的入射光能够以所需的角度折射并尽可能多地入射到本征半导体层10中。
本发明实施例还提出了一种X射线探测器，其包括上述任一实施例提出的探测基板。本发明实施例的X射线探测器具有较高的信噪比，探测性能优越。
图4为本发明的制备探测基板的方法的一个实施例的示意性流程图。
如图4所示，本发明实施例的制备探测基板的方法包括：
S101、在基板上形成第一掺杂半导体薄膜；
S102、在所述基板上形成刻蚀保护薄膜，并刻蚀去除待形成PIN器件的本征半导体层的区域处的部分刻蚀保护薄膜；
S103、在所述区域处以及刻蚀后的刻蚀保护薄膜上形成本征半导体薄膜；
S104、在本征半导体薄膜上形成第二掺杂半导体薄膜；
S105、对刻蚀保护薄膜、本征半导体薄膜和第二掺杂半导体薄膜进行刻蚀，形成包括第一掺杂半导体层、本征半导体层以及第二掺杂半导体层的PIN器件以及覆盖本征半导体层的侧壁的刻蚀保护层。
在本发明实施例的制备方法中，在基板上制备PIN器件时，在S101中形成第一掺杂半导体薄膜之后，在形成本征半导体薄膜之前，通过S102先在基板上形成一层刻蚀保护薄膜8’，所形成的刻蚀保护薄膜8’的厚度与待形成的本征半导体层的厚度相当，并对刻蚀保护薄膜8’的对应于待形成PIN器件的本征半导体层的区域的部分进行刻蚀去除，参见图6所示。此后，通过S103在该经刻蚀的区域以及刻蚀后的刻蚀保护薄膜8’上形成本征半导体薄膜，通过S104在本征半导体薄膜上形成第二掺杂半导体薄膜，并通过刻蚀形成包括第一掺杂半导体层、本征半导体层以及第二掺杂半导体层的单个PIN器件以及覆盖本征半导体层的侧壁的刻蚀保护层。其中，第一掺杂半导体薄膜和第二掺杂半导体薄膜中的一个为P型半导体薄膜，另一个为N型半导体薄膜，相应地，在所形成的PIN器件中，第一掺杂半导体层和第二掺杂半导体层中的一个为P型半导体层，另一个为N型半导体层。通过S105在刻蚀形成PIN器件时，刻蚀掉大部分的刻蚀保护薄膜8’，保留刻蚀保护薄膜8’的覆盖在本征半导体层侧壁处的一部分作为刻蚀保护层8，从而确保在刻蚀形成PIN器件期间，PIN器件的本征半导体层的侧壁由刻蚀保护层8所覆盖而免于受到刻蚀或者减少受到刻蚀的面积，
本发明实施例通过在制备探测基板时，在待形成PIN器件的本征半导体层的区域外围设置刻蚀保护薄膜，并在刻蚀形成PIN器件时保留刻蚀保护薄膜的一部分覆盖于本征半导体层的侧壁处作为刻蚀保护层，使得PIN器件的本征半导体层的侧壁免受刻蚀或减少被刻蚀的面积，能够有效地降低本征半导体层侧壁处因晶体材料表面缺陷形成的漏电流，同时提高本征半导体层吸收的入射光量，从而提高了所制备的探测基板的信噪比。
图5-图10为本发明的制备探测基板的方法的另一个实施例的各工序示意性结构图。
在本发明实施例中，在制备基板1后，先在基板1上制备TFT器件，包括在基板1上制备栅极金属层2，在栅极金属层2及基板1上沉积栅极绝缘层3和包括非晶硅层4与掺杂非晶硅层5的有源层，然后在有源层及栅极绝缘层3上制备金属电极层6，之后沉积形成第一掺杂半导体薄膜并对所形成的第一掺杂半导体薄膜进行图案化以同时形成TFT器件区的沟道保护层7’和PIN器件区的第一掺杂半导体层7，如图5所示。需要说明的是，该制备TFT器件的方式仅为示例性的，本发明的制备探测基板的方法中在基板上制备TFT器件的方式不限于此。
本发明实施例中，以待形成的PIN器件是其中第一掺杂半导体层7为N型半导体层、第二掺杂半导体层11为P型半导体层的N-I-P结构为例，制备时从基板1起依次形成N型半导体薄膜、本征半导体薄膜10’和P型半导体薄膜，其中N型半导体薄膜可以采用诸如IGZO等材料形成。当然，本发明不限于此，在本发明其他实施例中，待形成的PIN器件也可以是其中第一掺杂半导体层7为P型半导体层、第二掺杂半导体层11为N型半导体层的P-I-N结构，则制备时从基板1起依次形成P型半导体薄膜、本征半导体薄膜10’和N型半导体薄膜。
如图6所示，在基板上形成刻蚀保护薄膜8’，并对刻蚀保护薄膜8’的对应于待形成本征半导体层10的区域的部分进行刻蚀处理，在该区域处形成内侧具有刻蚀表面的凹部。
如图7所示，依次在上述待形成本征半导体10的区域和经过上述刻蚀处理后的刻蚀保护薄膜8’上形成刻蚀修复薄膜9’、本征半导体薄膜10’、第二掺杂半导体薄膜11’和上部电极材料薄膜12’，然后如图8所示，对刻蚀保护薄膜8’、刻蚀修复薄膜9’、本征半导体薄膜10’、第二掺杂半导体薄膜11’和上部电极材料薄膜12’进行刻蚀，形成包括第一掺杂半导体层7、本征半导体层10、第二掺杂半导体层11和上部电极12的PIN器件，同时形成了覆盖本征半导体层10的侧壁的刻蚀保护层8和在刻蚀保护层8和本征半导体层10之间的刻蚀修复层9。图8中示出了在刻蚀过程中已将刻蚀保护薄膜8’的大部分刻蚀去除，只保留覆盖于本征半导体层10侧壁处的一部分作为刻蚀保护层8。如图9所示，在形成PIN器件和刻蚀保护层8后，除去TFT器件区域的沟道保护层7’，并在PIN器件和TFT器件上依次形成钝化层13和第一封装层14。如图10所示，对PIN器件的上部电极12处的钝化层13部分进行开孔露出上部电极12的至少一部分，在开孔处以及第一封装层14上先后制备透明电极层15和导电金属层16，然后在导电金属层16上形成第二封装层17，完成探测基板的制备。其中，第一封装层14和第二封装层17例如可由树脂形成。
本发明实施例中通过在探测基板中PIN器件的本征半导体层10侧壁处设置刻蚀保护层8并在刻蚀保护层8与本征半导体层10的侧壁之间设置刻蚀修复层9，能够进一步提高本征半导体层10侧壁表面的平滑度，有效地降低本征半导体层10侧壁处的漏电流，减少PIN器件中的暗电流，有效地改善探测基板的信噪比。
在本发明实施例中，可以根据第一封装层14、刻蚀保护薄膜8’与本征半导体层10的折射率来调整刻蚀保护层8的外侧壁和内侧壁刻蚀表面的倾角来实现所需的折射光路，达到聚光的效果。例如，对于待形成的刻蚀保护层8的外侧壁，可根据封装层14的折射率与刻蚀保护薄膜8’的折射率确定入射光在从封装层14进入待形成的刻蚀保护层8时的折射角，进而在刻蚀过程中根据该折射角来调整刻蚀保护层8的外侧壁倾角使得进入所形成的刻蚀保护层8的折射光相对于基板在一定的角度范围内。对于待形成的刻蚀保护层8的内侧壁，可根据本征半导体层10的折射率与刻蚀保护薄膜8’的折射率确定入射光在从待形成的刻蚀保护层8进入本征半导体层10时的折射角，进而根据该折射角来调整刻蚀保护薄膜8’的内侧刻蚀表面倾角使得从所形成的刻蚀保护层8进入本征半导体层10的折射光相对于基板在一定的角度范围内。本发明实施例通过优化器件结构，实现了聚光的效果，能够有效地增加本征半导体层10吸收的入射光，提高探测基板的信噪比。
以上所述仅为本发明较佳的实施例，并非因此限制本申请要求保护的范围，所以凡运用本申请说明书及图示内容作出等效结构变化，均包含在本申请的保护范围内。

Claims (10)

1.一种探测基板，包括：
基板；
形成于所述基板上的PIN器件，所述PIN器件包括P型半导体层、本征半导体层和N型半导体层；
刻蚀保护层，其形成于所述PIN器件的侧壁处并覆盖所述本征半导体层的侧壁。
2.如权利要求1所述的探测基板，还包括：
刻蚀修复层，其形成于所述本征半导体层与所述刻蚀保护层之间。
3.如权利要求1所述的探测基板，其中，所述刻蚀保护层由透光的绝缘材料形成。
4.如权利要求1中任一项所述的探测基板，其中，所述本征半导体层的折射率高于所述刻蚀保护层的折射率。
5.如权利要求1-4中任一项所述的探测基板，还包括：
覆盖所述PIN器件的封装层，所述刻蚀保护层的折射率高于所述封装层的折射率。
6.一种X射线探测器，其特征在于，包括如权利要求1-5中任一项所述的探测基板。
7.一种制备探测基板的方法，包括：
在基板上形成第一掺杂半导体薄膜；
在所述基板上形成刻蚀保护薄膜，并刻蚀去除待形成PIN器件的本征半导体层的区域处的部分刻蚀保护薄膜；
在所述区域处以及刻蚀后的所述刻蚀保护薄膜上形成本征半导体薄膜；
在所述本征半导体薄膜上形成第二掺杂半导体薄膜，其中，第一掺杂半导体薄膜和第二掺杂半导体薄膜中的一个为P型半导体薄膜，另一个为N型半导体薄膜；
对所述刻蚀保护薄膜、所述本征半导体薄膜和所述第二掺杂半导体薄膜进行刻蚀，形成包括第一掺杂半导体层、本征半导体层以及第二掺杂半导体层的PIN器件，以及覆盖所述本征半导体层的侧壁的刻蚀保护层。
8.如权利要求7所述的方法，还包括：
在刻蚀去除所述区域处的部分刻蚀保护薄膜后，在所述刻蚀保护薄膜的被刻蚀表面形成刻蚀修复层。
9.如权利要求7所述的方法，还包括：
在刻蚀去除所述区域处的部分刻蚀保护薄膜时，基于所述本征半导体层的折射率与所述刻蚀保护薄膜的折射率来调整所述刻蚀保护薄膜的在所述区域处的刻蚀表面的倾角。
10.如权利要求7-9中任一项所述的方法，还包括：
在进行刻蚀以形成所述PIN器件时，基于待在所述PIN器件上形成的封装层的折射率和所述刻蚀保护薄膜的折射率来调整所述刻蚀保护层的外侧壁的倾角。
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