CN108417533B - Method for manufacturing contact hole - Google Patents
Method for manufacturing contact hole Download PDFInfo
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- CN108417533B CN108417533B CN201810330029.4A CN201810330029A CN108417533B CN 108417533 B CN108417533 B CN 108417533B CN 201810330029 A CN201810330029 A CN 201810330029A CN 108417533 B CN108417533 B CN 108417533B
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- Prior art keywords
- contact hole
- hard mask
- mask layer
- grid
- drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Abstract
The invention discloses a method for manufacturing a contact hole, which comprises the following steps: providing a semiconductor substrate with a plurality of grid structures, wherein side walls are formed on the side faces of the semiconductor substrate, and active drain regions are formed on the two sides of the semiconductor substrate; step two, forming a hard mask layer; step three, carrying out photoetching on the hard mask layer, wherein the etched hard mask layer is positioned on the surface of the gate structure on at least one side of the contact hole at the top of the source region or the drain region formed subsequently; step four, forming an interlayer film; fifthly, defining a forming area of the contact hole by photoetching; sixthly, etching the interlayer film in the contact hole forming area to form an opening of the contact hole, wherein at least one side surface of the bottom of the opening of the contact hole at the top of the source region and the drain region is defined by the hard mask layer and the corresponding side wall in a self-alignment mode; and step seven, filling metal in the opening of the contact hole. The invention can realize the bottom self-alignment of the contact hole at the top of the source drain region and prevent the contact hole at the top of the source drain region from being contacted with the grid structure.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a contact hole.
Background
With the development of 28nm and more advanced processes, spacer (Space) and line width (CD) become smaller and smaller, and the offset of the photolithography and etching processes is more likely to cause mis-etching of the contact tungsten. As shown in fig. 1A to 1B, which are structural diagrams of steps of a conventional contact hole manufacturing method, the conventional method includes the following steps:
step one, a semiconductor substrate such as a silicon substrate 101 is provided, a gate structure 103 is formed on the semiconductor substrate 101, and a side wall 104 is formed on the side surface of the gate structure 103.
The gate structure 103 is formed by stacking a gate dielectric layer and a polysilicon gate. Alternatively, the gate structure 103 is formed by stacking a gate dielectric layer and a metal gate, such as a metal aluminum gate.
A well region such as a P-well (PW)102 is also formed on the surface of the silicon substrate 101, and the P-well 102 can be used as a channel region of an NMOS transistor.
Active and drain regions are formed on both sides of the gate structure 103. The surface of the channel region covered by the gate structure 103 is used to form a channel connecting the source and drain regions, and the length of the channel, i.e., the width of the gate structure 103, is CD. The spacers 104 are formed on two sides of the gate structure 103 in a self-aligned manner, and the Space between the spacers 104 is Space.
Step two, the interlayer film 105 is formed thereafter.
Step three, defining a forming area of the contact hole 106 by photoetching, and etching the interlayer film 105 in the forming area of the contact hole 106 to form an opening of the contact hole 106.
With the reduction of the CD and Space and the shift of the photolithography process and the etching process itself of the interlayer film 105, it is easy to cause the opening of the contact hole 106 to shift to both sides and open the interlayer film 105 on the top of the gate structure 103, as shown by the broken-line frame 107.
And fourthly, filling metal such as metal tungsten into the opening of the contact hole 106 to form the contact hole 106. The contact hole 106 at the top of the source and drain regions in the region shown by dashed box 107 in fig. 1B would make direct contact with the back gate structure 103, thereby creating a short circuit problem.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for manufacturing a contact hole, which can realize the bottom self-alignment of the contact hole at the top of a source drain region and prevent the contact hole at the top of the source drain region from being contacted with a grid structure.
In order to solve the above technical problem, the method for manufacturing the contact hole provided by the invention comprises the following steps:
providing a semiconductor substrate, forming a plurality of grid structures on the semiconductor substrate, forming a source region and a drain region on two sides of each grid structure, wherein the source region or the drain region is shared by two adjacent grid structures; and forming a side wall on the side surface of each grid structure.
And step two, forming a hard mask layer.
Step three, carrying out photoetching on the hard mask layer, wherein the etched hard mask layer is positioned on the surface of the gate structure on at least one side of the contact hole at the top of the source region or the drain region formed subsequently; the material of the hard mask layer is the same as that of the side wall and is different from that of a subsequent interlayer film, and the material of the hard mask layer can be used as a stop layer during the interlayer film etching; the hard mask layer is connected with the side walls on two sides of the corresponding grid structure to form a self-aligned boundary of the bottom of the corresponding contact hole; and removing the hard mask layer in the forming area of the contact hole at the top of the grid structure.
And step four, forming an interlayer film, wherein the interlayer film completely fills the space between the grid electrode structures and extends to the top of the grid electrode structures.
And fifthly, defining a forming area of a contact hole by photoetching, wherein the contact hole comprises a contact hole positioned at the top of the grid structure, a contact hole positioned at the top of the source region and a contact hole positioned at the top of the drain region.
And sixthly, etching the interlayer film in the contact hole forming area to form an opening of the contact hole, wherein at least one side surface of the bottom of the opening of the contact hole at the top of the source region and the drain region is defined by the hard mask layer and the corresponding side wall in a self-alignment manner, so that the contact holes of the source region and the drain region and the corresponding grid structures are prevented from being in short circuit contact when the photoetching process of the contact hole is deviated.
And step seven, filling metal in the opening of the contact hole to form the contact hole.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the material of the interlayer film is silicon oxide.
The further improvement is that the material of the hard mask layer and the material of the side wall are both silicon nitride.
The gate structure is further improved by superposing a gate dielectric layer and a polysilicon gate.
The further improvement is that the grid structure is formed by overlapping a grid dielectric layer and a metal grid.
In a further improvement, the filling metal in the seventh step is tungsten.
The invention forms a hard mask layer and carries out photoetching on the hard mask layer before forming the interlayer film, the etched hard mask layer is at least reserved at the top of the grid structure at one side of the contact hole at the top of the source drain region, namely the source region or the drain region, then the interlayer film deposition and the photoetching process of the contact hole are carried out, the etching process of the contact hole is to etch the interlayer film, because the hard mask layer is arranged on the corresponding side of the contact hole at the top of the source drain region, the hard mask layer and the adjacent side wall can be used as the bottom self-aligned boundary of the etching process of the corresponding contact hole, even if the line width and the size of the interval area are reduced and the deviation is generated by the photoetching and etching process, the bottom of the offset part of the contact hole can be positioned on the surface of the hard mask layer finally, therefore, the contact hole at the top of the source drain region can be prevented from being contacted with the grid structure, and the short circuit caused by the contact of the contact hole at the top of the source drain region and the grid structure can also be prevented.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A to 1B are structural views of steps of a conventional contact hole manufacturing method;
FIG. 2 is a flow chart of a method for fabricating a contact hole according to an embodiment of the present invention;
FIG. 3A is a top view of a second step of the method for forming a contact hole of the present invention;
FIG. 3B is a cross-sectional view taken along line AA of FIG. 3A;
FIG. 4A is a top view of a contact hole fabrication method of an embodiment of the present invention after completion of step three;
FIG. 4B is a cross-sectional view taken along line AA of FIG. 4A;
FIG. 5A is a top view of a contact hole fabrication method of the present invention after completion of step four;
FIG. 5B is a cross-sectional view taken along line AA of FIG. 5A;
FIG. 6A is a top view of a seventh step of a method for forming a contact hole according to an embodiment of the present invention;
fig. 6B is a cross-sectional view taken along line BB of fig. 6A.
Detailed Description
The manufacturing method of the contact hole comprises the following steps:
step one, as shown in fig. 3B, providing a semiconductor substrate 1, forming a plurality of gate structures 3 on the semiconductor substrate 1, forming a source region and a drain region on two sides of each gate structure 3, and the source region or the drain region is shared by two adjacent gate structures 3; side walls 4 are formed on the side surfaces of the gate structures 3.
The semiconductor substrate 1 is a silicon substrate.
A well region such as a P well 2 is also formed on the surface of the silicon substrate 101, and the P well 2 can be used as a channel region of an NMOS transistor.
The grid structure 3 is formed by superposing a grid dielectric layer and a polysilicon grid. Or, the gate structure 3 is formed by overlapping a gate dielectric layer and a metal gate.
And step two, forming a hard mask layer 5. FIG. 3A is a top view of a second step of the contact hole manufacturing method of the present invention; as shown in fig. 3B, which is a cross-sectional view along line AA of fig. 3A.
Step three, as shown in fig. 4A, is a top view of the contact hole manufacturing method of the embodiment of the invention after step three is completed; FIG. 4B is a cross-sectional view taken along line AA of FIG. 4A; photoetching the hard mask layer 5, wherein the etched hard mask layer 5 is positioned on the surface of the gate structure 3 on at least one side of the contact hole 7 at the top of the source region or the drain region formed subsequently; the material of the hard mask layer 5 is the same as that of the side wall 4 and is different from that of the subsequent interlayer film 6, and the material of the hard mask layer 5 can be used as a stop layer when the interlayer film 6 is etched; the hard mask layer 5 is connected with the corresponding side walls 4 on two sides of the gate structure 3 to form a self-aligned boundary of the bottom of the corresponding contact hole 7; and removing the hard mask layer 5 in the forming area of the contact hole 7 at the top of the gate structure 3.
The material of the interlayer film 6 is silicon oxide. The hard mask layer 5 and the side wall 4 are both made of silicon nitride.
Step four, as shown in fig. 5A, is a top view of the contact hole manufacturing method of the embodiment of the invention after step four is completed; FIG. 5B is a cross-sectional view taken along line AA of FIG. 5A; an interlayer film 6 is formed, which interlayer film 6 completely fills the space between the gate structures 3 and extends to the top of the gate structures 3.
Step five, as shown in fig. 6A, is a top view of the contact hole manufacturing method of the embodiment of the invention after step seven is completed; fig. 6B is a cross-sectional view taken along line BB of fig. 6A. And defining a forming area of a contact hole 7 by photoetching, wherein the contact hole 7 comprises the contact hole 7 positioned at the top of the gate structure 3, the contact hole 7 positioned at the top of the source region and the contact hole 7 positioned at the top of the drain region.
And sixthly, etching the interlayer film 6 in the forming area of the contact hole 7 to form an opening of the contact hole 7, wherein at least one side surface of the bottom of the opening of the contact hole 7 at the top of the source region and the drain region is defined by the hard mask layer 5 and the corresponding side wall 4 in a self-alignment manner, so that the contact hole 7 of the source region and the drain region is prevented from being in short circuit contact with the corresponding gate structure 3 when the photoetching process of the contact hole 7 is deviated.
And step seven, filling metal in the opening of the contact hole 7 to form the contact hole 7. In the method of the embodiment of the invention, the filling metal is tungsten.
In the embodiment of the invention, before the interlayer film 6 is formed, a hard mask layer 5 is formed and the hard mask layer 5 is subjected to photoetching, the etched hard mask layer 5 at least remains at the top of the contact hole 7 at one side of the contact hole 7 at the top of the source drain region, namely the source region or the drain region, and then the interlayer film 6 deposition and the photoetching process of the contact hole 7 are carried out, the etching process of the contact hole 7 is to etch the interlayer film 6, because the hard mask layer 5 is arranged at the corresponding side of the contact hole 7 at the top of the source drain region, the hard mask layer 5 and the adjacent side wall 4 can be used as the bottom self-aligned boundary of the etching process of the corresponding contact hole 7, even if the line width and the size of the spacing region are reduced and the photoetching and the etching process deviate, the bottom of the offset part of the contact hole 7 can be finally positioned on the surface of the hard mask layer 5, as shown by dotted line, therefore, the contact hole 7 at the top of the source drain region can be prevented from being contacted with the gate structure 3, and the contact hole 7 at the top of the source drain region can be prevented from being contacted with the gate structure 3 to generate short circuit.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (7)
1. A method for manufacturing a contact hole is characterized by comprising the following steps:
providing a semiconductor substrate, forming a plurality of grid structures on the semiconductor substrate, forming a source region and a drain region on two sides of each grid structure, wherein the source region or the drain region is shared by two adjacent grid structures; forming a side wall on the side surface of each grid structure;
step two, forming a hard mask layer;
step three, carrying out photoetching on the hard mask layer, wherein the etched hard mask layer is only positioned on the surface of the grid structure on at least one side of the contact hole at the top of the source region or the drain region formed subsequently, the top view surface structure of the hard mask layer on the surface of the grid structure on at least one side of the contact hole at the top of the source region or the drain region is square, and the hard mask layer except the square hard mask layer on the surface of the grid structure on at least one side of the contact hole at the top of the source region or the drain region is removed;
the material of the hard mask layer is the same as that of the side wall and is different from that of a subsequent interlayer film, and the material of the hard mask layer can be used as a stop layer during the interlayer film etching; the hard mask layer is connected with the side walls on two sides of the corresponding grid structure to form a self-aligned boundary of the bottom of the corresponding contact hole; removing the hard mask layer in the forming area of the contact hole at the top of the grid structure;
forming an interlayer film, wherein the interlayer film completely fills the space between the grid electrode structures and extends to the top of the grid electrode structures;
step five, defining a forming area of a contact hole by photoetching, wherein the contact hole comprises a contact hole positioned at the top of the grid structure, a contact hole positioned at the top of the source region and a contact hole positioned at the top of the drain region;
sixthly, etching the interlayer film in the contact hole forming area to form an opening of the contact hole, wherein at least one side surface of the bottom of the opening of the contact hole at the top of the source region and the drain region is defined by the hard mask layer and the corresponding side wall in a self-alignment manner, so that the contact holes of the source region and the drain region and the corresponding gate structures are prevented from being in short circuit contact when the photoetching process of the contact hole is deviated;
and step seven, filling metal in the opening of the contact hole to form the contact hole.
2. The method for manufacturing a contact hole according to claim 1, wherein: the semiconductor substrate is a silicon substrate.
3. The method for manufacturing a contact hole according to claim 2, wherein: the material of the interlayer film is silicon oxide.
4. The method for manufacturing a contact hole according to claim 3, wherein: and the hard mask layer and the side wall are both made of silicon nitride.
5. The method for manufacturing a contact hole according to claim 1, wherein: the grid structure is formed by superposing a grid dielectric layer and a polysilicon grid.
6. The method for manufacturing a contact hole according to claim 1, wherein: the grid structure is formed by overlapping a grid dielectric layer and a metal grid.
7. The method for manufacturing a contact hole according to claim 1, wherein: and step seven, filling tungsten as the metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810330029.4A CN108417533B (en) | 2018-04-13 | 2018-04-13 | Method for manufacturing contact hole |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810330029.4A CN108417533B (en) | 2018-04-13 | 2018-04-13 | Method for manufacturing contact hole |
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| CN108417533A CN108417533A (en) | 2018-08-17 |
| CN108417533B true CN108417533B (en) | 2021-04-13 |
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| CN201810330029.4A Active CN108417533B (en) | 2018-04-13 | 2018-04-13 | Method for manufacturing contact hole |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101150064A (en) * | 2006-09-21 | 2008-03-26 | 联华电子股份有限公司 | Method for removing clearance wall, metal semiconductor transistor parts and its making method |
| KR20090001396A (en) * | 2007-06-29 | 2009-01-08 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| CN107895723A (en) * | 2016-09-05 | 2018-04-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and preparation method thereof, electronic installation |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002151686A (en) * | 2000-11-15 | 2002-05-24 | Nec Corp | Semiconductor device and manufacturing method thereof |
| KR100492898B1 (en) * | 2001-12-14 | 2005-06-03 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| JP5134193B2 (en) * | 2005-07-15 | 2013-01-30 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
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- 2018-04-13 CN CN201810330029.4A patent/CN108417533B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101150064A (en) * | 2006-09-21 | 2008-03-26 | 联华电子股份有限公司 | Method for removing clearance wall, metal semiconductor transistor parts and its making method |
| KR20090001396A (en) * | 2007-06-29 | 2009-01-08 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| CN107895723A (en) * | 2016-09-05 | 2018-04-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and preparation method thereof, electronic installation |
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