CN108417533A - The manufacturing method of contact hole - Google Patents

The manufacturing method of contact hole Download PDF

Info

Publication number
CN108417533A
CN108417533A CN201810330029.4A CN201810330029A CN108417533A CN 108417533 A CN108417533 A CN 108417533A CN 201810330029 A CN201810330029 A CN 201810330029A CN 108417533 A CN108417533 A CN 108417533A
Authority
CN
China
Prior art keywords
contact hole
step
hard mask
gate structure
mask layer
Prior art date
Application number
CN201810330029.4A
Other languages
Chinese (zh)
Inventor
叶婷
龚昌鸿
于明非
朱绍佳
Original Assignee
上海华力集成电路制造有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海华力集成电路制造有限公司 filed Critical 上海华力集成电路制造有限公司
Priority to CN201810330029.4A priority Critical patent/CN108417533A/en
Publication of CN108417533A publication Critical patent/CN108417533A/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches

Abstract

The invention discloses a kind of manufacturing methods of contact hole, including step:Step 1: provide one be formed with multiple sides be formed with side wall and both sides be formed with source-drain area gate structure semiconductor substrate;Step 2: forming hard mask layer;Step 3: carrying out chemical wet etching to hard mask layer, the hard mask layer after etching is located at the surface of the gate structure of at least side of the contact hole at the top of the source region being subsequently formed or drain region;Step 4: forming interlayer film;Step 5: lithographic definition goes out the forming region of contact hole;Step 6: performing etching the opening to form contact hole to the interlayer film of the forming region of contact hole, at least one side of the bottom of the opening of the contact hole at the top of source region and drain region is defined by hard mask layer and corresponding side wall autoregistration;Step 7: filling metal in the opening of contact hole.The present invention can realize the bottom autoregistration of the contact hole at the top of source-drain area, and contact hole and gate structure at the top of source-drain area is prevented to be in contact.

Description

The manufacturing method of contact hole

Technical field

The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of manufacturing method of contact hole.

Background technology

With the development of 28nm and more advanced technologies, spacer region (Space) and line width (CD) are smaller and smaller, lithography and etching The offset of processing procedure more easily causes the mistake etching of contact tungsten.Be such as Figure 1A to Figure 1B existing contact hole each step of manufacturing method in Structure chart, existing method include the following steps:

Step 1: providing semi-conductive substrate such as silicon substrate 101, formed by gate structure in semiconductor substrate 101 103, it is formed with side wall 104 in the side of gate structure 103.

Gate structure 103 is formed by stacking by gate dielectric layer and polysilicon gate.Alternatively, gate structure 103 is by gate dielectric layer It is formed by stacking with metal gate such as metal alum gate.

It is usually also formed by well region such as p-well (PW) 102 on the surface of silicon substrate 101, p-well 102 can be as the ditch of NMOS tube Road area.

Active area and drain region are formed in 103 both sides of gate structure.It uses on the surface of the channel region covered by gate structure 103 In the raceway groove for forming connection source region and drain region, the length of raceway groove namely the width of gate structure 103 are CD.104 autoregistration of side wall The both sides of gate structure 103 are formed in, the spacing between side wall 104 is Space.

Step 2: forming interlayer film 105 later.

Step 3: lithographic definition goes out the interlayer film of the forming region of contact hole 106 and the forming region to contact hole 106 105 perform etching the opening to form contact hole 106.

With the offset of the etching technics of the diminution of CD and Space and photoetching process and interlayer film 105 itself, it is easy to make It is offset to both sides at the opening of contact hole 106 and opens the interlayer film 105 at 103 top of gate structure, such as 107 institute of dotted line frame Show.

Step 4: forming contact hole 106 in the opening of contact hole 106 filling metal such as tungsten later.Void in Figure 1B Gate structure 103 is in direct contact contact hole 106 in region shown in wire frame 107 at the top of source-drain area after the meeting, is asked to generate short circuit Topic.

Invention content

Technical problem to be solved by the invention is to provide a kind of manufacturing methods of contact hole, can realize at the top of source-drain area The bottom autoregistration of contact hole prevents contact hole and gate structure at the top of source-drain area to be in contact.

In order to solve the above technical problems, the manufacturing method of contact hole provided by the invention includes the following steps:

Step 1: providing semi-conductive substrate, it is formed with multiple gate structures on the semiconductor substrate, each described The both sides of gate structure form active area and drain region, and the source region or the drain region are total for two adjacent gate structures With;It is formed with side wall in the side of each gate structure.

Step 2: forming hard mask layer.

Step 3: carry out chemical wet etching to the hard mask layer, the hard mask layer after etching, which is located at, to be subsequently formed The surface of the gate structure of at least side of contact hole at the top of the source region or drain region;The material of the hard mask layer and The material identical of the side wall and materials all different with the material of subsequent interlayer film and the hard mask layer can be used as described Stop-layer when interlayer film etches;The hard mask layer and the side wall of the corresponding gate structure both sides are joined together to form The autoregistration boundary of the bottom of the corresponding contact hole;The forming region of contact hole at the top of the gate structure it is described hard Mask layer removes.

Step 4: forming interlayer film, the interval between the gate structure is filled up completely and is extended to by the interlayer film The top of the gate structure.

Step 5: lithographic definition goes out the forming region of contact hole, the contact hole includes being located at the top of the gate structure Contact hole, the contact hole at the top of the source region and the contact hole at the top of the drain region.

Step 6: performing etching to form opening for the contact hole to the interlayer film of the forming region of the contact hole Mouthful, at least one side of the bottom of the opening of the contact hole at the top of the source region and the drain region by the hard mask layer and The corresponding side wall autoregistration definition, occurs the source region and the drain region when preventing the photoetching process of the contact hole from deviating The contact hole and the corresponding gate structure phase shorted contacts.

Step 7: filling metal in the opening of the contact hole forms the contact hole.

A further improvement is that the semiconductor substrate is silicon substrate.

A further improvement is that the material of the interlayer film is silica.

A further improvement is that the material of the material of the hard mask layer and the side wall is all silicon nitride.

A further improvement is that the gate structure is formed by stacking by gate dielectric layer and polysilicon gate.

A further improvement is that the gate structure is formed by stacking by gate dielectric layer and metal gate.

A further improvement is that it is tungsten to fill metal in step 7.

The present invention forms one layer of hard mask layer and simultaneously carries out chemical wet etching to hard mask layer by before forming interlayer film, Hard mask layer after etching at least remaines in the top of the gate structure of the contact hole side at the top of source-drain area i.e. source region or drain region, The lithographic etch process of interlayer film deposition and contact hole is carried out later, the etching technics of contact hole is performed etching to interlayer film, Since the respective side of the contact hole at the top of source-drain area is provided with hard mask layer, hard mask layer and adjacent side wall, which can be used as, to be corresponded to Contact hole etching technics bottom autoregistration boundary, even if due to line width and the size of spacer region diminution and photoetching and When etching technics generates deviation, the bottom of the Offset portion of contact hole can also be made finally to be positioned at the surface of hard mask layer, to Contact hole and gate structure at the top of source-drain area can be prevented to be in contact, also so as to preventing the contact hole at the top of source-drain area and grid Structure is in contact and the short circuit that generates.

Description of the drawings

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

Figure 1A-Figure 1B is the structure chart in each step of manufacturing method of existing contact hole;

Fig. 2 is the flow chart of the manufacturing method of contact hole of the embodiment of the present invention;

Fig. 3 A are the vertical views after the completion of the manufacturing method step 2 of contact hole of the embodiment of the present invention;

Fig. 3 B are the sectional views of the AA lines along Fig. 3 A;

Fig. 4 A are the vertical views after the completion of the manufacturing method step 3 of contact hole of the embodiment of the present invention;

Fig. 4 B are the sectional views of the AA lines along Fig. 4 A;

Fig. 5 A are the vertical views after the completion of the manufacturing method step 4 of contact hole of the embodiment of the present invention;

Fig. 5 B are the sectional views of the AA lines along Fig. 5 A;

Fig. 6 A are the vertical views after the completion of the manufacturing method step 7 of contact hole of the embodiment of the present invention;

Fig. 6 B are the sectional views of the BB lines along Fig. 6 A.

Specific implementation mode

The manufacturing method of contact hole of the present invention includes the following steps:

Step 1: as shown in Figure 3B, providing semi-conductive substrate 1, multiple grids being formed in the semiconductor substrate 1 Structure 3 forms active area and drain region in the both sides of each gate structure 3, and the source region or the drain region are adjacent two A gate structure 3 shares;It is formed with side wall 4 in the side of each gate structure 3.

The semiconductor substrate 1 is silicon substrate.

It is usually also formed by well region such as p-well 2 on the surface of silicon substrate 101, p-well 2 can be as the channel region of NMOS tube.

The gate structure 3 is formed by stacking by gate dielectric layer and polysilicon gate.Alternatively, the gate structure 3 is by gate medium Layer and metal gate are formed by stacking.

Step 2: forming hard mask layer 5.As shown in Figure 3A, it is the manufacturing method step 2 of contact hole of the embodiment of the present invention Vertical view after the completion;As shown in Figure 3B, it is the sectional view of AA lines along Fig. 3 A.

Step 3: as shown in Figure 4 A, be contact hole of the embodiment of the present invention manufacturing method step 3 after the completion of vertical view; Fig. 4 B are the sectional views of the AA lines along Fig. 4 A;Chemical wet etching, the hard mask layer 5 after etching are carried out to the hard mask layer 5 The surface of the gate structure 3 of at least side of contact hole 7 at the top of the source region being subsequently formed or drain region;It is described The material identical of the material of hard mask layer 5 and the side wall 4 and all different with the material of the subsequent interlayer film 6 and hard mask The stop-layer when material of layer 5 can be etched as the interlayer film 6;3 liang of the hard mask layer 5 and the corresponding gate structure The side wall 4 of side is joined together to form the autoregistration boundary of the bottom of the corresponding contact hole 7;3 top of the gate structure Contact hole 7 forming region the hard mask layer 5 remove.

The material of the interlayer film 6 is silica.The material of the material of the hard mask layer 5 and the side wall 4 is all nitrogen SiClx.

Step 4: as shown in Figure 5A, be contact hole of the embodiment of the present invention manufacturing method step 4 after the completion of vertical view; Fig. 5 B are the sectional views of the AA lines along Fig. 5 A;Interlayer film 6 is formed, the interlayer film 6 is complete by the interval between the gate structure 3 Full packing and the top for extending to the gate structure 3.

Step 5: as shown in Figure 6A, be contact hole of the embodiment of the present invention manufacturing method step 7 after the completion of vertical view; Fig. 6 B are the sectional views of the BB lines along Fig. 6 A.Lithographic definition goes out the forming region of contact hole 7, and the contact hole 7 includes being located at institute State contact hole 7, the contact hole 7 at the top of the source region and the contact hole at the top of the drain region at 3 top of gate structure 7。

Step 6: performing etching to form the contact hole 7 to the interlayer film 6 of the forming region of the contact hole 7 It is open, at least one side of the bottom of the opening of the contact hole 7 at the top of the source region and the drain region is by the hard mask Layer 5 and corresponding 4 autoregistration of the side wall definition, prevent the contact hole 7 photoetching process deviate when occur the source region and 3 phase shorted contacts of the contact hole 7 in the drain region and the corresponding gate structure.

Step 7: filling metal in the opening of the contact hole 7 forms the contact hole 7.Present invention method In, filling metal is tungsten.

The embodiment of the present invention is by before forming interlayer film 6, forming one layer of hard mask layer 5 and being carried out to hard mask layer 5 Chemical wet etching, the hard mask layer 5 after etching at least remain in the grid of 7 side of contact hole at the top of source-drain area i.e. source region or drain region The top of structure 3 carries out the lithographic etch process of interlayer film 6 deposition and contact hole 7 later, and the etching technics of contact hole 7 is pair Interlayer film 6 performs etching, since the respective side of the contact hole 7 at the top of source-drain area is provided with hard mask layer 5,5 He of hard mask layer Adjacent side wall 4 can be as the bottom autoregistration boundary of the etching technics of corresponding contact hole 7, even if due to line width and spacer region Size diminution and lithography and etching technique when generating deviation, can also make the bottom of the Offset portion of contact hole 7 finally fixed Positioned at the surface of hard mask layer 5, as shown in the dotted line frame 8a and 8b of Fig. 6 B, so as to prevent 7 He of contact hole at the top of source-drain area Gate structure 3 is in contact, the short circuit also generated so as to prevent contact hole 7 at the top of source-drain area and gate structure 3 to be in contact.

The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered It is considered as protection scope of the present invention.

Claims (7)

1. a kind of manufacturing method of contact hole, which is characterized in that include the following steps:
Step 1: providing semi-conductive substrate, it is formed with multiple gate structures on the semiconductor substrate, in each grid The both sides of structure form active area and drain region, and the source region or the drain region share for two adjacent gate structures; It is formed with side wall in the side of each gate structure;
Step 2: forming hard mask layer;
Step 3: carrying out chemical wet etching to the hard mask layer, the hard mask layer after etching is described positioned at being subsequently formed The surface of the gate structure of at least side of contact hole at the top of source region or drain region;The material of the hard mask layer and described The material identical of side wall and materials all different with the material of subsequent interlayer film and the hard mask layer can be used as the interlayer Stop-layer when film etches;The hard mask layer and the side wall of the corresponding gate structure both sides are joined together to form correspondence The contact hole bottom autoregistration boundary;The hard mask of the forming region of contact hole at the top of the gate structure Layer removal;
Step 4: forming interlayer film, the interval between the gate structure is filled up completely and extends to described by the interlayer film The top of gate structure;
Step 5: lithographic definition goes out the forming region of contact hole, the contact hole includes being located at connecing at the top of the gate structure Contact hole, the contact hole at the top of the source region and the contact hole at the top of the drain region;
Step 6: performing etching the opening to form the contact hole, institute to the interlayer film of the forming region of the contact hole At least one side of the bottom of the opening of the contact hole at the top of source region and the drain region is stated by the hard mask layer and correspondence Side wall autoregistration definition, the institute in the source region and the drain region occurs when preventing the photoetching process of the contact hole from deviating State contact hole and the corresponding gate structure phase shorted contacts;
Step 7: filling metal in the opening of the contact hole forms the contact hole.
2. the manufacturing method of contact hole as described in claim 1, it is characterised in that:The semiconductor substrate is silicon substrate.
3. the manufacturing method of contact hole as claimed in claim 2, it is characterised in that:The material of the interlayer film is silica.
4. the manufacturing method of contact hole as claimed in claim 3, it is characterised in that:The material of the hard mask layer and the side The material of wall is all silicon nitride.
5. the manufacturing method of contact hole as described in claim 1, it is characterised in that:The gate structure is by gate dielectric layer and more Crystal silicon grid are formed by stacking.
6. the manufacturing method of contact hole as described in claim 1, it is characterised in that:The gate structure is by gate dielectric layer and gold Belong to grid to be formed by stacking.
7. the manufacturing method of contact hole as described in claim 1, it is characterised in that:It is tungsten that metal is filled in step 7.
CN201810330029.4A 2018-04-13 2018-04-13 The manufacturing method of contact hole CN108417533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810330029.4A CN108417533A (en) 2018-04-13 2018-04-13 The manufacturing method of contact hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810330029.4A CN108417533A (en) 2018-04-13 2018-04-13 The manufacturing method of contact hole

Publications (1)

Publication Number Publication Date
CN108417533A true CN108417533A (en) 2018-08-17

Family

ID=63135367

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810330029.4A CN108417533A (en) 2018-04-13 2018-04-13 The manufacturing method of contact hole

Country Status (1)

Country Link
CN (1) CN108417533A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030113993A1 (en) * 2001-12-14 2003-06-19 Sung-Kwon Lee Method for fabricating semiconductor device
US20040067628A1 (en) * 2000-11-15 2004-04-08 Hiroki Koga Semiconductor device including an insulated gate field effect transistor and method of manufacting the same
US20070013076A1 (en) * 2005-07-15 2007-01-18 Kazutaka Akiyama Semiconductor device and method of manufacturing thereof
CN101150064A (en) * 2006-09-21 2008-03-26 联华电子股份有限公司 Method for removing clearance wall, metal semiconductor transistor parts and its making method
KR20090001396A (en) * 2007-06-29 2009-01-08 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
CN107895723A (en) * 2016-09-05 2018-04-10 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and preparation method thereof, electronic installation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040067628A1 (en) * 2000-11-15 2004-04-08 Hiroki Koga Semiconductor device including an insulated gate field effect transistor and method of manufacting the same
US20030113993A1 (en) * 2001-12-14 2003-06-19 Sung-Kwon Lee Method for fabricating semiconductor device
US20070013076A1 (en) * 2005-07-15 2007-01-18 Kazutaka Akiyama Semiconductor device and method of manufacturing thereof
CN101150064A (en) * 2006-09-21 2008-03-26 联华电子股份有限公司 Method for removing clearance wall, metal semiconductor transistor parts and its making method
KR20090001396A (en) * 2007-06-29 2009-01-08 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
CN107895723A (en) * 2016-09-05 2018-04-10 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and preparation method thereof, electronic installation

Similar Documents

Publication Publication Date Title
TWI544529B (en) Finfet device and method for manufacturing the same
US10217669B2 (en) Isolation components for transistors formed on fin features of semiconductor substrates
US9337203B2 (en) Semiconductor device with line-type air gaps and method for fabricating the same
US9064932B1 (en) Methods of forming gate structures by a gate-cut-last process and the resulting structures
CN104425284B (en) Stomata overlying silicon framework of the matrix fin field-effect transistor independent of grid length
TWI460821B (en) Semiconductor device and method of fabricating the same
JP4477953B2 (en) Method for manufacturing memory element
CN104009070B (en) Metal gate and gate contact structure for FinFET
US6812111B2 (en) Methods for fabricating MOS transistors with notched gate electrodes
TWI390729B (en) Semiconductor structures integrating damascene-body finfet's and planar devices on a common substrate and methods for forming such semiconductor structures
US7535061B2 (en) Fin-field effect transistors (Fin-FETs) having protection layers
JP5134760B2 (en) Manufacturing method of recess channel array transistor using mask layer having high etching selectivity with silicon substrate
US7358142B2 (en) Method for forming a FinFET by a damascene process
US7470588B2 (en) Transistors including laterally extended active regions and methods of fabricating the same
KR100521369B1 (en) High speed and low power consumption semiconductor device and method for fabricating the same
KR100614240B1 (en) Semiconductor devices including a field effect transistor and methods of the same
US7253060B2 (en) Gate-all-around type of semiconductor device and method of fabricating the same
US8507342B2 (en) Semiconductor device with buried bit lines and method for fabricating the same
US7361956B2 (en) Semiconductor device having partially insulated field effect transistor (PiFET) and method of fabricating the same
US7615817B2 (en) Methods of manufacturing semiconductor devices and semiconductor devices manufactured using such a method
KR100471173B1 (en) Transistor having multi channel and method of fabricating the same
JP5230737B2 (en) Method for manufacturing adjacent silicon fins of different heights
KR100413829B1 (en) Trench Isolation Structure and Method for Fabricating the Same
US7910440B2 (en) Semiconductor device and method for making the same
US7189617B2 (en) Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination