CN108401454B

CN108401454B - Transaction scheduling method, processor, distributed system and unmanned aerial vehicle

Info

Publication number: CN108401454B
Application number: CN201780004456.7A
Authority: CN
Inventors: 唐上昌; 陈学义
Original assignee: SZ DJI Technology Co Ltd
Current assignee: SZ DJI Technology Co Ltd
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2021-10-22
Anticipated expiration: 2037-06-30
Also published as: CN108401454A; WO2019000398A1

Abstract

Provided are a transaction scheduling method, a processor, a distributed system and a unmanned aerial vehicle. The method can be applied to a distributed system with multiple processors, each processor in the distributed system is configured with a virtual clock, and the virtual clocks of the processors in the distributed system are synchronous, and the method comprises the following steps: any first processor in the distributed system acquires a first transaction to be scheduled (310); the first processor determining a scheduled time of the first transaction relative to a virtual clock of the first processor (320); the first processor schedules (330) the first transaction based on a scheduled time of the first transaction relative to a virtual clock of the first processor. The technical scheme can improve the cooperative scheduling process of the distributed system.

Description

Transaction scheduling method, processor, distributed system and unmanned aerial vehicle

Copyright declaration

The disclosure of this patent document contains material which is subject to copyright protection. The copyright is owned by the copyright owner. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office official records and records.

Technical Field

The present application relates to the field of distributed systems, and more particularly, to a transaction scheduling method, a processor, a distributed system, and an unmanned aerial vehicle.

Background

A distributed system generally consists of multiple subsystems, which may cooperate with each other to schedule one or more transactions cooperatively.

In a distributed system, in order to implement cooperative scheduling, the processors generally need to exchange cooperative messages through a dedicated communication interface, and then software on each processor executes a synchronization process, and after the processors are synchronized, each processor performs cooperative scheduling on transactions, which results in a complex cooperative scheduling process. Therefore, there is a need to improve the co-scheduling process of distributed systems.

Disclosure of Invention

The application provides a transaction scheduling method, a processor, a distributed system and an unmanned aerial vehicle, which can improve the cooperative scheduling process of the distributed system.

In a first aspect, a transaction scheduling method is provided, where the method is applicable to a distributed system having multiple processors, each processor in the distributed system is configured with a virtual clock, and the virtual clocks of the processors in the distributed system are synchronized, and the method includes: any first processor in the distributed system acquires a first transaction to be scheduled; the first processor determining a scheduled time of the first transaction relative to a virtual clock of the first processor; the first processor schedules the first transaction according to a scheduling time of the first transaction relative to a virtual clock of the first processor.

In a second aspect, a processor is provided that includes means capable of performing the method of the first aspect.

In a third aspect, a processor is provided, where the processor is a first processor in a distributed system, each processor in the distributed system is configured with a virtual clock, and the virtual clocks of the processors in the distributed system are synchronized, and the first processor includes: a memory for storing computer instructions; a controller to execute computer instructions stored in the memory to perform the following operations: acquiring a first transaction to be scheduled; determining a scheduled time of the first transaction relative to a virtual clock of the first processor; and scheduling the first transaction according to the scheduling time of the first transaction relative to the virtual clock of the first processor.

In a fourth aspect, there is provided a distributed system comprising a processor as described in the third aspect.

In a fifth aspect, there is provided a drone comprising a distributed system as described in the fourth aspect.

In a sixth aspect, a computer-readable storage medium is provided, having stored therein instructions, which, when executed on a processor, cause the processor to perform the method according to the first aspect.

In a seventh aspect, a computer program product is provided comprising instructions which, when run on a processor, cause the processor to perform the method according to the first aspect.

The method and the device can improve the cooperative scheduling process of the distributed system.

Drawings

Fig. 1 is an exemplary diagram of an overall architecture of a distributed system.

Fig. 2 is a schematic flow chart of virtual clock synchronization provided by an embodiment of the present invention.

Fig. 3 is a schematic flow chart of a transaction scheduling method according to an embodiment of the present invention.

Fig. 4 is a schematic block diagram of a processor provided by an embodiment of the present invention.

Fig. 5 is a schematic block diagram of a processor according to another embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a distributed system provided by an embodiment of the present invention.

Fig. 7 is a schematic structural diagram of the unmanned aerial vehicle provided in the embodiment of the present invention.

Detailed Description

The technical scheme provided by the application can be used as one of bottom layer supporting technologies of a distributed system, and is applied to scenes needing to carry out cooperative scheduling or having requirements on clock synchronization. For example, the technical scheme provided by the application can be applied to the clock synchronization of the telecommunication base station or the clock synchronization of the basic network. For another example, the technical scheme provided by the application can be applied to automatic systems such as vehicle-mounted distributed control systems, high-speed distributed servo control systems, unmanned aerial vehicles, unmanned vehicles and mobile robots.

As shown in fig. 1, a distributed system typically includes a plurality of processors, which may be connected by a communication channel. The communication channel may be responsible for exchanging clock synchronization messages and/or scheduling assignment messages between different processors.

For the convenience of understanding, the following takes the control system of the drone as an example, and illustrates the cooperative scheduling process of the conventional distributed system.

Traditional four-axis unmanned aerial vehicle's control system only need control the motor and the remote control unit of four axles, and control system's demand is simple. Therefore, only one processor (such as a Micro Controller Unit (MCU)) or a system-on-a-chip (SOC)) needs to be arranged inside the control system of the conventional four-axis drone to complete the control of the drone.

Along with the development of unmanned aerial vehicle technology, unmanned aerial vehicle's demand to control system is higher and higher. For example, the control systems of current drones typically contain multiple types of subsystems for implementing different functions. For example, the control system of the drone may include a flight control subsystem, a pan-tilt subsystem, a camera subsystem, an obstacle avoidance subsystem, a map transmission subsystem, an application subsystem, and the like. As subsystems become more complex in function and the processing performance requirements of processors may vary from subsystem to subsystem, many subsystems have evolved from sharing a processor to using a dedicated processor. Therefore, the control systems of present day drones typically contain multiple processors of different types. As an example, the control system of the drone may include an MCU, an SOC, a Digital Signal Processing (DSP), and a dedicated hardware accelerator, among others. A processor in the drone control system may be provided with a dedicated communication interface, such as a Universal Serial Bus (USB) interface, a Serial Peripheral Interface (SPI), a universal asynchronous receiver/transmitter (UART), a Mobile Industry Processor Interface (MIPI), and the like. Further, the processors in the drone control system may be interconnected by a communication channel. It follows that the control systems of present drones are gradually evolving into distributed systems comprising multiple processors.

With the complication of the unmanned aerial vehicle technology, in the control system of the unmanned aerial vehicle, in order to control the unmanned aerial vehicle to perform a certain complex task, the respective processors of the respective subsystems are generally required to coordinate to jointly complete the task. For example, when it is desired to capture an image of a target scene by a drone, the drone is affected by strong winds, causing the fuselage to shake. Under the condition, the holder subsystem and the camera subsystem of the unmanned aerial vehicle can be coordinated, so that the unmanned aerial vehicle can still stably shoot a target scene under the influence of strong wind.

When the processors in the distributed system need to perform cooperative scheduling, the processors generally need to exchange cooperative messages through a dedicated communication interface, and then software on each processor executes a synchronization process, and after the processors are synchronized, the processors perform cooperative scheduling on transactions, so that the cooperative scheduling process is complex.

Further, when one processor in the distributed system sends a cooperative message to another processor, if the receiving processor does not respond to the cooperative message in time for some reason (for example, the processor is currently scheduling some transaction with a large computation), the cooperative scheduling process of the cooperative transaction may fail.

The problem of the distributed system in the cooperative scheduling is exemplified by taking the unmanned aerial vehicle as an example, but the application scenario of the technical scheme provided by the embodiment of the invention is not limited to the unmanned aerial vehicle scenario, and the method can be applied to any distributed system requiring clock synchronization or cooperative scheduling, and particularly can be applied to a distributed system in which processors are not connected through a real-time bus.

In order to improve a cooperative scheduling mode of a distributed system, the embodiment of the invention configures a virtual clock for a processor in the distributed system. The virtual clocks of the processors in the distributed system may have the same clock frequency. The clock frequency or clock period granularity of the virtual clock may be different for distributed systems of different requirements. For example, the clock period of the virtual clock may be a clock period on the order of microseconds or a clock period on the order of milliseconds. The virtual clock may be a variable whose value may represent a count value of the virtual clock, and thus a time of the virtual clock (the time of the virtual clock may be referred to as a virtual time). The format of the variable used for representing the virtual clock is not specifically limited in the embodiments of the present invention, and the variable may be selected as a 32-bit variable or a 64-bit variable. The larger the length of the variable is, the less the variable is possible to reach the maximum value during the operation of the distributed system, so that the calculation problem caused by quick turnover (i.e. recounting from 0) after the variable reaches the maximum value can be effectively avoided, and the complexity of software processing is further simplified. Use unmanned aerial vehicle as an example, can set for the variable length of virtual clock by the time of endurance of comprehensive consideration unmanned aerial vehicle, make unmanned aerial vehicle power-on work in-process as far as possible, quick upset can not take place for the variable of this virtual clock. For example, for a drone, the variable length of the virtual clock may be defined as 64 bits.

Each processor in the distributed system may be responsible for initializing and calibrating a respective virtual clock. Taking any processor in a distributed system (hereinafter referred to as a first processor) as an example, before the first processor uses its own virtual clock, a variable for characterizing the virtual clock of the first processor may be initialized; determining a virtual time of a virtual clock of a first processor; and assigning a value to the variable according to the virtual time of the virtual clock of the first processor to calibrate the virtual clock of the first processor.

When initializing a variable, an initial value of the variable may be set to 0. The first processor may then communicate with the other processors to obtain the virtual time of the virtual clock. The virtual time may be represented by a count value of a virtual clock. The first processor may then use the count value to assign a variable of the virtual clock of the first processor to complete the calibration of the virtual clock of the first processor.

In addition, the first processor may also be responsible for synchronizing the time accuracy of the virtual clock, updating the virtual clock, and maintaining the current time and state of the virtual clock. For example, the first processor may continuously perform an add-1 operation on the value of the variable of the virtual clock at the clock frequency of the virtual clock.

It should be noted that the clock frequency or the precision of the virtual clock may be determined according to the application of the distributed system, where the requirement for the precision of the cooperative scheduling is high, the clock frequency or the precision of the virtual clock may be set to be higher, and where the requirement for the precision of the cooperative scheduling is low, the clock frequency or the precision of the virtual clock may be set to be lower, so as to simplify the implementation.

The embodiment of the invention does not specifically limit the synchronization mode of the virtual clock, and different clock synchronization modes and algorithms can be selected according to the application occasions of the distributed system. Taking the drone as an example, a control system of the drone may perform clock synchronization in a master-slave manner, for example, a virtual clock of a distributed system may be synchronized based on a clock synchronization algorithm provided by a 1588V2 protocol.

The following describes a master-slave clock synchronization method provided by an embodiment of the present invention in detail.

First, a processor in the distributed system may be defined as a master processor, and other processors in the distributed system may be defined as slave processors. The master processor can use the own virtual clock as a clock synchronization source of the distributed system and communicate with the slave processors, so that the virtual clocks of the slave processors are synchronized with the virtual clock of the master processor, and the frequency and the phase of the virtual clocks of the slave processors and the virtual clock of the master processor are kept consistent.

Assuming that the first processor is a slave processor in a distributed system, the first processor may communicate with a master processor to acquire line delay information between the first processor and the master processor; then, the first processor may determine a time difference between a virtual clock of the first processor and a virtual clock of the main processor according to the line delay information; then, the first processor may adjust the virtual clock of the first processor according to the time difference, so that the virtual clock of the first processor is synchronized with the virtual clock of the main processor.

Specifically, as shown in fig. 2, the first processor receives the synchronization message sent by the main processor, and records a virtual time t2 when the first processor receives the synchronization message; the first processor receives a following message of the synchronous message sent by the main processor, wherein the following message comprises a virtual time t1 of the synchronous message sent by the main processor; the first processor sends a delay request message to the main processor and records the virtual time t3 when the first processor sends the delay request message; the first processor receives a delayed response message sent by the host processor, the delayed response message including a virtual time t4 at which the host processor received the delayed request message.

The determining, by the first processor, a time difference between the virtual clock of the first processor and the virtual clock of the main processor according to the line delay information may include: the first processor determines a time difference based on virtual time t1, virtual time t2, virtual time t3, and virtual time t 4.

For example, the first processor may calculate the master-to-slave delay1 (t2-t1) and then calculate the slave-to-master delay2 (t4-t 3). Assuming that the master-to-slave delay and the slave-to-master delay are equal, the first processor may calculate a time difference T of the virtual clock of the first processor and the virtual clock of the master processor (delay1-delay 2). Of course, the first processor may calculate the time difference between the virtual clock of the first processor and the virtual clock of the main processor based on the formula T (T2-T1-T4+ T3) without calculating the delay.

In other embodiments, the first processor may also be a main processor in a distributed system, and the first processor may send a synchronization message and a following message of the synchronization message to the other processors, where the following message includes a virtual time t1 at which the first processor sends the synchronization message; a first processor receives delay request messages sent by other processors; the first processor sends a delay response message to the other processors, the delay response message including the virtual time t4 at which the first processor receives the delay request message, so that the other processors determine a time difference between the virtual clock of the first processor and the virtual clocks of the other processors based on the virtual time t1 and the virtual time t4, and adjust the virtual clocks of the other processors based on the time difference so that the virtual clocks of the other processors are synchronized with the virtual clock of the first processor.

In this embodiment, the first processor is taken as a master processor, and the other processors are taken as slave processors for illustration. In this embodiment, the specific synchronization process of the other processors is similar to the synchronization process of the first processor as the slave processor described in the previous embodiment, and in order to avoid repetition, the detailed description is omitted here.

The synchronization process of the virtual clock is mainly described above. It should be understood that the above-described virtual clock synchronization process is only an example, and actually, other conventional clock synchronization algorithms may also be used to synchronize the virtual clocks of the processors in the distributed system, which is not specifically limited in this embodiment of the present invention. By keeping the virtual clocks of the processors in the distributed system synchronous, the processors in the distributed system can schedule various transactions by taking uniform time (namely virtual time corresponding to the virtual clocks) as a reference, the processors in the distributed system only need to maintain the virtual clocks regularly and keep the synchronism among the virtual clocks, and a cooperation message does not need to be sent through an application layer protocol before each cooperation scheduling as in the traditional distributed system, so that the software implementation is simplified.

On the basis of virtual clock synchronization, the following describes in detail a transaction scheduling method provided by an embodiment of the present invention with reference to fig. 3.

Fig. 3 is a schematic flow chart of a transaction scheduling method according to an embodiment of the present invention. Fig. 3 is mainly illustrated by taking the transaction scheduling process of the first processor in the distributed system as an example. The first processor may be any one of the processors in a distributed system. The method of FIG. 3 may include steps 310-330, which are described in detail below with respect to FIG. 3.

In step 310, a first processor retrieves a first transaction to be scheduled. A first processor of the plurality of processors acquires a target task to be scheduled.

In step 320, the first processor determines a scheduled time of the first transaction relative to a virtual clock of the first processor.

The first transaction may be any one of the transactions, and the triggering manner of the first transaction and the determination manner of the scheduling time of the first transaction relative to the virtual clock of the first processor may be various, for example, the first transaction may be autonomously triggered by the first processor and the scheduling time of the first transaction relative to the virtual clock of the first processor may be allocated; in another example, a first transaction may be triggered by another processor and assigned a scheduled time relative to the virtual clock of the first processor, and then the other processor sends the first transaction and its scheduled time relative to the virtual clock to the first processor via a message (e.g., a task assignment message).

In step 330, the first processor schedules the first transaction based on its scheduled time relative to the virtual clock of the first processor.

As can be seen from the description of the corresponding embodiment in fig. 3, the transaction scheduling processes of the processors in the distributed system are independent from each other, except that the scheduling time of the transaction is based on a uniform virtual clock. In other words, each processor schedules its respective transaction with the same virtual clock as a reference, and the processor may not even need to know that it is scheduling in coordination with other processors, and the coordination between them is nevertheless done due to the common time reference.

The implementation of step 330 is described in detail below.

In some embodiments, step 330 may include: the first processor converts the scheduling time of the first transaction relative to a virtual clock of the first processor into a local scheduling time of the first transaction, wherein the local scheduling time of the first transaction is the scheduling time of the first transaction relative to the local clock of the first processor; the first processor schedules the first transaction according to its local schedule time.

The first processor may convert the scheduled time of the virtual clock of the first processor to the local scheduled time of the first transaction based on a relationship of a clock frequency of the virtual clock of the first processor to a clock frequency of a local clock of the first processor. Assuming that the clock frequency of the virtual clock of the first processor is 2 times the clock frequency of the local clock, the current time of the virtual clock of the first processor is 300 (where the time is represented by the count value of the virtual clock), the scheduled time of the first transaction with respect to the virtual clock of the first processor is 305, and the current time of the local clock of the first processor is 500 (where the time is represented by the count value of the local clock), the local scheduled time of the first transaction can be calculated as 510 according to the relationship between the clock frequencies of the two clocks.

The first processor may schedule the first transaction based on its locally scheduled time in a variety of ways.

As one example, the first transaction may be scheduled in a conventional transaction scheduling manner. Specifically, the first transaction may be added to the scheduling queue of the first processor, and then a periodically triggered timer is set, and each time the timer triggers an interrupt signal, the first processor checks whether there is a transaction to be scheduled in the scheduling queue. Although such a transaction scheduling method is simple, there is a problem of power waste. For example, when a timer sends an interrupt signal, if there is no transaction to be scheduled at that time, the transmission power of the interrupt signal of the timer is wasted.

Optionally, in some embodiments, before the first processor schedules the first transaction according to its local schedule time, the method of fig. 3 may further include: the method comprises the steps that a first processor receives a first interrupt signal triggered by a first timer, wherein the first interrupt signal is used for indicating that a local clock of the first processor reaches the local scheduling time of a previous transaction of a first transaction; responding to the first interrupt signal, the first processor schedules a previous transaction of the first transaction and adjusts the timing duration of the first timer, so that the trigger time of a next interrupt signal of the first timer is the local scheduling time of the first transaction; the scheduling, by the first processor, the first transaction according to the local scheduling time of the first transaction may include: in response to a next interrupt signal, the first processor schedules a first transaction.

In the embodiment of the invention, the first timer is introduced, and triggers the interrupt signal aperiodically to instruct the first processor to schedule the transaction, but the timing duration of the first timer is reset every time one transaction is scheduled, so that the timing duration of the first timer is equal to the time interval from the current time to the local scheduling time of the next transaction, thereby saving the system power and improving the accuracy of transaction scheduling.

Optionally, in some embodiments, before the first processor schedules the first transaction according to its local schedule time, the method of fig. 3 may further include: the first processor determining a scheduled end time for the first transaction; when the time interval between the scheduling end time of the first transaction and the local scheduling time of the next transaction of the first transaction is less than the preset time interval, the first processor merges the first transaction and the next transaction of the first transaction into one transaction.

Specifically, the preset time interval may be a clock cycle granularity of a scheduled transaction of the first processor. For example, the first processor has scheduled a transaction (hereinafter transaction 1) in 340ms, and transaction 1 has executed 2.95ms, i.e., the scheduled end time of transaction 1 is 342.95 ms. If the local scheduling time of the next scheduled transaction (hereinafter referred to as transaction 2) is 343ms, which is 50 μ s different from the local scheduling time of transaction 2, if the minimum clock granularity of the scheduled transaction of the first processor is 100 μ s, then the first processor does not need to wait 50 μ s to re-activate the first processor to schedule transaction 2, and the first processor can directly start scheduling transaction 2, which is equivalent to combining transaction 1 and transaction 2 into one transaction for scheduling. The embodiment of the invention optimizes the transaction scheduling mode of the processor.

Optionally, in some embodiments, the first processor scheduling the first transaction according to its local scheduling time may include: in the process of scheduling the transactions in the first scheduling queue by the first processor, in response to that the local time of the first processor reaches the local scheduling time of the first transaction, the first processor schedules the first transaction, wherein the first scheduling queue is one of a plurality of scheduling queues of the first processor, the plurality of scheduling queues further include a second scheduling queue and a third scheduling queue, the first scheduling queue contains the transactions of which the local scheduling time is located in the current period, the second scheduling queue contains the transactions of which the local scheduling time is located in the first period, and the third scheduling queue contains the transactions of which the local scheduling time is located after the first period, wherein the first period is the next period of the current period.

Optionally, in some embodiments, the method of fig. 3 may further include: the first processor receives a second interrupt signal triggered by a second timer, wherein the second interrupt signal is used for indicating the end of the current time period; in response to the second interrupt signal, the first processor schedules transactions in the second scheduling queue and updates transactions in the first scheduling queue and the third scheduling queue such that the first scheduling queue contains transactions having a local scheduling time that is within a second time period, and the third scheduling queue contains transactions having a local scheduling time that is after the second time period, wherein the second time period is a next time period of the first time period.

The form of the scheduling queue is not particularly limited in the embodiment of the present invention, and for example, the transaction to be scheduled may be recorded in the form of a scheduling table. The following description will be made by taking a schedule as an example.

The first scheduling queue can be called a ping schedule table of the first processor, the second scheduling queue can be called a pong schedule table of the first processor, and the third scheduling queue can be called a remaining transaction schedule table. The ping schedule may contain transactions with a locally scheduled time in the current time period. The pong schedule may contain transactions whose local schedule time is in the next period. The remaining transaction schedule may contain the remaining transactions to be scheduled for the first processor.

Taking the period length of 10ms as an example, the ping schedule table may include transactions whose local scheduling time is 0-10ms, and the pong table may include transactions whose local scheduling time is 10-20 ms. The remaining transaction schedule may contain transactions whose local schedule time is 20ms later. The first processor firstly schedules transactions in the ping scheduling table within 0-10 ms; after 10ms is finished, the first processor points to the pong schedule to schedule the transaction with the local scheduling time of 10-20 ms. In addition, the first processor needs to update the ping schedule and the rest transaction schedules, and the transactions which are positioned in 20-30ms in the rest transaction schedules are added into the ping schedule. After 20ms has ended, the first processor redirects to the ping schedule to schedule transactions with local scheduling times between 20-30ms, and so on.

As can be seen from the above description, the first processor alternately uses the ping schedule (or the first scheduling queue) and the pong schedule (or the second scheduling queue) as the current schedule (or the current scheduling queue), so that a software scheduler inside the first processor does not need to search all transactions to be scheduled for currently needing to be scheduled, but only needs to search in the current schedule (or the current scheduling queue), thereby effectively reducing the implementation complexity of the scheduling process of the first processor.

It should be noted that, when a certain new transaction to be scheduled is acquired, the first processor may add the new transaction to a corresponding scheduling table (or scheduling queue) according to the local scheduling time of the new transaction. Taking the current scheduling table as a ping scheduling table (first scheduling queue), if the local scheduling time of the new transaction is in the current period, the new transaction can be added to the ping scheduling table, if the local scheduling time of the new transaction is in the next period of the current period, the new transaction can be added to a pong scheduling table (second scheduling queue), otherwise, the new transaction can be added to the rest of the transaction scheduling tables (third scheduling queue).

In addition, the embodiment of the present invention introduces a second timer, where the second timer may periodically send an interrupt signal to the first processor with the length of the current time period as a timing duration (e.g., 10ms), and trigger the first processor to update the current schedule (or the current scheduling queue).

In the following, embodiments of the apparatus of the present invention are described, and since embodiments of the apparatus can perform the above-described method, reference can be made to the foregoing embodiments of the method for parts not described in detail.

Fig. 4 is a schematic block diagram of a processor provided by an embodiment of the present invention. The processor of fig. 4 may be the first processor described above, and the first processor 400 may include an obtaining module 410, a first determining module 420, and a scheduling module 430, the functions of which are described in detail below in the first processor 400.

The fetch module 410 may fetch a first transaction to be scheduled.

The first determination module 420 may determine a scheduled time of the first transaction relative to a virtual clock of the first processor 400.

The scheduling module 430 may schedule the first transaction according to a scheduled time of the first transaction relative to a virtual clock of the first processor 400.

Optionally, in some embodiments, the scheduling module 430 may be specifically configured to convert the scheduled time of the first transaction relative to the virtual clock of the first processor 400 into a local scheduled time of the first transaction, where the local scheduled time of the first transaction is the scheduled time of the first transaction relative to the local clock of the first processor 400; and scheduling the first transaction according to the local scheduling time of the first transaction.

Optionally, in some embodiments, the first processor 400 may be further configured to receive a first timer-triggered first interrupt signal, where the first interrupt signal is used to indicate that a local clock of the first processor 400 reaches a local scheduled time of a previous transaction of the first transaction; in response to the first interrupt signal, scheduling a previous transaction of the first transaction, and adjusting the timing duration of the first timer, so that the trigger time of a next interrupt signal of the first timer is the local scheduling time of the first transaction; the scheduling module 430 is specifically configured to schedule the first transaction by the first processor 400 in response to the next interrupt signal.

Optionally, in some embodiments, the first processor 400 determines a scheduled end time of the first transaction; when the time interval between the scheduled end time of the first transaction and the local scheduled time of the next transaction of the first transaction is less than the preset time interval, the first processor 400 merges the first transaction and the next transaction of the first transaction into one transaction.

Optionally, in some embodiments, the scheduling module 430 is specifically configured to schedule the first transaction in response to that the local time of the first processor 400 reaches the local scheduling time of the first transaction during the process that the first processor 400 schedules the transactions in a first scheduling queue, where the first scheduling queue is one of a plurality of scheduling queues of the first processor 400, the plurality of scheduling queues further include a second scheduling queue and a third scheduling queue, the first scheduling queue includes the transactions whose local scheduling time is in the current time period, the second scheduling queue includes the transactions whose local scheduling time is in the first time period, and the third scheduling queue includes the transactions whose local scheduling time is after the first time period, where the first time period is the next time period of the current time period.

Optionally, in some embodiments, the first processor 400 may further include a receiving module, configured to receive a second interrupt signal triggered by a second timer, where the second interrupt signal is used to indicate that the current time period is over. The scheduling module 430 is further configured to schedule transactions in a second scheduling queue in response to the second interrupt signal, and update transactions in the first scheduling queue and the third scheduling queue, so that the first scheduling queue contains transactions whose local scheduling time is in a second time period, and the third scheduling queue contains transactions whose local scheduling time is after the second time period, where the second time period is a next time period to the first time period.

Optionally, in some embodiments, the first processor 400 may further include a communication processing module for communicating with other processors in the distributed system to synchronize the virtual clock of the first processor 400 with the virtual clocks of the other processors.

Optionally, in some embodiments, the first processor 400 is a slave processor in the plurality of processors, the plurality of processors further includes a master processor, and the communication processing module is specifically configured to communicate with the master processor to acquire line delay information between the first processor 400 and the master processor; determining a time difference between a virtual clock of the first processor 400 and a virtual clock of the main processor according to the line delay information; adjusting the virtual clock of the first processor 400 according to the time difference, so that the virtual clock of the first processor 400 is synchronized with the virtual clock of the main processor.

Optionally, in some embodiments, the communication processing module is specifically configured to receive a synchronization message sent by the host processor, and record a virtual time t2 when the first processor 400 receives the synchronization message; receiving a following message of the synchronization message sent by the main processor, wherein the following message comprises a virtual time t1 of the main processor sending the synchronization message; sending a delay request message to the main processor, and recording a virtual time t3 when the first processor 400 sends the delay request message; and receiving a delay response message sent by the main processor, wherein the delay response message comprises the virtual time t4 when the main processor receives the delay request message.

Optionally, in some embodiments, the communication processing module is specifically configured to determine the time difference according to the virtual time t1, the virtual time t2, the virtual time t3, and the virtual time t 4.

Optionally, in some embodiments, the time difference T ═ (T2-T1-T4+ T3).

Optionally, in some embodiments, the first processor 400 is a master processor in the plurality of processors, the other processors are slave master processors of the distributed system, and the communication processing module is specifically configured to send a synchronization message and a following message of the synchronization message to the other processors, where the following message includes a virtual time t1 at which the first processor 400 sends the synchronization message; receiving delay request messages sent by other processors; sending a delayed response message to the other processors, the delayed response message including the virtual time t4 at which the first processor 400 receives the delay request message, so that the other processors determine a time difference between the virtual clock of the first processor 400 and the virtual clock of the other processors based on the virtual time t1 and the virtual time t4, and adjust the virtual clock of the other processors based on the time difference, so that the virtual clock of the other processors is synchronized with the virtual clock of the first processor 400.

Optionally, in some embodiments, the first processor 400 may further include an initialization module, a third determination module, and an assignment module. The initialization module is configured to initialize variables that characterize the virtual clock of the first processor 400. The third determining module is configured to determine a virtual time of a virtual clock of the first processor 400. The assigning module is configured to assign a value to the variable according to the virtual time of the virtual clock of the first processor 400, so as to calibrate the virtual clock of the first processor 400.

Optionally, in some embodiments, the first processor 400 may further include a fourth determining module and an updating module. The fourth determining module is configured to determine the clock frequency of the virtual clock of the first processor 400, where the clock frequencies of the virtual clocks in the distributed system are the same. The update module is configured to update the count value of the variable according to the clock frequency of the virtual clock of the first processor 400.

Fig. 5 is a schematic block diagram of a processor according to another embodiment of the present invention. The processor of fig. 5 may be any one of the first processors in a distributed system. Each processor in the distributed system is configured with a virtual clock, and the virtual clocks of the processors in the distributed system are synchronized. The first processor 500 includes a memory 510 and a controller 520.

Memory 510 may be used to store computer instructions.

The controller 520 may be used to execute computer instructions stored in memory to perform the following operations: acquiring a first transaction to be scheduled; determining a scheduled time of the first transaction relative to a virtual clock of the first processor 500; the first transaction is scheduled according to its scheduled time relative to the virtual clock of the first processor 500.

Optionally, in some embodiments, the scheduling the first transaction according to the scheduled time of the first transaction with respect to the virtual clock of the first processor 500 may include: converting a scheduled time of the first transaction relative to a virtual clock of the first processor 500 into a local scheduled time of the first transaction, wherein the local scheduled time of the first transaction is the scheduled time of the first transaction relative to the local clock of the first processor 500; the first transaction is scheduled according to its local schedule time.

Optionally, in some embodiments, before scheduling the first transaction according to its local scheduling time, the controller 520 is further configured to: receiving a first interrupt signal triggered by a first timer, the first interrupt signal being used to indicate that a local clock of the first processor 500 reaches a local scheduling time of a previous transaction of the first transaction; responding to the first interrupt signal, scheduling a previous transaction of the first transaction, and adjusting the timing duration of the first timer, so that the trigger time of a next interrupt signal of the first timer is the local scheduling time of the first transaction; the scheduling the first transaction according to the local scheduling time of the first transaction may include: in response to a next interrupt signal, a first transaction is scheduled.

Optionally, in some embodiments, before the scheduling of the first transaction according to the local scheduling time of the first transaction, the controller 520 is further configured to: determining a scheduled end time for the first transaction; and when the time interval between the scheduling ending time of the first transaction and the local scheduling time of the next transaction of the first transaction is less than the preset time interval, combining the first transaction and the next transaction of the first transaction into one transaction.

Optionally, in some embodiments, the scheduling the first transaction according to the local scheduling time of the first transaction may include: in the process of scheduling the transaction in the first scheduling queue by the first processor 500, the first transaction is scheduled in response to the local time of the first processor 500 reaching the local scheduling time of the first transaction, where the first scheduling queue is one of the scheduling queues of the first processor 500, the scheduling queues further include a second scheduling queue and a third scheduling queue, the first scheduling queue contains the transaction whose local scheduling time is in the current time period, the second scheduling queue contains the transaction whose local scheduling time is in the first time period, and the third scheduling queue contains the transaction whose local scheduling time is after the first time period, where the first time period is the next time period of the current time period.

Optionally, in some embodiments, the controller 520 may also be configured to: receiving a second interrupt signal triggered by a second timer, wherein the second interrupt signal is used for indicating the end of the current time period; and in response to the second interrupt signal, scheduling the transactions in the second scheduling queue, and updating the transactions in the first scheduling queue and the third scheduling queue, so that the first scheduling queue contains the transactions with the local scheduling time in a second time period, and the third scheduling queue contains the transactions with the local scheduling time after the second time period, wherein the second time period is the next time period of the first time period.

Optionally, in some embodiments, before scheduling the first transaction according to its scheduled time relative to the virtual clock of the first processor 500, the controller 520 may be further configured to: communicate with other processors in the distributed system to synchronize the virtual clock of the first processor 500 with the virtual clocks of the other processors.

Optionally, in some embodiments, the first processor 500 is a slave processor of a plurality of processors, the plurality of processors further including a master processor, and communicating with other processors of the distributed system to synchronize the virtual clock of the first processor 500 with the virtual clocks of the other processors may include: communicating with the main processor to acquire line delay information between the first processor 500 and the main processor; determining a time difference between the virtual clock of the first processor 500 and the virtual clock of the main processor according to the line delay information; according to the time difference, the virtual clock of the first processor 500 is adjusted so that the virtual clock of the first processor 500 is synchronized with the virtual clock of the main processor.

Optionally, in some embodiments, the communicating with the main processor to acquire the line delay information between the first processor 500 and the main processor may include: receiving a synchronization message sent by the main processor, and recording the virtual time t2 when the first processor 500 receives the synchronization message; receiving a following message of the synchronous message sent by the main processor, wherein the following message comprises a virtual time t1 of the synchronous message sent by the main processor; sending a delay request message to the main processor, and recording a virtual time t3 when the first processor 500 sends the delay request message; and receiving a delay response message sent by the main processor, wherein the delay response message comprises the virtual time t4 when the main processor receives the delay request message.

Optionally, in some embodiments, the determining a time difference between the virtual clock of the first processor 500 and the virtual clock of the main processor according to the line delay information may include: the time difference is determined from virtual time t1, virtual time t2, virtual time t3, and virtual time t 4.

Optionally, in some embodiments, the time difference T ═ (T2-T1-T4+ T3).

Optionally, in some embodiments, the first processor 500 is a master processor of a plurality of processors, and the other processors are slave master processors of a distributed system, and communicating with the other processors of the distributed system to synchronize the virtual clock of the first processor 500 with the virtual clocks of the other processors may include: sending a synchronization message to the other processors and a follow-up message of the synchronization message, the follow-up message containing the virtual time t1 at which the first processor 500 sends the synchronization message; receiving delay request messages sent by other processors; and sending a delay response message to the other processors, wherein the delay response message comprises the virtual time t4 for the first processor 500 to receive the delay request message, so that the other processors determine the time difference between the virtual clock of the first processor 500 and the virtual clocks of the other processors based on the virtual time t1 and the virtual time t4, and adjust the virtual clocks of the other processors based on the time difference, so that the virtual clocks of the other processors are synchronized with the virtual clock of the first processor 500.

Optionally, in some embodiments, before scheduling the first transaction according to its scheduled time relative to the virtual clock of the first processor 500, the controller 520 may be further configured to: initializing variables for characterizing a virtual clock of the first processor 500; determining a virtual time of a virtual clock of the first processor 500; the variable is assigned a value to calibrate the virtual clock of the first processor 500 based on the virtual time of the virtual clock of the first processor 500.

Optionally, in some embodiments, the controller 520 is further configured to: determining a clock frequency of a virtual clock of the first processor 500, wherein the clock frequencies of the virtual clocks in the distributed system are the same; the count value of the variable is updated according to the clock frequency of the virtual clock of the first processor 500.

The embodiment of the invention also provides a distributed system. As shown in fig. 6, the distributed system 600 includes the first processor 500 described above. For example, each processor in the distributed system 600 may perform the functions as performed by the first processor 500 above.

The embodiment of the invention also provides the unmanned aerial vehicle. As shown in fig. 7, the drone 700 may include a distributed system 600 as shown in fig. 6.

In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware or any other combination. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Video Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A transaction scheduling method is applied to a distributed system with a plurality of processors, each processor in the distributed system is configured with a virtual clock, and the virtual clocks of the processors in the distributed system are synchronized,

the method comprises the following steps:

any first processor in the distributed system acquires a first transaction to be scheduled;

the first processor determining a scheduled time of the first transaction relative to a virtual clock of the first processor;

the first processor schedules the first transaction according to a scheduling time of the first transaction relative to a virtual clock of the first processor.

2. The method of claim 1, wherein the first processor scheduling the first transaction based on a scheduled time of the first transaction relative to a virtual clock of the first processor comprises:

the first processor converts the scheduling time of the first transaction relative to the virtual clock of the first processor into the local scheduling time of the first transaction, wherein the local scheduling time of the first transaction is the scheduling time of the first transaction relative to the local clock of the first processor;

the first processor schedules the first transaction according to the local scheduling time of the first transaction.

3. The method of claim 2, wherein prior to the first processor scheduling the first transaction according to the local scheduled time of the first transaction, the method further comprises:

the first processor receives a first interrupt signal triggered by a first timer, wherein the first interrupt signal is used for indicating that a local clock of the first processor reaches a local scheduling time of a previous transaction of the first transaction;

in response to the first interrupt signal, the first processor schedules a previous transaction of the first transaction and adjusts the timing duration of the first timer so that the trigger time of a next interrupt signal of the first timer is the local scheduling time of the first transaction;

the first processor schedules the first transaction according to the local scheduling time of the first transaction, including:

in response to the next interrupt signal, the first processor schedules the first transaction.

4. The method of claim 2, wherein prior to the first processor scheduling the first transaction according to the local scheduled time of the first transaction, the method further comprises:

the first processor determining a scheduled end time for the first transaction;

when the time interval between the scheduling end time of the first transaction and the local scheduling time of the next transaction of the first transaction is less than the preset time interval, the first processor merges the first transaction and the next transaction of the first transaction into one transaction.

5. The method of claim 2, wherein the first processor scheduling the first transaction according to the local scheduled time of the first transaction comprises:

in the process of scheduling, by the first processor, a transaction in a first scheduling queue, in response to a local time of the first processor reaching a local scheduling time of the first transaction, the first processor schedules the first transaction, where the first scheduling queue is one of a plurality of scheduling queues of the first processor, the plurality of scheduling queues further includes a second scheduling queue and a third scheduling queue, the first scheduling queue contains the transaction whose local scheduling time is in a current time period, the second scheduling queue contains the transaction whose local scheduling time is in a first time period, and the third scheduling queue contains the transaction whose local scheduling time is after the first time period, where the first time period is a next time period of the current time period.

6. The method of claim 5, wherein the method further comprises:

the first processor receives a second interrupt signal triggered by a second timer, wherein the second interrupt signal is used for indicating the end of the current time period;

in response to the second interrupt signal, the first processor schedules transactions in a second scheduling queue and updates transactions in the first scheduling queue and the third scheduling queue such that the first scheduling queue contains transactions having a local scheduling time that is a second time period, and the third scheduling queue contains transactions having a local scheduling time that is a subsequent time period to the second time period.

7. The method of claim 1, wherein prior to the first processor scheduling the first transaction according to its scheduled time relative to its virtual clock, the method further comprises:

the first processor communicates with other processors in the distributed system to synchronize a virtual clock of the first processor with virtual clocks of the other processors.

8. The method of claim 7, wherein the first processor is a slave processor of the plurality of processors, the plurality of processors further comprising a master processor,

the first processor communicating with other processors in the distributed system to synchronize a virtual clock of the first processor with virtual clocks of the other processors, comprising:

the first processor communicates with the main processor to acquire line delay information between the first processor and the main processor;

the first processor determines the time difference between the virtual clock of the first processor and the virtual clock of the main processor according to the line delay information;

and the first processor adjusts the virtual clock of the first processor according to the time difference, so that the virtual clock of the first processor is synchronous with the virtual clock of the main processor.

9. The method of claim 8, wherein the first processor communicating with the host processor to obtain line delay information between the first processor and the host processor comprises:

the first processor receives the synchronization message sent by the main processor and records the virtual time t2 when the first processor receives the synchronization message;

the first processor receives a following message of the synchronous message sent by the main processor, wherein the following message comprises a virtual time t1 of the main processor sending the synchronous message;

the first processor sends a delay request message to the main processor and records the virtual time t3 when the first processor sends the delay request message;

the first processor receives a delay response message sent by the main processor, wherein the delay response message comprises a virtual time t4 when the main processor receives the delay request message.

10. The method of claim 9, wherein the first processor determining a time difference between a virtual clock of the first processor and a virtual clock of the host processor based on the line delay information comprises:

the first processor determines the time difference from the virtual time t1, virtual time t2, virtual time t3, and virtual time t 4.

11. The method of claim 10, wherein the time difference T = (T2-T1-T4+ T3).

12. The method of claim 7, wherein the first processor is a master processor of the plurality of processors, the other processors are slave master processors of the distributed system,

the first processor sends a synchronization message and a following message of the synchronization message to the other processors, wherein the following message contains the virtual time t1 when the first processor sends the synchronization message;

the first processor receives delay request messages sent by other processors;

the first processor sends a delay response message to the other processors, wherein the delay response message comprises a virtual time t4 when the first processor receives the delay request message, so that the other processors determine a time difference between the virtual clock of the first processor and the virtual clock of the other processors based on the virtual time t1 and the virtual time t4, and adjust the virtual clock of the other processors based on the time difference, so that the virtual clock of the other processors is synchronous with the virtual clock of the first processor.

13. The method of claim 1, wherein prior to the first processor scheduling the first transaction according to its scheduled time relative to its virtual clock, the method further comprises:

the first processor initializing a variable characterizing a virtual clock of the first processor;

the first processor determining a virtual time of a virtual clock of the first processor;

and the first processor assigns values to the variables according to the virtual time of the virtual clock of the first processor so as to calibrate the virtual clock of the first processor.

14. The method of claim 13, wherein the method further comprises:

the first processor determining a clock frequency of a virtual clock of the first processor, wherein the clock frequencies of the virtual clocks in the distributed system are the same;

and the first processor updates the count value of the variable according to the clock frequency of the virtual clock of the first processor.

15. A processor, wherein the processor is a first processor in a distributed system, wherein each processor in the distributed system is configured with a virtual clock, and wherein the virtual clocks of each processor in the distributed system are synchronized,

the first processor comprises:

a memory for storing computer instructions;

a controller to execute computer instructions stored in the memory to perform the following operations:

acquiring a first transaction to be scheduled;

determining a scheduled time of the first transaction relative to a virtual clock of the first processor;

and scheduling the first transaction according to the scheduling time of the first transaction relative to the virtual clock of the first processor.

16. The processor of claim 15, wherein said scheduling the first transaction based on a scheduled time of the first transaction relative to a virtual clock of the first processor comprises:

converting a scheduled time of the first transaction relative to a virtual clock of the first processor to a local scheduled time of the first transaction, wherein the local scheduled time of the first transaction is the scheduled time of the first transaction relative to a local clock of the first processor;

and scheduling the first transaction according to the local scheduling time of the first transaction.

17. The processor of claim 16, wherein prior to said scheduling said first transaction according to its local schedule time, said controller is further to:

receiving a first interrupt signal triggered by a first timer, wherein the first interrupt signal is used for indicating that a local clock of the first processor reaches a local scheduling time of a previous transaction of the first transaction;

in response to the first interrupt signal, scheduling a previous transaction of the first transaction, and adjusting the timing duration of the first timer, so that the trigger time of a next interrupt signal of the first timer is the local scheduling time of the first transaction;

the scheduling the first transaction according to the local scheduling time of the first transaction includes:

scheduling the first transaction in response to the next interrupt signal.

18. The processor of claim 16, wherein prior to said scheduling said first transaction according to its local schedule time, said controller is further to:

determining a scheduled end time for the first transaction;

19. The processor of claim 16, wherein said scheduling the first transaction according to the local schedule time of the first transaction comprises:

in the process of scheduling, by the first processor, a transaction in a first scheduling queue, in response to a local time of the first processor reaching a local scheduling time of the first transaction, scheduling the first transaction, where the first scheduling queue is one of a plurality of scheduling queues of the first processor, the plurality of scheduling queues further includes a second scheduling queue and a third scheduling queue, the first scheduling queue contains transactions whose local scheduling times are in a current period, the second scheduling queue contains transactions whose local scheduling times are in a first period, and the third scheduling queue contains transactions whose local scheduling times are after the first period, where the first period is a next period of the current period.

20. The processor of claim 19, wherein the controller is further to:

receiving a second interrupt signal triggered by a second timer, wherein the second interrupt signal is used for indicating the end of the current time period;

in response to the second interrupt signal, scheduling transactions in a second scheduling queue and updating transactions in the first scheduling queue and the third scheduling queue such that the first scheduling queue contains transactions having a local scheduling time that is a second time period, and the third scheduling queue contains transactions having a local scheduling time that is a subsequent time period to the second time period, wherein the second time period is a next time period to the first time period.

21. The processor of claim 15, wherein prior to the scheduling of the first transaction according to the scheduled time of the first transaction relative to the virtual clock of the first processor, the controller is further to:

communicating with other processors in the distributed system to synchronize the virtual clock of the first processor with the virtual clocks of the other processors.

22. The processor of claim 21, wherein the first processor is a slave processor of a plurality of processors, the plurality of processors further comprising a master processor,

the communicating with other processors in the distributed system to synchronize the virtual clock of the first processor with the virtual clocks of the other processors, comprising:

communicating with the main processor to obtain line delay information between the first processor and the main processor;

determining a time difference between a virtual clock of the first processor and a virtual clock of the main processor according to the line delay information;

and adjusting the virtual clock of the first processor according to the time difference so that the virtual clock of the first processor is synchronous with the virtual clock of the main processor.

23. The processor of claim 22, wherein said communicating with said main processor to obtain line delay information between said first processor and said main processor comprises:

receiving a synchronization message sent by the main processor, and recording the virtual time t2 when the first processor receives the synchronization message;

receiving a following message of the synchronization message sent by the main processor, wherein the following message comprises a virtual time t1 of the main processor sending the synchronization message;

sending a delay request message to the main processor, and recording a virtual time t3 when the first processor sends the delay request message;

and receiving a delay response message sent by the main processor, wherein the delay response message comprises the virtual time t4 when the main processor receives the delay request message.

24. The processor of claim 23, wherein said determining a time difference between a virtual clock of the first processor and a virtual clock of the host processor based on the line delay information comprises:

determining the time difference according to the virtual time t1, the virtual time t2, the virtual time t3 and the virtual time t 4.

25. The processor of claim 24, wherein the time difference T = (T2-T1-T4+ T3).

26. The processor of claim 21, wherein the first processor is a master processor of a plurality of processors, the other processors are slave master processors of the distributed system,

sending a synchronization message and a following message of the synchronization message to the other processors, the following message containing a virtual time t1 at which the first processor sends the synchronization message;

receiving delay request messages sent by other processors;

sending a delay response message to the other processors, the delay response message including the virtual time t4 at which the first processor receives the delay request message, so that the other processors determine a time difference between the virtual clock of the first processor and the virtual clock of the other processors based on the virtual time t1 and the virtual time t4, and adjust the virtual clock of the other processors based on the time difference, so that the virtual clock of the other processors is synchronized with the virtual clock of the first processor.

27. The processor of claim 15, wherein prior to the scheduling of the first transaction according to the scheduled time of the first transaction relative to the virtual clock of the first processor, the controller is further to:

initializing a variable characterizing a virtual clock of the first processor;

determining a virtual time of a virtual clock of the first processor;

and assigning values to the variables according to the virtual time of the virtual clock of the first processor so as to calibrate the virtual clock of the first processor.

28. The processor of claim 27, wherein the controller is further to:

determining a clock frequency of a virtual clock of the first processor, wherein the clock frequencies of the virtual clocks in the distributed system are the same;

and updating the count value of the variable according to the clock frequency of the virtual clock of the first processor.

29. A distributed system, characterized in that the distributed system comprises a processor according to any of claims 15-28.

30. A drone comprising a distributed system according to claim 29.