CN108401454A

CN108401454A - Transaction scheduling method, processor, distributed system and unmanned plane

Info

Publication number: CN108401454A
Application number: CN201780004456.7A
Authority: CN
Inventors: 唐上昌; 陈学义
Original assignee: Shenzhen Dajiang Innovations Technology Co Ltd
Current assignee: Shenzhen Dajiang Innovations Technology Co Ltd
Priority date: 2017-06-30
Filing date: 2017-06-30
Publication date: 2018-08-14
Anticipated expiration: 2037-06-30
Also published as: CN108401454B; WO2019000398A1

Abstract

A kind of transaction scheduling method, processor, distributed system and unmanned plane are provided.This method can be applied to the distributed system with multiprocessor, in distributed system everywhere in reason device be each equipped with dummy clock, and in distributed system everywhere in the dummy clock of reason device synchronize, this method includes：Any one first processor in distributed system obtains the first affairs (310) to be scheduled；First processor determines scheduling time (320) of first affairs with respect to the dummy clock of first processor；Scheduling time of the first processor according to the first affairs with respect to the dummy clock of first processor, the first affairs are scheduled (330).Above-mentioned technical proposal can improve the cooperative scheduling process of distributed system.

Description

Transaction scheduling method, processor, distributed system and unmanned plane

Copyright notice

This patent document disclosure includes material protected by copyright.The copyright is all for copyright holder.Copyright Owner does not oppose the patent document in the presence of anyone replicates the proce's-verbal of Patent＆Trademark Office and archives or should Patent discloses.

Technical field

This application involves distributed system fields, more specifically, are related to a kind of transaction scheduling method, processor, distribution Formula system and unmanned plane.

Background technology

Distributed system is generally made of multiple subsystems, can be cooperated between each subsystem, with cooperative scheduling one A or multiple affairs.

In a distributed system, in order to realize cooperative scheduling, generally required between processor first pass through it is dedicated communication connect Oral sex mutually cooperates with message, then executes synchronizing process by the software on each processor, waits each processor synchronous and then by each processing Device carries out cooperative scheduling to affairs, causes the process of cooperative scheduling complicated.Therefore, there is an urgent need for improve the cooperative scheduling of distributed system Process.

Invention content

A kind of transaction scheduling method of the application offer, processor, distributed system and unmanned plane, can improve distributed system The cooperative scheduling process of system.

In a first aspect, providing a kind of transaction scheduling method, the method can be applied to the distributed system with multiprocessor System, in the distributed system everywhere in reason device be each equipped with dummy clock, and in the distributed system everywhere in reason device Dummy clock synchronizes, the method includes：Any one first processor in the distributed system obtains to be scheduled the One affairs；The first processor determines the scheduling time of the dummy clock of the relatively described first processor of first affairs； The first processor is according to scheduling time of the dummy clock of the relatively described first processor of first affairs, to described One affairs are scheduled.

Second aspect provides a kind of processor, includes the module for the method being able to carry out in first aspect.

The third aspect, provides a kind of processor, and the processor is the first processor in distributed system, the distribution Manage device everywhere in formula system and be each equipped with dummy clock, and in the distributed system everywhere in reason device dummy clock it is same Step, the first processor include：Memory, for storing computer instruction；Controller is deposited for executing in the memory The computer instruction of storage, to execute following operation：Obtain the first affairs to be scheduled；Determine first affairs relatively described The scheduling time of the dummy clock of one processor；According to the tune of the dummy clock of the relatively described first processor of first affairs The time is spent, first affairs are scheduled.

Fourth aspect, provides a kind of distributed system, and the distributed system includes the processor as described in the third aspect.

5th aspect, provides a kind of unmanned plane, includes the distributed system as described in fourth aspect.

6th aspect, provides a kind of computer readable storage medium, finger is stored in the computer readable storage medium It enables, when it runs on a processor so that processor executes method as described in relation to the first aspect.

7th aspect provides a kind of computer program product including instruction, when it runs on a processor so that place Manage the method for device execution as described in relation to the first aspect.

The application can improve the cooperative scheduling process of distributed system.

Description of the drawings

Fig. 1 is the general frame exemplary plot of distributed system.

Fig. 2 is the schematic flow chart that dummy clock provided in an embodiment of the present invention synchronizes.

Fig. 3 is the schematic flow chart of transaction scheduling method provided in an embodiment of the present invention.

Fig. 4 is the schematic diagram of processor provided by one embodiment of the present invention.

Fig. 5 is the schematic diagram for the processor that another embodiment of the present invention provides.

Fig. 6 is the schematic diagram of distributed system provided in an embodiment of the present invention.

Fig. 7 is the schematic diagram of unmanned plane provided in an embodiment of the present invention.

Specific implementation mode

Technical solution provided by the present application can be used as one of base layer support technology of distributed system, be applied to carry out Cooperative scheduling synchronizes clock the scene required.For example, when technical solution provided by the present application can be applied to telecomm base station Clock is synchronous or basic network clock synchronizes.For another example, technical solution provided by the present application can be applied to vehicle-carrying distribution control system, In the automated systems such as high speed Distributed Servo control system, unmanned plane, unmanned vehicle, mobile robot.

As shown in Figure 1, distributed system generally includes multiple processors, communication channel phase can be passed through between processor Even.The communication channel can be responsible for interacting clock sync message and/or scheduling assignment message between the various processors.

In order to make it easy to understand, below by taking the control system of unmanned plane as an example, to the cooperative scheduling mistake of traditional distributed system Journey is illustrated.

The control system of four traditional axis unmanned planes only needs to control the motor and remote control equipment of four axis, controls The demand of system processed is simple.Therefore, it only needs that a processor (such as one is arranged inside the control system of four traditional axis unmanned planes A micro-control unit (microcontroller unit, MCU) or a system on chip (system-on-a-chip, SOC)) The control to the unmanned plane can be completed.

With the development of unmanned air vehicle technique, demand of the unmanned plane to control system is higher and higher.For example, current unmanned plane Control system generally comprise a plurality of types of subsystems for realizing different function.For example, the control system of unmanned plane can To pass subsystem, application subsystem etc. comprising winged control subsystem, holder subsystem, camera sub-system, avoidance subsystem, figure.By It becomes increasingly complex in subsystem function, and requirement of the different sub-systems to the process performance of processor may also be different, many sons System is gradually developed by a shared processor before and uses dedicated processor.Therefore, the control system of unmanned plane at present Generally comprise different types of multiple processors.As an example, the control system of unmanned plane can include MCU, SOC, number Word signal processing (digital signal processing, DSP) and dedicated hardware accelerators etc..Unmanned aerial vehicle control system In processor dedicated communication interface can be set, as universal serial bus (universal serial bus, USB) connects Mouth, Serial Peripheral Interface (SPI) (serial peripheral interface, SPI), universal asynchronous receiving-transmitting transmitter (universal Asynchronous receiver/transmitter, UART), mobile industry processor interface (mobile industry Processor interface, MIPI) etc..Further, the processor in unmanned aerial vehicle control system can pass through communication channel Interconnection.It can be seen that the control system of current unmanned plane is gradually evolved into the distributed system comprising multiprocessor.

It is a certain multiple in order to control unmanned plane execution in the control system of unmanned plane with the complication of unmanned air vehicle technique Miscellaneous task, it usually needs manage device everywhere in subsystems and coordinated, to complete the task jointly.For example, when wishing logical When crossing the image of unmanned plane photographic subjects scene, unmanned plane is influenced by high wind, and fuselage is caused to be shaken.In such case Under, the holder subsystem and camera sub-system of unmanned plane can be coordinated so that under the influence of high wind, unmanned plane is remained able to mesh Mark scene carries out stable shooting.

When processor in distributed system needs cooperative scheduling, generally requires and first pass through dedicated communication interface interaction association Same message, then synchronizing process is executed by the software on each processor, wait each processor synchronous and then by each processor to affairs Cooperative scheduling is carried out, causes the process of cooperative scheduling complicated.

Further, when a processor in distributed system sends collaboration message to another processor, if made For the processor of recipient, (for example the processor is currently dispatching the larger affairs of certain calculation amounts) not for some reason The collaboration message is timely responded to, the cooperative scheduling procedure failure of association's affairs is may result in.

Above by taking unmanned plane as an example, to distributed system in cooperative scheduling there are the problem of be illustrated, but Technical solution application scenarios provided in an embodiment of the present invention are not limited to unmanned plane scene, may be applicable to clock synchronization or collaboration In any distributed system of scheduling, it is particularly applicable to the distributed system being connected not over real-time bus between processor System.

In order to improve the cooperative scheduling mode of distributed system, the embodiment of the present invention is that the processor in distributed system is matched Dummy clock is set.The dummy clock that device is managed everywhere in distributed system can be with clock frequency having the same.For difference The distributed system of demand, the clock frequency of dummy clock or the granularity of clock cycle can be different.For example, dummy clock when The clock period can be the clock cycle of musec order, can also be the clock cycle of millisecond magnitude.Dummy clock can be one Variable, the value of the variable can indicate the count value of dummy clock, to indicate dummy clock time (can will be virtual when The time of clock is known as virtual time).The embodiment of the present invention is not specifically limited the format of the variable for characterizing dummy clock, 32 variables can be chosen for, 64 variables can also be chosen for.The length of variable is bigger, works the phase in distributed system Between, which reaches the possibility of maximum value with regard to smaller, so as to effectively avoid variable from reaching maximum value quickly overturning later (i.e. since 0 again count) and the computational problem brought, and then simplify the complexity of software processing.By taking unmanned plane as an example, The cruise duration of unmanned plane can be considered to set the variable-length of dummy clock, as possible so that unmanned plane worked on power Cheng Zhong, the variable of the dummy clock will not occur quickly to overturn.For example, for unmanned plane, it can be by the variable of dummy clock Length is defined as 64.

Device is managed everywhere in distributed system can be responsible for that respective dummy clock is initialized and calibrated.With distribution For any one processor (calling first processor in the following text) in formula system, the dummy clock of its own is used in first processor Before, first the variable of the dummy clock for characterizing first processor can be initialized；Determine the void of first processor The virtual time of quasi- clock；And the virtual time of the dummy clock according to first processor, it is variable assignments, to calibrate at first Manage the dummy clock of device.

When to initialization of variable, the initial value of variable can be set as 0.Then, first processor can be with its elsewhere Reason device is communicated, to obtain the virtual time of dummy clock.The count value that dummy clock may be used in the virtual time indicates. Then, it is the variable assignments of the dummy clock of first processor that first processor, which can use the count value, to complete first The calibration of the dummy clock of processor.

In addition, first processor can also be responsible for the time precision of synchronous dummy clock, dummy clock is updated, and Safeguard the current time and state of dummy clock.For example, first processor can be according to the clock frequency of dummy clock to virtual The value of the variable of clock constantly executes plus 1 operation.

It should be noted that the clock frequency or precision of dummy clock can according to the application scenario of distributed system and Fixed, high to the required precision of cooperative scheduling occasion, can be by the higher of the clock frequency of dummy clock or precision setting, to association It, can be real to simplify by the lower of the clock frequency of dummy clock or precision setting with the low occasion of required precision of scheduling It is existing.

The embodiment of the present invention is not specifically limited the method for synchronization of dummy clock, can be according to the application of distributed system Occasion chooses different clock synchronization modes and algorithm.By taking unmanned plane as an example, the control system of unmanned plane may be used principal and subordinate's Mode is synchronized into row clock, such as can be based on the clock synchronization algorithm that 1588V2 agreements provide to the dummy clock of distributed system It synchronizes.

It describes in detail below to a kind of master-salve clock method of synchronization provided in an embodiment of the present invention.

It is possible, firstly, to some processor in distributed system is defined as primary processor, other in distributed system Processor is defined as from processor.Primary processor can using the dummy clock of itself as the clock synchronisation source of distributed system, And it being communicated with from processor so that the dummy clock of dummy clock and primary processor from processor synchronizes, to So that being consistent from the frequency and phase of the dummy clock of the dummy clock and primary processor of processor.

Assuming that first processor is the slave processor in distributed system, first processor can be communicated with primary processor, To obtain the line delay information between first processor and primary processor；Then, first processor can be according to line delay Information determines the time difference of the dummy clock of first processor and the dummy clock of primary processor；Then, first processor can be with According to the time difference, adjust the dummy clock of first processor so that the dummy clock of first processor and primary processor it is virtual Clock synchronizes.

Specifically, as shown in Fig. 2, first processor receives the synchronization message that primary processor is sent, and the first processing is recorded Device receives the virtual time t2 of synchronization message；The synchronization message that first processor reception primary processor is sent follows message, with Include the virtual time t1 that primary processor sends synchronization message with message；First processor sends delay request to primary processor and disappears Breath, and record the virtual time t3 that first processor sends delay request message；First processor receives what primary processor was sent Postpone response message, delay response message includes the virtual time t4 that primary processor receives delay request message.

Above-mentioned first processor determines the dummy clock of first processor and the void of primary processor according to line delay information The time difference of quasi- clock may include：First processor is according to virtual time t1, virtual time t2, virtual time t3 and virtual time T4 determines the time difference.

For example, first processor can first calculate it is main to from delay delay1=(t2-t1), then calculate and prolong to main Slow delay2=(t4-t3).Assuming that it is main to from delay with from equal to main delay, then first processor can calculate the The time difference T=(delay1-delay2) of the dummy clock of one processor and the dummy clock of primary processor.Certainly, at first Computing relay can also be not necessarily to by managing device, be directly based upon the dummy clock that formula T=(t2-t1-t4+t3) calculates first processor With the time difference of the dummy clock of primary processor.

In other embodiments, above-mentioned first processor can also be the primary processor in distributed system, the first processing What device can send synchronization message and synchronization message to other processors follows message, and it includes first processor hair to follow message Send the virtual time t1 of synchronization message；First processor receives the latency request message of other processors transmission；First processor To other processor forward delay interval response messages, delay response message includes that first processor receives the virtual of delay request message Time t4, so as to other processors based on virtual time t1 and virtual time t4 determine first processor dummy clock and other Time difference between the dummy clock of processor, and adjust based on the time difference dummy clock of other processors so that its elsewhere The dummy clock for managing device is synchronous with the dummy clock of first processor.

The embodiment is using first processor as primary processor, other processors are used as and for processor illustrate Bright.In this embodiment, the first processor of the specific synchronizing process of other processors and previous embodiment description be used as from Synchronizing process when processor is similar, and to avoid repeating, and will not be described here in detail.

The synchronizing process of dummy clock is essentially described above.It should be understood that the synchronizing process of dummy clock described above It is merely illustrative of, in fact, other traditional clock synchronization algorithms can also be used to the processor in distributed system Dummy clock synchronizes, and the embodiment of the present invention is not specifically limited this.By keeping managing device everywhere in distributed system Dummy clock synchronize so that processor in distributed system can (i.e. dummy clock be corresponding virtually with the unified time Time) on the basis of every affairs are scheduled, as long as everywhere in distributed system manage device periodic maintenance dummy clock, keep Synchronism between them, without as traditional distributed system, being assisted by application layer before each cooperative scheduling View sends collaboration message, to simplify software realization.

On the basis of dummy clock synchronizes, with reference to Fig. 3, transaction scheduling provided in an embodiment of the present invention is described in detail Method.

Fig. 3 is the schematic flow chart of transaction scheduling method provided in an embodiment of the present invention.Fig. 3 is mainly in a distributed manner It is illustrated for the transaction scheduling process of first processor in system.First processor can be in distributed system Any one processor.The method of Fig. 3 may include step 310-330, and the step of Fig. 3 is described in detail below.

In the step 310, first processor obtains the first affairs to be scheduled.The first processing in the multiple processor Device obtains goal task to be scheduled.

In step 320, first processor determines scheduling time of first affairs with respect to the dummy clock of first processor.

First affairs can be any one affairs, the triggering mode of the first affairs and the first affairs with respect to the first processing The method of determination of the scheduling time of the dummy clock of device can there are many, for example, first can independently be triggered by first processor Affairs, and distribute scheduling time of first affairs with respect to the dummy clock of first processor；For another example, it can be touched by other processors The first affairs are sent out, and distribute scheduling time of first affairs with respect to the dummy clock of first processor, then, other processors are logical It crosses message (such as task assignment message) and the scheduling time of the first affairs and its relative virtual clock is sent to first processor.

In a step 330, scheduling time of the first processor according to the first affairs with respect to the dummy clock of first processor, First affairs are scheduled.

From the description of the corresponding embodiments of Fig. 3 as can be seen that managing the transaction scheduling process of device everywhere in distributed system Independently of each other, only the scheduling time of affairs using unified dummy clock as benchmark.In other words, each processor is with identical Dummy clock respective affairs are scheduled as benchmark, processor possibly even be not necessarily to know its with other processing Device carries out cooperative scheduling, and the collaboration between them naturally is completed because of common time reference.

The realization method of step 330 is described in detail below.

In some embodiments, step 330 may include：First processor is virtual with respect to first processor by the first affairs The scheduling time of clock is converted to the local scheduling time of the first affairs, wherein the local scheduling time of the first affairs is the first thing The scheduling time of the local clock of the opposite first processor of business；First processor is according to local scheduling time pair of the first affairs One affairs are scheduled.

First processor can be based on the dummy clock of first processor clock frequency and first processor local when The relationship of the clock frequency of clock, when the scheduling time of the dummy clock of first processor is converted to the local scheduling of the first affairs Between.Assuming that the clock frequency of the dummy clock of first processor is 2 times of the clock frequency of local clock, the void of first processor The current time of quasi- clock is 300 (time here is indicated with the count value of dummy clock), and the first affairs are with respect to first The scheduling time of the dummy clock of processor is 305, the current time of the local clock of first processor be 500 (here when Between be to be indicated with the count value of local clock), then according to the relationship of the clock frequency of two clocks, the first thing can be calculated The local scheduling time of business is 510.

The mode that local scheduling time pair first affairs of the first processor based on the first affairs are scheduled can have more Kind.

As an example, traditional the first affairs of transaction scheduling mode pair may be used to be scheduled.It specifically, can be with First the first affairs are added in the scheduling queue of first processor, then the timer that a cycle triggers is set, this is fixed When device often trigger an interrupt signal, first processor check in scheduling queue whether the affairs of scheduling in need.Such thing Although scheduling mode of being engaged in is simple, there are problems that power dissipation.For example, when timer sends some interrupt signal, if At this time and there is no the affairs for needing to dispatch, the transmission power of the interrupt signal of the timer is then wasted.

Optionally, in some embodiments, in first processor according to the first thing of local scheduling time pair of the first affairs Before business is scheduled, the method for Fig. 3 may also include：First processor receives the first interrupt signal of first timer triggering, First interrupt signal is used to indicate the local scheduling time of the former transaction of local clock the first affairs of arrival of first processor； In response to the first interrupt signal, first processor dispatches the former transaction of the first affairs, and when adjusting the timing of first timer It is long so that the triggered time of next interrupt signal of first timer is the local scheduling time of the first affairs；At above-mentioned first Reason device is scheduled according to the first affairs of local scheduling time pair of the first affairs may include：In response to next interrupt signal, One the first affairs of processor scheduling.

First timer is introduced in the embodiment of the present invention, which is not periodic triggers interrupt signal, instruction First processor is scheduled affairs, as soon as but often dispatch an affairs, reset the timing length of the first timer, So that the timing length of the first timer is equal to current time to the time interval of the local scheduling time of next affairs, in this way System power can be saved, the precision of transaction scheduling can also be improved.

Optionally, in some embodiments, in first processor according to the first thing of local scheduling time pair of the first affairs Before business is scheduled, the method for Fig. 3 may also include：When the first processor determines the finishing scheduling of first affairs Between；When between the finishing scheduling time of first affairs and the local scheduling time of next affairs of first affairs when Between interval when being less than preset time interval, the first processor is by next thing of first affairs and first affairs An affairs are merged into business.

Specifically, above-mentioned prefixed time interval can be the clock cycle granularity of the scheduling affairs of first processor.For example, First processor scheduled an affairs (calling affairs 1 in the following text) in 340ms, and affairs 1 perform 2.95ms, that is to say, that affairs 1 The finishing scheduling time be 342.95ms.If the local scheduling time of next scheduled affairs (calling affairs 2 in the following text) is 343ms, at this time also poor 50 μ s of the local scheduling time from affairs 2, if the minimum clock grain of the scheduling affairs of first processor Degree is 100 μ s, then encourages first processor to dispatch affairs 2 again without waiting for 50 μ s, and first processor can directly start to dispatch Affairs 2 are equivalent to and affairs 1 and affairs 2 are merged into an affairs are scheduled.The embodiment of the present invention optimizes the thing of processor Business scheduling mode.

Optionally, in some embodiments, first processor is according to the first affairs of local scheduling time pair of the first affairs It is scheduled and may include：During first processor dispatches the affairs in the first scheduling queue, in response to first processor Local zone time reach local scheduling time of the first affairs, the first affairs of first processor pair are scheduled, wherein first adjusts One in multiple scheduling queues that queue is first processor is spent, multiple scheduling queues further include the second scheduling queue and third Scheduling queue, the first scheduling queue include the affairs for the local scheduling time being located at present period, and the second scheduling queue includes local Scheduling time is located at the affairs of the first period, and third scheduling queue is located at the thing after the first period comprising the local scheduling time Business, wherein the first period was the subsequent period of present period.

Optionally, in some embodiments, the method for Fig. 3 may also include：First processor receives second timer triggering The second interrupt signal, the second interrupt signal is used to indicate present period and terminates；In response to the second interrupt signal, first processor The affairs in the second scheduling queue are dispatched, and the affairs in the first scheduling queue and third scheduling queue are updated so that First scheduling queue includes the affairs for the local scheduling time being located at for the second period, meta position when third scheduling queue includes local scheduling Affairs after the second period, wherein the second period was the subsequent period of the first period.

The embodiment of the present invention is not specifically limited the form of scheduling queue, such as the form record of dispatch list may be used Affairs to be scheduled.It is illustrated by taking dispatch list as an example below.

Above-mentioned first scheduling queue is properly termed as the table tennis dispatch list of first processor, and the second scheduling queue is properly termed as first Pang the dispatch list of processor, third scheduling queue are properly termed as remaining transaction scheduling table.Table tennis dispatch list can include local scheduling Time is located at the affairs of present period.Pang dispatch list can include the affairs for the local scheduling time being located at subsequent period.Its remaining matter Business dispatch list can include the remaining affairs to be dispatched of first processor.

By taking Period Length is 10ms as an example, then table tennis dispatch list can include the affairs for the local scheduling time being located at 0-10ms, Pang degree table can include the affairs for the local scheduling time being located at 10-20ms.When remaining transaction scheduling table can include local scheduling Between be located at 20ms after affairs.Affairs of the first processor in 0-10ms first dispatches table tennis dispatch list；After 10ms terminates, the One processor is directed toward pang dispatch list, and the affairs to be located at 10-20ms to the local scheduling time are scheduled.In addition, the first processing Device also needs to be updated table tennis dispatch list and remaining transaction scheduling table, will be located at 20-30ms's in remaining transaction scheduling table Affairs are added in table tennis dispatch list.After 20ms terminates, first processor is directed toward table tennis dispatch list again, with to the local scheduling time Affairs positioned at 20-30ms are scheduled, and so on.

It can be seen from the above description that first processor is alternately by table tennis dispatch list (or first scheduling queue) and pang scheduling Table (or second scheduling queue) is used as current scheduling table (or current scheduling queue), so, soft inside first processor Part scheduler currently needs the affairs dispatched without being searched in all affairs to be scheduled, it is only necessary to current scheduling table (or Current scheduling queue) in search, effectively reduce first processor scheduling process implementation complexity.

It should be noted that when first processor gets some new affairs to be scheduled, it can be according to the new affairs The local scheduling time adds it to corresponding dispatch list (or scheduling queue).Using current scheduling table as table tennis dispatch list, (first adjusts Spend queue) for, if the local scheduling time of the new affairs is located at present period, new affairs can be added to table tennis and dispatched New affairs can be added to pang tune by table if the local scheduling time of the new affairs is located at the subsequent period of present period Otherwise new affairs can be added to remaining transaction scheduling table (third scheduling queue) by degree table (the second scheduling queue).

In addition, the embodiment of the present invention introduces second timer, which can be with the length of present period Timing length (such as 10ms), to first processor periodicity sending interrupt signal, triggering first processor to current scheduling table (or Current scheduling queue) it is updated.

The device of the invention embodiment is described below, since device embodiment can execute the above method, The part not being described in detail may refer to front each method embodiment.

Fig. 4 is the schematic diagram of processor provided by one embodiment of the present invention.The processor of Fig. 4 can be above The first processor of description, the first processor 400 may include acquisition module 410, the first determining module 420 and scheduler module 430, the function of the module in first processor 400 is described in detail below.

Acquisition module 410 can obtain the first affairs to be scheduled.

First determining module 420 can determine the tune of first affairs dummy clock of the first processor 400 relatively Spend the time.

Scheduler module 430 can according to first affairs relatively the scheduling of the dummy clock of the first processor 400 when Between, first affairs are scheduled.

Optionally, in some embodiments, scheduler module 430 can be specifically used for first affairs relatively described first The scheduling time of the dummy clock of processor 400 is converted to the local scheduling time of first affairs, wherein first thing The local scheduling time of business is the scheduling time of first affairs local clock of the first processor 400 relatively；According to The local scheduling time of first affairs is scheduled first affairs.

Optionally, in some embodiments, first processor 400 can be additionally used in receive first timer triggering first Break signal, the local clock that first interrupt signal is used to indicate the first processor 400 reach first affairs The local scheduling time of former transaction；In response to first interrupt signal, the former transaction of first affairs is dispatched, and is adjusted The timing length of the whole first timer so that the triggered time of next interrupt signal of the first timer is described the The local scheduling time of one affairs；Scheduler module 430 is specifically used in response to next interrupt signal, the first processor 400 scheduling first affairs.

Optionally, in some embodiments, when the first processor 400 determines the finishing scheduling of first affairs Between；When between the finishing scheduling time of first affairs and the local scheduling time of next affairs of first affairs when Between interval be less than preset time interval when, the first processor 400 will be under first affairs and first affairs One affairs merge into an affairs.

Optionally, in some embodiments, the scheduler module 430 is specifically used for dispatching in the first processor 400 During affairs in first scheduling queue, first thing is reached in response to the local zone time of the first processor 400 The local scheduling time of business is scheduled first affairs, wherein first scheduling queue is the first processor One in 400 multiple scheduling queues, the multiple scheduling queue further includes the second scheduling queue and third scheduling queue, institute It includes the affairs that the local scheduling time is located at present period to state the first scheduling queue, and second scheduling queue includes local scheduling Time is located at the affairs of the first period, and the third scheduling queue is located at comprising the local scheduling time after first period Affairs, wherein first period is the subsequent period of the present period.

Optionally, in some embodiments, first processor 400 may also include receiving module, for receiving the second timing Second interrupt signal of device triggering, second interrupt signal are used to indicate the present period and terminate.The scheduler module 430 Be additionally operable in response to second interrupt signal, dispatch the affairs in the second scheduling queue, and to first scheduling queue and Affairs in the third scheduling queue are updated so that first scheduling queue includes the local scheduling time to be located at second The affairs of period, the third scheduling queue are located at the affairs after second period, wherein institute comprising the local scheduling time State the subsequent period that the second period was first period.

Optionally, in some embodiments, the first processor 400 may also include Communications Processor Module, be used for and institute Other processor communications in distributed system are stated, by the dummy clock of the first processor 400 and other described processing The dummy clock of device synchronizes.

Optionally, in some embodiments, the first processor 400 is the slave processor in the multiple processor, The multiple processor further includes primary processor, and the Communications Processor Module is specifically used for communicating with the primary processor, to obtain Take the line delay information between the first processor 400 and the primary processor；According to the line delay information, determine The time difference of the dummy clock of the dummy clock of the first processor 400 and the primary processor；According to the time difference, adjust The dummy clock of the whole first processor 400 so that the dummy clock of the first processor 400 and the primary processor Dummy clock synchronizes.

Optionally, in some embodiments, the Communications Processor Module is specifically used for receiving what the primary processor was sent Synchronization message, and record the virtual time t2 that the first processor 400 receives the synchronization message；Receive the primary processor The synchronization message sent follows message, the void for following message to send the synchronization message comprising the primary processor Pseudotime t1；Delay request message is sent to the primary processor, and records the first processor 400 and sends the delay and ask Seek the virtual time t3 of message；The delay response message that the primary processor is sent is received, the delay response message includes institute State the virtual time t4 that primary processor receives the delay request message.

Optionally, in some embodiments, the Communications Processor Module is specifically used for according to the virtual time t1, virtually Time t2, virtual time t3 and virtual time t4, determine the time difference.

Optionally, in some embodiments, the time difference T=(t2-t1-t4+t3).

Optionally, in some embodiments, the first processor 400 is the primary processor in the multiple processor, Other described processors be the distributed system slave primary processor, the Communications Processor Module be specifically used for it is described other Processor sends the message that follows of synchronization message and the synchronization message, and described to follow message include the first processor 400 send the virtual time t1 of the synchronization message；Receive the latency request message that other described processors are sent；To it is described its His processor forward delay interval response message, the delay response message receives the delay comprising the first processor 400 asks The virtual time t4 for seeking message, so that other described processors determine institute based on the virtual time t1 and the virtual time t4 When stating the time difference between the dummy clock of first processor 400 and the dummy clock of other processors, and being based on described Between difference adjustment other processors dummy clock so that the dummy clock of other processors and the first processor 400 dummy clock synchronizes.

Optionally, in some embodiments, the first processor 400 may also include initialization module, and third determines mould Block and assignment module.The initialization module be used for the variable of the dummy clock for characterizing the first processor 400 into Row initialization.The third determining module is used to determine the virtual time of the dummy clock of the first processor 400.The tax It is worth the virtual time for the dummy clock that module is used for according to the first processor 400, is the variable assignments, described in calibration The dummy clock of first processor 400.

Optionally, in some embodiments, the first processor 400 may also include the 4th determining module and update mould Block.4th determining module is used to determine the clock frequency of the dummy clock of the first processor 400, wherein the distribution The clock frequency of each dummy clock in formula system is identical.The update module is used for the void according to the first processor 400 The clock frequency of quasi- clock, updates the count value of the variable.

Fig. 5 is the schematic diagram for the processor that another embodiment of the present invention provides.The processor of Fig. 5 can be distribution Any one first processor in formula system.Device is managed everywhere in distributed system and is each equipped with dummy clock, and distributed The dummy clock that device is managed everywhere in system synchronizes.The first processor 500 includes memory 510 and controller 520.

Memory 510 can be used for storing computer instruction.

Controller 520 can be used for executing the computer instruction stored in memory, to execute following operation：It obtains and waits dispatching The first affairs；Determine scheduling time of first affairs with respect to the dummy clock of first processor 500；It is opposite according to the first affairs The scheduling time of the dummy clock of first processor 500 is scheduled the first affairs.

Optionally, in some embodiments, the tune according to the first affairs with respect to the dummy clock of first processor 500 The time is spent, the first affairs are scheduled and may include：By the first affairs with respect to the dummy clock of first processor 500 scheduling when Between be converted to local scheduling time of the first affairs, wherein the local scheduling time of the first affairs be the first affairs with respect to first at Manage the scheduling time of the local clock of device 500；It is scheduled according to the first affairs of local scheduling time pair of the first affairs.

Optionally, in some embodiments, it is scheduled according to the first affairs of local scheduling time pair of the first affairs Before, controller 520 is additionally operable to execute following operation：The first interrupt signal of first timer triggering is received, first interrupts letter Number be used to indicate first processor 500 local clock reach the first affairs former transaction the local scheduling time；In response to First interrupt signal, dispatches the former transaction of the first affairs, and adjusts the timing length of first timer so that first timer Next interrupt signal triggered time be the first affairs the local scheduling time；When the local scheduling according to the first affairs Between the first affairs are scheduled may include：In response to next interrupt signal, the first affairs are dispatched.

Optionally, in some embodiments, it is carried out according to the first affairs of local scheduling time pair of the first affairs described Before scheduling, controller 520 is additionally operable to execute following operation：Determine the finishing scheduling time of first affairs；When described Time interval between the local scheduling time of next affairs of the finishing scheduling time of one affairs and first affairs is less than When preset time interval, next affairs of first affairs and first affairs are merged into an affairs.

Optionally, in some embodiments, described to be adjusted according to the first affairs of local scheduling time pair of the first affairs Degree may include：During first processor 500 dispatches the affairs in the first scheduling queue, in response to first processor 500 Local zone time reach local scheduling time of the first affairs, the first affairs are scheduled, wherein the first scheduling queue is the One in multiple scheduling queues of one processor 500, multiple scheduling queues further include the second scheduling queue and third scheduling team Row, the first scheduling queue includes the affairs for the local scheduling time being located at present period, when the second scheduling queue includes local scheduling Between be located at the affairs of the first period, third scheduling queue is located at the affairs after the first period comprising the local scheduling time, wherein First period was the subsequent period of present period.

Optionally, in some embodiments, controller 520 can also be used to execute following operation：Second timer is received to touch Second interrupt signal of hair, the second interrupt signal are used to indicate present period and terminate；In response to the second interrupt signal, scheduling second Affairs in scheduling queue, and the affairs in the first scheduling queue and third scheduling queue are updated so that the first scheduling Queue includes the affairs for the local scheduling time being located at for the second period, and third scheduling queue includes when the local scheduling time being located at second Affairs after section, wherein the second period was the subsequent period of the first period.

Optionally, in some embodiments, in the dummy clock according to the first affairs with respect to first processor 500 Scheduling time, before being scheduled to the first affairs, controller 520 can also be used to execute following operation：With in distributed system Other processor communications, the dummy clock of first processor 500 is synchronous with the dummy clock of other processors.

Optionally, in some embodiments, first processor 500 is the slave processor in multiple processors, multiple processing Device further includes primary processor, it is described with distributed system in other processor communications, by first processor 500 it is virtual when Clock and the dummy clock of other processors synchronize may include：It is communicated with primary processor, to obtain first processor 500 and main process task Line delay information between device；According to line delay information, the dummy clock and primary processor of first processor 500 are determined The time difference of dummy clock；According to the time difference, the dummy clock of first processor 500 is adjusted so that the void of first processor 500 Quasi- clock is synchronous with the dummy clock of primary processor.

Optionally, in some embodiments, described to be communicated with primary processor, to obtain first processor 500 and main process task Line delay information between device may include：The synchronization message that primary processor is sent is received, and records the reception of first processor 500 The virtual time t2 of synchronization message；Receive the synchronization message that primary processor is sent follows message, and it includes main process task to follow message Device sends the virtual time t1 of synchronization message；Delay request message is sent to primary processor, and records the transmission of first processor 500 Postpone the virtual time t3 of request message；The delay response message that primary processor is sent is received, delay response message includes main place Manage the virtual time t4 that device receives delay request message.

Optionally, in some embodiments, described according to line delay information, determine first processor 500 it is virtual when The time difference of the dummy clock of clock and primary processor may include：According to virtual time t1, virtual time t2, virtual time t3 and void Pseudotime t4, determines the time difference.

Optionally, in some embodiments, time difference T=(t2-t1-t4+t3).

Optionally, in some embodiments, first processor 500 is the primary processor in multiple processors, other processing Device is the slave primary processor of distributed system, described other processor communications with distributed system, by first processor 500 dummy clock and the dummy clock of other processors synchronize may include：To other processors transmission synchronization message and together Step message follows message, and it includes the virtual time t1 that first processor 500 sends synchronization message to follow message；Receive its elsewhere Manage the latency request message that device is sent；To other processor forward delay interval response messages, delay response message includes the first processing Device 500 receives the virtual time t4 of delay request message, so that other processors are true based on virtual time t1 and virtual time t4 Determine the time difference between the dummy clock of first processor 500 and the dummy clock of other processors, and is adjusted based on the time difference The dummy clock of other processors so that the dummy clock of other processors is synchronous with the dummy clock of first processor 500.

Optionally, in some embodiments, in the scheduling according to the first affairs with respect to the dummy clock of first processor 500 Time, before being scheduled to the first affairs, controller 520 can also be used to execute following operation：To being used to characterize the first processing The variable of the dummy clock of device 500 is initialized；Determine the virtual time of the dummy clock of first processor 500；According to The virtual time of the dummy clock of one processor 500 is variable assignments, to calibrate the dummy clock of first processor 500.

Optionally, in some embodiments, controller 520 is additionally operable to execute following operation：Determine first processor 500 The clock frequency of the clock frequency of dummy clock, each dummy clock wherein in distributed system is identical；According to first processor The clock frequency of 500 dummy clock, the count value of more new variables.

The embodiment of the present invention also provides a kind of distributed system.As shown in fig. 6, the distributed system 600 includes retouching above The first processor 500 stated.For example, each processor in distributed system 600 can execute at as mentioned in the above first Manage the function performed by device 500.

The embodiment of the present invention also provides a kind of unmanned plane.As shown in fig. 7, the unmanned plane 700 may include as shown in FIG. 6 Distributed system 600.

In the above-described embodiments, can come wholly or partly by software, hardware, firmware or any other combination real It is existing.When implemented in software, it can entirely or partly realize in the form of a computer program product.The computer program Product includes one or more computer instructions.When loading on computers and executing the computer program instructions, all or It partly generates according to the flow or function described in the embodiment of the present invention.The computer can be all-purpose computer, special meter Calculation machine, computer network or other programmable devices.The computer instruction can be stored in computer readable storage medium In, or from a computer readable storage medium to the transmission of another computer readable storage medium, for example, the computer Instruction can pass through wired (such as coaxial cable, optical fiber, number from a web-site, computer, server or data center User's line (digital subscriber line, DSL)) or wireless (such as infrared, wireless, microwave etc.) mode to another Web-site, computer, server or data center are transmitted.The computer readable storage medium can be computer capacity Any usable medium enough accessed is either deposited comprising data such as one or more usable mediums integrated server, data centers Store up equipment.The usable medium can be magnetic medium (for example, floppy disk, hard disk, tape), optical medium (such as digital video light Disk (digital video disc, DVD)) or semiconductor medium (such as solid state disk (solid state disk, SSD)) etc..

Those of ordinary skill in the art may realize that lists described in conjunction with the examples disclosed in the embodiments of the present disclosure Member and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually It is implemented in hardware or software, depends on the specific application and design constraint of technical solution.Professional technician Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed Scope of the present application.

In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit It divides, only a kind of division of logic function, formula that in actual implementation, there may be another division manner, such as multiple units or component It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or The mutual coupling, direct-coupling or communication connection discussed can be the indirect coupling by some interfaces, device or unit It closes or communicates to connect, can be electrical, machinery or other forms.

The unit illustrated as separating component may or may not be physically separated, aobvious as unit The component shown may or may not be physical unit, you can be located at a place, or may be distributed over multiple In network element.Some or all of unit therein can be selected according to the actual needs to realize the mesh of this embodiment scheme 's.

In addition, each functional unit in each embodiment of the application can be integrated in a processing unit, it can also It is that each unit physically exists alone, it can also be during two or more units be integrated in one unit.

The above, the only specific implementation mode of the application, but the protection domain of the application is not limited thereto, it is any Those familiar with the art can easily think of the change or the replacement in the technical scope that the application discloses, and should all contain It covers within the protection domain of the application.Therefore, the protection domain of the application should be based on the protection scope of the described claims.

Claims

1. a kind of transaction scheduling method, which is characterized in that the method can be applied to the distributed system with multiprocessor, institute State and manage device everywhere in distributed system and be each equipped with dummy clock, and in the distributed system everywhere in reason device it is virtual when Clock synchronizes,

The method includes：

Any one first processor in the distributed system obtains the first affairs to be scheduled；

The first processor determines the scheduling time of the dummy clock of the relatively described first processor of first affairs；

The first processor is according to scheduling time of the dummy clock of the relatively described first processor of first affairs, to institute The first affairs are stated to be scheduled.

2. the method as described in claim 1, which is characterized in that the first processor is relatively described according to first affairs The scheduling time of the dummy clock of first processor is scheduled first affairs, including：

The first processor is converted to the scheduling time of the dummy clock of the relatively described first processor of first affairs The local scheduling time of first affairs, wherein the local scheduling time of first affairs is the opposite institute of first affairs State the scheduling time of the local clock of first processor；

The first processor is scheduled first affairs according to the local scheduling time of first affairs.

3. method as claimed in claim 2, which is characterized in that in the first processor according to the local of first affairs Before scheduling time is scheduled first affairs, the method further includes：

The first processor receives the first interrupt signal of first timer triggering, and first interrupt signal is used to indicate institute State first processor local clock reach first affairs former transaction the local scheduling time；

In response to first interrupt signal, the first processor dispatches the former transaction of first affairs, and adjusts institute State the timing length of first timer so that the triggered time of next interrupt signal of the first timer is first thing The local scheduling time of business；

The first processor is scheduled first affairs according to the local scheduling time of first affairs, including：

In response to next interrupt signal, the first processor dispatches first affairs.

4. method as claimed in claim 2, which is characterized in that in the first processor according to the local of first affairs Before scheduling time is scheduled first affairs, the method further includes：

The first processor determines the finishing scheduling time of first affairs；

When between the local scheduling time of next affairs of the finishing scheduling time and first affairs of first affairs When time interval is less than preset time interval, the first processor is next by first affairs and first affairs Affairs merge into an affairs.

5. method as claimed in claim 2, which is characterized in that the first processor is adjusted according to the local of first affairs Spending the time is scheduled first affairs, including：

During the first processor dispatches the affairs in the first scheduling queue, in response to the sheet of the first processor The ground time reaches the local scheduling time of first affairs, and the first processor is scheduled first affairs, Described in the first scheduling queue be the first processor multiple scheduling queues in one, the multiple scheduling queue also wraps The second scheduling queue and third scheduling queue are included, first scheduling queue includes the thing for the local scheduling time being located at present period Business, second scheduling queue include the affairs for the local scheduling time being located at for the first period, and the third scheduling queue includes this Ground scheduling time is located at the affairs after first period, wherein first period is lower a period of time of the present period Section.

6. method as claimed in claim 5, which is characterized in that the method further includes：

The first processor receives the second interrupt signal of second timer triggering, and second interrupt signal is used to indicate institute Present period is stated to terminate；

In response to second interrupt signal, the first processor dispatches the affairs in the second scheduling queue, and to described the Affairs in one scheduling queue and the third scheduling queue are updated so that first scheduling queue includes local scheduling Time is located at the affairs of the second period, and the third scheduling queue is located at comprising the local scheduling time after second period Affairs, wherein second period is the subsequent period of first period.

7. the method as described in claim 1, which is characterized in that in the first processor according to first affairs with respect to institute The scheduling time for stating the dummy clock of first processor, before being scheduled to first affairs, the method further includes：

The first processor and other processor communications in the distributed system, by the virtual of the first processor Clock is synchronous with the dummy clock of other processors.

8. the method for claim 7, which is characterized in that the first processor be the multiple processor in from Device is managed, the multiple processor further includes primary processor,

The first processor and other processor communications in the distributed system, by the virtual of the first processor Clock is synchronous with the dummy clock of other processors, including：

The first processor is communicated with the primary processor, to obtain between the first processor and the primary processor Line delay information；

The first processor determines the dummy clock of the first processor and the main place according to the line delay information Manage the time difference of the dummy clock of device；

The first processor adjusts the dummy clock of the first processor according to the time difference so that at described first The dummy clock for managing device is synchronous with the dummy clock of the primary processor.

9. method as claimed in claim 8, which is characterized in that the first processor is communicated with the primary processor, to obtain The line delay information between the first processor and the primary processor is taken, including：

The first processor receives the synchronization message that the primary processor is sent, and records described in the first processor reception The virtual time t2 of synchronization message；

The first processor receives the message that follows for the synchronization message that the primary processor is sent, described to follow message package The virtual time t1 of the synchronization message is sent containing the primary processor；

The first processor sends delay request message to the primary processor, and records described in the first processor transmission Postpone the virtual time t3 of request message；

The first processor receives the delay response message that the primary processor is sent, and the delay response message includes described Primary processor receives the virtual time t4 of the delay request message.

10. method as claimed in claim 9, which is characterized in that the first processor is according to the line delay information, really The time difference of the dummy clock of the fixed first processor and the dummy clock of the primary processor, including：

The first processor determines institute according to the virtual time t1, virtual time t2, virtual time t3 and virtual time t4 State the time difference.

11. method as claimed in claim 10, which is characterized in that the time difference T=(t2-t1-t4+t3).

12. the method for claim 7, which is characterized in that the first processor is the master in the multiple processor Processor, other described processors are the slave primary processor of the distributed system,

The first processor sends the message that follows of synchronization message and the synchronization message to other described processors, described It includes the virtual time t1 that the first processor sends the synchronization message to follow message；

The first processor receives the latency request message that other described processors are sent；

For the first processor to other described processor forward delay interval response messages, the delay response message includes described the One processor receives the virtual time t4 of the delay request message, so that other described processors are based on the virtual time t1 And the virtual time t4 is determined between the dummy clock of the first processor and the dummy clock of other processors Time difference, and adjust based on the time difference dummy clock of other processors so that other processors it is virtual Clock is synchronous with the dummy clock of the first processor.

13. the method as described in claim 1, which is characterized in that opposite according to first affairs in the first processor The scheduling time of the dummy clock of the first processor, before being scheduled to first affairs, the method further includes：

The first processor initializes the variable of the dummy clock for characterizing the first processor；

The first processor determines the virtual time of the dummy clock of the first processor；

The first processor is the variable assignments, with school according to the virtual time of the dummy clock of the first processor The dummy clock of the accurate first processor.

14. method as claimed in claim 13, which is characterized in that the method further includes：

The first processor determines the clock frequency of the dummy clock of the first processor, wherein in the distributed system Each dummy clock clock frequency it is identical；

The first processor updates the counting of the variable according to the clock frequency of the dummy clock of the first processor Value.

15. a kind of processor, which is characterized in that the processor is the first processor in distributed system, the distribution Manage device everywhere in system and be each equipped with dummy clock, and in the distributed system everywhere in the dummy clock of reason device synchronize,

The first processor includes：

Memory, for storing computer instruction；

Controller, for executing the computer instruction stored in the memory, to execute following operation：

Obtain the first affairs to be scheduled；

Determine the scheduling time of the dummy clock of the relatively described first processor of first affairs；

According to the scheduling time of the dummy clock of the relatively described first processor of first affairs, first affairs are carried out Scheduling.

16. processor as claimed in claim 15, which is characterized in that it is described according to first affairs relatively described first at The scheduling time for managing the dummy clock of device, first affairs are scheduled, including：

The scheduling time of the dummy clock of the relatively described first processor of first affairs is converted into first affairs The local scheduling time, wherein the local scheduling time of first affairs is the relatively described first processor of first affairs The scheduling time of local clock；

First affairs are scheduled according to the local scheduling time of first affairs.

17. processor as claimed in claim 16, which is characterized in that in the local scheduling according to first affairs Between first affairs are scheduled before, the controller is additionally operable to execute following operation：

The first interrupt signal of first timer triggering is received, first interrupt signal is used to indicate the first processor Local clock reaches the local scheduling time of the former transaction of first affairs；

In response to first interrupt signal, the former transaction of first affairs is dispatched, and adjusts the first timer Timing length so that when the triggered time of next interrupt signal of the first timer is the local scheduling of first affairs Between；

The local scheduling time according to first affairs is scheduled first affairs, including：

In response to next interrupt signal, first affairs are dispatched.

18. processor as claimed in claim 16, which is characterized in that in the local scheduling according to first affairs Between first affairs are scheduled before, the controller is additionally operable to execute following operation：

Determine the finishing scheduling time of first affairs；

19. processor as claimed in claim 16, which is characterized in that the local scheduling time according to first affairs First affairs are scheduled, including：

During the first processor dispatches the affairs in the first scheduling queue, in response to the sheet of the first processor The ground time reaches the local scheduling time of first affairs, is scheduled to first affairs, wherein first scheduling Queue is one in multiple scheduling queues of the first processor, and the multiple scheduling queue further includes the second scheduling queue With third scheduling queue, first scheduling queue includes the affairs for the local scheduling time being located at present period, and described second adjusts Degree queue includes the affairs for the local scheduling time being located at for the first period, and the third scheduling queue is located at comprising the local scheduling time Affairs after first period, wherein first period is the subsequent period of the present period.

20. processor as claimed in claim 19, which is characterized in that the controller is additionally operable to execute following operation：

The second interrupt signal of second timer triggering is received, second interrupt signal is used to indicate the present period knot Beam；

In response to second interrupt signal, the affairs in the second scheduling queue are dispatched, and to first scheduling queue and institute The affairs stated in third scheduling queue are updated so that first scheduling queue includes when the local scheduling time being located at second The affairs of section, the third scheduling queue are located at the affairs after second period comprising the local scheduling time, wherein described Second period was the subsequent period of first period.

21. processor as claimed in claim 15, which is characterized in that described according to first affairs relatively described first The scheduling time of the dummy clock of processor, before being scheduled to first affairs, the controller be additionally operable to execute with Lower operation：

With other processor communications in the distributed system, by the dummy clock of the first processor with it is described other The dummy clock of processor synchronizes.

22. processor as claimed in claim 21, which is characterized in that the first processor is in the multiple processor From processor, the multiple processor further includes primary processor,

It is described with the distributed system in other processor communications, by the dummy clock of the first processor with it is described The dummy clock of other processors synchronizes, including：

It is communicated with the primary processor, to obtain the line delay information between the first processor and the primary processor；

According to the line delay information, the dummy clock of the dummy clock and the primary processor of the first processor is determined Time difference；

According to the time difference, the dummy clock of the first processor is adjusted so that the dummy clock of the first processor It is synchronous with the dummy clock of the primary processor.

23. processor as claimed in claim 22, which is characterized in that it is described to be communicated with the primary processor, described in acquisition Line delay information between first processor and the primary processor, including：

The synchronization message that the primary processor is sent is received, and records the first processor and receives the virtual of the synchronization message Time t2；

The message that follows for the synchronization message that the primary processor is sent is received, it is described that message is followed to include the primary processor Send the virtual time t1 of the synchronization message；

Delay request message is sent to the primary processor, and records the first processor and sends the delay request message Virtual time t3；

The delay response message that the primary processor is sent is received, the delay response message includes that the primary processor receives institute State the virtual time t4 of delay request message.

24. processor as claimed in claim 23, which is characterized in that it is described according to the line delay information, determine described in The time difference of the dummy clock of the dummy clock of first processor and the primary processor, including：

According to the virtual time t1, virtual time t2, virtual time t3 and virtual time t4, the time difference is determined.

25. processor as claimed in claim 24, which is characterized in that the time difference T=(t2-t1-t4+t3).

26. processor as claimed in claim 21, which is characterized in that the first processor is in the multiple processor Primary processor, other described processors are the slave primary processor of the distributed system,

Send the message that follows of synchronization message and the synchronization message to other described processors, described to follow message include institute State the virtual time t1 that first processor sends the synchronization message；

Receive the latency request message that other described processors are sent；

To other described processor forward delay interval response messages, the delay response message includes that the first processor receives institute The virtual time t4 for stating delay request message, so that other described processors are based on the virtual time t1 and the virtual time T4 determines the time difference between the dummy clock of the first processor and the dummy clock of other processors, and is based on institute State the dummy clock of time difference adjustment other processors so that at the dummy clock of other processors and described first The dummy clock for managing device synchronizes.

27. processor as claimed in claim 15, which is characterized in that described according to first affairs relatively described first The scheduling time of the dummy clock of processor, before being scheduled to first affairs, the controller be additionally operable to execute with Lower operation：

The variable of dummy clock for characterizing the first processor is initialized；

Determine the virtual time of the dummy clock of the first processor；

It is the variable assignments according to the virtual time of the dummy clock of the first processor, to calibrate first processing The dummy clock of device.

28. processor as claimed in claim 27, which is characterized in that the controller is additionally operable to execute following operation：

Determine the clock frequency of the dummy clock of the first processor, wherein each dummy clock in the distributed system Clock frequency is identical；

According to the clock frequency of the dummy clock of the first processor, the count value of the variable is updated.

29. a kind of distributed system, which is characterized in that the distributed system includes such as any one of claim 15-28 institutes The processor stated.

30. a kind of unmanned plane, which is characterized in that including distributed system as claimed in claim 29.