CN108399882B

CN108399882B - Display panel, driving circuit and driving method thereof and display device

Info

Publication number: CN108399882B
Application number: CN201810161988.8A
Authority: CN
Inventors: 邹宗骏; 孙莹; 许育民
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2018-02-27
Filing date: 2018-02-27
Publication date: 2021-04-02
Anticipated expiration: 2038-02-27
Also published as: CN108399882A

Abstract

The invention discloses a display panel, a driving circuit, a driving method and a display device thereof, wherein the driving circuit comprises N driving circuit unit groups which are sequentially cascaded and N initial signal selection circuits, and each driving circuit unit group comprises a plurality of driving circuit units which are sequentially cascaded; by controlling the start signal selection circuit, the scanning signals can be sequentially output by the first scanning signal output end of the driving circuit unit from each driving circuit unit group at the first time, and the scanning signals can be output by the second scanning signal output end of the driving circuit unit from at least one driving circuit unit group at the second time. According to the invention, the driving circuit performs display scanning at the first time, performs fingerprint driving at the second time, and the fingerprint driving and the display scanning share the driving circuit, so that the frame area is reduced, and the realization of a full-screen is facilitated.

Description

Display panel, driving circuit and driving method thereof and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel, a driving circuit and a driving method thereof, and a display device.

Background

The fingerprint is the line that is formed by unsmooth skin on the finger abdomen of human finger end, also called the palm seal, is protruding line on the epidermis, because people's fingerprint is heredity and environment combined action, it is also closely related with human health, therefore the fingerprint people all have, but is different, because the fingerprint repetition rate is minimum, about 150 parts per billion, so it is called "human ID card", based on the difference characteristics of fingerprint, along with the development of science and technology, multiple display device that has fingerprint identification function has appeared in the market, such as cell-phone, panel computer and intelligent wearable equipment. Before a user operates the display device with the fingerprint identification function, the user can carry out authority verification only by touching the display device with a finger, and the authority verification process is simplified.

Display device with fingerprint identification function of prior art, display module assembly and fingerprint identification system separation design to can do the fingerprint identification system at the positive apron below Home key position of display device, make display device have the frame of broad, be unfavorable for forming the full face screen.

To this, prior art provides one kind with fingerprint identification system and display module assembly integrated technical scheme, specifically, integrates a plurality of fingerprint identification components and parts in display module assembly's display area, forms fingerprint identification components and parts array, then sets up drive circuit through the frame district at display module assembly, realizes the drive of fingerprint identification components and parts array, accomplishes fingerprint identification. However, the frame area in the prior art has been provided with the drive circuit who is used for driving display pixel, if set up the drive circuit who drives fingerprint identification components and parts array again simultaneously, can increase display module's frame area undoubtedly, still is unfavorable for forming the full-face screen.

Therefore, it is an urgent need in the art to provide a display panel, a driving circuit, a driving method and a display device thereof, which can complete the integration of a fingerprint identification system and a display module in a full-screen display device.

Disclosure of Invention

In view of the above, the present invention provides a display panel, a driving circuit, a driving method and a display device thereof, which solve the technical problem that in the prior art, when a fingerprint identification system is integrated with a display module, the area of a frame area of the display module is increased, which is not beneficial to forming a full-screen.

In order to solve the above technical problems, the present invention provides a driving circuit of a display panel.

The driving circuit comprises N driving circuit unit groups and N starting signal selection circuits which are sequentially cascaded, wherein N is a natural number greater than 1; the x-th-stage drive circuit unit group comprises M drive circuit units which are sequentially cascaded, wherein the x-th-stage drive circuit unit group is any one stage of drive circuit unit group in the drive circuit, M is a natural number which is greater than or equal to 1, and the number of the drive circuit units in the drive circuit unit groups of different stages is the same or different; the driving circuit unit comprises a scanning signal input end, a control signal input end, a first scanning signal output end, a second scanning signal output end and a shifting signal output end, wherein the shifting signal output end outputs a shifting signal, the first scanning signal output end outputs a first scanning signal, the second scanning signal output end outputs a second scanning signal, the control signal input end receives a first signal at a first time and receives a second signal at a second time, the first signal is an enable signal of the first scanning signal output end, and the second signal is an enable signal of the second scanning signal output end; the start signal selection circuit comprises a first start signal input end, a second start signal input end and a start signal output end, wherein the start signal output end is conducted with the first start signal input end at the first time, and the start signal output end is conducted with the second start signal input end at the second time; in the xth-stage driving circuit unit group, a scanning signal input end of the 1 st-stage driving circuit unit is connected with a starting signal output end of an xth-stage starting signal selection circuit, from the 2 nd-stage driving circuit unit to the mth-stage driving circuit unit, the scanning signal input end is respectively connected with a shifting signal output end of the previous-stage driving circuit unit, and a shifting signal output end of the mth-stage driving circuit unit is connected with a first starting signal input end of the (x + 1) th-stage starting signal selection circuit; and a first start signal input end of the 1 st stage start signal selection circuit receives a first shift start signal at the first time, and a second start signal input end of at least one start signal selection circuit in each stage start signal selection circuit receives a second shift start signal at the second time.

In order to solve the above technical problem, the present invention provides a display panel.

The display panel includes: the application provides a drive circuit of any display panel; a display pixel; one end of the scanning signal line is connected with the display pixel, and the other end of the scanning signal line is connected with a first scanning signal output end of the driving circuit; and one end of the fingerprint identification element is connected with the chip for fingerprint identification, the other end of the fingerprint identification element is connected with a second scanning signal output end of the driving circuit, wherein the first scanning signal output end outputs scanning signals to control the display pixels to display gray scales at the first time, and the second scanning signal output end outputs driving signals to control the fingerprint identification element to perform fingerprint identification at the second time.

In order to solve the above technical problem, the present invention provides a display device.

The display device comprises any one of the display panels provided by the invention.

In order to solve the above technical problem, the present invention provides a driving method of a display panel, the display panel including any one of the driving circuits provided by the present invention, the driving method including: inputting a first signal and a first shift start signal to the driving circuit, and detecting whether the display panel is touched; determining a position where the display panel is touched when it is detected that the display panel is touched; selecting at least one driving circuit unit group from N sequentially cascaded driving circuit unit groups of the driving circuit according to the determined touched position; and stopping inputting the first signal to the driving circuit, and inputting a second signal and a second shift start signal to the selected driving circuit cell group.

Compared with the prior art, the display panel, the driving circuit and the driving method thereof and the display device have the advantages that:

can be integrated fingerprint identification function in current display module assembly to fingerprint identification can multiplexing display scanning's drive circuit, reduces the frame, has carried out the group setting to drive circuit simultaneously, in order to realize when fingerprint identification, adopts partial drive circuit unit group to realize regional scanning, saves the consumption, also can accomplish the fingerprint scanning fast simultaneously and obtain the fingerprint identification result, improves fingerprint identification's reaction rate.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic diagram of a driving circuit according to an embodiment of the present invention;

fig. 2 is a circuit diagram of a driving circuit unit in the driving circuit according to the embodiment of the invention;

fig. 3 is a circuit diagram of a driving circuit unit in another driving circuit according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a start signal selection circuit in the driving circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another driving circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a sub-region of a driving circuit according to an embodiment of the present invention;

FIG. 7 is a timing diagram of a driving circuit according to an embodiment of the present invention;

fig. 8 is a circuit diagram of a driving circuit unit in another driving circuit according to an embodiment of the present invention;

fig. 9 is a circuit diagram of a second control circuit in the driving circuit according to the embodiment of the invention;

FIG. 10 is a circuit diagram of a start signal selection circuit in another driving circuit according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of another driving circuit according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a section of another driver circuit according to an embodiment of the present invention;

FIG. 13 is a timing diagram of another driving circuit according to an embodiment of the present invention;

FIG. 14 is a schematic diagram of a display panel according to an embodiment of the present invention;

fig. 15 is a flowchart of a driving method of a display panel according to an embodiment of the invention;

fig. 16 is a schematic diagram of a display device according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Fig. 1 is a schematic diagram of a driving circuit of a display panel according to an embodiment of the present invention, and as shown in fig. 1, the driving circuit includes N sequentially cascaded driving circuit unit groups and N start signal selecting circuits, where N is a natural number greater than 1, the N sequentially cascaded driving circuit unit groups are respectively a1 st-stage driving circuit unit group DG1, a2 nd-stage driving circuit unit group DG2, … through an nth-stage driving circuit unit group DGN, and the N start signal selecting circuits are respectively a1 st-stage start signal selecting circuit SC1, a2 nd-stage start signal selecting circuit SC2, … through an nth-stage start signal selecting circuit SCN.

For any one stage of driving circuit unit group, the driving circuit unit group includes a plurality of driving circuit units, and the number of the driving circuit units in different stage of driving circuit unit groups may be the same or different, which is not limited in this application.

Taking an arbitrary one-stage driving circuit cell group in the driving circuit, that is, the x-th stage driving circuit cell group DGx as an example, x is equal to or greater than 1 and equal to or less than N. As shown in fig. 1, the xth-stage driving circuit unit group DGx includes M driving circuit units sequentially cascaded, where M is a natural number greater than or equal to 1, and the M driving circuit units are respectively the 1 st-stage driving circuit unit D1_xAnd a2 nd stage driving circuit unit D2_x… up to the Mth stage driving circuit unit DM_xThe other stage driving circuit unit groups are similar and are not described herein again.

And any one stage of drive circuit unit in any one stage of drive circuit unit group comprises a scanning signal input end, a control signal input end, a first scanning signal output end, a second scanning signal output end and a shifting signal output end.

The 1 st-stage driving circuit unit D1 in the x-th-stage driving circuit unit group DGx remains_xFor example, with continued reference to FIG. 1, the level 1 driving circuit unit D1_xIncludes a scan signal input IN1_xControl signal input end C and first scanning signal output end GO1_xA second scan signal output terminal FPO1_xAnd a shift signal output terminal NE1_xThe other driving circuit units in the x-th driving circuit unit group DGx, and the driving circuit units in the other driving circuit unit groups and the 1 st driving circuit unit D1_xSimilarly, no further description is provided herein.

Wherein, the shift signal output terminal NE1_xA first scan signal output terminal GO1 for outputting a shift signal_xFor outputting a first scan signal, a second scan signal output terminal FPO1_xFor outputting the second scan signal, the control signal input terminal C can receive the first scan signal output terminal GO1 at different times_xOr the second scan signal output terminal FPO1_xThus, by transmitting different signals to the control signal input terminal C, the 1 st stage driving circuit unit D1 can be driven_xFirst scanning signal output terminal GO1_xOr the second scan signal output terminal FPO1_xEnable, first scanning signal output GO1_xAnd a second scan signal output terminal FPO1_xConnecting different driven devices on the display panel to enable the driving circuit to drive different driven devices in a time-sharing manner, e.g. the first scan signal output GO1_xA second scan signal output terminal FPO1 connected to the scan lines of the display panel for providing scan drive signals to the display pixels_xFingerprint connected with display panelAnd the identification element provides a fingerprint identification driving signal for the fingerprint identification element, so that display scanning and fingerprint identification can be driven by one driving circuit.

Each stage of the start signal selection circuit includes a first start signal input terminal, a second start signal input terminal and a start signal output terminal, and referring to fig. 1 for the x-th stage of the start signal selection circuit SCx, the x-th stage of the start signal selection circuit SCx includes a first start signal input terminal SI1_xA second start signal input terminal SI2_xAnd a start signal output terminal SO_xThe other stage start signal selection circuits are similar and are not described herein again. At different times, the start signal output SO_xOptionally a first start signal input terminal SI1_xIs conducted or connected to the second start signal input SI2_xConducting, i.e. starting at the signal output SO at different times_xCan output a first start signal input terminal SI1_xThe received signal can also output a second start signal input terminal SI2_xThe received signal.

The 1 st stage driving circuit unit D1 is still exemplified as the x-th stage driving circuit unit group DGx in the one stage driving circuit unit group_xScanning signal input terminal IN1_xIs supplied from the x-th stage start signal selection circuit SCx, and is driven from the 2 nd stage driving circuit unit D2_xInitial to Mth stage driving circuit unit DM_xWhen the scan signal input terminal of each stage of the driving circuit unit is connected to the shift signal output terminal of the one stage of the driving circuit unit, i.e., from the 2 nd stage of the driving circuit unit D2_xAt the beginning, the signal of the scanning signal input end of each stage of driving circuit unit is provided by the shifting signal output end of the previous stage of driving circuit unit, so that the shifting signals are sequentially transmitted among the driving circuit units in the first stage of driving circuit unit group, and the driving circuit units sequentially output effective driving signals.

Between each stage start signal selection circuit and each stage drive circuit unit group, the 1 st stage drive circuit unit in each stage drive circuit unit group corresponds to the stage drive circuit unit groupThe last stage of driving circuit unit in each stage of driving circuit unit group is connected with the next stage of starting signal selection circuit corresponding to the stage of driving circuit unit group. Specifically, still taking the xth-stage driving circuit unit group DGx as an example, with continuing reference to fig. 1, in the xth-stage driving circuit unit group DGx, the 1 st-stage driving circuit unit D1_xScanning signal input terminal IN1_xA start signal output terminal SO connected to the x-th stage start signal selection circuit SCx_xM-th stage driving circuit unit DM_xIs shifted to the signal output terminal NEM_xA first start signal input terminal SI1 of the x +1 th stage start signal selection circuit SCx +1 is connected_x+1. That is, for each stage of the driving circuit unit group, the initial shift signal received by the first stage driving circuit unit is provided by the start signal output terminal of the start signal selecting circuit, the shift signal output by the last stage driving circuit unit is output to the first start signal input terminal of the next stage start signal selecting circuit, and for the first start signal input terminal SI1 of the 1 st stage start signal selecting circuit SC1₁It receives the first shift start signal STV.

As can be seen from the above description, the initial shift signal provided to each stage of the driving circuit unit group is output from the start signal output terminal of the start signal selection circuit, so that the start signal selection circuit provides the driving circuit unit group with the signal received from the first start signal input terminal when the start signal output terminal is conducted with the first start signal input terminal, and provides the driving circuit unit group with the signal received from the second start signal input terminal when the start signal output terminal is conducted with the second start signal input terminal.

For the driving circuit shown in fig. 1, at a first time, the first start signal input terminal SI1 of the 1 st stage start signal selection circuit SC1 is first supplied₁The first shift start signal STV is input, and the first start signal input terminal and the start signal output terminal of each stage of start signal selection circuit are turned on at a first time, SO that the start signal output terminal SO of the 1 st stage of start signal selection circuit SC1₁Output the firstA shift start signal STV, and further the stage 1 driving circuit unit D1 of the stage 1 driving circuit unit group DG1₁Scanning signal input terminal IN1₁Receiving a first shift start signal STV; since the control signal input terminal of the driving circuit unit receives the first signal, which is the enable signal of the first scan signal output terminal, at the first time, the level 1 driving circuit unit D1₁After the first shift start signal STV is shifted, the first shift start signal goes through a first scanning signal output end GO1₁Output to the first scanning signal output terminal GO1₁Lines or devices connected thereto, e.g., scan lines of a display panel, etc., and a1 st-stage driving circuit unit D1₁Is not shown, and a shifted signal output terminal NE1₁Will be connected with the first scanning signal output GO1₁The output signal synchronized shift signal is outputted to the 2 nd stage driving circuit unit D2₁Scanning signal input terminal IN2₁. Then, the 2 nd stage driving circuit unit D2₁A scan signal input terminal IN2₁The received signal is shifted and passes through a first scanning signal output end GO2₁Output to the first scanning signal output terminal GO2₁Connected lines or devices, and a2 nd-stage driving circuit unit D2₁Is not shown, and a shifted signal output terminal NE2₁Will be connected with the first scanning signal output GO2₁And outputting the shifting signal synchronized with the output signal to a scanning signal input end of the next stage of driving circuit unit. And so on until the last stage of driving circuit unit DM₁Will scan the signal input terminal INM₁After the received signal is shifted, the signal passes through a first scanning signal output end GOM₁GOM output to the first scanning signal output terminal₁Connected lines or devices, and, at the same time, a final stage driving circuit unit DM₁Is shifted to the signal output terminal NEM₁Will be connected with the first scanning signal output terminal GOM₁The shift signal synchronized with the output signal is output to the first start signal input terminal SI1 of the 2 nd stage start signal selection circuit SC2₂。

Since the first start signal input terminal and the start signal output terminal of each stage of the start signal selection circuit are turned on at the first time, the start signal of the 2 nd stage of the start signal selection circuit SC2Signal output terminal SO₂Output first start signal input terminal SI1₂The received signals, and thus the 1 st stage driving circuit unit D1 of the 2 nd stage driving circuit unit group DG2₂Scanning signal input terminal IN1₂Receives the last stage driving circuit unit DM of the 1 st stage driving circuit unit group DG1₁Is shifted to the signal output terminal NEM₁The output shifted signal. Since the control signal input terminal of the driving circuit unit receives the first signal, which is the enable signal of the first scan signal output terminal, at the first time, the level 1 driving circuit unit D1₂Will shift the signal output NEM₁The output shift signal is shifted and passes through a first scanning signal output end GO1₂Output to the first scanning signal output terminal GO1₂Lines or devices connected thereto, e.g., scan lines of a display panel, etc., and a1 st-stage driving circuit unit D1₂Is not shown, and a shifted signal output terminal NE1₂Will be connected with the first scanning signal output GO1₂The output signal synchronized shift signal is outputted to the 2 nd stage driving circuit unit D2₂Scanning signal input terminal IN2₂. Then, the 2 nd stage driving circuit unit D2₂A scan signal input terminal IN2₂The received signal is shifted and passes through a first scanning signal output end GO2₂Output to the first scanning signal output terminal GO2₂Connected lines or devices, and a2 nd-stage driving circuit unit D2₂Is not shown, and a shifted signal output terminal NE2₂Will be connected with the first scanning signal output GO2₂And outputting the shifting signal synchronized with the output signal to a scanning signal input end of the next stage of driving circuit unit. And so on until the last stage of driving circuit unit DM₂Will scan the signal input terminal INM₂After the received signal is shifted, the signal passes through a first scanning signal output end GOM₂GOM output to the first scanning signal output terminal₂Connected lines or devices, and, at the same time, a final stage driving circuit unit DM₂The shift signal output terminal NEM will be connected to the first scanning signal output terminal GOM₂The shift signal synchronized with the output signal is output to the first start signal input terminal SI1 of the 3 rd stage start signal selection circuit SC3₃。

As can be seen from the above description, the 1 st stage driving circuit unit D1 of the 1 st stage driving circuit unit group DG1₁Scanning signal input terminal IN1₁Receiving a first shift start signal STV, and sequentially shifting and outputting the first shift start signal STV through first scan signal output ends of the driving circuit units of each stage of the 1 st-stage driving circuit unit group DG 1; then, the 1 st stage driving circuit unit D1 of the 2 nd stage driving circuit unit group DG2₂Scanning signal input terminal IN1₂Receives the last stage driving circuit unit DM from the 1 st stage driving circuit unit group DG1₁The output shift input signals synchronized with the shift signal are sequentially shifted and output through the first scan signal output terminals of the respective driver circuit units of the 2 nd driver circuit unit group DG 2.

In this way, from the 2 nd stage driving circuit unit group DG2 to the nth stage driving circuit unit group DGN, between the driving circuit unit groups of each stage, the scanning signal input terminal of the 1 st stage driving circuit unit of the driving circuit unit group of each stage receives a signal synchronized with the shift signal output terminal of the last stage driving circuit unit of the driving circuit unit group of the previous stage. In each stage of the driving circuit unit group, the 1 st stage driving circuit unit to the last stage driving circuit unit respectively shift the received shift signals and then output the shift signals through the first scanning signal output end, that is, after the driving circuit receives the first shift start signal STV, all the driving circuit units of each stage of the driving circuit unit group sequentially output the driving signals, and when the first scanning signal output end of each driving circuit unit is respectively and sequentially connected with each scanning line of the display panel, full-screen display scanning of the display panel can be realized.

When the driving circuit is required to drive elements in a certain area of the display panel, for example, fingerprint identification elements integrated on the display panel and located in the certain area are driven, so that when fingerprint identification is completed, after the driving circuit unit group corresponding to the certain area is determined, the driving circuit unit group is controlled to output a driving signal, and the other driving circuit unit groups do not output the driving signal. Specifically, to determine the driver corresponding to the areaFor the circuit unit group being the xth stage driving circuit unit group DGx, at the second time, the second start signal input terminal SI2 of the xth stage start signal selection circuit SCx is first inputted_xInputting a second shift start signal FPSTVx, and switching on the second start signal input end and the start signal output end of each stage of start signal selection circuit at a second time to switch on the start signal output end SO of the xth stage of start signal selection circuit SCx_xOutputs the second shift start signal FPSTVx, and further the 1 st stage driving circuit unit D1 of the x stage driving circuit unit group DGx_xScanning signal input terminal IN1_xReceiving a second shift start signal FPSTVx; since the control signal input terminal of the driving circuit unit receives the second signal, which is the enable signal of the second scan signal output terminal, at the second time, the level 1 driving circuit unit D1_xThe second shift start signal FPSTVx is shifted and then passes through the second scan signal output terminal FPO1_xOutput to and second scan signal output terminal FPO1_xConnected fingerprint identification element, and a1 st-stage driving circuit unit D1_xIs not shown, and a shifted signal output terminal NE1_xWill be connected with the second scan signal output terminal FPO1_xThe shift signal synchronized with the output signal is output to the 2 nd stage driving circuit unit D2_xScanning signal input terminal IN2_x. Then, the 2 nd stage driving circuit unit D2_xA scan signal input terminal IN2_xThe received signal is shifted and passes through the second scan signal output terminal FPO2_xOutput to and second scan signal output terminal FPO2_xConnected lines or devices, and a2 nd-stage driving circuit unit D2_xIs not shown, and a shifted signal output terminal NE2_xAnd a second scan signal output terminal FPO2_xAnd outputting the shifting signal synchronized with the output signal to a scanning signal input end of the next stage of driving circuit unit. And so on until the last stage of driving circuit unit DM_xWill scan the signal input terminal INM_xAfter the received signal is shifted, the signal passes through a second scanning signal output end FPOM_xOutput and second scanning signal output end FPOM_xConnected fingerprint identification component.

For the slave 1 st stage driving circuit unitThe group DG1 to the x-1 st stage driving circuit cell group DGx-1 do not input the start shift signal to the corresponding 1 st stage start signal selection circuit SC1 to x-1 st stage start signal selection circuit SC1, which do not output the driving signal, for the x +1 th stage driving circuit cell group DGx +1 to N-th stage driving circuit cell group DGN, the start shift signal is not input to the corresponding x +1 th stage start signal selection circuit SCx +1 to N-th stage start signal selection circuit SCN, and the last stage driving circuit cell DM of the x-th stage driving circuit cell group DGx_xIs shifted to the signal output terminal NEM_xOutputs the shift signal to the first start signal input terminal SI1 of the x +1 th stage start signal selection circuit SCx +1_x+1However, the start signal output terminal SO of the x +1 th stage start signal selection circuit SCx +1_x+1Not associated with the first start signal input SI1_x+1Conducting, unable to shift the signal output end NEM_xThe outputted shift signal is transferred to the 1 st stage driving circuit unit D1 of the x +1 th stage driving circuit unit group DGx +1_x+1Scanning signal input terminal IN1_x+1Therefore, none of the drive circuit unit groups other than the x-th stage drive circuit unit group DGx can output a drive signal.

In the driving circuit provided in this embodiment, the first scanning signal output terminal in the driving circuit unit is connected to the scanning line of the display panel, and the second scanning signal output terminal is connected to the fingerprint identification element, which is equivalent to the driving of realizing display scanning and fingerprint identification by using the same driving circuit, that is, when fingerprint identification is added to the display panel, the driving circuit capable of multiplexing display scanning realizes fingerprint identification without separately setting the driving circuit for fingerprint identification, which is easy to form a narrow frame.

For fingerprint identification, the effective scanning interval only needs a part of the display area on the display panel, and if the driving circuit completes full-screen scanning as in display scanning during fingerprint identification, power consumption is wasted undoubtedly, so the driving circuit in the embodiment includes a plurality of driving circuit unit groups, which is equivalent to partitioning the driving circuit for display scanning, that is, each driving circuit unit group serves as a partition, and each partition can independently realize fingerprint identification scanning on an area on the display panel without full-screen scanning, so that the power consumption of the driving circuit can be reduced.

In summary, adopt the display panel's that this embodiment provided drive circuit, can be at integrated fingerprint identification function in current display module assembly to fingerprint identification can multiplexing display scan's drive circuit, reduces the frame, has carried out the group setting to drive circuit simultaneously, in order to realize when fingerprint identification, adopts partial drive circuit unit group to realize regional scanning, saves the consumption, also can accomplish the fingerprint scanning fast simultaneously and obtain the fingerprint identification result, improves fingerprint identification's reaction rate.

In an embodiment, the driving circuit units are implemented by using CMOS type shift registers, fig. 2 is a circuit diagram of the driving circuit units in the driving circuit provided by the embodiment of the present invention, and referring to fig. 1 and fig. 2, in this embodiment, the driving circuit unit D1 of the 1 st stage in the x-th stage driving circuit unit group DGx is still used_xFor example, the other driver circuit cells in the x-th driver circuit cell group DGx and the driver circuit cells in the other driver circuit cell groups are the same as the 1 st driver circuit cell D1_xSimilarly, no further description is provided herein.

Stage 1 driving circuit unit D1_xComprises a first clock signal input terminal CKV1, a second clock signal input terminal CKV2, and a scan signal input terminal IN1_xAnd a shift signal output terminal NE1_xControl signal input end C and first scanning signal output end GO1_xAnd a second scan signal output terminal FPO1_xWherein the first clock signal input terminal CKV1 and the second clock signal input terminal CKV2 receive the clock signal provided by the control chip, and the scan signal input terminal IN1_xAnd a shift signal output terminal NE1_xControl signal input end C and first scanning signal output end GO1_xAnd a second scan signal output terminal FPO1_xReference is made to the above description, which is not repeated herein.

Drive circuit unit D1_xAlso included is a first shift register comprising latches LA, and a first control circuit CC1,A first nand gate NA1, a first buffer BU1, a second nand gate NA2 and a second buffer BU 2. Specifically, the clock input terminal of the latch LA is connected to the first clock input terminal CKV1, and the input terminal of the latch LA is connected to the scan signal input terminal IN1_xThe output terminal of the latch LA is connected to the shift signal output terminal NE1_x。

A first input of the first nand-gate NA1 is connected to the output of the latch LA, and a second input of the first nand-gate NA1 is connected to the second clock signal input CKV 2. The input terminal of the first buffer BU1 is connected to the output terminal of the first nand gate NA1, and the output terminal of the first buffer BU1 is connected to the first scan signal output terminal GO1_xAre connected. A first input of the second nand gate NA2 is coupled to the output of the latch LA, and a second input of the second nand gate NA2 is coupled to the second clock signal input CKV 2. The input terminal of the second buffer BU2 is connected to the output terminal of the second nand gate NA2, and the output terminal of the second buffer BU2 and the second scan signal output terminal FPO1_xAre connected.

The first control circuit CC1 is connected to the control signal input terminal C, the first nand gate NA1 and the second nand gate NA2, wherein the first control circuit CC1 controls the output terminal of the second nand gate NA2 to continuously output the inactive level signal when the control signal input terminal C receives the first signal, and at this time, the second scan signal output terminal FPO1_xA first scan signal output terminal GO1 for continuously outputting non-active level signal_xA scan signal input terminal IN1_xShifting and outputting the received signal; when the control signal input terminal C receives the second signal, the output terminal of the first nand gate NA1 is controlled to continuously output the inactive level signal, and at this time, the first scan signal output terminal GO1_xA second scan signal output terminal FPO1 for continuously outputting non-active level signal_xA scan signal input terminal IN1_xThe received signal is shifted out.

Specifically, in an embodiment, fig. 3 is a circuit diagram of a driving circuit unit in another driving circuit provided in an embodiment of the present invention, and in this embodiment, the driving circuit unit D1 is still used_xFor example, as shown in FIG. 3Drive circuit unit D1 in drive circuit_xComprises a first clock input terminal CKV1, a second clock input terminal CKV2, a positive scan signal input terminal INF1_xAn inverse scan signal input terminal INB1_xAnd a shift signal output terminal NE1_xA first control signal input terminal FPOFF, a second control signal input terminal GOFF, and a first scanning signal output terminal GO1_xAnd a second scan signal output terminal FPO1_xWherein the positive scan signal input terminal INF1_xAnd an inverse scan signal input terminal INB1_xAre scan signal input terminals, and when the driving circuit performs a positive scan, the positive scan signal input terminal INF1_xEnable, when the driving circuit performs reverse scan, the reverse scan signal input terminal INF1_xAnd enabling. In one embodiment, as shown in FIG. 3, the first input enable signal terminal U2D and the second input enable signal terminal D2U control the positive scan signal input terminal INF1_xOr inverse scan signal input terminal INF1_xEnabling, for example, when the first input enable signal terminal U2D receives a high signal and the second input enable signal terminal D2U receives a low signal, the scan signal input terminal INF1 is scanned_xWhen the first input enable signal terminal U2D receives a low level signal and the second input enable signal terminal D2U receives a high level signal, the scan bar signal input terminal INB1 is inverted_xAnd enabling. The first control signal input terminal GOFF and the second control signal input terminal FPOFF are both driving circuit units D1_xThe first signal is that the first control signal input terminal GOFF receives a high level signal, the second control signal input terminal FPOFF receives a low level signal, the second signal is that the first control signal input terminal GOFF receives a low level signal, and the second control signal input terminal FPOFF receives a high level signal.

The first nand gate NA1 and the second nand gate NA2 respectively include two N-type transistors connected in series and two P-type transistors connected in parallel, wherein in the first nand gate NA1 and the second nand gate NA2, a first end of the two N-type transistors connected in series is connected to the first control circuit CC1, a first end of the two P-type transistors connected in parallel is connected to the positive voltage VGH, and a second end of the two N-type transistors connected in series is connected to a second end of the two P-type transistors connected in parallel.

The first control circuit CC1 includes: the first nand gate circuit comprises a first P-type transistor P1, a first N-type transistor N1, a second P-type transistor P2 and a second N-type transistor N2, wherein a control end of the first P-type transistor P1 is connected with a first control signal input terminal GOFF, a first connection end of the first P-type transistor P1 is connected with a positive voltage VGH, and a second connection end of the first P-type transistor P1 is connected with an output end NA1-O of the first nand gate NA 1.

A control end of the first N-type transistor N1 is connected to the first control signal input terminal GOFF, a first connection end of the first N-type transistor N1 is connected to the negative voltage VGL, and a second connection end of the first N-type transistor N1 is connected to a first end of the first nand gate NA1 after two serially connected N-type transistors are serially connected.

The control terminal of the second P-type transistor P2 is connected to the second control signal input terminal FPOFF, the first connection terminal of the second P-type transistor P2 is connected to the positive voltage VGH, and the second connection terminal of the second P-type transistor P2 is connected to the output terminal NA2-O of the second nand gate NA 2.

The control end of the second N-type transistor N2 is connected to the second control signal input end FPOFF, the first connection end of the second N-type transistor N2 is connected to the negative voltage VGL, and the second connection end of the second N-type transistor is connected to the first end of the second nand gate NA2 after the two serially connected N-type transistors are serially connected.

In this embodiment, the first control signal input terminal GOFF receives a high level signal, and the second control signal input terminal FPOFF receives a low level signal, i.e. the driving circuit unit D1_xThe control signal input end of the latch circuit receives a first signal, so that the first P-type transistor P1 is turned off, the first N-type transistor N1 is turned on, the second P-type transistor P2 is turned on, the second N-type transistor N2 is turned off, the output end NA2-O of the second NAND gate NA2 continuously outputs a positive voltage signal VGH, and a signal output by the latch LA passes through the first NAND gate NA1 and the first buffer BU1 to reach the first scanning signal output end GO1_xAnd (6) outputting.

The first control signal input terminal GOFF receives low level signal, the second control signal input terminal FPOFF receives high level signal, that is, the driving circuit is singleElement D1_xThe control signal input terminal of the latch receives a second signal, so that the first P-type transistor P1 is turned on, the first N-type transistor N1 is turned off, the second P-type transistor P2 is turned off, the second N-type transistor N2 is turned on, the output terminal NA1-O of the first NAND gate NA1 continuously outputs a positive voltage signal VGH, and the signal output by the latch LA passes through the second NAND gate NA2 and the second buffer BU2 to reach the second scan signal output terminal FPO1_xAnd (6) outputting.

Fig. 4 is a circuit diagram of a start signal selection circuit in a driving circuit according to an embodiment of the present invention, in this embodiment, taking an x-th stage start signal selection circuit SCx in the driving circuit as an example, as shown in fig. 4, the start signal selection circuit includes two branches, where a first branch includes two third P-type transistors P3 and a third N-type transistor N3 connected in parallel, a control terminal of the third P-type transistor P3 is connected to a second control signal input terminal FPOFF, a control terminal of the third N-type transistor N3 is connected to a first control signal input terminal GOFF, and a first terminal of the third P-type transistor P3 and a first terminal of the third N-type transistor N3 connected in parallel is connected to a first start signal input terminal SI1_xA second terminal of the third P-type transistor P3 and the third N-type transistor N3 connected in parallel is connected to the start signal output terminal SO_x. The first end of the second branch is connected with a second initial signal input end SI2_xThe second end of the second branch is connected with the starting signal output end SO_x. The on-off state of the first branch is controlled by the on-off states of the third P-type transistor P3 and the third N-type transistor, the second branch is in a long-pass state and is a normally closed branch, only one conducting wire does not have a switching tube, and a switching tube in a normally closed state can be arranged. The first control signal input terminal GOFF receives a high level signal, the second control signal input terminal FPOFF receives a low level signal, that is, the driving circuit unit D1_xWhen the first signal is received at the control signal input terminal of the first branch circuit, the second start signal input terminal SI2 is turned on_xWithout receiving a valid signal, start signal output SO_xOutput first start signal input terminal SI1_xA received signal; a low level signal is received at a first control signal input terminal GOFF, and a high level signal is received at a second control signal input terminal FPOFFFlat signal, i.e. drive circuit unit D1_xWhen the control signal input end receives the second signal, the first branch is switched off, and the initial signal output end SO_xOutput second start signal input terminal SI2_xThe received signal.

Specifically, fig. 5 is a schematic diagram of another driving circuit provided in an embodiment of the present invention, in this embodiment, as shown in fig. 5, a first-stage driving circuit unit group and a corresponding start signal selection circuit are regarded as one partition, fig. 5 shows three partitions of the driving circuit, the three partitions sequentially include an x-1 th-stage driving circuit unit group DGx-1, an x-th-stage driving circuit unit group DGx, and an x +1 th-stage driving circuit unit group DGx +1, and the start signal selection circuits in the partitions are illustrated as switches. Specifically, the driving circuit units of each stage of the driving circuit unit group include a first clock signal input terminal CKV1, a second clock signal input terminal CKV2, a forward scan signal input terminal INF, a reverse scan signal input terminal INB, a shift signal output terminal NEXT, a first control signal input terminal GOFF, a second control signal input terminal FPOFF, a first scan signal output terminal GOUT, a second scan signal output terminal FPOUT, a first input enable signal terminal U2D, a second input enable signal terminal D2U, and a reset signal input terminal GRESET.

Fig. 6 is a schematic diagram of a partition of a driving circuit according to an embodiment of the present invention, fig. 6 illustrates three driving circuit units in the partition, the circuit composition of a single driving circuit unit can refer to fig. 3, and the circuit composition of a start signal selecting circuit can refer to fig. 4.

Fig. 7 is a timing diagram of the driving circuit according to the embodiment of the invention, please refer to fig. 3 to 7, taking normal scan as an example, at a first time T1, the first control signal input terminal GOFF receives a high level signal, the second control signal input terminal FPOFF receives a low level signal, the first clock signal input terminal CKV1 and the second clock signal input terminal CKV2 receive clock signals, the first input enable signal terminal U2D receives a high level signal, the second input enable signal terminal D2U receives a low level signal, the normal scan signal input terminal INF is enabled, and the reset signal input terminal GRESET receives a pulse signal before providing the shift start signal to the driving circuit, so as to reset the driving circuit.

Since the first control signal input terminal GOFF receives a high level signal and the second control signal input terminal FPOFF receives a low level signal, the start signal output terminal outputs a signal received by the first start signal input terminal, and the driving circuit units in each driving circuit unit group sequentially output driving signals through the first scan signal output terminal, respectively.

Specifically, throughout the first time T1, the second start signal input terminal of each start signal selection circuit is in a high impedance state for the start signal selection circuits, as shown in fig. 7, and the second start signal input terminal SI2 of the x-th stage start signal selection circuit is used_xFor example, during the first time T1, the second start signal input terminal SI2_xContinuously in a high impedance state. For the driving circuit unit, the second scan signal output terminal FPOUT continuously outputs the inactive signal, as shown in fig. 6, the second scan signal output terminal FPOUT is connected to the driving line, as shown in fig. 7, and taking the second driving line FP2 connected to the second scan signal output terminal FPOUT of the 2 nd stage driving circuit unit in one partition as an example, the second driving line FP2 continuously outputs the low level signal during the first time T1.

Within t1-1, the first start signal input terminal SI1 of the 1 st stage start signal selection circuit₁Receiving the first shift start signal, the start signal output terminal SO of the 1 st stage start signal selection circuit₁And a first start signal input terminal SI1₁Turning on, outputting a first shift start signal to the scan signal input terminal INF of the first driving circuit unit in the first partition, where in t1-2, the first scan signal output terminal GOUT of the first driving circuit unit outputs a scan signal to the first scan line G1 connected to the first scan signal output terminal GOUT, so that the first scan line G1 receives the scan signal in t1-2, that is, the first scan line G1 is in a high state in t 1-2; at the same time, the NEXT output terminal of the first driver circuit unit outputs a shift signal to the scan signal input terminal INF of the second driver circuit unit in the first division, and the second driver circuit unit outputs a shift signal to the scan signal input terminal INF of the second driver circuit unit in the first division at t1-3The first scan signal output terminal GOUT of the cell outputs the scan signal to the second scan line G2 connected to the first scan signal output terminal GOUT, so that the second scan line G2 receives the scan signal at t1-3, i.e., the second scan line G2 is at the high level at t 1-2; meanwhile, the NEXT output end of the second driving circuit unit outputs a shift signal to the scanning signal input end INF of the third driving circuit unit in the first sub-area, and so on until the first scanning signal output ends GOUT of all the driving circuit units in the first sub-area output scanning signals; then, a shift signal is output from a shift signal output end NEXT of the last drive circuit unit in the first subarea to a first start signal input end of a2 nd-stage start signal selection circuit, a start signal output end of the 2 nd-stage start signal selection circuit is conducted with the first start signal input end, the shift signal output from the shift signal output end NEXT of the last drive circuit unit in the first subarea is output to a scanning signal input end of the first drive circuit unit in the second subarea, and so on until the first scanning signal output ends of all the drive circuit units in the second subarea output scanning signals; finally, all the drive circuit units in each partition output scanning signals to complete full-screen scanning, and in the process, the display panel normally displays and detects touch.

When a touch is detected and it is determined that the xth partition needs to drive the fingerprint identification device for fingerprint identification, at a second time T2, the first control signal input terminal GOFF receives a low level signal, the second control signal input terminal FPOFF receives a high level signal, so that the start signal output terminal outputs a signal received by the second start signal input terminal, and the driving circuit units in each driving circuit unit group sequentially output driving signals through the second scanning signal output terminals, respectively.

Specifically, throughout the second time T2, the first start signal input terminal of each start signal selection circuit is in a high impedance state for the start signal selection circuits, as shown in FIG. 7, and the first start signal input terminal SI1 of the 1 st start signal selection circuit is used₁For example, at a second time T2, first togetherInitial signal input terminal SI1₁Continuously in a high impedance state. For the driving circuit unit, the first scan signal output terminal GOUT continuously outputs the inactive signal, and as shown in fig. 7, taking the first scan line G1 connected to the first scan signal output terminal GOUT of the driving circuit unit of the 1 st stage in a sub-area other than the x-th sub-area as an example, the first scan line G1 continuously outputs the low level signal during the second time T2.

At t2-1, the second start signal input terminal SI2 of the x-th stage start signal selection circuit_xReceiving the second shift start signal, the start signal output terminal SO of the x-th stage start signal selection circuit_xAnd a second start signal input terminal SI2_xTurning on, outputting a second shift start signal to the scan signal input terminal INF of the first driving circuit unit in the xth partition, and outputting a driving signal from the second scan signal output terminal FPOUT of the first driving circuit unit to the first driving line FP1 connected to the second scan signal output terminal FPOUT in t2-2, so that the first driving line FP1 receives the driving signal in t2-2, that is, the first driving line FP1 is in a high state in t 2-2; meanwhile, the shift signal output terminal NEXT of the first driver circuit unit outputs a shift signal to the scan signal input terminal INF of the second driver circuit unit in the xth partition, and the second scan signal output terminal FPOUT of the second driver circuit unit outputs a drive signal to the second driver line FP2 connected to the second scan signal output terminal FPOUT at t2-3, so that the second driver line FP2 receives the drive signal at t1-3, that is, the second driver line FP2 is in a high level state at t 2-3; meanwhile, the NEXT output end of the shift signal of the second drive circuit unit outputs a shift signal to the scan signal input end INF of the third drive circuit unit in the xth sub-area, and so on until the FPOUT of the second scan signal output ends of all the drive circuit units in the xth sub-area all output drive signals, so as to complete the driving of the fingerprint identification elements in the area of the display panel corresponding to the xth sub-area, and realize the fingerprint identification.

In one embodiment, the driving circuit unit is implemented by using a PMOS type shift register, and FIG. 8 provides an embodiment of the present inventionReferring to fig. 1 and 8, in this embodiment, the circuit unit D1 of the 1 st stage in the x-th stage driving circuit unit group DGx is still driven_xFor example, the other driver circuit cells in the x-th driver circuit cell group DGx and the driver circuit cells in the other driver circuit cell groups are the same as the 1 st driver circuit cell D1_xSimilarly, no further description is provided herein.

Drive circuit unit D1_xIt further comprises a second shift register comprising an output unit OU, a pull-down unit DU and a pull-up unit UU, and a second control circuit CC 2. In particular, the output OU1 of the output unit OU_xAnd shift signal output terminal NE1_xConnected to each other, the output unit OU includes a first node N1 and a second node N2.

Pull-down unit DU and scan signal input IN1_xA first clock input terminal CKV1, a second clock input terminal CKV2 and a second node N2 connected to each other for receiving a scan signal input terminal IN1_xThe signals received by the first clock signal input terminal CKV1 and the second clock signal input terminal CKV2 control the potential of the second node N2.

The pull-up unit UU is connected to the first clock signal input terminal CKV1, the first node N1 and the second node N2, and is configured to control the potential of the first node N1 according to the signal received by the first clock signal input terminal CKV1 and the potential of the second node N2.

A second control circuit CC2, a control signal input terminal C, and a first scan signal output terminal GO1_xAnd a second scan signal output terminal FPO1_xRespectively, wherein the second control circuit CC2 controls the output OU1 of the output unit OU when the control signal input terminal C receives the first signal_xAnd a first scanning signal output terminal GO1_xOn, output OU1_xThe output signal passes through a first scanning signal output terminal GO1_xAnd (6) outputting. The output OU1 of the control output unit OU is controlled when the control signal input terminal C receives a second signal_xAnd a second scan signal output terminal FPO1_xOn, output OU1_xThe output signal passes through the second scan signal output terminal FPO1_xAnd (6) outputting.

Specifically, in one embodiment, with continued reference to fig. 8, the pull-down unit DU includes five P-type transistors, the pull-up unit UU includes two P-type transistors, and the output unit OU includes two P-type transistors and two storage capacitors. Fig. 9 is a circuit diagram of a second control circuit in the driving circuit according to the embodiment of the invention, and as shown in fig. 8 and 9, the second control circuit CC2 includes a fourth N-type transistor N4 and a fourth P-type transistor P4. Wherein, the control terminal of the fourth N-type transistor N4 is connected to the control signal input terminal C, and the first connection terminal of the fourth N-type transistor N4 is connected to the output terminal OU1 of the output unit OU_xA second connection terminal of the fourth N-type transistor N4 is connected to the first scan signal output terminal GO1_x. The control terminal of the fourth P-type transistor P4 is connected to the control signal input terminal C, and the first connection terminal of the fourth P-type transistor P4 is connected to the output terminal OU1 of the output unit_xThe second connection terminal of the fourth P-type transistor is connected to the second scan signal output terminal FPO1_x。

In this embodiment, the driving circuit unit D1_xWhen the control signal input terminal receives the first signal, that is, the control signal input terminal C receives the high level signal, the fourth P-type transistor P4 is turned off, and the output terminal OU1 of the output unit OU_xAnd a second scan signal output terminal FPO1_xIs turned off, the fourth N-type transistor N4 is turned on, and the output unit OUOutput port OU1_xAnd a first scanning signal output terminal GO1_xA conduction channel is formed between the output unit OU and the output unit OU, and the output signal passes through the first scanning signal output end GO1_xAnd (6) outputting.

Drive circuit unit D1_xWhen the control signal input terminal receives the second signal, that is, the control signal input terminal C receives the low level signal, the fourth P-type transistor P4 is turned on, and the output terminal OU1 of the output unit OU_xAnd a second scan signal output terminal FPO1_xA conducting channel is formed between the first and second N-type transistors, the fourth N-type transistor N4 is turned off, and the output end OU1 of the output unit OU_xAnd a first scanning signal output terminal GO1_xIs cut off, and the output signal of the output unit OU passes through the second scan signal output terminal FPO1_xAnd (6) outputting.

Fig. 10 is a circuit diagram of a start signal selection circuit in another driving circuit according to an embodiment of the present invention, in this embodiment, taking the x-th stage start signal selection circuit SCx in the driving circuit as an example, as shown in fig. 10, the start signal selection circuit further includes a fifth N-type transistor N5 and a fifth P-type transistor P5. Specifically, the control terminal of the fifth N-type transistor N5 is connected to the control signal input terminal C, and the first connection terminal of the fifth N-type transistor N5 is connected to the first start signal input terminal SI1_xA second connection terminal of the fifth N-type transistor N5 is connected to the start signal output SO_x. A control terminal of the fifth P-type transistor P5 is connected to the control signal input terminal C, and a first connection terminal of the fifth P-type transistor P5 is connected to the second start signal input terminal SI2_xA second connection terminal of the fifth P-type transistor P5 is connected to the start signal output terminal SO_x。

In this embodiment, the driving circuit unit D1_xWhen the control signal input terminal receives the first signal, that is, the control signal input terminal C receives the high level signal, the fifth P-type transistor P5 is turned off, and the start signal output terminal SO_xAnd a second start signal input terminal SI2_xIs turned off, the fifth N-type transistor N5 is turned on, and the start signal output terminal SO_xAnd a first start signal input terminal SI1_xA conduction channel is formed between the two, and the starting signal output end SO_xOutput a first start signal inputTerminal SI1_xThe received signal.

Drive circuit unit D1_xWhen the control signal input terminal receives the second signal, that is, the control signal input terminal C receives the low level signal, the fifth P-type transistor P5 is turned on, and the start signal output terminal SO_xAnd a second start signal input terminal SI2_xA conducting channel is formed between the first and second transistors, the fifth N-type transistor N5 is turned off, and the start signal output terminal SO is connected to the second transistor_xAnd a first start signal input terminal SI1_xCut-off between, start signal output SO_xOutput second start signal input terminal SI2_xThe received signal.

Specifically, fig. 11 is a schematic diagram of another driving circuit according to an embodiment of the present invention, and as shown in fig. 11, one stage of driving circuit unit group and the corresponding start signal selection circuit are regarded as one partition, fig. 11 shows four partitions of the driving circuit, and the four partitions sequentially include a1 st stage driving circuit unit group DG1 and a1 st stage start signal selection circuit SC1, a2 nd stage driving circuit unit group DG2 and a2 nd stage start signal selection circuit SC2, a 3 rd stage driving circuit unit group DG3 and a 3 rd stage start signal selection circuit SC4, and a 4 th stage driving circuit unit group DG4 and a 4 th stage start signal selection circuit SC 4. Specifically, the driving circuit units of each stage of the driving circuit unit group include a first clock signal input terminal CKV1, a second clock signal input terminal CKV2, a scan signal input terminal IN, a shift signal output terminal NEXT, a control signal input terminal C, a first scan signal output terminal GOUT, a second scan signal output terminal FPOUT, and a reset signal input terminal Greset.

Fig. 12 is a schematic diagram of a partition of another driving circuit according to an embodiment of the present invention, fig. 12 shows two driving circuit units in a partition, and the circuit composition of a single driving circuit unit can refer to fig. 8.

Referring to fig. 13, referring to fig. 8 to 13, at a first time T1, the control signal input terminal C receives a high level signal, the first clock signal input terminal CKV1 and the second clock signal input terminal CKV2 receive clock signals, and the reset signal input terminal Greset receives a pulse signal before providing a shift start signal to the driving circuit to reset the driving circuit.

Since the control signal input terminal C receives a high level signal, the start signal output terminal outputs a signal received by the first start signal input terminal, and the driving circuit units in each driving circuit unit group sequentially output driving signals through the first scanning signal output terminals, respectively.

Specifically, for the start signal selection circuits, the second start signal input terminal of each start signal selection circuit is continuously inputted with the inactive signal for the whole first time T1, as shown in fig. 13, and the second start signal input terminal SI2 of the x-th stage start signal selection circuit is used_xFor example, during the first time T1, the second start signal input terminal SI2_xThe non-valid signal is continuously received. For the driving circuit unit, the second scan signal output terminal FPOUT continuously outputs the inactive signal, and as shown in fig. 7, the second scan signal output terminal FPOUT continuously outputs the low level signal.

Within t1-1, the first start signal input terminal SI1 of the 1 st stage start signal selection circuit₁Receiving the first shift start signal, the start signal output terminal SO of the 1 st stage start signal selection circuit₁And a first start signal input terminal SI1₁Turning on, outputting a first shift start signal to a scan signal input terminal IN of a first driving circuit unit IN the first partition, where a first scan signal output terminal GOUT of the first driving circuit unit outputs a scan signal at t 1-2; meanwhile, the NEXT output end NEXT of the shift signal of the first driving circuit unit outputs a shift signal to the scanning signal input end IN of the second driving circuit unit IN the first sub-area, and at the NEXT moment, the first scanning signal output end GOUT of the second driving circuit unit outputs a scanning signal, and so on until the first scanning signal output ends GOUT of all the driving circuit units IN the first sub-area output a scanning signal; the NEXT output terminal of the last driver circuit cell in the first division outputs a shift signal to the first start signal input terminal of the 2 nd stage start signal selection circuit SC2, the 2 nd stage start signal selection circuitThe initial signal output end of the path is conducted with the first initial signal input end, the shifting signal output by the shifting signal output end NEXT of the last driving circuit unit in the first subarea is output to the scanning signal input end of the first driving circuit unit in the second subarea, and so on until the first scanning signal output ends of all the driving circuit units in the second subarea output scanning signals; finally, all the drive circuit units in each partition output scanning signals to complete full-screen scanning, and in the process, the display panel normally displays and detects touch.

When a touch is detected and it is determined that the xth partition needs to drive the fingerprint identification element for fingerprint identification, at a second time T2, the control signal input terminal C receives a low level signal, so that the start signal output terminal outputs a signal received by the second start signal input terminal, and the driving circuit units in each driving circuit unit group sequentially output driving signals through the second scanning signal output terminals, respectively.

Specifically, throughout the second time T2, for the start signal selection circuits, the first start signal input terminal of each start signal selection circuit continuously receives the low level signal, as shown in FIG. 13, and the first start signal input terminal SI1 of the 1 st start signal selection circuit₁For example, at the second time T2, the first start signal input terminal SI1₁The low level signal is continuously received. For the driving circuit unit, the first scan signal output terminal GOUT continuously outputs the inactive signal, and as shown in fig. 13, the first scan signal output terminal GOUT of the driving circuit unit of the 1 st stage in one of the partitions other than the x-th partition outputs the low level signal.

At t2-1, the second start signal input terminal SI2 of the x-th stage start signal selection circuit_xReceiving the second shift start signal, the start signal output terminal SO of the x-th stage start signal selection circuit_xAnd a second start signal input terminal SI2_xTurning on to output the second shift start signal to the scan signal input terminal INF of the first driver circuit unit in the x-th sub-area, and at t2-2, the second scan signal output terminal FPOUT of the first driver circuit unit outputs the driveAnd simultaneously, a shift signal is output from a shift signal output end NEXT of the first drive circuit unit to a scanning signal input end IN of a second drive circuit unit IN the xth subarea, a drive signal is output from a second scanning signal output end FPOUT of the second drive circuit unit at the NEXT moment, and so on until the second scanning signal output ends FPOUT of all the drive circuit units IN the xth subarea output the drive signals, so that the drive of the fingerprint identification elements IN the area of the display panel corresponding to the xth subarea is completed, and the fingerprint identification is realized.

The above embodiments of the driving circuit of the display panel according to the embodiments of the present invention also provide a display panel, where the display panel includes any one of the above driving circuits, and has the features and corresponding technical effects, which are not described herein again.

In an embodiment, fig. 14 is a schematic diagram of a display panel according to an embodiment of the invention, and as shown in fig. 14, the display panel includes a driving circuit DC, display pixels (not shown), scanning signal lines (not shown), and a fingerprint identification device (not shown).

One end of the scanning signal line is connected with the display pixel, and the other end of the scanning signal line is connected with a first scanning signal output end of the driving circuit; one end of the fingerprint identification element is connected with the chip IC for fingerprint identification through a receiving line FPRX, and the other end of the fingerprint identification element is connected with a second scanning signal output end of the driving circuit DC through a driving line FPTX.

The driving circuit includes a plurality of partitions, and as shown in fig. 14, the driving circuit is divided into six partitions including a first partition U1, a second partition U2, and up to a sixth partition U6, and each partition includes a one-stage driving circuit cell group and a one-stage start signal selection circuit.

At the first time, the driving circuit drives the driving circuit units in all the subareas to sequentially output scanning signals through the first scanning signal output end so as to control the display pixels to carry out gray scale display. And at the second time, the driving circuit units in the driving part partitions of the driving circuit output driving signals through the second scanning signal output ends so as to control the fingerprint identification elements to carry out fingerprint identification. As shown in fig. 14, at the second time, the driving circuit drives the driving circuit units in the third partition U3 to sequentially output driving signals through the second scan signal output terminal, so as to control the fingerprint identification elements in the area on the display panel corresponding to the third partition to perform fingerprint identification.

Adopt the display panel that this embodiment provided, can be at integrated fingerprint identification function in current display module assembly to fingerprint identification can multiplexing display scanning's drive circuit, reduces the frame, has carried out the subregion setting to drive circuit simultaneously, in order to realize when fingerprint identification, adopts partial drive circuit unit group to realize regional scanning, saves the consumption, also can accomplish fingerprint scanning fast simultaneously and obtain the fingerprint identification result, improves fingerprint identification's reaction rate.

The invention also provides a driving method of the display panel, the display panel comprises any one of the driving circuits, and the display panel has the characteristics and the corresponding technical effects, which are not described again. Fig. 15 is a flowchart of a driving method of a display panel according to an embodiment of the present invention, and in an embodiment, as shown in fig. 15, the driving method includes the following steps S101 to S104.

Step S101: a first signal and a first shift start signal are input to a driving circuit, and whether a display panel is touched or not is detected.

The driving circuit receives the first signal and the first shift start signal, so that the driving circuit units in each driving circuit unit group sequentially output scanning signals through the first scanning signal output end respectively, and full-screen scanning is realized.

Step S102: when it is detected that the display panel is touched, a position where the display panel is touched is determined.

Step S103: and selecting at least one driving circuit unit group from the N sequentially cascaded driving circuit unit groups of the driving circuit according to the determined touched position.

When touch is detected, the touched position of the display panel needs to be preliminarily judged according to the touched position, and then which partition driving fingerprint identification element needs to carry out fingerprint identification is obtained, namely at least one driving circuit unit group is selected from the N sequentially cascaded driving circuit unit groups.

Step S104: the input of the first signal to the drive circuit is stopped, and the second signal and the second shift start signal are input to the selected drive circuit cell group.

The driving circuit receives the second signal, and the selected start signal selection circuit in the partition receives the second shift start signal, so that the driving circuit units in the driving circuit unit group in the partition sequentially output driving signals through the second scanning signal output end respectively, and region driving is realized.

Fig. 16 is a schematic view of a display device according to an embodiment of the present invention, where the display device includes any one of the display panels provided in the present invention, and has features and corresponding technical effects, which are not described herein again.

As can be seen from the above embodiments, the display panel, the driving circuit, the driving method and the display device of the present invention have the following advantages:

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A driving circuit of a display panel is characterized in that,

the driving circuit comprises N driving circuit unit groups and N starting signal selection circuits which are sequentially cascaded, wherein N is a natural number greater than 1;

the x-th-stage drive circuit unit group comprises M drive circuit units which are sequentially cascaded, wherein the x-th-stage drive circuit unit group is any one stage of drive circuit unit group in the drive circuit, M is a natural number which is greater than or equal to 1, and the number of the drive circuit units in the drive circuit unit groups of different stages is the same or different;

the driving circuit unit comprises a scanning signal input end, a control signal input end, a first scanning signal output end, a second scanning signal output end and a shifting signal output end, wherein the shifting signal output end outputs a shifting signal, the first scanning signal output end outputs a first scanning signal, the second scanning signal output end outputs a second scanning signal, the control signal input end receives a first signal at a first time and receives a second signal at a second time, the first signal is an enable signal of the first scanning signal output end, the second signal is an enable signal of the second scanning signal output end, the first scanning signal is used for display scanning, and the second scanning signal is used for fingerprint identification scanning;

the start signal selection circuit comprises a first start signal input end, a second start signal input end and a start signal output end, wherein the start signal output end is conducted with the first start signal input end at the first time, and the start signal output end is conducted with the second start signal input end at the second time;

in the xth-stage driving circuit unit group, a scanning signal input end of the 1 st-stage driving circuit unit is connected with a starting signal output end of an xth-stage starting signal selection circuit, from the 2 nd-stage driving circuit unit to the mth-stage driving circuit unit, the scanning signal input end is respectively connected with a shifting signal output end of the previous-stage driving circuit unit, and a shifting signal output end of the mth-stage driving circuit unit is connected with a first starting signal input end of the (x + 1) th-stage starting signal selection circuit; and

the first start signal input end of the 1 st stage start signal selection circuit receives a first shift start signal at the first time, and the second start signal input end of at least one start signal selection circuit in each stage of start signal selection circuits receives a second shift start signal at the second time.

2. The driving circuit of the display panel according to claim 1, wherein the driving circuit unit further comprises a first clock signal input terminal, a second clock signal input terminal, a first shift register, and a first control circuit, wherein,

the first shift register includes:

the clock signal input end of the latch is connected with the first clock signal input end, the input end of the latch is connected with the scanning signal input end, and the output end of the latch is connected with the shifting signal output end;

a first input end of the first NAND gate is connected with the output end of the latch, and a second input end of the first NAND gate is connected with the second clock signal input end;

the input end of the first buffer is connected with the output end of the first NAND gate, and the output end of the first buffer is connected with the first scanning signal output end;

a first input end of the second NAND gate is connected with the output end of the latch, and a second input end of the second NAND gate is connected with the second clock signal input end;

the input end of the second buffer is connected with the output end of the second NAND gate, and the output end of the second buffer is connected with the output end of the second scanning signal;

the first control circuit is connected to the control signal input terminal, the first nand gate and the second nand gate, respectively, wherein the first control circuit controls the output terminal of the second nand gate to continuously output the inactive level signal when the control signal input terminal receives the first signal, and controls the output terminal of the first nand gate to continuously output the inactive level signal when the control signal input terminal receives the second signal.

3. The display panel driving circuit according to claim 2,

the control signal input end comprises a first control signal input end and a second control signal input end, the first signal is that the first control signal input end receives a high level signal, the second control signal input end receives a low level signal, the second signal is that the first control signal input end receives a low level signal, and the second control signal input end receives a high level signal;

the first NAND gate and the second NAND gate respectively comprise two N-type transistors connected in series and two P-type transistors connected in parallel, wherein in the first NAND gate and the second NAND gate, the first ends of the two N-type transistors connected in series after being connected in series are connected with the first control circuit, the first ends of the two P-type transistors connected in parallel after being connected in parallel are connected with a positive voltage, and the second ends of the two N-type transistors connected in series after being connected in series are connected with the second ends of the two P-type transistors connected in parallel after being connected in parallel;

the first control circuit includes:

the control end of the first P-type transistor is connected with the first control signal input end, the first connecting end of the first P-type transistor is connected with a positive voltage, and the second connecting end of the first P-type transistor is connected with the output end of the first NAND gate;

the control end of the first N-type transistor is connected with the first control signal input end, the first connecting end of the first N-type transistor is connected with a negative voltage, and the second connecting end of the first N-type transistor is connected with the first end of the first NAND gate after two serially connected N-type transistors are serially connected;

the control end of the second P-type transistor is connected with the second control signal input end, the first connecting end of the second P-type transistor is connected with a positive voltage, and the second connecting end of the second P-type transistor is connected with the output end of the second NAND gate;

and the control end of the second N-type transistor is connected with the second control signal input end, the first connecting end of the second N-type transistor is connected with the negative voltage, and the second connecting end of the second N-type transistor is connected with the first end of the second NAND gate after the two serially connected N-type transistors are serially connected.

4. The driving circuit of the display panel according to claim 3, wherein the start signal selection circuit further comprises:

the first branch circuit comprises a third P-type transistor and a third N-type transistor which are connected in parallel, the control end of the third P-type transistor is connected with the second control signal input end, the control end of the third N-type transistor is connected with the first control signal input end, the first ends of the two third P-type transistors and the third N-type transistors which are connected in parallel are connected with the first start signal input end, and the second ends of the two third P-type transistors and the third N-type transistors which are connected in parallel are connected with the start signal output end;

and the first end of the second branch is connected with the second initial signal input end, and the second end of the second branch is connected with the initial signal output end.

5. The driving circuit of the display panel according to claim 1, wherein the driving circuit unit further comprises a first clock signal input terminal, a second shift register, and a second control circuit, wherein,

the second shift register includes:

the output end of the output unit is connected with the shift signal output end, and the output unit comprises a first node and a second node;

the pull-down unit is connected with the scanning signal input end, the first clock signal input end, the second clock signal input end and the second node and is used for controlling the potential of the second node according to signals received by the scanning signal input end, the first clock signal input end and the second clock signal input end;

the pull-up unit is connected with the first clock signal input end, the first node and the second node and is used for controlling the potential of the first node according to the signal received by the first clock signal input end and the potential of the second node;

the second control circuit is connected with the control signal input end, the first scanning signal output end and the second scanning signal output end respectively, wherein the second control circuit controls the output end of the output unit to be communicated with the first scanning signal output end when the control signal input end receives the first signal, and controls the output end of the output unit to be communicated with the second scanning signal output end when the control signal input end receives the second signal.

6. The driving circuit of the display panel according to claim 5, wherein the second control circuit comprises:

a control end of the fourth N-type transistor is connected with the control signal input end, a first connection end of the fourth N-type transistor is connected with the output end of the output unit, and a second connection end of the fourth N-type transistor is connected with the first scanning signal output end; and

and the control end of the fourth P-type transistor is connected with the control signal input end, the first connecting end of the fourth P-type transistor is connected with the output end of the output unit, and the second connecting end of the fourth P-type transistor is connected with the second scanning signal output end.

7. The driving circuit of the display panel according to claim 6, wherein the start signal selection circuit further comprises:

a control end of the fifth N-type transistor is connected with the control signal input end, a first connection end of the fifth N-type transistor is connected with the first starting signal input end, and a second connection end of the fifth N-type transistor is connected with the starting signal output end; and

and the control end of the fifth P-type transistor is connected with the control signal input end, the first connecting end of the fifth P-type transistor is connected with the second starting signal input end, and the second connecting end of the fifth P-type transistor is connected with the starting signal output end.

8. A display panel, comprising:

a drive circuit of the display panel according to any one of claims 1 to 7;

a display pixel;

one end of the scanning signal line is connected with the display pixel, and the other end of the scanning signal line is connected with a first scanning signal output end of the driving circuit;

a fingerprint identification element, one end of which is connected with the chip for fingerprint identification and the other end is connected with the second scanning signal output end of the driving circuit,

and at the first time, the first scanning signal output end outputs a scanning signal to control the display pixels to display gray scales, and at the second time, the second scanning signal output end outputs a driving signal to control the fingerprint identification element to carry out fingerprint identification.

9. A display device characterized by comprising the display panel according to claim 8.

10. A driving method of a display panel including the driving circuit according to any one of claims 1 to 7, the driving method comprising:

inputting a first signal and a first shift start signal to the driving circuit, and detecting whether the display panel is touched;

determining a position where the display panel is touched when it is detected that the display panel is touched;

selecting at least one driving circuit unit group from N sequentially cascaded driving circuit unit groups of the driving circuit according to the determined touched position;

and stopping inputting the first signal to the driving circuit, and inputting a second signal and a second shift start signal to the selected driving circuit cell group.