CN108390675A - A kind of XOR gate phase discriminator - Google Patents
A kind of XOR gate phase discriminator Download PDFInfo
- Publication number
- CN108390675A CN108390675A CN201810461029.8A CN201810461029A CN108390675A CN 108390675 A CN108390675 A CN 108390675A CN 201810461029 A CN201810461029 A CN 201810461029A CN 108390675 A CN108390675 A CN 108390675A
- Authority
- CN
- China
- Prior art keywords
- resistance
- input
- nmos tube
- input pipe
- phase discriminator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005611 electricity Effects 0.000 claims description 11
- 230000007423 decrease Effects 0.000 abstract description 4
- 238000001514 detection method Methods 0.000 abstract 1
- 230000005540 biological transmission Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a kind of XOR gate phase discriminators, usually a loop is constituted with digital module to use, including four input current mode logic XOR gate phase discriminators and assembly line comparator, assembly line comparator includes first resistor potential-divider network, second resistance potential-divider network and multiple comparators.Four input current mode logic XOR gate phase discriminators indicate the phase difference between input signal by the raising and decline of two output voltages, and not only phase demodulation speed is fast, but also phase demodulation resolution ratio is twice of traditional XOR gate phase discriminator；The output voltage of phase discriminator is directly inputted to resistance pressure-dividing network, simple in structure compared with existing capacitance switch formula potential-divider network, and load is relatively low, and power consumption is smaller；Output state word after phase-detection is sent to digital circuit by assembly line comparator.
Description
Technical field
The present invention relates to integrated circuit fields, and in particular to a kind of phase discriminator with assembly line comparator is arrived, for detecting
Phase difference between input signal.
Background technology
Digital analog converter (Digital to Analog Converter, abbreviation DAC) is exactly to convert digital signals into mould
Quasi- signal, most importantly correct transmission of the data per level-one in the research of the circuit, in order to ensure the correct transmission of data,
The key points and difficulties of design are the sequence problem between its numeric field clock and analog domain clock, if sampling location it is undesirable or
Mistake occurs, the performance of DAC will be directly influenced.Therefore design it is a kind of quickly, low-power consumption, high resolution phase discriminator can pole
The big correctness and reliability for improving data sampling.
Invention content
Goal of the invention：It is of the existing technology in order to solve the problems, such as, it improves phase demodulation speed and phase demodulation resolution ratio, the present invention carries
For a kind of XOR gate phase discriminator.
Technical solution：A kind of XOR gate phase discriminator, including four input XOR gate phase discriminators and assembly line comparator, described four
The input terminal for inputting XOR gate phase discriminator connects two pairs of differential signals, a pair of of phase discriminator output voltage of output end output；The stream
Watermark comparer includes first resistor potential-divider network, second resistance potential-divider network and multiple comparators, first resistor potential-divider network
It is symmetrical with second resistance potential-divider network, include two NMOS tubes and multiple resistance, multiple resistance be connected on two NMOS tubes it
Between, the number of resistance is equal with comparator number in resistance pressure-dividing network；A pair of of phase discriminator output voltage is separately connected the first electricity
The input terminal of potential-divider network, second resistance potential-divider network is hindered, first resistor potential-divider network, second resistance potential-divider network are through each resistance
Multiple output voltages are obtained after partial pressure；The reverse phase of the multiple output voltages and multiple comparators of first resistor potential-divider network is defeated
Enter end connection, multiple output voltages of second resistance potential-divider network is connect with the in-phase input end of multiple comparators, multiple ratios
Compared with the output end output state word of device.
Preferably, four input XOR gate phase discriminators include six NMOS input pipes and two resistance, six NMOS input pipes
Including input pipe M0, input pipe M1, input pipe M2, input pipe M3, input pipe M4, input pipe M5, two resistance are resistance R1, electricity
Hinder R2；The grid of input pipe M0 accesses input signal clkp, the grid and input pipe of input pipe M1 with the grid of input pipe M3
The grid of M2 meets input signal clkn, and the grid of input pipe M4 meets input signal d, and the grid of input pipe M5 meets input signal db,
Resistance R1 mono- terminates supply voltage, and the other end is connected with the drain electrode of input pipe M0, input pipe M2, and the node voltage that three ends are connected
As phase discriminator output voltage voutn, mono- section of resistance R2 connects supply voltage, the drain electrode of the other end and input pipe M1, input pipe M3
It is connected, and the node voltage that three ends are connected is as phase discriminator output voltage voutp, input pipe M0, input pipe M1 source electrodes and input
Pipe M4 drain electrodes are connected, and input pipe M2, input pipe M3 source electrodes are connected with input pipe M5 drain electrodes, and input pipe M4 and input pipe M5 source electrodes are equal
Ground connection；Input signal clkp and clkn is a pair of of differential signal, and input signal d and db is a pair of of differential signal；Phase discriminator exports
Voltage voutn and phase discriminator output voltage voutp is a pair of of phase discriminator output voltage.
Preferably, first resistor potential-divider network includes NMOS tube M6, NMOS tube M8, resistance Rn1, resistance Rn2 ... resistance
Rnt；Second resistance potential-divider network includes NMOS tube M7, NMOS tube M9, resistance Rp1, resistance Rp2 ... resistance Rpt；Wherein t is
The number of comparator；The drain electrode of NMOS tube M6 and NMOS tube M7 connect supply voltage, and grid and the phase discriminator of NMOS tube M6 export
Voltage voutn is connected, and the grid of NMOS tube M7 is connected with phase discriminator output voltage voutp, NMOS tube M8 and NMOS tube M9
Grid access biasing circuit, be sequentially connected resistance Rn1, resistance Rn2 ... resistance Rnt to NMOS from the source level of NMOS tube M6
The drain electrode of pipe M8, t are the number of resistance in every group of resistance pressure-dividing network, voltage is divided into Vn0, Vn1 by t resistance ... Vnt；From
The source level of NMOS tube M7 is sequentially connected the drain electrode of resistance Rp1, resistance Rp2 ... resistance Rpt to NMOS tube M9, and t resistance will be electric
Press and be divided into Vp0, Vp1 ... Vpt；The inverting input of the comparator accesses voltage Vn, the corresponding electricity of in-phase input end access
Press Vp.
Preferably, the output end output state word of multiple comparators is connected with following digital circuit.
Preferably, the pipe breadth length ratio of NMOS tube M6 and NMOS tube M7 is equal；The pipe of NMOS tube M8 and NMOS tube M9 are wide
Length is than equal.
Preferably, every group of resistance pressure-dividing network includes 16 resistance, and comparator also has 16.
Advantageous effect：A kind of XOR gate phase discriminator provided by the invention, four inputs constituted using current mode logic structure
XOR gate phase discriminator, not only phase demodulation speed is fast, and its phase demodulation resolution ratio is twice of traditional XOR gate phase discriminator, phase discriminator output
Voltage is directly inputted to resistance pressure-dividing network, compared with existing capacitance switch formula resistance pressure-dividing network, the knot of the design circuit
Structure is simple, and load is relatively low, and power consumption is also smaller, has a good application prospect.
Description of the drawings
Fig. 1 is the XOR gate phase detector circuit schematic diagram that four input current mode logic structures of the invention are constituted；
Fig. 2 is the assembly line comparator configuration schematic diagram that resistance pressure-dividing network of the present invention is constituted with comparator.
Specific implementation mode
The invention will be further described in the following with reference to the drawings and specific embodiments.
A kind of XOR gate phase discriminator, including four input XOR gate phase discriminators and assembly line comparator, the four inputs exclusive or
The input terminal of door phase discriminator connects two pairs of differential signals, a pair of of phase discriminator output voltage of output end output.As shown in Figure 1, four is defeated
It includes six NMOS input pipes and two resistance to enter XOR gate phase discriminator, and six NMOS input pipes include input pipe M0, input pipe
M1, input pipe M2, input pipe M3, input pipe M4, input pipe M5, two resistance are resistance R1, resistance R2；The grid of input pipe M0
Input signal clkp is accessed with the grid of input pipe M3, the grid of input pipe M1 connects input signal with the grid of input pipe M2
The grid of clkn, input pipe M4 meet input signal d, and the grid of input pipe M5 connects input signal db, resistance R1 mono- termination power electricity
Pressure, the other end are connected with the drain electrode of input pipe M0, input pipe M2, and the node voltage that three ends are connected is as phase discriminator output voltage
Mono- section of voutn, resistance R2 connects supply voltage, and the other end is connected with the drain electrode of input pipe M1, input pipe M3, and the section that three ends are connected
Point voltage is connected as phase discriminator output voltage voutp, input pipe M0, input pipe M1 source electrodes with input pipe M4 drain electrodes, input pipe
M2, input pipe M3 source electrodes are connected with input pipe M5 drain electrodes, input pipe M4 and input pipe M5 source groundings；Input signal clkp with
Clkn is a pair of of differential signal, and input signal d and db is a pair of of differential signal；Phase discriminator output voltage voutn and phase discriminator are defeated
It is a pair of of phase discriminator output voltage to go out voltage voutp.
If input signal d is high level in preceding half period, left one side of something circuit is started to work, if clkp is height at this time,
Clkn is low, then output voltage voutn is begun to decline, and voutp starts to increase, the stationary value after voltage decline, raising and input
The size of phase difference is related between signal, and when input signal d jumps to low level, db jumps to high level, then the right side half
Side circuit is started to work, if clkp is height at this time, clkn is low, then output voltage voutp is begun to decline, and voutn starts to increase,
Voltage declines, the size of phase difference is related between stationary value and input signal after raising.
The assembly line comparator includes first resistor potential-divider network, second resistance potential-divider network and 16 comparators.Such as
Shown in Fig. 2, first resistor potential-divider network and second resistance potential-divider network are symmetrical, include two NMOS tubes and 16 resistance, 16
A resistance is connected between two NMOS tubes, and the number of resistance is equal with comparator number in resistance pressure-dividing network；A pair of of phase demodulation
Device output voltage is separately connected the input terminal of first resistor potential-divider network, second resistance potential-divider network, first resistor potential-divider network,
Second resistance potential-divider network obtains 16 output voltages after each electric resistance partial pressure；By 16 outputs of first resistor potential-divider network
Voltage is connect with the inverting input of 16 comparators, by 16 output voltages and 16 comparators of second resistance potential-divider network
In-phase input end connection, the output end output state word of 16 comparators, output state word is connected with following digital circuit.
As shown in Fig. 2, first resistor potential-divider network includes NMOS tube M6, NMOS tube M8, resistance Rn1, resistance Rn2 ... electricity
Hinder Rn16；Second resistance potential-divider network includes NMOS tube M7, NMOS tube M9, resistance Rp1, resistance Rp2 ... resistance Rp16；NMOS
The drain electrode of pipe M6 and NMOS tube M7 connect supply voltage, and the grid of NMOS tube M6 is connected with phase discriminator output voltage voutn,
The grid of NMOS tube M7 is connected with phase discriminator output voltage voutp, and the grid of NMOS tube M8 and NMOS tube M9 access biasing
Circuit vbias constitutes constant-current source.It is sequentially connected resistance Rn1, resistance Rn2 ... resistance Rn16 extremely from the source level of NMOS tube M6
Voltage is divided into Vn0, Vn1 by the drain electrode of NMOS tube M8,16 resistance ... Vn15；It is sequentially connected resistance from the source level of NMOS tube M7
Voltage is divided into Vp0, Vp1 by the drain electrode of Rp1, resistance Rp2 ... resistance Rp16 to NMOS tube M9,16 resistance ... Vp16；Institute
The inverting input access voltage Vn of comparator is stated, in-phase input end accesses corresponding voltage Vp.Wherein, corresponding relation refers to first
The anti-phase input of comparator terminates voltage Vn0, and in-phase input end accesses corresponding voltage Vp0；The anti-phase input of first comparator
Termination voltage Vn1, in-phase input end access corresponding voltage Vp1 ...
The pipe breadth length ratio of NMOS tube M6 and NMOS tube M7 is equal；The pipe breadth length ratio phase of NMOS tube M8 and NMOS tube M9
Deng.Connect 16 divider resistances between M7 source electrodes and M9 drain electrodes, so the electric current for flowing through this 16 resistance is equal, due to M8 and
M9 pipe breadth length ratios are equal, so the electric current that the two constant-current sources provide is equal, and since M6 is equal with M7 pipe breadth length ratios, institute
With when input voltage voutn is equal with voutp voltages, by resistor voltage divider circuit it is found that output voltage Vn0~Vn15 and output
Voltage Vp15~Vp0 distinguishes correspondent equal, and since Vp8 is equal to Vn7, and Vn7 is more than Vn8, it can thus be appreciated that Vp15~Vp8 is exhausted
To being more than Vn15~Vn8, Vp7~Vp0 is absolutely less than Vn7~Vn0, then after 16 comparators, output state word q15~q8
For 8 high level, q7~q0 is 8 low levels.When input voltage voutn and voutp change, output state word q15
The number of low and high level will change in~q0, and the input voltage voutn and voutp of assembly line comparator is defeated by phase discriminator
Go out voltage offer, phase difference size changes phase discriminator output voltage voutn, voutp follow input signal again between, finally
The size of phase difference between input signal is transformed into assembly line comparator output state word, digital circuit is defeated by detecting 16
The number of word low and high level of doing well judges the phase difference between input signal, with this completes phase discrimination function.
Why the use of the number of resistance in the number of comparator and every group of resistance pressure-dividing network is in the present embodiment 16,
It is that phase is divided equally into 16 equal portions in 180 degree, the phase difference defined between input signal is 0~16 equal portions, when phase difference is
When 16 equal portions, the rising edge for defining input signal is mutually aligned, during actual use can also select other numbers as needed
Mesh, but the number of comparator and resistance in every group of resistance pressure-dividing network need to be consistent.Table 1 illustrates input signal in different phases
When potential difference, low and high level number in assembly line comparator output state word q15~q0, Pd indicates the equal numbers of phase difference.
Table 1
Claims (6)
1. a kind of XOR gate phase discriminator, which is characterized in that including four input XOR gate phase discriminators and assembly line comparators, described four
The input terminal for inputting XOR gate phase discriminator connects two pairs of differential signals, a pair of of phase discriminator output voltage of output end output；The stream
Watermark comparer includes first resistor potential-divider network, second resistance potential-divider network and multiple comparators, first resistor potential-divider network
It is symmetrical with second resistance potential-divider network, include two NMOS tubes and multiple resistance, multiple resistance be connected on two NMOS tubes it
Between, the number of resistance is equal with comparator number in resistance pressure-dividing network；A pair of of phase discriminator output voltage is separately connected the first electricity
The input terminal of potential-divider network, second resistance potential-divider network is hindered, first resistor potential-divider network, second resistance potential-divider network are through each resistance
Multiple output voltages are obtained after partial pressure；The reverse phase of the multiple output voltages and multiple comparators of first resistor potential-divider network is defeated
Enter end connection, multiple output voltages of second resistance potential-divider network is connect with the in-phase input end of multiple comparators, multiple ratios
Compared with the output end output state word of device.
2. XOR gate phase discriminator according to claim 1, which is characterized in that four input XOR gate phase discriminators include six
NMOS input pipes and two resistance, six NMOS input pipes include input pipe M0, input pipe M1, input pipe M2, input pipe M3, defeated
Enter pipe M4, input pipe M5, two resistance are resistance R1, resistance R2；The grid of input pipe M0 and the grid of input pipe M3 access
The grid of input signal clkp, input pipe M1 and the grid of input pipe M2 meet input signal clkn, and the grid of input pipe M4 connects defeated
Enter signal d, the grid of input pipe M5 meets input signal db, and resistance R1 mono- terminates supply voltage, the other end and input pipe M0, input
The drain electrode of pipe M2 is connected, and the node voltage that three ends are connected connects power supply electricity as phase discriminator output voltage voutn, mono- section of resistance R2
Pressure, the other end are connected with the drain electrode of input pipe M1, input pipe M3, and the node voltage that three ends are connected is as phase discriminator output voltage
Voutp, input pipe M0, input pipe M1 source electrodes are connected with input pipe M4 drain electrodes, input pipe M2, input pipe M3 source electrodes and input pipe M5
Drain electrode is connected, input pipe M4 and input pipe M5 source groundings；Input signal clkp and clkn is a pair of of differential signal, input letter
Number d and db is a pair of of differential signal；Phase discriminator output voltage voutn and phase discriminator output voltage voutp is that a pair of of phase discriminator is defeated
Go out voltage.
3. XOR gate phase discriminator according to claim 2, which is characterized in that first resistor potential-divider network includes NMOS tube
M6, NMOS tube M8, resistance Rn1, resistance Rn2 ... resistance Rnt；Second resistance potential-divider network include NMOS tube M7, NMOS tube M9,
Resistance Rp1, resistance Rp2 ... resistance Rpt；Wherein t is the number of comparator；The drain electrode of NMOS tube M6 and NMOS tube M7 connect electricity
The grid of source voltage, NMOS tube M6 is connected with phase discriminator output voltage voutn, grid and the phase discriminator output electricity of NMOS tube M7
Pressure voutp is connected, and the grid of NMOS tube M8 and NMOS tube M9 access biasing circuit, are sequentially connected from the source level of NMOS tube M6
The drain electrode of resistance Rn1, resistance Rn2 ... resistance Rnt to NMOS tube M8, t are the number of resistance in every group of resistance pressure-dividing network, t
Voltage is divided into Vn0, Vn1 by a resistance ... Vnt；It is sequentially connected resistance Rp1, resistance Rp2 ... electricity from the source level of NMOS tube M7
The Vpt that hinders the drain electrode of Rpt to NMOS tube M9, voltage is divided into Vp0, Vp1 by t resistance ...；The inverting input of the comparator
Voltage Vn is accessed, in-phase input end accesses corresponding voltage Vp.
4. XOR gate phase discriminator according to claim 1, which is characterized in that the output end output state word of multiple comparators
It is connected with following digital circuit.
5. XOR gate phase discriminator according to claim 3, which is characterized in that the wide length of the pipe of NMOS tube M6 and NMOS tube M7
Than equal；The pipe breadth length ratio of NMOS tube M8 and NMOS tube M9 is equal.
6. XOR gate phase discriminator according to claim 3, which is characterized in that every group of resistance pressure-dividing network includes 16 electricity
Resistance, comparator also have 16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810461029.8A CN108390675B (en) | 2018-05-15 | 2018-05-15 | Phase discriminator of exclusive-or gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810461029.8A CN108390675B (en) | 2018-05-15 | 2018-05-15 | Phase discriminator of exclusive-or gate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108390675A true CN108390675A (en) | 2018-08-10 |
| CN108390675B CN108390675B (en) | 2024-02-02 |
Family
ID=63071825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810461029.8A Active CN108390675B (en) | 2018-05-15 | 2018-05-15 | Phase discriminator of exclusive-or gate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108390675B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281060A (en) * | 2011-04-02 | 2011-12-14 | 长沙景嘉微电子有限公司 | Phase discriminator circuit applied to clock data recovery |
| CN102347765A (en) * | 2010-07-26 | 2012-02-08 | 中兴通讯股份有限公司 | Clock and data recovery system, phase adjustment method and phase discriminator |
| CN102931981A (en) * | 2012-11-13 | 2013-02-13 | 苏州磐启微电子有限公司 | Ultra-low power consumption phase locked loop circuit |
| CN106849939A (en) * | 2017-01-24 | 2017-06-13 | 四川和芯微电子股份有限公司 | CMOS phase discriminators |
| CN208272955U (en) * | 2018-05-15 | 2018-12-21 | 南京德睿智芯电子科技有限公司 | A kind of XOR gate phase discriminator |
-
2018
- 2018-05-15 CN CN201810461029.8A patent/CN108390675B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347765A (en) * | 2010-07-26 | 2012-02-08 | 中兴通讯股份有限公司 | Clock and data recovery system, phase adjustment method and phase discriminator |
| CN102281060A (en) * | 2011-04-02 | 2011-12-14 | 长沙景嘉微电子有限公司 | Phase discriminator circuit applied to clock data recovery |
| CN102931981A (en) * | 2012-11-13 | 2013-02-13 | 苏州磐启微电子有限公司 | Ultra-low power consumption phase locked loop circuit |
| CN106849939A (en) * | 2017-01-24 | 2017-06-13 | 四川和芯微电子股份有限公司 | CMOS phase discriminators |
| CN208272955U (en) * | 2018-05-15 | 2018-12-21 | 南京德睿智芯电子科技有限公司 | A kind of XOR gate phase discriminator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108390675B (en) | 2024-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI622283B (en) | A clock and data recovery circuit and a phase interpolator therefor | |
| CN104113342B (en) | High-speed data synchronous circuit used for high-speed digital-to-analog converter | |
| CN106982182A (en) | A kind of high-speed adaptive DFF | |
| KR100799683B1 (en) | Cascaded folding and interpolating analog-to-digital converter | |
| EP3567720A1 (en) | Mismatch and reference common-mode offset insensitive single-ended switched capacitor gain stage | |
| CN208272955U (en) | A kind of XOR gate phase discriminator | |
| CN106603070A (en) | Phase-locked loop low in stray and quick in locking | |
| CN108390675A (en) | A kind of XOR gate phase discriminator | |
| CN207706157U (en) | Circuit occurs for four phases, 25% duty cycle clock for sampling holder | |
| CN206259921U (en) | A kind of quick response dynamic latch comparator | |
| Shi et al. | Hardware‐efficient slope‐error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver | |
| TWI736223B (en) | Digital slope analog to digital converter device and signal conversion method | |
| WO2011090155A1 (en) | A/d converter circuit | |
| CN110235372A (en) | A kind of Double Data Rate temporal interpolation quantizer with reduction kickback noise | |
| CN105991138B (en) | Asynchronous successive approximation modulus conversion circuit | |
| TW201419766A (en) | Successive approximation analog-to-digital converter | |
| CN104113337B (en) | A kind of production line analog-digital converter | |
| CN100410862C (en) | Resistance touch screen measuring system | |
| US20040130468A1 (en) | Differential sampling circuit for generating a differential input signal DC offset | |
| CN111929522B (en) | State detection circuit and control detection method | |
| CN102611451B (en) | Distributed sampling holding circuit of rail-to-rail input range | |
| Verbeke et al. | Inverse Alexander phase detector | |
| CN100539427C (en) | Circulation flow line type analog digital converter | |
| CN101594148B (en) | Flash ADC with current inserted structure | |
| US5987038A (en) | Sync detect circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |