CN108389800A - The manufacturing method of shield grid trench FET - Google Patents

The manufacturing method of shield grid trench FET Download PDF

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Publication number
CN108389800A
CN108389800A CN201810094738.7A CN201810094738A CN108389800A CN 108389800 A CN108389800 A CN 108389800A CN 201810094738 A CN201810094738 A CN 201810094738A CN 108389800 A CN108389800 A CN 108389800A
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China
Prior art keywords
layer
epitaxial layer
manufacturing
trench
screen oxide
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CN201810094738.7A
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Inventor
余强
焦伟
姚鑫
桑雨果
骆菲
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China Resources Microelectronics Chongqing Ltd
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China Resources Microelectronics Chongqing Ltd
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Priority to CN201810094738.7A priority Critical patent/CN108389800A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

The present invention provides a kind of manufacturing method of shield grid trench FET, and high-density plasma is used when manufacturing the isolating oxide layer of shield grid trench FET（HDP）, and wet etching treatment is carried out before depositing the layer, utilize high-density plasma（HDP）The deposit feature of layer, makes its filling have peculiar pattern：Middle flat in groove, groove both sides are in spike, the planarization process before the etching then to discard tradition, such as chemically-mechanicapolish polish（CMP）Ended, but direct wet etching treatment, obtain the target depth of isolating oxide layer in the removal and groove of isolating layer on top simultaneously, reach the process goal effect essentially identical with common process, process costs and process time are greatly reduced, is with a wide range of applications in semiconductor device design and manufacturing field.

Description

The manufacturing method of shield grid trench FET
Technical field
The invention belongs to semiconductor device design and manufacturing fields, more particularly to a kind of shield grid trench field-effect crystal The manufacturing method of pipe.
Background technology
Shield grid groove MOSFET is current state-of-the-art power MOSFET device technology, can be achieved at the same time low electric conduction (Rdson) and low Reverse recovery capacitance (Crss) are hindered, to reduce the conduction loss and switching loss of system simultaneously, is improved System service efficiency.
As shown in Figure 1, by taking N-type device as an example, the cellular construction of existing common shielding gate groove (SGT) MOSFET includes：
N is lightly doped-Type epitaxial layer 104 is formed in heavy doping N++On type silicon substrate 102, metal-drain 100 is formed in weight Adulterate N++Under type silicon substrate 102；
Deep trench 106, which is formed in, is lightly doped N-In type epitaxial layer 104,106 side wall of groove is with screen oxide 108, ditch Filled with shielding polysilicon 110 and grid polycrystalline silicon 116 in slot 106；Have between shielding polysilicon 110 and grid polycrystalline silicon 116 Oxide layer 112 is isolated；
The areas PXing Ti 118, which are formed in, is lightly doped N-104 surface of type epitaxial layer, source region 120 are formed in the areas PXing Ti 118；It connects Contact hole 124 passes through oxide isolation floor 122 and source region 120 to enter the areas PXing Ti 118；Metal source 130 is arranged in 124 He of contact hole On oxide isolation layer 122；
Grid polycrystalline silicon 116 draws (not shown) by laying out pattern in 106 end of groove, and shielding polysilicon 110 passes through Laying out pattern makes it be connected with source electrode 120, and source electrode 120 and the areas PXing Ti 118 are drawn jointly by metal source 130.
As shown in Fig. 2 a to Fig. 2 h, by taking N-type device as an example, the manufacturing method of existing common shield grid groove MOSFET is main Step includes：
As shown in Figure 2 a, in 102 growing epitaxial layers 104 of silicon substrate, groove 106 is formed in the epitaxial layer 104； 106 sidewall growth screen oxide 108 of the groove is subsequently filled shielding polysilicon 110；
As shown in Figure 2 b, surface screen oxide 108 and shielding polysilicon 110 is thinned to target thickness；
As shown in Figure 2 c, one layer of silicon nitride (SIN) 111 is deposited in crystal column surface；By photoetching on shielding polysilicon 110 It is rectangular at a window, then dry etching falls silicon nitride in window；
As shown in Figure 2 d, dry etching or wet etching will shield polysilicon 110 and screen oxide 108 returns quarter etching To target depth；
As shown in Figure 2 e, high-density plasma (HDP) oxide layer is deposited, to form Isolated Shield polysilicon 110 and grid The isolating oxide layer 112 of pole polysilicon 116；
As shown in figure 2f, chemically mechanical polishing (CMP) crystal column surface isolating oxide layer terminates in silicon nitride layer (SIN) 111；
As shown in Figure 2 g, surfaces nitrided silicon layer (SIN) 111 is removed, returns and carves etching isolating oxide layer 112 to first object depth Degree；
As shown in fig. 2h, gate oxide 114 is grown, and grid polycrystalline silicon 116, which is deposited and returned, is etched to slightly less than silicon face About 1000 angstroms to 3000 angstroms；Positive ion implanting p type impurity, to form the areas PXing Ti (P-Body) 118；Positive ion implanting N-type Impurity, to form source electrode (Source) 120；The deposit of spacer medium layer (ILD) 122, the etching of contact hole (Contact) 124, source electrode Metal layer 130 deposits back quarter, passivation layer deposit (not shown), the deposit of drain metal layer 100 etc..
Existing method is to obtain the target depth of isolating oxide layer, as shown in Figure 2 c, needs to deposit cutoff layer (stop- Layer) silicon nitride (SIN) 111, and need to return in the layer and carve window, it is needed again using chemically mechanical polishing in step 6) (CMP) technology, and the technique is required to terminate on cutoff layer (stop-layer) silicon nitride (SIN) 111, it is follow-up to need to remove this again Stop-layer, complex process and requirement strictly, cause manufacturing cost higher.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of shield grid trench field-effect crystalline substances The manufacturing method of body pipe, for solving the problems, such as that the manufacturing cost of shield grid trench FET in the prior art is excessively high.
In order to achieve the above objects and other related objects, the present invention provides a kind of system of shield grid trench FET Make method, including step：1) substrate is provided, epitaxial layer is formed in the upper surface of the substrate, is formed in the epitaxial layer Deep trench forms screen oxide in inner wall and the epi-layer surface of the deep trench, shields in being filled in the deep trench Polysilicon is covered, the shielding polysilicon also covers the screen oxide above the epitaxial layer；2) it is thinned described outer Prolong the shielding polysilicon and the screen oxide above layer, the screen oxide is remained with above the epitaxial layer； 3) it is returned as mask using the screen oxide and etches the shielding polysilicon, to form an etching groove, the etching groove both sides Appear the screen oxide in the deep trench；4) screen oxide of etching groove both sides described in wet etching, together When make it is described shielding polysilicon upper section protrude from the screen oxide；5) isolating oxide layer, the isolation are deposited Oxide layer includes the filling part being filled in the deep trench and the lug boss being covered in above the epitaxial layer；6) wet method is carved It loses back and carves the isolating oxide layer, the lug boss is removed while the filling part is etched to target thickness and positioned at described The screen oxide on epitaxial layer；7) gate oxidation is deposited in the inner wall of the deep trench and the isolation oxidation layer surface Layer fills grid polycrystalline silicon to form grid to form gate trench in the gate trench；And 8) in the deep trench Body area is formed in the epitaxial layer of both sides, source electrode is formed in the body area, and upper metal knot is formed above the epitaxial layer Structure forms drain metal layer in the substrate lower surface.
Preferably, in the step 4) wet etching, the shielding oxygen of the upper section both sides of the shielding polysilicon Change interlayer to be partially removed to be respectively formed side grooves, after the wet etching, the etching groove both sides and the epitaxial layer Surface remains with the certain thickness screen oxide.
Further, the side grooves include curved bottom.
Further, in step 5), the isolating oxide layer is formed using high-density plasma deposition process, it is described every Include to fill out and the lug boss of needle pattern described in flat condition from oxide layer, so that in step 6), by the filling part The lug boss and the screen oxide on the epitaxial layer are completely removed while being etched to target thickness.
Preferably, in step 1), the thickness of the screen oxide is not less than 1000 angstroms.
Preferably, the bottom in the body area is not less than the bottom of the gate trench.
Preferably, the substrate, the epitaxial layer, the source electrode are adulterated with the first conductive type ion, the body area It is adulterated with the second conductive type ion, first conduction type conductive-type opposite each other with second conduction type Type.
Further, the substrate includes N++ type substrates, and the epitaxial layer includes N-type epitaxial layer, the N-type source packet The source electrode of type containing N+, the body area include P-type body area.
Preferably, step 7) further includes the steps that the grid polycrystalline silicon carve, so that the gate polycrystalline The top surface of silicon is less than the top surface of the epitaxial layer.
Preferably, it includes step that step 8) forms the upper metal structure above the epitaxial layer：8-1) in the grid Pole polysilicon and deposition spacer medium layer on the epitaxial layer, etch the spacer medium layer to form source contact openings and grid The bottom of pole contact hole, the source contact openings appears the body area, and side wall appears the source electrode, and the gate contact hole appears The grid polycrystalline silicon；And 8-2) in heavy on the spacer medium layer, the source contact openings and the gate contact hole Product metal layer, to realize the electrical extraction of the source electrode and the grid polycrystalline silicon.
Further, step 8-2) before depositing the metal layer, further include in the source contact openings described in The step of doping contact zone is formed in body area.
As described above, the manufacturing method of the shield grid trench FET of the present invention, has the advantages that：
Present invention eliminates the depth of isolating oxide layer and the cutoff layers that must carry out in order to obtain in common process method Deposit, return carve, removal, and chemically mechanical polishing (CMP) cut-off or levelling, increase only isolating oxide layer (high density Plasma oxide layer) deposit before wet etching step make the isolation using the characteristic of high-density plasma fill process The filling of oxide layer has peculiar pattern, combines isotropic wet etching characteristic, and target thickness is formed in deep trench The isolating oxide layer that excess surface is removed while isolating oxide layer reaches and is imitated with the essentially identical process goal of common process Fruit greatly reduces process costs and process time, is with a wide range of applications in semiconductor device design and manufacturing field.
Description of the drawings
Fig. 1 is shown as a kind of structural schematic diagram of shield grid trench FET in the prior art.
Fig. 2 a~Fig. 2 h are shown as each step institute of manufacturing method of shield grid trench FET in the prior art The structural schematic diagram of presentation.
Manufacturing method each step that Fig. 3~Fig. 9 is shown as the shield grid trench FET of the present invention is presented Structural schematic diagram.
Figure 10 is shown as the manufacturing method steps flow chart schematic diagram of the shield grid trench FET of the present invention.
Component label instructions
100 drain metal layers
102 substrates
104 epitaxial layers
106 deep trench
108 screen oxides
109 etching grooves
110 shielding polysilicons
112 isolating oxide layers
113 side grooves
114 gate oxides
115 curved bottoms
116 grid polycrystalline silicons
118 body areas
120 source electrodes
122 spacer medium layers
124 source contact openings
130 metal layers
S11~S18 steps 1)~step 8)
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from Various modifications or alterations are carried out under the spirit of the present invention.
Please refer to Fig. 3~Figure 10.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, package count when only display is with related component in the present invention rather than according to actual implementation in illustrating then Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its Assembly layout kenel may also be increasingly complex.
As shown in Fig. 3~Figure 10, the present embodiment provides a kind of shield grid trench FETs (SGT MOSFET) Manufacturing method, the shield grid trench FET can be N-type device, or P-type device, the present embodiment is with N It is illustrated for type device.The manufacturing method includes step：
As shown in Fig. 3 and Figure 10, step 1) S11 is carried out first, a substrate 102 is provided, in the upper surface of the substrate 102 Epitaxial layer 104 is formed, forms deep trench 106 in the epitaxial layer 104, in inner wall and the extension of the deep trench 106 104 surface of layer form screen oxide 108, in filling shielding polysilicon 110, the shielding polysilicon in the deep trench 106 110 also coverings are located at the screen oxide 108 above the epitaxial layer 104.
The substrate 102 can be silicon substrate, germanium silicon substrate, the silicon carbide substrates etc. of N++ types doping, in the present embodiment In, the substrate 102 selects the silicon substrate for the doping of N++ types, and it is N-type single-crystal Si epitaxial layers that the epitaxial layer 104, which is selected,.
Deep trench 106 is formed in the epitaxial layer 104 using photo etching process, then use thermal oxidation technology in The inner wall of the deep trench 106 forms screen oxide 108, the thickness of the screen oxide 108 with 104 surface of the epitaxial layer Degree is not less than 1000 angstroms, to reach good shield effectiveness, for example, the thickness of the screen oxide 108 can be between 1000 Angstrom~8000 angstroms between.
As shown in Fig. 4 and Figure 10, step 2) S12 is then carried out, the shielding polycrystalline of 104 top of the epitaxial layer is thinned Silicon 110 and the screen oxide 108,104 top of the epitaxial layer remain with the screen oxide 108.
For example, the shielding polysilicon 110 that 104 top of the epitaxial layer is thinned in mechanical-chemistry grinding technique may be used With the screen oxide 108,104 top of the epitaxial layer remains with the screen oxide 108, as covering for subsequent etching Film.
As shown in Fig. 5 and Figure 10, step 3) S13 is then carried out, is returned for mask with the screen oxide 108 and carves etching institute Shielding polysilicon 110 is stated, to form an etching groove 109,109 both sides of the etching groove appear described in the deep trench 106 Screen oxide 108.
As an example, the depth of the etching groove 109 can between 106 depth of the deep trench a quarter to two points One of between, with ensure it is described shielding polysilicon 110 required reserved, and for subsequent screen oxide 108 and grid it is more Crystal silicon 116 improves enough making spaces.
As shown in Fig. 6 and Figure 10, step 4) S14 is then carried out, the shielding of 109 both sides of etching groove described in wet etching Oxide layer 108, while the upper section of the shielding polysilicon 110 being made to protrude from the screen oxide 108.
As an example, in the wet etching, the shielding oxidation of the upper section both sides of the shielding polysilicon 110 It is partially removed between layer 108 to be respectively formed side grooves 113, after the wet etching, 109 both sides of the etching groove and described 104 surface of epitaxial layer remains with the certain thickness screen oxide 108.Further, the side grooves 113 include arc Shape bottom 115.
As shown in Fig. 7 and Figure 10, step 5) S15 is then carried out, isolating oxide layer 112, the isolating oxide layer 112 are deposited Including the filling part being filled in the deep trench 106 and the lug boss for being covered in 104 top of the epitaxial layer.
As an example, the isolating oxide layer 112 is formed using high-density plasma deposition process, by step 4) institute The structure and morphology of formation and the characteristic of high-density plasma deposition process, the isolating oxide layer 112 include flat condition It is described to fill out and the lug boss of needle pattern, so that subsequent step 6) in, the filling part is etched to target thickness Completely remove the lug boss and the screen oxide 108 on the epitaxial layer 104 simultaneously.
As shown in Fig. 8 and Figure 10, step 6) S16 is then carried out, wet etching, which returns, carves the isolating oxide layer 112, by institute It states and removes the lug boss and the shielding oxidation on the epitaxial layer 104 while filling part is etched to target thickness Layer 108.
It is returned based on isotropic wet etching and carves the isolating oxide layer 112, due to the peculiar shape of isolating oxide layer 112 Looks, the lug boss of needle pattern can be easier to preferentially be removed, and the flat condition in the deep trench 106 is filled out It fills portion then partly to be retained, as the isolating oxide layer that the shielding polysilicon 110 and grid polycrystalline silicon 116 is finally isolated 112。
As shown in FIG. 9 and 10, then carry out step 7) S17 and step 8) S18, in the deep trench 106 inner wall and 112 surface of isolating oxide layer deposition gate oxide 114 fills grid to form gate trench in the gate trench Polysilicon 116 is to form grid, the step of to the grid polycrystalline silicon 116 carve, so that the grid polycrystalline silicon 116 Top surface be less than the top surface of the epitaxial layer 104, body area is formed in the epitaxial layer 104 of 106 both sides of the deep trench 118, source electrode 120 is formed in the body area 118, upper metal structure is formed above the epitaxial layer 104, in the substrate 102 lower surfaces form drain metal layer 100.
As an example, there is the first conductive type ion to mix for the substrate 102, the epitaxial layer 104, the source electrode 120 Miscellaneous, the body area 118 is adulterated with the second conductive type ion, and first conduction type and second conduction type are each other Opposite conduction type.For example, for N-type device, the substrate 102 includes N++ type substrates, and the epitaxial layer 104 includes N- Type epitaxial layer, the N-type source 120 include N+ type source electrodes, and the body area 118 includes P-type body area 118.
As an example, the bottom in the body area 118 is not less than the bottom of the gate trench, the i.e. bottom in the body area 118 Portion and the bottom of the gate trench have a difference in height Woverlap, to further increase the grid polycrystalline silicon 116 to described The channel controllability of shield grid trench FET.
Specifically, it includes step that step 8) forms the upper metal structure above the epitaxial layer 104：
Step 8-1), in deposition spacer medium layer 122 on the grid polycrystalline silicon 116 and the epitaxial layer 104, etch institute Spacer medium layer 122 is stated to form source contact openings 124 and gate contact hole, the bottom of the source contact openings 124 appears The body area 118, side wall appear the source electrode 120, and the gate contact hole appears the grid polycrystalline silicon 116；
Step 8-2), in heavy on the spacer medium layer 122, the source contact openings 124 and the gate contact hole Product metal layer 130, to realize the electrical extraction of the source electrode 120 and the grid polycrystalline silicon 116.
Preferably, step 8-2) before depositing the metal layer 130, further include in the source contact openings 124 The step of doping contact zone is formed in the body area 118, in the present embodiment, it is that P+ type doping connects that the doping contact zone, which is selected, Area is touched, to reduce the contact resistance of the metal layer 130 and the body area 118.Finally, it is made annealing treatment so that the gold Belong to floor 130 and form Ohmic contact with the source electrode 120, the body area 118 and the grid polycrystalline silicon 116, to further decrease Contact resistance.
As described above, the manufacturing method of the shield grid trench FET of the present invention, has the advantages that：
Present invention eliminates the depth of isolating oxide layer 112 and the cut-offs that must carry out in order to obtain in common process method The deposit of layer returns and carves, removes, and chemically-mechanicapolish polishes the cut-off or levelling of (CMP), and it is (high to increase only isolating oxide layer 112 Density plasma oxide layer) deposit before wet etching step make this using the characteristic of high-density plasma fill process The filling of isolating oxide layer 112 has peculiar pattern, combines isotropic wet etching characteristic, is formed in deep trench 106 The isolating oxide layer 112 that excess surface is removed while isolating oxide layer 112 of target thickness, reaches and the basic phase of common process Same process goal effect, greatly reduces process costs and process time, has in semiconductor device design and manufacturing field It is widely applied foreground.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as At all equivalent modifications or change, should by the present invention claim be covered.

Claims (11)

1. a kind of manufacturing method of shield grid trench FET, which is characterized in that including step：
1) substrate is provided, epitaxial layer is formed in the upper surface of the substrate, deep trench is formed in the epitaxial layer, in described The inner wall of deep trench forms screen oxide with the epi-layer surface, described in filling shielding polysilicon in the deep trench Shielding polysilicon also covers the screen oxide above the epitaxial layer；
2) the shielding polysilicon and the screen oxide above the epitaxial layer is thinned, is remained with above the epitaxial layer The screen oxide；
3) it is returned as mask using the screen oxide and etches the shielding polysilicon, to form an etching groove, the etching groove Both sides appear the screen oxide in the deep trench；
4) screen oxide of etching groove both sides described in wet etching, while making the upper section of the shielding polysilicon Protrude from the screen oxide；
5) isolating oxide layer is deposited, the isolating oxide layer includes the filling part being filled in the deep trench and is covered in institute State the lug boss above epitaxial layer；
6) wet etching, which returns, carves the isolating oxide layer, and the protrusion is removed while the filling part is etched to target thickness Portion and the screen oxide on the epitaxial layer；
7) gate oxide is deposited in the inner wall of the deep trench and the isolation oxidation layer surface, to form gate trench, in institute It states and fills grid polycrystalline silicon in gate trench to form grid；And
8) body area is formed in the epitaxial layer of the deep trench both sides, source electrode is formed in the body area, in the extension Layer top forms upper metal structure, and drain metal layer is formed in the substrate lower surface.
2. the manufacturing method of shield grid trench FET according to claim 1, it is characterised in that：Step 4) institute It states in wet etching, is partially removed between the screen oxide of the upper section both sides of the shielding polysilicon to distinguish shape At side grooves, after the wet etching, the etching groove both sides and the epi-layer surface remain with certain thickness described Screen oxide.
3. the manufacturing method of shield grid trench FET according to claim 2, it is characterised in that：The side Groove includes curved bottom.
4. the manufacturing method of shield grid trench FET according to claim 2, it is characterised in that：Step 5) In, the isolating oxide layer is formed using high-density plasma deposition process, the isolating oxide layer includes the institute of flat condition It states and fills out and the lug boss of needle pattern, it is complete while the filling part is etched to target thickness so that in step 6) The lug boss and the screen oxide on the epitaxial layer are removed entirely.
5. the manufacturing method of shield grid trench FET according to claim 1, it is characterised in that：Step 1) In, the thickness of the screen oxide is not less than 1000 angstroms.
6. the manufacturing method of shield grid trench FET according to claim 1, it is characterised in that：The body area Bottom be not less than the gate trench bottom.
7. the manufacturing method of shield grid trench FET according to claim 1, it is characterised in that：The lining Bottom, the epitaxial layer, the source electrode are adulterated with the first conductive type ion, and there is the second conductive type ion to mix in the body area It is miscellaneous, first conduction type conduction type opposite each other with second conduction type.
8. the manufacturing method of shield grid trench FET according to claim 7, it is characterised in that：The substrate Including N++ type substrates, the epitaxial layer includes N-type epitaxial layer, and the N-type source includes N+ type source electrodes, and the body area includes P- The areas Xing Ti.
9. the manufacturing method of shield grid trench FET according to claim 1, it is characterised in that：Step 7) is also Include the steps that the grid polycrystalline silicon carve, so that the top surface of the grid polycrystalline silicon is less than the epitaxial layer Top surface.
10. the manufacturing method of shield grid trench FET according to claim 1, it is characterised in that：Step 8) It includes step that the upper metal structure is formed above the epitaxial layer：
8-1) in depositing spacer medium layer on the grid polycrystalline silicon and the epitaxial layer, the spacer medium layer is etched to be formed The bottom in source contact openings and gate contact hole, the source contact openings appears the body area, and side wall appears the source electrode, institute It states gate contact hole and appears the grid polycrystalline silicon；
8-2) in deposited metal layer on the spacer medium layer, the source contact openings and the gate contact hole, to realize The electrical extraction of the source electrode and the grid polycrystalline silicon.
11. the manufacturing method of shield grid trench FET according to claim 10, it is characterised in that：Step 8- 2) further include the step that doping contact zone is formed in the body area in the source contact openings before depositing the metal layer Suddenly.
CN201810094738.7A 2018-01-31 2018-01-31 The manufacturing method of shield grid trench FET Pending CN108389800A (en)

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Application publication date: 20180810