CN108376740A - Composite channel transistor and preparation method thereof - Google Patents
Composite channel transistor and preparation method thereof Download PDFInfo
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- CN108376740A CN108376740A CN201810048091.4A CN201810048091A CN108376740A CN 108376740 A CN108376740 A CN 108376740A CN 201810048091 A CN201810048091 A CN 201810048091A CN 108376740 A CN108376740 A CN 108376740A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
- H10K10/488—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising a layer of composite material having interpenetrating or embedded materials, e.g. a mixture of donor and acceptor moieties, that form a bulk heterojunction
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- Chemical & Material Sciences (AREA)
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- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of composite channel transistors, including：Interlayer dielectric layer in semiconductor substrate；Grid in interlayer dielectric layer；Gate dielectric on grid；Composite channel layer on gate dielectric and interlayer dielectric layer；Source-drain area positioned at composite channel layer both ends；The passivation layer coated on interlayer dielectric layer and by the surrounding of composite channel layer and upper surface；In passivation layer and connect the source-drain electrode of source-drain area.The present invention selects the graphene with high mobility and the organic film with gap tunable that composite channel layer is collectively formed, it can effectively solve the problems, such as that graphene does not have band gap and Organic Thin Film Transistors mobility low, prepare the composite channel transistor with high mobility, and it can be compatible with existing CMOS technology, preparation process simple possible, it is convenient to prepare small size, large-scale composite channel transistor array.The invention also discloses a kind of preparation methods of composite channel transistor.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology fields, more particularly, to a kind of composite channel transistor
And preparation method thereof.
Background technology
As feature sizes of semiconductor devices presses Moore's Law scaled down, chip integration is continuously improved, traditional base
In silicon semiconductor device due to technological limits and various negative effects, be difficult meet again device and circuit performance and power consumption want
It asks.Domestic and international major scientific research institution and semiconductor maker study various new materials and new device structure one after another, existing to replace
Some silicon semiconductor devices.
In recent years, graphene is because the electron mobility of its superelevation is (up to 200000cm2/ Vs) become the hot spot studied, but
It is since graphene does not have band gap (bandgap) so that its dim future in the application similar to transistor.
On the other hand, with the development of organic conductive polymer, for the insulating layer, semiconductor and grid of inorganic field effect pipe
Pole all starts to have tried to be substituted with organic matter, to develop into a kind of novel organic film FET.
Compared with inorganic thin film field-effect transistor, organic film FET has following major advantages：
(1) film technique of organic film is more, updates (such as numerator self-assembly technique), and the size of device can be made smaller
(molecular scale), integrated level higher, and can effectively reduce operation power.
(2) also more simple (it is not required for strictly controlling atmospheric condition and severe to the manufacture craft of organic field-effect tube
The purity requirement at quarter), thus the cost of device can be effectively reduced.
(3) organic film is adjusted and is modified by the structure to organic molecule, can adjust the size of its band gap.
But most of organic materials are because of its mobility all very littles, to its electric conductivity and not fully up to expectations.Therefore, such as
What utilizes the advantage of graphene and organic film respectively, prepares the composite channel transistor of high mobility, and can be with CMOS works
Skill is compatible with, and is urgent problem.
Invention content
It is an object of the invention to overcome drawbacks described above of the existing technology, provide a kind of composite channel transistor and its
Preparation method.
To achieve the above object, technical scheme is as follows：
The present invention provides a kind of composite channel transistors, include from bottom to top：
Interlayer dielectric layer in semiconductor substrate；
Grid in interlayer dielectric layer；
Gate dielectric on grid；
Composite channel layer on gate dielectric and interlayer dielectric layer；
Source-drain area positioned at composite channel layer both ends；
Passivation layer on interlayer dielectric layer, the passivation layer coat the surrounding of composite channel layer and upper surface；
Source-drain electrode in passivation layer, the source-drain electrode connect source-drain area；
Wherein, the lamination that the composite channel layer is formed at least one layer of graphene and at least one layer of organic film.
Preferably, the organic film material is acene, Oligopoly thiophene, perylene, naphthalene, anthracene, rubrene, TTF derivatives
At least one of object.The grid material is at least one of metal, polysilicon and conducting polymer.The gate dielectric
Layer material is SiO2, SiN, SiON, high-k dielectric material, at least one of metal oxide and organic insulating material.
Preferably, graphene film of the source-drain area above the interlayer dielectric layer to grid both sides adulterates by shape
At.
The present invention also provides a kind of preparation methods of composite channel transistor, include the following steps：
Step S01：Semi-conductive substrate is provided, forms interlayer dielectric layer on the semiconductor substrate, and in the layer
Between form a groove on dielectric layer；
Step S02：The deposition of gate material in the groove forms grid；
Step S03：Gate dielectric is formed on the grid；
Step S04：Composite channel layer is formed on the gate dielectric；
Step S05：Source-drain area is formed at the both ends of the composite channel layer；
Step S06：Device surface in the composite channel layer forms passivation layer；
Step S07：Source-drain electrode is formed in the passivation layer above the source-drain area；
Wherein, the lamination shape that the composite channel layer is made of at least one layer of graphene and at least one layer of organic film
At.
Preferably, in step S04, by deposition and/or shifting process, composite channel layer is formed.
Preferably, in step S05, the source-drain area passes through the graphene film above the interlayer dielectric layer to grid both sides
It adulterates and is formed.
Preferably, when the top layer of the composite channel layer is graphene layer, by directly to the composite channel layer
The graphene film of both sides is doped, and forms the source-drain area；When the top layer of the composite channel layer is organic thin film layer
When, photoetching, etching technics are first passed through, the organic thin film layer of the composite channel layer both sides is removed, makes graphene layer below
Expose, then, is doped by the graphene film to exposed portion, forms the source-drain area.
Preferably, in step S07, the source-drain electrode is at least one of metal, conducting polymer and graphene.
It can be seen from the above technical proposal that the present invention is by graphene of the selection with high mobility and with adjustable band
Composite channel layer is collectively formed in the organic film of gap, and forms source-drain area using being entrained in graphene film, can effectively solve
Certainly graphene does not have band gap and the low problem of Organic Thin Film Transistors mobility, and it is brilliant to prepare the composite channel with high mobility
Body pipe, and can be compatible with existing CMOS technology, preparation process simple possible, it is convenient to prepare small size, big rule
The composite channel transistor array of mould.
Description of the drawings
Fig. 1 is a kind of composite channel transistor arrangement schematic diagram of a preferred embodiment of the present invention；
Fig. 2-Fig. 3 is the composite channel schematic diagram of a layer structure of two kinds of preferred embodiments of the invention；
Fig. 4 is a kind of preparation method flow diagram of composite channel transistor of the present invention；
Fig. 5-Figure 11 is processing step schematic diagram when preparing a kind of composite channel transistor according to the method for Fig. 4.
Specific implementation mode
Below in conjunction with the accompanying drawings, the specific implementation mode of the present invention is described in further detail.
It should be noted that in following specific implementation modes, when embodiments of the present invention are described in detail, in order to clear
Ground indicates the structure of the present invention in order to illustrate, spy does not draw to the structure in attached drawing according to general proportion, and has carried out part
Amplification, deformation and simplified processing, therefore, should avoid in this, as limitation of the invention to understand.
In specific implementation mode of the invention below, referring to Fig. 1, Fig. 1 is one kind of a preferred embodiment of the present invention
Composite channel transistor arrangement schematic diagram.As shown in Figure 1, a kind of composite channel transistor of the present invention, is at least wrapped from bottom to top
It includes：Semiconductor substrate 101, interlayer dielectric layer 102, grid 103, gate dielectric 104, composite channel layer 105, source-drain area 107,
Passivation layer 106, the device architecture of the equal composition field-effect transistor of source-drain electrode 108.
It please refers to Fig.1.The connected grid 103 for being arranged in lower layer of gate dielectric 104 and the compound ditch positioned at upper layer
Between channel layer 105.Wherein, the size of grid and gate dielectric is both less than the size of composite channel layer；Also, grid and grid
Dielectric layer can be located substantially at the medium position below composite channel layer.It is equipped with field-effect transistor at the both ends of composite channel layer
Source-drain area (i.e. one end is source region, the other end is drain region) 107.
At least one of metal, polysilicon, conducting polymer can be used in grid material.Wherein, gate metal for example may be used
Using W, Cu, Al etc.；Polyacetylene, polythiophene, polypyrrole, polyaniline, polyhenylene, polyphenylene ethylene for example can be used in conducting polymer
Alkene and poly bis alkynes etc..
SiO can be used in gate dielectric material2, SiN, SiON, high-k dielectric material, metal oxide, organic insulating material
At least one of.Wherein, the general Shandong alkane (CYEP) of organic insulating material such as cyanoethyl, polymethyl methacrylate (PMMA) etc..
Fig. 2-Fig. 3 is please referred to, Fig. 2-Fig. 3 is the composite channel schematic diagram of a layer structure of two kinds of preferred embodiments of the invention.Fig. 1
In the laminated construction that is formed at least one layer of graphene and at least one layer of organic film of composite channel layer 105.For example, as schemed
Shown in 2, composite channel layer 105 can be by the layer graphene film 105a positioned at lower layer and one layer of organic film positioned at upper layer
105b is formed.Alternatively, as shown in figure 3, composite channel layer 105 can also by positioned at lower layer a layer graphene film 105c,
The interlayer structure of one layer of organic film 105d positioned at middle level and another layer graphene film 105e positioned at upper layer is formed.This
It invents without being limited thereto.
Organic film material can be used in acene, Oligopoly thiophene, perylene, naphthalene, anthracene, rubrene, TTF derivatives extremely
Few one kind.Such as pentacene, C60, C8-BTBT, tetra cyanogen subculture dimethyl benzene quinone, polyacetylene, polythiophene and metal phthalocyanine can be used
Deng.The band gap width of organic film material is 0.75~3eV.
Source-drain area 107 may be used the graphene film above grid and be formed；For example, source-drain area can be by grid both sides
Interlayer dielectric layer above graphene film in composite channel layer be doped and formed in raceway groove both sides.Wherein, doping member
Element can be As, B, P etc..
Please continue to refer to Fig. 1.Passivation there are one being also set up on interlayer dielectric layer in the composite channel transistor of the present invention
Layer 106；Passivation layer 106 coats the surrounding of composite channel layer 105 and upper surface above device.
Be additionally provided in the passivation layer positioned at source-drain area top position source-drain electrode (i.e. above source region be equipped with source electrode,
Drain electrode is equipped with above drain region) 108；Source-drain electrode 108 connects source-drain area 107.Metal, conducting polymer may be used in source-drain electrode
At least one of object and graphene make；For example, the making of Ni metal material can be used in source-drain electrode, alternatively, source-drain electrode
It can be formed by the material comprising graphene film.
In addition, being also connected with the lower layer of composite channel layer 105 in passivation layer 106 is equipped with interlayer dielectric layer 102.Grid 103
It is set in interlayer dielectric layer 102, interlayer dielectric layer coats the surrounding of grid and lower surface.Under interlayer dielectric layer 102
Layer, which is also connected, is equipped with semiconductor substrate 101.
Below by way of specific implementation mode and attached drawing, a kind of preparation method of composite channel transistor of the present invention is carried out
It is described in detail.
Referring to Fig. 4, Fig. 4 is a kind of preparation method flow diagram of composite channel transistor of the present invention；Meanwhile it please join
Fig. 5-Figure 11 is read, Fig. 5-Figure 11 is processing step schematic diagram when preparing a kind of composite channel transistor according to the method for Fig. 4.Such as
Shown in Fig. 4, a kind of preparation method of composite channel transistor of the invention can be used for preparing above-mentioned composite channel transistor,
Include the following steps：
Step S01：Semi-conductive substrate is provided, forms interlayer dielectric layer on the semiconductor substrate, and in the layer
Between form a groove on dielectric layer.
Please refer to Fig. 5.First, conventional semiconductor substrate 201 can be used, grow forming layer in semiconductor substrate 201
Between dielectric layer 202.Interlayer dielectric layer 202 can be used conventional material and be formed.Then, can be situated between in interlayer by photoetching, etching technics
Groove 203 is formed in electric layer 202.In the present embodiment, the depth of groove 203 can be 60nm (nanometer).
Step S02：The deposition of gate material in the groove forms grid.
Please refer to Fig. 6.Then, the deposition of gate material in groove 203, and can be used outside polishing process removal groove 203
The extra grid material in portion, to form grid 204 in a groove.Grid material can be metal, polysilicon and conducting polymer
At least one of object.In the present embodiment, grid material is metal Al.
Step S03：Gate dielectric is formed on the grid.
Please refer to Fig. 7.Then, in device surface gate dielectric layer material, and by photoetching, etching technics, make shape
At gate dielectric 205 be located at the top of grid 204.Gate dielectric material can be SiO2, SiN, SiON, high-k dielectric material,
At least one of metal oxide and organic insulating material.In the present embodiment, gate dielectric material HfO2, thickness can
For 3nm.
Step S04：Composite channel layer is formed on the gate dielectric.
Please refer to Fig. 8.Then, composite channel layer can be formed in above-mentioned device surface by deposition and/or shifting process.
Wherein, the lamination that composite channel layer is made of at least one layer of graphene and at least one layer of organic film is formed.For example, compound ditch
Channel layer can be formed at least by the layer graphene 206 positioned at lower layer and one layer of organic film 207 positioned at 206 upper layer of graphene.
Then, photoetching, etching technics can be first passed through, removal makes multiple positioned at the organic thin film layer 207 at composite channel layer both ends
It closes the organic thin film layer in channel layer and is only located at 204 top of grid, be located at interlayer dielectric to expose at composite channel layer both ends
Graphene film 206 on layer 202.
Organic film can be at least one in acene, Oligopoly thiophene, perylene, naphthalene, anthracene, rubrene, TTF derivatives
Kind.In the present embodiment, the composition of composite channel layer is followed successively by the graphene of 5nm and the pentacene of 10nm.
Step S05：Source-drain area is formed at the both ends of the composite channel layer.
Please refer to Fig. 9.Then, the graphene layer 206 that composite channel layer both ends are exposed above grid is doped, is formed
Source-drain area 208.By doping, source-drain area is formd in raceway groove both sides；Doped chemical can be As, B, P etc..In the present embodiment
In, B doping is carried out to the graphene layer of PMOS, As doping is carried out to the graphene layer of NMOS.
It should be noted that when the top layer of composite channel layer is graphene layer, it can be directly to composite channel layer both ends
Graphene film be doped, form the source-drain area.Only when the top layer of composite channel layer is organic thin film layer,
Photoetching, etching technics are first passed through, the organic thin film layer at removal composite channel layer both ends makes graphene layer below expose, so
Afterwards, it is doped by the graphene film to exposed portion, forms the source-drain area.
Step S06：Device surface in the composite channel layer forms passivation layer.
Please refer to Fig.1 0.Then, deposition forms passivation layer 209 in composite channel layer and source-drain area.Passivation material can
For SiO2, at least one of SiN, SiON and low-k (low k) material.In the present embodiment, passivation layer SiOC,
Thickness is 300nm.
Step S07：Source-drain electrode is formed in the passivation layer above the source-drain area.
Please refer to Fig.1 1.It then, can be by photoetching, etching technics, in the passivation layer 209 above source-drain area 208
Through-hole is formed, and fills source-drain electrode thin-film material, for example, Cu in through-holes.
Finally, it can be planarized by polishing, form the source-drain electrode 210 concordant with passivation layer surface.
Above-mentioned source-drain electrode may be used at least one of metal, conducting polymer and graphene and be made.
In conclusion the present invention is total by selecting the graphene with high mobility and the organic film with gap tunable
Source-drain area is formed with formation composite channel layer, and using being entrained in graphene film, can effectively solve the problem that graphene does not have band
Gap and the low problem of Organic Thin Film Transistors mobility, prepare the composite channel transistor with high mobility, and can
It is compatible with existing CMOS technology, preparation process simple possible, it is convenient to it is brilliant to prepare small size, large-scale composite channel
Body pipe array.
Above-described to be merely a preferred embodiment of the present invention, the embodiment is not to be protected to limit the patent of the present invention
Range, therefore equivalent structure variation made by every specification and accompanying drawing content with the present invention are protected, similarly should be included in
In protection scope of the present invention.
Claims (10)
1. a kind of composite channel transistor, which is characterized in that include from bottom to top：
Interlayer dielectric layer in semiconductor substrate；
Grid in interlayer dielectric layer；
Gate dielectric on grid；
Composite channel layer on gate dielectric and interlayer dielectric layer；
Source-drain area positioned at composite channel layer both ends；
Passivation layer on interlayer dielectric layer, the passivation layer coat the surrounding of composite channel layer and upper surface；
Source-drain electrode in passivation layer, the source-drain electrode connect source-drain area；
Wherein, the lamination that the composite channel layer is formed at least one layer of graphene and at least one layer of organic film.
2. composite channel transistor according to claim 1, which is characterized in that the organic film material is acene, low
At least one of polythiophene, perylene, naphthalene, anthracene, rubrene, TTF derivatives.
3. composite channel transistor according to claim 1, which is characterized in that the grid material is metal, polysilicon
At least one of with conducting polymer.
4. composite channel transistor according to claim 1, which is characterized in that the gate dielectric material is SiO2、
At least one of SiN, SiON, high-k dielectric material, metal oxide and organic insulating material.
5. composite channel transistor according to claim 1, which is characterized in that the source-drain area passes through to grid both sides
Graphene film above interlayer dielectric layer is adulterated and is formed.
6. a kind of preparation method of composite channel transistor, which is characterized in that include the following steps：
Step S01：Semi-conductive substrate is provided, forms interlayer dielectric layer on the semiconductor substrate, and be situated between in the interlayer
A groove is formed in electric layer；
Step S02：The deposition of gate material in the groove forms grid；
Step S03：Gate dielectric is formed on the grid；
Step S04：Composite channel layer is formed on the gate dielectric；
Step S05：Source-drain area is formed at the both ends of the composite channel layer；
Step S06：Device surface in the composite channel layer forms passivation layer；
Step S07：Source-drain electrode is formed in the passivation layer above the source-drain area；
Wherein, the lamination that the composite channel layer is made of at least one layer of graphene and at least one layer of organic film is formed.
7. the preparation method of composite channel transistor according to claim 6, which is characterized in that in step S04, by heavy
Product and/or shifting process form composite channel layer.
8. the preparation method of composite channel transistor according to claim 6, which is characterized in that in step S05, the source
Graphene film of the drain region above the interlayer dielectric layer to grid both sides is adulterated and is formed.
9. the preparation method of composite channel transistor according to claim 8, which is characterized in that when the composite channel layer
Top layer when being graphene layer, by being directly doped to the graphene film of the composite channel layer both sides, form institute
State source-drain area；When the top layer of the composite channel layer is organic thin film layer, photoetching, etching technics are first passed through, described in removal
The organic thin film layer of composite channel layer both sides makes graphene layer below expose, then, passes through the graphene to exposed portion
Film is doped, and forms the source-drain area.
10. the preparation method of composite channel transistor according to claim 6, which is characterized in that described in step S07
Source-drain electrode is at least one of metal, conducting polymer and graphene.
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| CN108376740B (en) * | 2018-01-18 | 2022-03-29 | 上海集成电路研发中心有限公司 | Composite channel transistor and preparation method thereof |
| CN114864708A (en) * | 2022-05-06 | 2022-08-05 | 北京交通大学 | Multi-grid graphene field effect transistor type photoelectric sensor and preparation method thereof |
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| CN114864708A (en) * | 2022-05-06 | 2022-08-05 | 北京交通大学 | Multi-grid graphene field effect transistor type photoelectric sensor and preparation method thereof |
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