CN108376683A - The production method and semiconductor devices of source electrode - Google Patents
The production method and semiconductor devices of source electrode Download PDFInfo
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- CN108376683A CN108376683A CN201810162039.1A CN201810162039A CN108376683A CN 108376683 A CN108376683 A CN 108376683A CN 201810162039 A CN201810162039 A CN 201810162039A CN 108376683 A CN108376683 A CN 108376683A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- Physics & Mathematics (AREA)
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- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
The present invention relates to the production method of source electrode and semiconductor devices, wherein, the production method of source electrode, which is included in above semiconductor base, forms multiple gate structures, and there is multiple gate structures the first gap and the second gap, the width in the first gap to be less than the width in unidirectional second gap；Dielectric layer and etching barrier layer are sequentially formed above gate structure；Etch media layer is until remove the dielectric layer in first gap, while the second gap is still covered by dielectric layer；Then the semiconductor base in the first gap is etched to form the second groove, removes remaining etching barrier layer and dielectric layer；Then ion implanting is carried out to form source electrode in the region of second groove.The production method of above-mentioned source electrode eliminates light shield technique, to advantageously reduce cost.The present invention also provides the semiconductor devices of the source electrode formed including the above method.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to the production methods and semiconductor devices of source electrode.
Background technology
With the fast development of semiconductor industry, in order to achieve the purpose that improve production efficiency and reduce production cost,
The integration density of IC chip is that the quantity of the semiconductor devices interconnected on the chip of unit area increases, while partly leading
The geometric dimension of body device reduces, however, this trend also increases the complexity of semiconductor device fabrication process, such as is wrapping
In the manufacturing process for including the semiconductor devices of mos field effect transistor (MOSFET), it is typically passed through multiple tracks
Light shield technique (generally comprise exposure imaging etching etc. a series of processes so that a certain function pattern layers) with formed such as grid,
The components such as source electrode and drain electrode still have further improved needs although expected purpose may be implemented.
Floating gate type flash memory is a kind of nonvolatile storage, and it includes gate dielectric, floating boom and control gate usually to have
FLOTOX (floating gate tunneling oxide, floating boom tunnel oxidation layer transistor) structure, wherein control gate is logical
Overcoupling is to control the storage and release of electronics in floating boom.At present in the making of floating gate type flash memory, existed using one of light shield technique
Groove is formed in the substrate of source area, is then carried out ion implanting in a groove and is formed source electrode, cost is higher.
Invention content
It is made the technical problem to be solved by the present invention is to the source electrode of existing floating gate type flash memory and needs special one of light shield technique
The caused higher problem of cost.
To solve the above problems, the present invention provides a kind of production method of source electrode, include the following steps：
Rectangular at multiple gate structures on a semiconductor substrate, the multiple gate structure has between the first gap and second
Gap, the width in first gap are less than the width in unidirectional second gap；It is formed above the gate structure
Dielectric layer, the upper surface positioned at second gap of the dielectric layer are concave surface, and it is the to define the region that the concave surface surrounds
One groove；Etching barrier layer is formed, the etching barrier layer is made to fill up first groove；The dielectric layer is etched, until going
Except the bottom surface of the dielectric layer in first gap, while second gap is still covered by the dielectric layer；Etch position
In the semiconductor base in first gap to form the second groove；It removes the remaining etching barrier layer and is given an account of
Matter layer；And ion implanting is carried out, to form source electrode in the region of second groove.
Optionally, etching barrier layer is formed, the step of making the etching barrier layer fill up first groove further includes：Make
The upper surface flush of the upper surface of etching barrier layer in first groove and the dielectric layer outside first groove.
Optionally, before forming dielectric layer above the gate structure, the production method of the source electrode further includes：It is formed
Protective layer, the protective layer cover the multiple gate structure.
Optionally, isolation structure is formed in the semiconductor base, second groove runs through the isolation structure.
Optionally, the thickness of the dielectric layer is more than the half of the width in first gap, and is less than same direction
Second gap width half.
Optionally, the material of the etching barrier layer includes anti-reflection coating.
Optionally, the material of the etching barrier layer includes silica.
Optionally, the step of semiconductor base for being located at first gap is to form the second groove is etched also to wrap
It includes：Remove the remaining etching barrier layer simultaneously.
Optionally, the gate structure includes floating boom.
In addition, the present invention also provides a kind of semiconductor devices, including gate structure, source electrode and drain electrode, wherein the source electrode
Making include the above method.
The production method of source electrode provided by the invention, does not need light shield, and the first gap between gate structure is partly led
The second groove is formd in body substrate, source electrode is formed in the region of the second groove by ion implanting, to eliminate one of light
Cover technique, advantageously reduces cost.
Semiconductor devices provided by the invention, the making of source electrode include the production method of above-mentioned source electrode, thus have class
As advantage.
Description of the drawings
Fig. 1 is the flow diagram of the production method of the source electrode of the embodiment of the present invention.
Fig. 2 is that semiconductor devices is shown using the section after the production method formation gate structure of the source electrode of the embodiment of the present invention
It is intended to.
Fig. 3 is that semiconductor devices forms the section signal after dielectric layer using the production method of the source electrode of the embodiment of the present invention
Figure.
Fig. 4 a and Fig. 4 b are that semiconductor devices forms etching barrier layer using the production method of the source electrode of the embodiment of the present invention
Diagrammatic cross-section afterwards.
Fig. 5 is that semiconductor devices utilizes the dielectric layer in the first gap of production method removal of the source electrode of the embodiment of the present invention
Diagrammatic cross-section afterwards.
Fig. 6 is that semiconductor devices is shown using the section after production method the second groove of formation of the source electrode of the embodiment of the present invention
It is intended to.
Fig. 7 be semiconductor devices using the production method of the source electrode of the embodiment of the present invention remove remaining etching barrier layer and
Diagrammatic cross-section after dielectric layer.
Reference sign：
100- semiconductor bases；200- semiconductor devices；210- gate structures；211- first grid structures；212- second
Gate structure；213- third gate structures；201- interpolar dielectric layers；202- control gates；110- isolation structures；220- dielectric layers；
The concave surfaces 220a-；221- protective layers；230- etching barrier layers；The first gaps 10-；The second gaps 20-；The first grooves of 30-；40-
Two grooves.
Specific implementation mode
The production method and semiconductor devices of the source electrode of the present invention are made below in conjunction with the drawings and specific embodiments further
It is described in detail.According to following explanation, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very
Simplified form and non-accurate ratio is used, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.For
For the sake of clear, the label of all identical components will not be marked in each figure by attached drawing.
Term " first " " second " in the specification and in the claims etc. is used between similar element distinguish,
And it is not necessarily for describing certain order or time sequencing.It is appreciated that in the appropriate case, these terms so used can replace
It changes.Similar, if method described herein includes series of steps, and the sequence of these steps presented herein not must
Must be can perform the unique order of these steps, and the step described in some can be omitted and/or some are not described here its
He can be added to this method at step.
Fig. 1 is the flow diagram of the production method of the source electrode of the embodiment of the present invention.Referring to Fig.1, the source electrode of the present embodiment
Production method include the following steps：
S1：Rectangular at multiple gate structures on a semiconductor substrate, the multiple gate structure has the first gap and the
Two gaps, the width in first gap are less than the width in unidirectional second gap；
S2：Dielectric layer, the upper surface positioned at second gap of the dielectric layer are formed above the gate structure
For concave surface, it is the first groove to define the region that the concave surface surrounds；
S3：Etching barrier layer is formed, the etching barrier layer is made to fill up first groove；
S4：The dielectric layer is etched, until the dielectric layer in first gap is removed, while second gap
Bottom surface still covered by the dielectric layer；
S5：Etching is located at the semiconductor base in first gap to form the second groove；
S6：Remove the remaining etching barrier layer and the dielectric layer；
S7：Ion implanting is carried out, to form source electrode in the region of second groove.
As it can be seen that the production method of above-mentioned source electrode, do not use light shield, the first gap between gate structure it is semiconductor-based
The second groove is formd in bottom, the second groove is used as the source electrode of semiconductor devices by ion implanting, to eliminate one of light
Cover technique, advantageously reduces cost.
Fig. 2 to Fig. 7 be the production method of above-mentioned source electrode in the production process, the section of the semiconductor devices of the present embodiment shows
It is intended to.Next the production method and semiconductor devices of the source electrode of the present embodiment are illustrated in conjunction with Fig. 2 to Fig. 7.
It should be noted that the thickness and each layer of the material of each layer that is above-mentioned and will mentioning below, each layer
Generation type, different material, no may be used in only the embodiment of the present invention a example in the case of difference
Same thickness and different generation types, these should not be construed as limiting the invention.
Fig. 2 is that semiconductor devices forms the section signal after gate structure using the production method of the source electrode of the present embodiment
Figure.With reference to Fig. 2, implementation steps S1, multiple gate structures 210, the multiple gate structure are formed above semiconductor base 100
210 there is the first gap 10 and the second gap 20, the width D 1 in the first gap 10 to be less than the width in unidirectional second gap 20
Spend D2 (measurement word " width " herein refers to corresponding construction in the both ends distance for being parallel to 100 surface of semiconductor base).
The material of semiconductor base 100 can be silicon, germanium, SiGe or silicon carbide etc., can also be insulator overlying silicon
(SOI) either germanium on insulator (geoi) (GOI) or can also be III, V compounds of group such as other materials, such as GaAs.
In other embodiments, semiconductor base 100 may include the epitaxial layer of doping, and semiconductor base 100 can also be according to design
Demand injects certain doping particle to change electrical parameter, and in the present embodiment, semiconductor base 100 is undoped or light
Spend the semiconductor substrate for including silicon of p-type doping.
Semiconductor base 100 may include the various doped regions of the design requirement depending on semiconductor devices 200.Further
, in the present embodiment, isolation structure 110 is formed in semiconductor base 100 so that each region and/or semiconductor devices 200 is isolated.
Isolation structure 110 is, for example, shallow trench isolation (STI), isolation structure 110 include silica or other suitable materials be used as every
From medium.Making those skilled in the art of isolation structure 110 can carry out according to the prior art, as an example, be formed
STI includes forming opening in a silicon substrate by lithography and etching technique, and be somebody's turn to do using the filling of one or more spacer mediums
Opening.
Semiconductor devices 200 includes gate structure 210, and further, semiconductor devices 200 may further include storage
Unit and/or logic circuit, in the present embodiment, semiconductor devices 200 includes floating gate type flash memory, for floating gate type flash memory, grid
Structure 210 can be the stacked gate structure for including floating boom, contrasted between solid dielectric layer and control gate.Semiconductor devices 200 can also include source
Pole and drain electrode, the present embodiment are illustrated by taking floating gate type flash memory as an example mainly for the forming method of its source electrode.In other implementations
In example, other component can be added in semiconductor devices 200, and some components described below can be replaced or disappear
It removes.
Can by deposition, lithographic patterning, etch process or a combination thereof multiple grid are formed on semiconductor base 100
Pole structure 210, as an example, gate structure 210 include first grid structure 211, second grid structure 212 and third grid
Pole structure 213.In the cross-section structure shown in Fig. 2 to Fig. 7, semiconductor base 100 includes isolation structure 110, in isolation structure
The gate structure 210 that 110 tops are formed includes interpolar dielectric layer 201 and control gate 202, and interpolar dielectric layer 201 may include oxygen
It may include oxide layer-nitride layer-oxide layer (ONO) structure, control gate 202 to change layer and/or nitration case, interpolar dielectric layer 201
Material for example including polysilicon.It will be appreciated by those skilled in the art that being also formed with gate dielectric on semiconductor base 100
Layer and floating boom (not shown), gate dielectric includes dielectric material, such as silica, silicon oxynitride, silicon nitride, high k dielectric material
Material, other dielectric materials or a combination thereof.Floating boom is formed in above gate dielectric, interpolar dielectric layer 201 cover floating boom so that
Floating boom is isolated with control gate 202.But the gate structure 210 of the present invention is without being limited thereto, for partly leading including non-floating gate type flash memory
Body device 200, gate structure 210 can also include other component.
Design and Features for semiconductor devices 200 need, first grid structure 211, second grid structure 212 and the
The distance between three gate structures 213 can be different, in the present embodiment, first grid structure 211 and second grid structure 212 it
Between have the first gap 10, between second grid structure 212 and third gate structure 213 have the second gap 20, the first gap
10 width D 1 is less than the width D 2 in unidirectional second gap 20, also, the source area of semiconductor devices 200 is set to the
The drain region in one gap 10, semiconductor devices 200 is set to the second gap 20.
Fig. 3 is that semiconductor devices forms the section signal after dielectric layer using the production method of the source electrode of the embodiment of the present invention
Figure.With reference to Fig. 3, implementation steps S2, dielectric layer 220 is formed above gate structure 210, dielectric layer 220 is located at the second gap
20 upper surface is concave surface 220a, and it is the first groove 30 to define the region that concave surface 220a is surrounded.
Specifically, dielectric layer 220 be covered in gate structure 210, the first gap 10 and the second gap 20 semiconductor base
100 tops, the forming method of dielectric layer 220 includes chemical vapor deposition (CVD), physical vapour deposition (PVD) (PVD), atomic layer deposition
(ALD), high-density plasma CVD (HDPCVD), metallorganic CVD (MOCVD), plasma enhanced CVD (PECVD) or other
Suitable depositing operation.Preferably, dielectric layer 220 is covered in be formed in a manner of conformal deposited (conformal coating)
Have on the semiconductor base 100 of gate structure 210.The material of dielectric layer 220 is preferably carved with the spacer medium in isolation structure 110
Erosion selects relatively high material, so that subsequently in etch media layer 220, the influence to isolation structure 110 is smaller.As showing
Example, the material (i.e. spacer medium) of isolation structure 110 includes silica, and the material of dielectric layer 220 includes silicon nitride.
It can be according to the thickness of gate structure 210, the size adjusting dielectric layer 220 in the first gap 10 and the second gap 20
Degree, so that the upper surface that dielectric layer 220 is located at the second gap 20 is concave surface 220a, it is preferred that dielectric layer 220 is filled at this time
The upper surface that first gap 10, i.e. dielectric layer 220 are located at the first gap 10 is plane or convex surface, for the sake of convenient, defines concave surface
The region that 220a is surrounded is the first groove 30.
Further, in order to fill up the first gap 10 and the first groove 30 of formation above the second gap 20, preferred embodiment
In, the thickness of dielectric layer 220 is more than the half of the width D 1 in the first gap 10, and one of the width D 2 less than the second gap 20
Half.
The present embodiment is before forming dielectric layer 220, in order to which in subsequent etching dielectric layer 220, preferably control etching is whole
Point and protection gate structure 210, form protective layer 221, protective layer 221 covers multiple grids above semiconductor base 100
Structure 210.Protective layer 221 for example including 50 toThick silica.Protective layer 221 can select and 110 phase of isolation structure
Same material, so as to remove the protective layer 221 of the same area simultaneously in subsequent etching isolation structure 110.In other realities
It applies in example, protective layer 221 can also select other to have the material of higher etching selection ratio with dielectric layer 220.In other reality
It applies in example, protective layer 221 can not also be formed.
Fig. 4 a and Fig. 4 b are that semiconductor devices forms etching barrier layer using the production method of the source electrode of the embodiment of the present invention
Diagrammatic cross-section afterwards.With reference to Fig. 4 a and Fig. 4 b, implementation steps S3, etching barrier layer 230 is formed, etching barrier layer 230 is made to fill out
Full first groove 30.
Etching barrier layer 230 is used to fill up the first groove 30 to protect the dielectric layer 220 of lower section, etching barrier layer 230 excellent
The higher material of etching selection of choosing and dielectric layer 220 during subsequent etching dielectric layer 220 to protect Jie below
Matter layer 220.In the present embodiment, the material of etching barrier layer 230 includes silica, and the forming method of etching barrier layer 230 includes
Chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition, high-density plasma CVD, metallorganic CVD, plasma enhancing
CVD or other suitable depositing operations.Etching barrier layer 230 can be covered in 220 surface of dielectric layer other than the first groove 30
(as shown in fig. 4 a), it can also only be protected for example, by dry etching, wet etching or chemical mechanical grinding (CMP) technique
Stay the etching barrier layer 230 (as shown in Figure 4 b) in the first groove 30.
In another embodiment, etching barrier layer 230 includes anti-reflection coating (BARC) or the quarter of other and dielectric layer 220
Erosion selects relatively high photoresist or mask layer, and anti-reflection coating or photoresist can form a film using such as spin coating method and fill up first
Groove 30 may then pass through such as ashing method and only retain etching barrier layer 230 in the first groove 30.
In preferred embodiment, in step S3, it can make for example, by dry etching, wet etching or CMP process first recessed
The upper surface flush of dielectric layer 220 outside the upper surface of etching barrier layer 230 in slot 30 and the first groove 30 is (such as Fig. 4 b institutes
Show), to reduce the etch period in step S4 and to improve the regional choice effect of etching.
Fig. 5 is that semiconductor devices utilizes the dielectric layer in the first gap of production method removal of the source electrode of the embodiment of the present invention
Diagrammatic cross-section afterwards.With reference to Fig. 5, implementation steps S4, etch media layer 220, until the dielectric layer in the first gap 10 of removal
220, while the bottom surface in the second gap 20 is still covered by dielectric layer 220.
By step S1 to S3, dielectric layer 220 covers the bottom surface in the first gap 10 and the second gap 20, and is located at
The upper surface intermediate region of dielectric layer 220 in second gap 20 is covered with etching barrier layer 230, that is, Jie being exposed
Upper surface area of the matter layer 220 above the first gap 10 is more than the dielectric layer 220 being exposed above the second gap 20
Upper surface area, so as to pass through the selection and adjustment of etching technics so that the top of the first gap 10 is exposed
The etch rate of dielectric layer 220 is more than the etch rate for the dielectric layer 220 that 20 top of the second gap is exposed so that step
The etching process of S4 can take the lead in removing the dielectric layer 220 in the first gap 10.
Specifically, a kind of enforceable etching technics is wet etching, wherein etching solution for example including phosphoric acid (mainly for
The present embodiment dielectric layer 220 includes silicon nitride), since the upper surface area of 10 dielectric layer 220 of the first gap is more than between second
Be not etched in gap 20 barrier layer 230 covering dielectric layer 220 upper surface area, etching solution consumption it is very fast and more, to
220 etch rate of dielectric layer in first gap 10 is larger, and the dielectric layer 220 in the first gap 10 takes the lead in being removed.
Another enforceable etching technics is dry etching, and it includes such as HBr, Cl that can utilize2、SF6、O2、N2、NF3、
Ar、He、CF4、CH2F2One or more plasma etch process etch media layers as etching gas in the group of composition
220.The dry etching pointer has due to microcosmic load effect (microloading) or is imitated with the relevant load of etching depth-to-width ratio
The Etch selectivity caused by (aspect ratio dependent etching, ARDE) is answered, due on the first gap 10
The upper surface area of the dielectric layer 220 of side is larger (i.e. figure rarefaction), and the barrier layer 230 that is not etched above the second gap 20 is covered
The upper surface area of the dielectric layer 220 of lid is smaller (i.e. graphics intensive area), to which the dielectric layer 220 in the first gap 10 etches speed
Rate is larger, and the dielectric layer 220 in the first gap 10 takes the lead in being removed.
Step S4 selective under conditions of not needing light shield can perform etching dielectric layer 220.The present embodiment exists
220 lower section of dielectric layer forms matcoveredn 221, in step S4 etch media layers 220, play etch stopper work
With influence of the reduction to gate structure 210.After etching removes the dielectric layer 220 in the first gap 10, the half of the first gap 10
100 surface of conductor substrate covers matcoveredn 221.In a further embodiment, dielectric layer 220 is formed directly into semiconductor base
100 and the top of gate structure 210, then pass through step S4, the semiconductor base 100 in the first gap 10 is exposed.In the first gap
After dielectric layer 220 in 10 is removed, stop the etching to dielectric layer 220, at this time remaining dielectric layer in the second gap 20
220 bottom surfaces for still covering the second gap 20 (do not expose the protective layer 221 or semiconductor-based of 20 bottom surface of the second gap
Bottom 100).
Fig. 6 is that semiconductor devices is shown using the section after production method the second groove of formation of the source electrode of the embodiment of the present invention
It is intended to.With reference to Fig. 6, step S5 is executed, etches the semiconductor base 100 in the first gap 10 to form the second groove 40.
After completing step S4, the first gap 10 exposes the isolation junction of protective layer 221 or semiconductor base 100
Structure 110 (situation that protective layer 221 is not formed below dielectric layer 220).In the present embodiment, the first gap 10 exposes guarantor
Sheath 221, the isolation structure 110 being formed at below protective layer 221 in semiconductor base 100, at this time second gap 20
Semiconductor base 100 (or protective layer 221) is still covered by remaining dielectric layer 220, also, the upper table of remaining dielectric layer 220
Face is covered with etching barrier layer 230.
In the present embodiment, the material of protective layer 221 and isolation structure 110 includes silica, the material packet of dielectric layer 220
Silicon nitride is included, so as to using in the first gap of etching technics pair 10 bigger to the etching selection of silica and silicon nitride
The isolation structure 110 being exposed is performed etching can also first be removed between first in other embodiments with forming the second groove 40
After protective layer 221 in gap 10, then etches isolation structure 110 and correspond to the spacer medium in the first gap 10 to form the second groove
40。
It is preferred that use anisotropic dry method etch technology with the spacer medium of vertical etch corresponding region, to from right
Quasi- mode forms the second groove 40.Second groove 40 can run through isolation structure 110, the i.e. etching process of step S5 until exposure
Go out semiconductor base 100 containing until silicon semiconductor substrate.It the region of second groove 40 can be as partly leading in the present embodiment
The source area of body device 200.
In the present embodiment, the material of etching barrier layer 230 includes silica, that is, includes and isolation structure 110 and protective layer
221 identical materials, therefore, etching barrier layer 230 can be removed in step s 6；But it in a further embodiment, etches
The material on barrier layer 230 is different from the material of isolation structure 110 and protective layer 221, by step S5, above the second gap 20
Etching barrier layer 230 still retain, then can be removed by subsequent step.
Fig. 7 is after removing remaining etching barrier layer and dielectric layer using the production method of the source electrode of the embodiment of the present invention
Diagrammatic cross-section.With reference to Fig. 7, step S6 is executed, remaining etching barrier layer 230 and dielectric layer 220 are removed.
In certain embodiments, etching barrier layer 230 includes that anti-reflection coating (BARC) or other media-resistant layers 220 etch
The photoresist of technique, also, etching barrier layer 230 is not also removed during etching isolation structure 110, then can be with
After forming the second groove 40, photoresist is removed using such as ashing method, but not limited to this, remaining etching barrier layer
230 can select different etching technics according to constituent material difference, achieve the purpose that remove remaining etching barrier layer 230 i.e.
It can.
After forming the second groove 40 and removing remaining etching barrier layer 230, residue is also covered in the second gap 20
Dielectric layer 220 it is to be removed.The techniques such as wet etching, dry etching can be utilized to remove remaining dielectric layer 220.The present embodiment
Remaining dielectric layer 220 is removed using the wet etching including phosphoric acid etching liquid.But not limited to this, remaining dielectric layer 220 can
To select different etching technics according to constituent material difference, achieve the purpose that remove remaining dielectric layer 220.
After removing remaining etching barrier layer 230 and dielectric layer 220, step S7 can be executed, carries out ion implanting,
To form source electrode in the region of the second groove 40.
Step S7 can be with perpendicular to the angle on 100 surface of semiconductor base or to favour semiconductor base 100
The angle of normal to a surface carries out ion implanting in the second groove 40, to form semiconductor devices in the region of the second groove 40
200 source electrode.The ion implanting can also include the region in the second gap 20 being exposed, to form semiconductor devices 200
Drain electrode.In the present embodiment, the ion of the ion implanting includes one kind in N-shaped ion, such as arsenic (As), phosphorus or antimony (Sb)
Or combination.In a further embodiment, the ion of the ion implantation technology can also include p-type ion.It is complete in ion implanting
At later, the doping concentration of annealing process adjustment ion can be utilized.Ion implanting is carried out to form source electrode to the second groove 40
Method those skilled in the art be referred to the prior art progress, details are not described herein again.
The production method of the source electrode of the present embodiment can also be another including being filled in the second groove 40 after ion implantation
Dielectric material (such as silica), with the multiple gate structures in interval 210.
By step S1 to S7, the present embodiment is in the case of without using light shield, by being formed on semiconductor base 100
(its upper surface forms the first groove above the second interval 20 between gate structure 210 for gate structure 210, dielectric layer 220
30), filled up in the first groove 30 etching barrier layer 230, etch media layer 220 until between removal gate structure 210 the
Dielectric layer 220 (bottom surface in the second gap 20 is still covered by dielectric layer 220 at this time), the first gap 10 of etching in one gap 10
Semiconductor base 100 with formed the second groove 40, the remaining etching barrier layer 230 of removal and dielectric layer 220 and carry out from
Son injection in the region of the second groove 40 so that form source electrode.The production method of above-mentioned source electrode eliminates light shield technique, to
Advantageously reduce cost.
The present embodiment further includes a kind of semiconductor devices 200, as shown in fig. 7, the semiconductor devices 200 includes gate structure
210, source electrode and drain electrode, wherein source electrode is formed after the region of the second groove 40 carries out ion implanting, and the second groove 40 is located at
In isolation structure 110 (such as STI) in semiconductor base 100, the making of the source electrode includes the making of the source electrode of the present embodiment
Method.In addition, drain electrode can be formed after carrying out ion implanting to the second gap 20 after the remaining dielectric layer of removal 220.
Further, in the present embodiment, gate structure 210 include the gate dielectric formed on semiconductor base 100,
Floating boom, interpolar dielectric layer 201 and control gate 202.To, semiconductor devices 200 can be with floating gate type flash memory structure and
Function.But not limited to this, semiconductor devices 200 can also be that other include the four of grid, source electrode, drain electrode and substrate (bulk)
End-apparatus part, such as semiconductor devices 200 may include n-channel field-effect transistor (NFET), p-channel field-effect transistor
(PFET), mos field effect transistor (MOSFET), CMOS transistor (CMOS),
One or more of high voltage transistor, high frequency transistors.Semiconductor devices 200 can also include other members appropriate
Part and combination.
The manufacturing process of semiconductor devices 200 described in the present embodiment, source electrode includes source described in the present embodiment
The production method of pole need not use light shield, to advantageously reduce cost.
It should be noted that the embodiment in this specification is described by the way of progressive, what each some importance illustrated
All it is the difference with preceding sections, just to refer each other in identical and similar place between various pieces.For embodiment
For disclosed semiconductor devices, due to corresponding with the production method of source electrode disclosed in embodiment, so the comparison of description is simple
It is single, referring to the explanation of the production method to source electrode in place of correlation.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of interest field of the present invention,
Any those skilled in the art without departing from the spirit and scope of the present invention, may be by the methods and techniques of the disclosure above
Content makes possible variation and modification to technical solution of the present invention, therefore, every content without departing from technical solution of the present invention,
According to the technical essence of the invention to any simple modifications, equivalents, and modifications made by above example, this hair is belonged to
Bright technical solution.
Claims (10)
1. a kind of production method of source electrode, which is characterized in that including：
Rectangular at multiple gate structures on a semiconductor substrate, the multiple gate structure has the first gap and the second gap,
The width in first gap is less than the width in unidirectional second gap；
Dielectric layer is formed above the gate structure, the upper surface positioned at second gap of the dielectric layer is concave surface,
It is the first groove to define the region that the concave surface surrounds；
Etching barrier layer is formed, the etching barrier layer is made to fill up first groove；
The dielectric layer is etched, until the dielectric layer in first gap is removed, while the bottom surface in second gap
Still covered by the dielectric layer；
Etching is located at the semiconductor base in first gap to form the second groove；
Remove the remaining etching barrier layer and the dielectric layer；And
Ion implanting is carried out, to form source electrode in the region of second groove.
2. the production method of source electrode as described in claim 1, which is characterized in that form etching barrier layer, the etching is made to hinder
Barrier fills up the step of first groove and further includes：Make the upper surface of the etching barrier layer in first groove and described the
The upper surface flush of the dielectric layer outside one groove.
3. the production method of source electrode as described in claim 1, which is characterized in that form dielectric layer above the gate structure
Before, the production method of the source electrode further includes：Protective layer is formed, the protective layer covers the multiple gate structure.
4. the production method of source electrode as described in claim 1, which is characterized in that be formed with isolation junction in the semiconductor base
Structure, second groove run through the isolation structure.
5. the production method of source electrode as described in claim 1, which is characterized in that the thickness of the dielectric layer is more than described first
The half of the width in gap, and the half of the width less than unidirectional second gap.
6. such as the production method of source electrode described in any one of claim 1 to 5, which is characterized in that the material of the etching barrier layer
Material includes anti-reflection coating.
7. such as the production method of source electrode described in any one of claim 1 to 5, which is characterized in that the material of the etching barrier layer
Material includes silica.
8. the production method of source electrode as claimed in claim 7, which is characterized in that etching is located at described the half of first gap
The step of conductor substrate is to form the second groove further include：Remove the remaining etching barrier layer simultaneously.
9. such as the production method of source electrode described in any one of claim 1 to 5, which is characterized in that the gate structure includes floating
Grid.
10. a kind of semiconductor devices, which is characterized in that including gate structure, source electrode and drain electrode, wherein the making of the source electrode
Include the production method of source electrode as described in any one of claim 1 to 9.
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|---|---|---|---|---|
| US6075267A (en) * | 1996-02-28 | 2000-06-13 | Ricoh Company, Ltd. | Split-gate non-volatile semiconductor memory device |
| CN1689160A (en) * | 2002-08-30 | 2005-10-26 | 富士通株式会社 | Semiconductor storage device and its manufacturing method |
| US7550807B2 (en) * | 2005-05-10 | 2009-06-23 | Sharp Kabushiki Kaisha | Semiconductor memory |
| CN105336781A (en) * | 2014-08-07 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Source-drain structure and manufacturing method therefor |
| CN106653759A (en) * | 2016-12-23 | 2017-05-10 | 武汉新芯集成电路制造有限公司 | Flash memory structure and manufacturing method thereof |
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2018
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6075267A (en) * | 1996-02-28 | 2000-06-13 | Ricoh Company, Ltd. | Split-gate non-volatile semiconductor memory device |
| CN1689160A (en) * | 2002-08-30 | 2005-10-26 | 富士通株式会社 | Semiconductor storage device and its manufacturing method |
| US7550807B2 (en) * | 2005-05-10 | 2009-06-23 | Sharp Kabushiki Kaisha | Semiconductor memory |
| CN105336781A (en) * | 2014-08-07 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Source-drain structure and manufacturing method therefor |
| CN106653759A (en) * | 2016-12-23 | 2017-05-10 | 武汉新芯集成电路制造有限公司 | Flash memory structure and manufacturing method thereof |
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