CN108376676B - Metal interconnection structure with porous dielectric layer - Google Patents
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- CN108376676B CN108376676B CN201810166456.3A CN201810166456A CN108376676B CN 108376676 B CN108376676 B CN 108376676B CN 201810166456 A CN201810166456 A CN 201810166456A CN 108376676 B CN108376676 B CN 108376676B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
- H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
Abstract
The invention provides a metal interconnection structure with a porous medium layer, which comprises a through hole structure arranged in the porous medium layer, wherein the edge part of the through hole is lower than the upper surface of an interconnection line in a lower medium layer; a metal interconnection structure is arranged in the through hole structure and is in contact with the upper surface and part of the side surface of the interconnection line; a capping layer is over the metal interconnect structure, the capping layer having a portion located at a top surface of the metal interconnect structure and a portion located below the top surface in a second recess structure around the top surface.
Description
Technical Field
The present invention relates to semiconductor interconnect structures, and more particularly to a semiconductor interconnect structure having a porous low-K or ultra-low-K interlevel dielectric layer.
Background
The rapid development of semiconductor integrated circuit technology is continuously placing new demands on the development of interconnection technology. At present, in the latter stage of semiconductor manufacturing, in order to connect integrated circuits formed by respective components, a metal material having relatively high conductivity is generally used, but as the size of semiconductor devices is shrinking, the interconnect structure becomes narrower and narrower, resulting in higher and higher interconnect resistance. Copper interconnect technology has been widely used in the processing of technology nodes at 90nm and 65nm, by virtue of its excellent conductivity.
In the existing process of forming a copper wiring or a copper interconnect, a trench or a via is formed by etching an insulating dielectric layer, and then a copper conductive material is filled in the trench or the via. However, as the space between the metal lines is gradually reduced, the insulating dielectric layer for isolating the metal lines is also becoming thinner, which may cause adverse interaction or crosstalk between the metal lines. Research shows that the crosstalk can be effectively reduced by reducing the dielectric constant (K) of the insulating dielectric layer for isolating the metal connecting line layer, and the resistance-capacitance delay effect (RC delay) of the interconnection can also be effectively reduced by reducing the K value of the material of the interlayer dielectric layer.
However, the use of low-K or ultra-low-K insulating dielectric materials puts new demands on the semiconductor manufacturing process, and on one hand, in order to obtain the low-K material or the ultra-low-K material and reduce the K value of the material, the material generally used is a porous material, but the mechanical strength of the porous material is low, which results in that the insulating dielectric layer is easily damaged in the process of etching the through hole or the trench, and on the other hand, the porous insulating dielectric layer is easily penetrated by external materials to cause pollution and reduce the reliability of the material. Research has shown that an additional "plugging" process can be used to form a closed structure with an "open" pore structure exposed to the outside during etching of a porous dielectric layer, so as to prevent a defect that metal impurities easily enter pores during formation of an interconnection structure, but the additional process not only increases the cost, but also easily changes the morphology of a through hole or a trench formed by etching, so that the finally formed interconnection structure is not ideal in effect; in addition, in general, other interconnect structures are disposed below the via or the trench formed by the interlayer dielectric layer, so that the underlying interconnect structures are easily damaged during etching, and meanwhile, in a deposition or heat treatment step between the metal (usually copper) filled in the via or the trench and the underlying interconnect layer, peeling is easily caused by stress action induced, so that the metal filled in the via or the trench and the underlying interconnect are not well contacted, which greatly affects the stability and reliability of the semiconductor device.
Meanwhile, after a metal interconnection structure (usually copper metal) is formed, in order to enhance the electromigration characteristic, it has been proved that the electromigration characteristic can be improved by more than 100 by replacing the Cu/dielectric interface with a Cu/metal interface, and a material of a metal cap layer usually selected is a metal containing Co (such as CoWP), but in a cleaning step after the interconnection structure is formed subsequently, diluted hydrofluoric acid is usually adopted, which corrodes the metal containing Co, and causes the performance of the device to be reduced.
In view of the above, it is desirable to provide an interconnect structure having a porous low-K or ultra-low-K interlayer dielectric layer, which, on one hand, reduces damage or contamination to the interlayer dielectric layer, and simultaneously prevents damage to the underlying interconnect structure, and when improving electromigration performance, the cap layer technology should have certain stability and can prevent acid corrosion.
Disclosure of Invention
The summary of the invention section introduces a series of concepts in a simplified form that are described in detail in the detailed description section.
The technical problem to be solved by the invention is to provide a semiconductor structure with a porous dielectric layer, which prevents the damage or pollution to an interlayer dielectric layer in the preparation process, prevents the damage to an interconnection line structure below, increases the firmness between metal filled in the interlayer dielectric layer and the interconnection line below, does not need an additional step of blocking the porous interlayer dielectric layer, reduces the cost, and has a cap layer structure with stable performance to improve the electromigration performance and the stability and the reliability of a semiconductor device.
In order to solve the above problem, a metal interconnection structure having a porous dielectric layer is characterized by comprising the following structures: the interconnection line structure is positioned in the lower dielectric layer; an etch stop detection layer rich in nitrogen located on the lower dielectric layer; a porous dielectric layer on the nitrogen-rich etch-stop detection layer; the through hole structure is arranged in the porous dielectric layer, the through hole extends downwards to the upper part of the interconnection line, the edge part of the through hole is lower than the upper surface of the interconnection line, a first groove structure is formed around the interconnection line in the lower dielectric layer, the through hole structure in the porous dielectric layer is formed by femtosecond laser etching, and the exposed hole structure is sealed by locally melting the exposed hole structure in the porous dielectric layer in the etching process; a metal interconnection structure is arranged in the through hole structure, the metal interconnection structure is contacted with the upper surface and part of the side surface of the interconnection line, and the metal interconnection structure comprises a part positioned in the first groove structure; the metal interconnection structure is provided with a capping layer above, and the capping layer is provided with a part located on the top surface of the metal interconnection structure and a part located below the top surface and located in a second groove structure around the top surface.
Furthermore, the material of the interconnection line structure is copper, and the material of the metal interconnection structure in the through hole structure is copper.
Further, the porous medium layer is made of a low-K or ultralow-K material.
Further, the nitrogen-rich etch stop detection layer is made of nitrogen-containing silicon oxide.
Further, the capping layer is a nitrogen-containing metal layer, wherein the metal is Ir or Ru.
Further, the metal interconnection structure in the through hole has a length extending downward from a contact portion with a side surface of the interconnection line, that is, the depth of the first groove is about 5 to 20 nm.
Further, a downward length of a portion of the capping layer below the top surface of the metal interconnect structure, that is, a depth of the second recess is about 5-20 nm.
Furthermore, the surface of the interconnection line structure is subjected to hydrogen reduction treatment, and the first groove structure in the lower dielectric layer is formed by over-etching in a hydrogen atmosphere.
Further, the second groove is formed by femtosecond laser etching.
Further, a barrier layer is further included in the first groove, and the barrier layer is located between the metal interconnection structure and the lower dielectric layer; and a barrier layer is also arranged in the second groove and is positioned between the capping layer and the porous medium layer.
Compared with the prior art, the invention has the following beneficial technical effects:
1. with ultra-short pulse times (typically 10)-15m/s) femtosecond laser has super-strong high focusing capability, the femtosecond laser can concentrate all energy thereof in a very small action area quickly and accurately, can etch quickly and accurately during etching, generates few side effects, does not need a procedure of cleaning and removing residues after etching, melts a dielectric layer at the edge of an exposed porous structure at high temperature generated during etching by the femtosecond laser, can block the exposed open pore structure by the molten dielectric layer, namely carries out closed treatment on the open pore structure during etching, and does not need to adopt extra stepsStep one, a through hole structure of a porous dielectric layer in the metal interconnection structure is formed by femtosecond laser etching without additional sealing treatment of the hole structure;
2. in order to prevent the surface of the interconnection line from being oxidized and reduce an oxide layer possibly formed on the surface of the interconnection line, hydrogen is introduced for reduction when the interconnection line layer is etched and exposed, and the hydrogen is continuously introduced after the interconnection line is exposed, even if the surface of the interconnection line has the oxide layer (usually copper oxide) in the previous step, the introduced hydrogen reduces the oxide layer into copper, namely the surface of the lower interconnection line structure in the metal interconnection structure is the surface subjected to hydrogen reduction treatment; and a first groove structure is arranged in the lower dielectric layer around the interconnection line structure, and the first groove structure is formed by over-etching in a hydrogen atmosphere. When the interconnection metal is filled, the interconnection metal is filled in the groove, and the formed interconnection metal wraps the interconnection line below the groove, so that the contact area is increased, and the contact firmness is improved, so that the stability and the reliability are improved.
3. The material of the capping layer above the metal interconnection structure is a nitrogen-containing metal layer, wherein the metal is Ir or Ru, the Ir or Ru metal is more stable than metal Co, the Ir or Ru metal is not corroded even in the subsequent cleaning process, meanwhile, the oxidation can be prevented, the electromigration characteristic of a Cu/metal interface can be improved, and in order to prevent the capping layer from falling off from the metal interconnection structure, the capping layer is formed on the top surface of the metal interconnection structure and is also formed in a second groove surrounding the periphery of the top surface of the metal interconnection structure, a clamping structure is formed, the contact area is increased, and the contact stability is improved.
In conclusion, the method can not only reduce the preparation process, but also improve the stability and reliability of the semiconductor device.
Drawings
FIG. 1 is a schematic diagram of a semiconductor interconnect structure in an embodiment of the invention;
fig. 2a shows the "open" hole structure exposed at the opening of the trench by conventional dry etching, and fig. 2b shows the "sealed" state of the hole structure at the opening of the trench by femtosecond laser etching according to the present invention.
Detailed Description
In the following description, the method for fabricating a semiconductor interconnect structure according to the present invention is described in further detail with reference to the accompanying drawings and examples, in order to provide a more thorough understanding of the present invention. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly facilitating the description of the embodiments of the present invention. In the embodiments, some technical features well known in the art are not described in order to avoid confusion with the present invention.
Referring to fig. 1, the metal interconnection structure of the present invention includes an interconnection line structure 2 located in an underlying dielectric layer 1. The lower dielectric layer 1 may further include a substrate base structure, the substrate base structure may be a semiconductor substrate common in the art, such as a silicon substrate or an SOI substrate structure, the lower dielectric layer 1 may be formed of an insulating material such as silicon oxide, silicon oxynitride, black diamond, or a methylsilicate compound, the interconnection line 2 in the lower dielectric layer may be a copper interconnection line, and the formation manner of the interconnection line 2 is a formation manner common in the art, which is not described herein again;
and the etching stop detection layer 3 which is rich in nitrogen and is positioned on the lower dielectric layer 1. And an etching termination detection layer 3 rich in nitrogen is formed on the lower dielectric layer 1, and the etching termination detection layer 3 covers the lower dielectric layer 1 and covers the interconnection line 2. The material of the etching termination detection layer rich in nitrogen is silicon oxide containing nitrogen, the forming process of the etching termination detection layer 3 rich in nitrogen is a chemical vapor deposition process, nitrogen or ammonia gas is introduced in the deposition process to improve the nitrogen content in the silicon oxide so as to be different from the nitrogen content in a subsequently formed substance (such as a subsequently formed dielectric layer) and facilitate the detection in the subsequent etching step for forming the through hole;
also included is a porous dielectric layer 4 on the nitrogen-rich etch-stop detection layer 3. A porous dielectric layer 4 is formed on the nitrogen-rich etch stop detection layer 3. The porous medium layer 4 is made of low-K or ultralow-K material, the low-K or ultralow-K porous medium layer can be made of silicon-based high polymer material with a dielectric constant value (K value) of 2.2-2.9, such as HSQ, MSQ and the like, and can also be made of porous SiLK, the method for forming the low-K or ultralow-K porous medium layer can be a spin coating process, and the thickness of the formed porous medium layer is 200-300 nm;
the through hole structure in the porous dielectric layer is formed by femtosecond laser etching, and the exposed hole structure is sealed by locally melting the exposed hole structure in the porous dielectric layer in the etching process. Specifically, when the through hole structure in the porous dielectric layer is formed, after the porous dielectric layer 4 is formed, the low-K buffer layer is formed on the porous dielectric layer 4, the low-K buffer layer may be made of porous silicon dioxide, and has a good contact performance with the porous dielectric layer below and a good contact performance with the metal hard mask layer above, and is formed between the metal hard mask layer and the porous dielectric layer, so that the functions of buffering transition and improving adhesion can be achieved. Forming a metal hard mask layer on the low-K buffer layer, wherein the thickness of the metal hard mask layer is 15-20nm, the low-K buffer layer and the metal hard mask layer can be formed by adopting a CVD or PVD method, the metal hard mask can be made of TaN, TiN or Ti and the like, a photoresist layer is coated on the metal hard mask layer, and the photoresist layer with an opening pattern is formed through an exposure and development process, wherein the opening pattern is aligned with the lower interconnection line structure, the width of the cross section of the opening is larger than the width of the cross section of the interconnection line, the width of the opening can be 1-50nm wider than the width of the cross section of the interconnection line, and the thickness of the photoresist layer with the opening pattern can be 250-300 nm; and then, taking the photoresist layer as a mask, carrying out first etching on the metal hard mask layer and the low-K buffer layer below the photoresist layer, wherein the first etching adopts oxygen plasma etching with first source power, the oxygen plasma etching is carbon dioxide plasma etching, and the metal hard mask layer and the low-K buffer layer are etchedA first opening is formed on the layer, and after the first opening structure is formed, the method further comprises the step of removing the residual photoresist. Next, an etching step for the porous dielectric layer is performed, as shown in fig. 2a, which is a schematic diagram of an existing dry etching, when an opening is formed in the porous dielectric layer by dry etching (usually, plasma etching), the porous dielectric layer (a dotted line portion in fig. 2 a) on both sides of the opening is etched, because the porous dielectric layer usually has a plurality of pore structures, and when the opening is formed by etching, the pore structures are also etched, that is, for example, a plurality of pore structures with exposed openings (the interior of the porous dielectric layer is the interior of the porous dielectric layer, and the appearance of the interior of the porous dielectric layer is not shown) are formed at an etching boundary in an enlarged portion, and the opened pore structures may have a plurality of impurities remaining in a subsequent cleaning step and a subsequent deposition step, and the impurities may enter the porous dielectric layer in a subsequent high-temperature process, and have a great influence on a dielectric constant of the porous dielectric layer, ultimately affecting device performance. The invention adopts the etching process of the femtosecond laser, the femtosecond laser is different from the traditional dry etching (plasma is adopted to bombard the surface to be etched), and the femtosecond laser has ultra-short pulse time (generally 10 times)-15m/s), has super-strong high focusing capacity, can quickly and accurately concentrate all energy thereof in a small action area, can quickly and accurately etch during etching, rarely generates side effects, and does not need a procedure of cleaning and removing residues after etching; the femtosecond laser melts the porous medium layer at the edge of the exposed porous structure at high temperature generated during etching, the melted porous medium layer can block the exposed open pore structure, namely, the open pore structure is subjected to closed processing in the etching process without adopting additional steps, such as the structure shown in fig. 2b, and the enlarged structure is the etched boundary after etching, and the open pore structure is blocked to a certain extent; after the porous dielectric layer is etched to form an opening, through detection, when the etching termination detection layer rich in nitrogen is etched, the femtosecond laser etching is stopped, nitrogen plasma is adopted to carry out third etching, and hydrogen is introduced to reduce in the etching processIn the gas, because the etching stop detection layer 3 is a nitrogen-rich material, a large amount of nitrogen-containing substances (the metal hard mask layer and the interlayer dielectric layer are both nitrogen-free substances, and even if nitrogen exists, the nitrogen is a small amount) are detected in the exhaust gas of etching, namely the etching stop detection layer is etched, and ammonia plasma etching is adopted in nitrogen plasma etching. The source power value of the third etching is larger than that of the first etching, so that the phenomenon that the edge of the photoresist opening is deformed under the action of ion bombardment and the subsequent opening appearance is influenced due to the high-power etching step in the etching process with the photoresist opening as a mask can be prevented, meanwhile, in the third etching step, the opening with the metal hard mask is used as the mask, the material of the opening is harder than that of the photoresist, the high-power etching cannot deform the opening appearance, and the high-power etching step can shorten the etching time. Introducing hydrogen in the etching process, mainly preventing the copper interconnection line from being oxidized by residual oxygen in the etching cavity after the interconnection line is exposed, continuously introducing the hydrogen after the interconnection line below the copper interconnection line is exposed, finally obtaining an opening structure in the interlayer dielectric layer, wherein the time of continuously introducing the hydrogen is 1-10min, and the continuously introducing the hydrogen mainly reduces an oxide layer which is inevitably oxidized on the surface of the copper interconnection line in the previous step so as to reduce the resistance of the copper interconnection line; in the process of forming a second opening structure by etching, over-etching is carried out on the lower dielectric layer, and a first groove structure is formed around the interconnection line;
the method further comprises the step of providing a metal interconnection structure 5 in the through hole structure, wherein the metal interconnection structure 5 is in contact with the upper surface and part of the side surface of the interconnection line, and the metal interconnection structure comprises a part located in the first groove structure. The specific forming process comprises the steps of forming a barrier layer, a seed crystal layer and a metal layer in a through hole structure in a formed porous dielectric layer and a first groove structure around a formed interconnection line, wherein the metal layer can be made of copper, the barrier layer can be made of TiN, the metal layer can be formed by adopting an electroplating process, then removing the redundant copper metal layer on the surface of the porous dielectric layer outside the through hole structure through a CMP (chemical mechanical polishing) process to form a metal interconnection structure, the filled interconnection metal layer can be filled in the first groove to further wrap the interconnection line below the through hole structure, so that the contact area is increased, the contact firmness is improved, the downward extending length of the contact part of the metal interconnection structure in the through hole and the side surface of the interconnection line is long, and the depth of the first groove is 5-20 nm;
a capping layer 6 is also included over the metal interconnect structure, the capping layer 6 having a portion located at a top surface of the metal interconnect structure 5 and a portion located below the top surface in a second recess structure around the top surface. The specific forming process comprises the steps of forming a second groove structure around the surface of the metal interconnection structure through femtosecond laser etching, and then forming a capping layer 6 after forming a barrier layer in the second groove, wherein the capping layer is located at the part below the top surface of the metal interconnection structure and extends downwards for a length, namely the depth of the second groove is 5-20 nm. The material of the capping layer is a nitrogen-containing metal layer, wherein the metal is Ir or Ru, the Ir or Ru metal is more stable than metal Co, the Ir or Ru metal is not corroded in the subsequent cleaning process, meanwhile, the oxidation can be prevented, the electromigration characteristic of a Cu/metal interface can be improved, and in order to prevent the capping layer from falling off from the metal interconnection structure, the capping layer is formed on the top surface of the metal interconnection structure and is also formed in a second groove surrounding the periphery of the top surface of the metal interconnection structure, a clamping structure is formed, the contact area is increased, and the contact stability is improved.
In conclusion, the semiconductor interconnection structure with the porous dielectric layer can reduce the preparation procedures, does not need extra steps of blocking an opened pore structure which is exposed more, can prevent the surface of a metal interconnection line from being oxidized, can improve the contact area between interconnection metal and the metal interconnection line below and the contact firmness of the interconnection metal and the metal interconnection line, and meanwhile has a stable capping layer structure to improve the electromigration performance and the stability and the reliability of a semiconductor device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. In addition, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many more modifications and variations can be made in accordance with the teachings of the present invention, and these modifications and variations fall within the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (7)
1. A metal interconnection structure with a porous dielectric layer, comprising the following structure:
the interconnection line structure is positioned in the lower dielectric layer;
an etch stop detection layer rich in nitrogen located on the lower dielectric layer;
a porous dielectric layer on the nitrogen-rich etch-stop detection layer;
the through hole structure is arranged in the porous medium layer and extends downwards to the upper part of the interconnection line, the edge part of the through hole structure is lower than the upper surface of the interconnection line, a first groove structure is formed around the interconnection line in the lower medium layer, the through hole structure in the porous medium layer is formed by femtosecond laser etching, and the exposed hole structure is sealed by locally melting the exposed hole structure in the porous medium layer in the etching process; a metal interconnection structure is arranged in the through hole structure, the metal interconnection structure is contacted with the upper surface and part of the side surface of the interconnection line, and the metal interconnection structure comprises a part positioned in the first groove structure; a capping layer is arranged above the metal interconnection structure, and the capping layer is provided with a part positioned on the top surface of the metal interconnection structure and a part positioned below the top surface and positioned in a second groove structure around the top surface;
the sealing layer is a nitrogen-containing metal layer, and the metal layer is made of Ir or Ru; the surface of the interconnection line structure is subjected to hydrogen reduction treatment, and the first groove structure in the lower dielectric layer is formed by over-etching in a hydrogen atmosphere; the second groove structure is formed by femtosecond laser etching.
2. The metal interconnect structure of claim 1, wherein the material of the interconnect structure is copper, and the material of the metal interconnect structure within the via structure is copper.
3. The metal interconnect structure of claim 1, wherein said porous dielectric layer is a low-K or ultra-low-K material.
4. The metal interconnect structure of claim 1 wherein said nitrogen-rich etch stop detection layer is a nitrogen-containing silicon oxide.
5. The metal interconnection structure according to claim 1, wherein a portion of the metal interconnection structure in the via structure contacting a side surface of the interconnection line extends downward by a length, that is, a depth of the first recess structure is 5 to 20 nm.
6. The metal interconnect structure of claim 1, wherein a portion of the capping layer below a top surface of the metal interconnect structure extends downward in a length of 5-20nm, i.e., a depth of the second recess structure.
7. The metal interconnect structure of claim 6, further comprising a barrier layer in said first trench structure, said barrier layer being located between said metal interconnect structure and an underlying dielectric layer; the second groove structure also comprises a barrier layer, and the barrier layer is positioned between the capping layer and the porous medium layer.
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| US10090241B2 (en) * | 2015-05-29 | 2018-10-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device, package structure and method of forming the same |
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| CN101278386A (en) * | 2005-09-30 | 2008-10-01 | 先进微装置公司 | Technique for forming a copper-based metallization layer including a conductive capping layer |
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