CN108376676A - A kind of metal interconnection structure with porous medium layer - Google Patents
A kind of metal interconnection structure with porous medium layer Download PDFInfo
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- CN108376676A CN108376676A CN201810166456.3A CN201810166456A CN108376676A CN 108376676 A CN108376676 A CN 108376676A CN 201810166456 A CN201810166456 A CN 201810166456A CN 108376676 A CN108376676 A CN 108376676A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
- H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
Abstract
The present invention provides a kind of metal interconnection structures with porous medium layer, it includes to have through-hole structure in porous medium layer, the marginal portion of through-hole is less than the upper surface of the interconnection line in underlying dielectric layers, the first groove structure is formed with around interconnection line in underlying dielectric layers, through-hole structure in porous medium layer etches to be formed using femtosecond laser, and the local melting of the pore structure of exposure in the porous medium layer is made to make the pore structure sealing of exposure in etching process；There is metal interconnection structure, metal interconnection structure to be contacted with the interconnection line upper surface and component side surface in through-hole structure；There is capping layer, the part and the part in top surface the second groove structure below positioned at around top surface that capping layer has the top surface positioned at metal interconnection structure above metal interconnection structure.
Description
Technical field
The present invention relates to semiconductor interconnection structures, having porous low K or ultralow K interlayer dielectric layers more particularly to one kind
Semiconductor interconnection structure.
Background technology
The rapid development of semiconductor integrated circuit technology constantly proposes new requirement to interconnection technique development.Currently, half
In the last part technology of conductor manufacture, in order to connect the integrated circuit of all parts composition, usually using with opposite high conductivity
Metal material, but as the size of semiconductor devices is constantly shunk, interconnection structure becomes more and more narrow, so as to cause interconnection electricity
It hinders higher and higher.Copper is widely used to the technology node of 90nm and 65nm by means of its excellent electric conductivity, copper interconnection technology
Technique in.
During existing formation thin copper film or copper-connection, groove or through-hole are formed by etching insulating medium layer, so
Afterwards copper conductive material is filled in groove or through-hole.However since the space between metal connecting line is gradually reduced, it is used for
Insulating medium layer between isolating metal line also thins down, and can cause occur not between metal connecting line in this way
The interaction or crosstalk of profit.It has now been discovered that, reduces the dielectric constant of the insulating medium layer for isolating metal connecting line layer
(K), this crosstalk can be effectively reduced, meanwhile, the resistance of interconnection can also effectively be reduced by reducing the K values of inter-level dielectric layer material
Capacitance delays effect (RC delay).
However, the use of low K or ultralow K insulating dielectric materials puts forward semiconductor fabrication process new requirement, one
Aspect reduces the K values of material to obtain low-K material or ultra low-K material, and commonly used material is porous material, however more
The mechanical strength of Porous materials is relatively low, this is resulted in during etching through hole or groove, and insulating medium layer is easy to be destroyed, separately
On the one hand, porous insulating medium layer is easy to be penetrated by foreign material, and pollutes, and reduces the reliability of material.
It learns research to point out, can will be exposed to external " open when etching porous medium layer by additional " closure " technique
" pore structure forms closed structure, to prevent the metal impurities when forming interconnection structure to be easily accessible the defects of hole, however
Additional technique not only causes the increase of cost, and the pattern for being also easy to the through-hole or groove that are formed to etching changes, and causes most
End form at interconnection structure effect be not highly desirable；And the through-hole or groove under normal conditions, formed in interlayer dielectric layer
Lower section is corresponding with other interconnecting constructions, in etching, is easy to cause to damage to the interconnecting construction of lower section, meanwhile, logical
The metal (being usually copper) filled in hole or groove between the interconnection layer of lower section in deposition or heat treatment step, answer by initiation
Force effect is easy to happen stripping, keeps the contact between the metal being filled in through-hole or groove and the interconnection line of lower section bad, this
A bit can all prodigious influence be caused on the stability of semiconductor devices and reliability.
Meanwhile after forming metal interconnection structure (being usually copper metal), in order to enhance electromigration characteristic, it has proved that
Cu/ metal interfaces replace Cu/ dielectric interfaces that can improve 100 or more electromigration characteristic, and the metal capping layer usually selected
Material is the metal (such as CoWP) containing Co, but in the cleaning step after being subsequently formed interconnection structure, generally use is dilute
The hydrofluoric acid released can cause device performance to decline the metal erosion of Co.
In view of the above problems, it is desirable to provide a kind of mutual connection of the interlayer dielectric layer with porous low K or ultralow K
On the one hand structure will reduce damage or pollution to interlayer dielectric layer, while also to prevent the damage to the interconnecting construction of lower section,
And when improving electric migration performance, the technology of cap layers will also have certain stability, can prevent acid corrosion.
Invention content
A series of concept of reduced forms is introduced in this part of the disclosure, this will carry out detailed in specific implementation part
Explanation.
The technical problem to be solved by the present invention is to provide a kind of semiconductor structure with porous medium layer, prevent from preparing
It to the damage of interlayer dielectric layer or pollution in journey, and prevents from that the interconnecting construction of lower section is caused to damage, while increasing interlayer Jie
Fastness between the metal filled in matter layer and lower section interconnection line, and without additional to porous interlayer dielectric layer
" closure " step reduces cost, and the cap layer structure with stability improves semiconductor devices to improve electric migration performance
Stability and reliability.
To solve the above problems, a kind of metal interconnection structure with porous medium layer, which is characterized in that including following knot
Structure：Interconnecting construction in underlying dielectric layers；The etch-stop detection layers rich in nitrogen on the underlying dielectric layers；
Porous medium layer in the etch-stop detection layers rich in nitrogen；There is through-hole structure in the porous medium layer,
The through-hole extends downwardly into above the interconnection line, and the marginal portion of the through-hole is less than the upper surface of the interconnection line,
The first groove structure is formed with around interconnection line in underlying dielectric layers, the through-hole structure in the porous medium layer uses femtosecond
Laser ablation is formed, and the local melting of the pore structure of exposure in the porous medium layer is made to make described in exposure in etching process
Pore structure seals；There is metal interconnection structure, the metal interconnection structure and the interconnection line upper table in the through-hole structure
Face and component side surface contact, and metal interconnection structure includes the part in first groove structure；It is described
There is above metal interconnection structure capping layer, the capping layer have the top surface positioned at the metal interconnection structure part and
Part in the top surface the second groove structure below positioned at around the top surface.
Further, the material of the interconnecting construction is copper, the metal interconnection structure in the through-hole structure
Material is copper.
Further, the porous medium layer is low K or ultra low-K material.
Further, the etch-stop detection layers rich in nitrogen are nitrogenous silica.
Further, the capping layer is nitrogenous metal layer, wherein the metal is Ir or Ru.
Further, the metal interconnection structure in the through-hole and interconnection line side surface contact portion are to downward
The length stretched, that is, the depth of first groove is about 5-20nm.
Further, the capping layer is located at the downward length of the top surface part below of the metal interconnection structure
Degree, that is, the depth of second groove is about 5-20nm.
Further, the surface of the interconnecting construction is the surface handled by hydrogen reducing, and the lower layer is situated between
Over etching is formed first groove structure in matter layer in a hydrogen atmosphere.
Further, second groove is to etch to be formed using femtosecond laser.
Further, further include having barrier layer in first groove, the barrier layer be located at metal interconnection structure with
Between lower dielectric layer；Further include having barrier layer in second groove, barrier layer is located at the capping layer and porous Jie
Between matter layer.
Compared with prior art, the present invention has beneficial technique effect below：
1, it (is usually 10 to have the ultrashort pulse time-15M/s femtosecond laser) has superpower high focusing power, femtosecond
Laser all can fast and accurately concentrate on its energy in the zone of action of very little, can fast and accurately be carved in etching
Erosion, and side effect is seldom generated, the process after having etched without cleaning removal residue, femtosecond laser is generated in etching
High temperature the dielectric layer of the edge of exposed porous structure is melted, the dielectric layer of fusing can be by exposed opening
Pore structure is blocked, that is, has just carried out closed processing to the pore structure of opening in etching process, without using
The through-hole structure of additional step, the porous dielectric layer in the metal interconnection structure etches to be formed using femtosecond laser, and
Seal treatment without additional pore structure；
2, the oxidation on interconnection line surface in order to prevent, and the oxide layer that will likely be formed in interconnection line surface is gone back
Original is passed through hydrogen and is restored, after exposing interconnection line, is continually fed into hydrogen when etching exposes interconnection line layer, even if
Interconnection line surface has oxide layer (being usually copper oxide) in previous step, and the hydrogen being passed through is reduced to copper, that is, gold
The surface for belonging to the interconnecting construction of the lower section in interconnection structure is the surface handled by hydrogen reducing；And in the medium of lower section
There is the first groove structure around interconnecting construction in layer, over etching is formed the first groove structure in a hydrogen atmosphere.It is filling
When interconnecting metal, interconnection metal is filled in groove, and the interconnection line below the interconnection metal " package " of formation is not only increased and connect
Contacting surface is accumulated, and improves the fastness of contact, to improve stability and reliability.
3, the material of the capping layer of the top of metal interconnection structure is nitrogenous metal layer, wherein the metal be Ir or
Ru, Ir or Ru metal are stablized than metal Co, will not corrode in follow-up cleaning process, while being also prevented from oxygen
Change, the electromigration feature of Cu/ metal interfaces can be improved, and capping layer is fallen off with metal interconnection structure in order to prevent,
And the top surface that capping layer is not made only in metal interconnection structure is also formed in around metal interconnection structure top surface
In second groove, the structure of engaging is formed, contact area is not only increased, also improves contact stabilization.
To sum up, this method can not only reduce preparation section, and can improve the stability of semiconductor devices and reliable
Property.
Description of the drawings
Fig. 1 is the semiconductor interconnection structure schematic diagram in the embodiment of the present invention；
For using " opening " pore structure of the opening exposure of groove when traditional dry etching, Fig. 2 b shown in Fig. 2 a
Shown in be in the present invention using femtosecond laser etching when groove opening at pore structure " sealing " state.
Specific implementation mode
In the following description, in conjunction with the accompanying drawings and embodiments to the preparation method of semiconductor interconnection structure proposed by the present invention
It is further to be described in detail, by concrete details in order to provide more thorough understanding of the invention.It should be noted that
Attached drawing is all made of very simplified form and uses non-accurate ratio, only to convenient, clearly aid illustration is of the invention
The purpose of embodiment.In embodiment, in order to avoid obscuring with the present invention, for some technical characteristics well known in the art
It is not described.
Please refer to the metal interconnection structure of the attached present invention shown in FIG. 1 comprising have the interconnection in underlying dielectric layers 1
Cable architecture 2.Can also include underlay substrate structure below underlying dielectric layers 1, underlay substrate structure can be in this field
Common semiconductor substrate, such as silicon substrate or SOI substrate structure, lower dielectric layer 1 can be silica, silicon oxynitride, black
The insulating materials such as diamond or methane-siliconic acid salt compound are formed, and the interconnection line 2 in lower dielectric layer can be copper interconnecting line, interconnection
The generation type of line 2 is generation type common in this field, and details are not described herein；
Further include the etch-stop detection layers 3 rich in nitrogen having on the underlying dielectric layers 1.In the layer dielectric
The etch-stop detection layers 3 rich in nitrogen are formed on layer 1, etch-stop detection layers 3 are covered on lower dielectric layer 1, and are covered
Lid interconnection line 2.The material of etch-stop detection layers therein rich in nitrogen is nitrogenous silica, the etching therein rich in nitrogen
The formation process of termination detection layer 3 is chemical vapor deposition depositing operation, and nitrogen or ammonia are passed through in deposition process, to improve
Nitrogen content in silica, to be different from the substance being subsequently formed the nitrogen content of (dielectric layer being such as subsequently formed), in order to
Subsequently convenient for detection in the etch step for forming through-hole；
It further include the porous medium layer 4 having in the etch-stop detection layers 3 rich in nitrogen.In the etching rich in nitrogen
Porous medium layer 4 is formed on termination detection layer 3.Porous medium layer 4 therein be low K either the low K of material of ultralow K or
The material of ultralow K porous medium layers can be the silicon substrate high molecular material that dielectric constant values (K values) are 2.2-2.9, such as HSQ, MSQ
Deng, can also be porous SiLK, formed the porous medium layer of low K or ultralow K method can be spin coating proceeding, formation it is more
The thickness of hole dielectric layer is 200-300nm；
Further include having that there is through-hole structure, the through-hole are extended downwardly into the porous medium layer on the interconnection line
Side, the marginal portion of the through-hole are less than the upper surface of the interconnection line, are formed with around the interconnection line in underlying dielectric layers
First groove structure, the through-hole structure in the porous medium layer etch to be formed using femtosecond laser, and institute is made in etching process
Stating the local melting of the pore structure of exposure in porous medium layer makes the pore structure sealing of exposure.Specifically, porous being formed
When through-hole structure in dielectric layer, after forming porous medium layer 4, low K buffer layers are formed on porous medium layer 4, low K is slow
The material for rushing layer can be porous silica, have a good contact performance with the porous medium layer of lower section, and with
The metal hard mask layer of top also has good contact performance, is formed between metal hard mask layer and porous medium layer,
It can play the role of buffering transition and improve adhesiveness.It is formed with metal hard mask layer on low K buffer layers, metallic hard is covered
The thickness of mold layer is 15-20nm, and the method shape of CVD or PVD may be used in low K buffer layers therein and metal hard mask layer
At the materials such as TaN, TiN or Ti may be used in metal hard mask, and photoresist layer is coated in metal hard mask layer, through overexposure
Developing process forms the photoresist layer with patterns of openings, wherein the interconnecting construction of patterns of openings alignment lower section, and
The width in the section of opening is more than the cross-sectional width of interconnection line, and the width of opening can be wider 1-50nm than interconnection line cross-sectional width,
The thickness of photoresist layer with patterns of openings can be 250-300nm；Then using photoresist layer as mask, to the metal of lower section
Hard mask layer and low K buffer layers carry out the first etching, and the first etching uses the oxygen plasma etch of the first source power, therein
Oxygen plasma etch is carbon dioxide plasma etching, and the first opening is formed in metal hard mask layer and low K buffer layers,
It is formed after the first hatch frame, further includes the steps that having the remaining photoresist of removal.Followed by the etching to porous medium layer
Step is as shown in Figure 2 a the schematic diagram using existing dry etching, (is being usually that plasma is carved using dry etching
Erosion) when forming opening in porous medium layer, the porous medium layers (dotted portion in Fig. 2 a) of the both sides that are open in etching, by
There would generally be many pore structures in porous medium layer, and when etching forms opening, pore structure can equally be carved
Etching boundary can be formed with many pore structure (inside therein for having opening exposed in erosion, that is, the part as amplified
For the inside of porous medium layer, the pattern of its inside is not shown), and these pore structures opened are walked in subsequent cleaning
Many impurity can be remained in rapid and deposition step, these impurity can enter porous medium layer in subsequent high-temperature technology
In, the dielectric constant of porous medium layer is had a huge impact, and finally influence the performance of device.And the present invention using
The etching technics of femtosecond laser, which is different from traditional dry etching, and (using plasma bombard to be etched
Surface), femtosecond laser have the ultrashort pulse time (be usually 10-15M/s), there is superpower high focusing power, can incite somebody to action
Its energy all fast and accurately concentrates in the zone of action of very little, can fast and accurately be etched in etching, and very
Side effect is generated less, the process after having etched without cleaning removal residue；The high temperature pair that femtosecond laser is generated in etching
The porous medium layer of the edge of exposed porous structure is melted, and the porous medium layer of fusing can be by exposed opening
Pore structure is blocked, that is, has just carried out closed processing to the pore structure of opening in etching process, without using
Additional step, structure as shown in Figure 2 b, its enlarged structure is the boundary of etching after the etch, to open pore structure
Certain closure is carried out；After etching porous medium layer forms opening, by detection, when etching into the erosion for being rich in nitrogen
When carving termination detection layer, then stop femtosecond laser etching, third etching is carried out using nitrogen plasma, and lead in etching process
Enter hydrogen reducing gas, since etch-stop detection layers 3 are the material rich in nitrogen, is detected in the exclusion gas of etching a large amount of
Nitrogen substance (metal hard mask layer and interlayer dielectric layer are all free from the substance of nitrogen, even if it is also minimal amount of to have nitrogen) is namely
Etch-stop detection layers are etched into, nitrogen plasma etching is etched using ammonia plasma treatment.Select the source work(of third etching
Rate value is more than the source power value of the first etching, can prevent during being performed etching as mask using photoresist opening, Gao Gong
Photoresist open edge caused by the etch step of rate can deform under ion bombardment effects, and influence subsequent opening shape
Looks, meanwhile, in third etch step, using the opening with metal hard mask as mask, material is harder than photoresist, Gao Gong
The etching of rate will not cause to deform to the pattern of opening, and high-power etch step can shorten etch period.Etched
It is passed through hydrogen in journey, mainly prevents after exposing interconnection line, remaining oxygen can aoxidize copper interconnecting line in etching cavity, and
And after the interconnection line for exposing lower section, it is continually fed into hydrogen, the final hatch frame obtained in interlayer dielectric layer is held
The continuous time for being passed through hydrogen is 1-10min, and being continually fed into hydrogen mainly will be inevitably mutual by copper in previous step
The oxide layer aoxidized on line surface is restored, to reduce the resistance of copper interconnecting line；And form the second opening knot in etching
During structure, over etching is carried out to lower dielectric layer, the first groove structure is formed with around interconnection line；
Further include having that there is metal interconnection structure 5 in the through-hole structure, the metal interconnection structure 5 and the interconnection
Line upper surface and component side surface contact, and metal interconnection structure includes the portion in first groove structure
Point.Its specific formation process is, the through-hole structure in the porous medium layer of formation and first around the interconnection line of formation recessed
Barrier layer, seed layer and metal layer are formed in slot structure, the material of metal layer therein can be copper, and barrier layer TiN can
To form metal layer using electroplating technique, then pass through CMP process by outside through-hole structure, porous media layer surface it is more
Remaining copper metal layer removal, forms metal interconnection structure, wherein the interconnecting metal layer filled can be filled in the first groove, in turn
Interconnection line below " package " not only increases contact area, and improves the fastness of contact, the institute in through-hole therein
State the length that metal interconnection structure is extended downwardly with interconnection line side surface contact portion, that is, the depth of first groove
Degree is 5-20nm；
Further include the capping layer 6 having above the metal interconnection structure, capping layer 6, which has, is located at the metal interconnection structure
The part of 5 top surface and the portion in the top surface the second groove structure below positioned at around the top surface
Point.Its specific formation process is to be formed with the second groove structure by femtosecond laser etching around metal interconnection structure surface,
Then it is formed after barrier layer in the second groove, forms capping layer 6, wherein capping layer is located at the top of the metal interconnection structure
The length that surface part below extends downwardly, that is, the depth of second groove is 5-20nm.Capping layer therein
Material is nitrogenous metal layer, wherein the metal is Ir or Ru, Ir or Ru metals are stablized than metal Co, even if follow-up
It will not corrode in cleaning process, while be also prevented from oxidation, the electromigration feature of Cu/ metal interfaces can be improved, and
Capping layer is fallen off with metal interconnection structure in order to prevent, and capping layer is not made only in the top surface of metal interconnection structure
It is also formed in the second groove around metal interconnection structure top surface, forms the structure of engaging, not only increase contact
Area also improves contact stabilization.
To sum up, preparation section should can be not only reduced with the semiconductor interconnection structure of porous medium layer, be not necessarily to additionally
Mostly the pore structure of exposed opening carries out the step of " closure ", and can prevent the oxidation on metal interconnecting wires surface, while energy
Enough contacts area improved between interconnection metal and the metal interconnecting wires of lower section and the contact fastness for improving the two, meanwhile, tool
There is stable capping layer structure to improve electric migration performance, improves the stability and reliability of semiconductor devices.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition, people in the art
For member it is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also make more changes
Shape and modification, these deformations and modification are all fallen in invention which is intended to be protected.Protection scope of the present invention is by affiliated
Claims and its equivalent scope are defined.
Claims (10)
1. a kind of metal interconnection structure with porous medium layer, which is characterized in that including with lower structure：
Interconnecting construction in underlying dielectric layers；
The etch-stop detection layers rich in nitrogen on the lower dielectric layer；
Porous medium layer in the etch-stop detection layers rich in nitrogen；
There is through-hole structure, the through-hole are extended downwardly into the porous medium layer above the interconnection line, the through-hole
Marginal portion be less than the upper surface of the interconnection line, be formed with the first groove knot around the interconnection line in underlying dielectric layers
Structure, the through-hole structure in the porous medium layer etch to be formed using femtosecond laser, and the porous media is made in etching process
The local melting of the pore structure of exposure makes the pore structure sealing of exposure in layer；There is metal interconnection in the through-hole structure
Structure, the metal interconnection structure is contacted with the interconnection line upper surface and component side surface, and metal interconnection structure packet
Include the part in first groove structure；There is capping layer, the capping layer tool above the metal interconnection structure
Have positioned at the metal interconnection structure top surface part and positioned at the top surface it is below be located at the top surface around
The second groove structure in part.
2. metal interconnection structure as described in claim 1, which is characterized in that the material of the interconnecting construction is copper, described
The material of the metal interconnection structure in through-hole structure is copper.
3. metal interconnection structure as described in claim 1, which is characterized in that the porous interlayer dielectric layer is low K or surpasses
Low-K material.
4. metal interconnection structure as described in claim 1, which is characterized in that the etch-stop detection layers rich in nitrogen are
Nitrogenous silica.
5. metal interconnection structure as described in claim 1, which is characterized in that the capping layer is nitrogenous metal layer, wherein
The metal is Ir or Ru.
6. metal interconnection structure as described in claim 1, which is characterized in that the metal interconnection structure in the through-hole with
The length that interconnection line side surface contact portion extends downwardly, that is, the depth of first groove is about 5-20nm.
7. metal interconnection structure as described in claim 1, which is characterized in that the capping layer is located at the metal interconnection structure
The length that extends downwardly of top surface part below, that is, the depth of second groove is about 5-20nm.
8. metal interconnection structure as claimed in claim 5, which is characterized in that the surface of the interconnecting construction is by hydrogen
The surface of reduction treatment, and over etching is formed first groove structure in the underlying dielectric layers in a hydrogen atmosphere.
9. metal interconnection structure as claimed in claim 6, which is characterized in that second groove is etched using femtosecond laser
It is formed.
Further include having barrier layer in first groove 10. such as claim 7 or 8 any one of them metal interconnection structures,
The barrier layer is between metal interconnection structure and lower dielectric layer；Further include having barrier layer in second groove, blocking
Layer is between the capping layer and the porous medium layer.
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Cited By (1)
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