CN108364928A - A kind of integrated circuit package structure and its processing method - Google Patents
A kind of integrated circuit package structure and its processing method Download PDFInfo
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- CN108364928A CN108364928A CN201810320806.7A CN201810320806A CN108364928A CN 108364928 A CN108364928 A CN 108364928A CN 201810320806 A CN201810320806 A CN 201810320806A CN 108364928 A CN108364928 A CN 108364928A
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- silver
- ring
- dao
- integrated circuit
- circuit package
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- 238000003672 processing method Methods 0.000 title claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 39
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical group [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 37
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 40
- 239000010949 copper Substances 0.000 claims description 40
- 229910052802 copper Inorganic materials 0.000 claims description 40
- 229910052709 silver Inorganic materials 0.000 claims description 19
- 239000004332 silver Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 13
- 238000003466 welding Methods 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 8
- 239000003292 glue Substances 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000002848 electrochemical method Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 claims 1
- 239000011347 resin Substances 0.000 description 22
- 229920005989 resin Polymers 0.000 description 22
- 238000009792 diffusion process Methods 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000009545 invasion Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000003570 air Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005518 electrochemistry Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a kind of integrated circuit package structure and its processing methods, the encapsulating structure includes Ji Dao, chip and encapsulating material, the front of the Ji Dao is formed with silver-colored ring, in the silver ring isolated area is formed between the settlement being enclosed for disposing the chip, the outer and the edges Ji Dao of the silver ring.Technical solution of the present invention improves the binding force between Ji Dao and encapsulating material, steam can be avoided to invade from source, improves the reliability of integrated circuit package structure on the whole.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of integrated circuit package structure and its processing method.
Background technology
The encapsulating structure of present integrated circuit such as EMSOP8, in order to realize that good heat dissipation, the back side on base island 01 be
It is exposed in air, a front surface and a side surface on base island 01 is then encapsulated by resin 02, wherein the full plating in base island front of storage chip 03
Silver, is formed with silver coating 04, silver-plated purpose be for welding ground, it is indispensable.
Practice finds that the binding force of resin and silver surface in encapsulating structure is not fine, result in Ji Dao front and
Resin-bonded is not close, be easy to cause steam intrusion.Moreover, anti-conducting resinl diffusion chemical treatment can be done in silver-plated layer surface, it should
If be not evaporated completely in the pyroprocess of production of the process layer before encapsulating, the knot of resin and silver surface can be further reduced
With joint efforts.
Invention content
A kind of integrated circuit package structure of offer of the embodiment of the present invention and its processing method, for improving wherein Ji Dao and envelope
Binding force between package material, avoids steam from invading, and improves the reliability of encapsulating structure.
The technical solution used for:
On the one hand, a kind of integrated circuit package structure, including Ji Dao, chip and encapsulating material, the positive shape of the Ji Dao are provided
Cheng Youyin rings, the silver ring are interior along the settlement being enclosed for disposing the chip, the outer of the silver ring and the base
Island forms isolated area between edge.
On the other hand, a kind of processing method of integrated circuit package structure as described above is provided, including:Make lead
Frame, the lead frame include Ji Dao and outer pin;In the copper coating of the lead frame, formed a thickness between 0.125 to
Copper plate between 0.25 micron;It is silver-plated in the positive face ring of the Ji Dao, a silver medal ring is formed, the interior edge of the silver ring is enclosed
Settlement for disposing the chip forms isolated area, the isolation between the outer and the edges Ji Dao of the silver ring
The width in area is not less than 10 microns;Utilize load glue fixed chip in the settlement, the chip and the outer pin it
Between welding lead, encapsulate the chip and the outer pin and lead with encapsulating material, formed as defined in shape.
As can be seen from the above technical solutions, the embodiment of the present invention has the following advantages:
It is electroplated to form silver-colored ring in base island front, for ground wire bonding, and the copper material on positive other regions islands Reng Weiji in base island itself
Matter, encapsulating material such as resin and base island contact portion in such encapsulating structure only have pole be partially it is silver-plated, it is most of
Be with copper surface contact, and the binding force of copper and resin be better than silver and resin combination, it can thus be avoided steam invade,
Improve the reliability of encapsulating structure.
If being appreciated that the outer of silver-colored ring, the side of Ji Dao and air overlap, due to the knot of resin and silver contact
It is bad with joint efforts, then edge can become steam point of entry, when encountering the region of copper surface contact of resin and Ji Dao,
The speed promoted to the inside can just be reduced, but steam still comes into encapsulating structure, just slow down after being into
The speed of interior diffusion still cannot preferably solve the problems, such as that steam is invaded.
And in technical solution of the present invention, isolated area is formed between silver-colored ring outer and the edges Ji Dao, and isolated area is still copper
Material and resin-encapsulated material tool are well bonded, and can prevent that steam is invaded from the edge of Ji Dao, thus from source
On solve the problems, such as steam invasion, it is ensured that the high reliability of encapsulating structure.
As it can be seen that technical solution of the present invention, on the one hand, replace full electroplate by setting silver-colored ring in base island front, reduce silver
With the contact area of encapsulating material, increase the contact area of the copper material and encapsulating material of Ji Dao itself, to reduce entering for steam
It invades, improves reliability;On the other hand, silver-colored ring is located at the inner region in base island front edge, one is reserved between the edges Ji Dao
Isolated area prevents that steam is invaded, solves water from source using the copper material of the isolated area and combining closely for encapsulating material
The problem of vapour is invaded;To realize and improve Ji Dao and encapsulating material binding force, steam is avoided to invade, improving encapsulating structure can
By property the technical issues of.
Description of the drawings
Technical solution in order to illustrate the embodiments of the present invention more clearly, below will be to institute in embodiment and description of the prior art
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the present invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is the schematic diagram of existing EMSOP8 integrated circuit package structures;
Fig. 2 is a kind of schematic diagram of integrated circuit package structure provided in an embodiment of the present invention;
Fig. 3 is a kind of flow chart of the processing method of integrated circuit package structure provided in an embodiment of the present invention.
Specific implementation mode
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The every other embodiment that member is obtained without making creative work should all belong to the model that the present invention protects
It encloses.
Term " first ", " second ", " third " in description and claims of this specification and above-mentioned attached drawing etc. are
For distinguishing different objects, rather than for describing particular order.In addition, term " comprising " and " having " and they are any
Deformation, it is intended that cover and non-exclusive include.Such as contain the process of series of steps or unit, method, system, product
Or equipment the step of being not limited to list or unit, but further include the steps that optionally not listing or unit, or it can
Selection of land further includes for the intrinsic other steps of these processes, method, product or equipment or unit.
Below by specific embodiment, it is described in detail respectively.
Referring to FIG. 2, the embodiment of the present invention provides a kind of integrated circuit package structure, including base island 11, chip 12 and envelope
Package material 13.Particularly, the front on the base island 11 is formed with silver-colored ring 17, and edge is enclosed for disposing in the silver ring 17
The settlement 21 of chip is stated, isolated area 22 is formed between the outer and the edges Ji Dao of the silver ring 17.
It should be noted that chip 12 is placed in the front on base island 11, encapsulating material 13 is used for 11 He of wrapping and encapsulating base island
A front surface and a side surface of chip 12, base island 11 is encapsulated in inside encapsulating material 13, but the back side on base island 11 is revealed in encapsulating material
13 outside.The integrated circuit package structure further includes outer pin 14, and it is so-called that outer pin 14 and base island 11 collectively form this field
Lead frame, lead frame in other words.Outer pin 14 and chip 12 can be realized by welding lead 15 to be electrically connected, and chip 12 can lead to
The front for crossing the silver-colored ring 17 that ground wire 16 is connected on base island 11 is grounded.Wherein, lead frame, including base island 11 and outer pin 14
Generally copper material, the generally optional resin of encapsulating material 13, chip 12 are generally semiconductor chip.Lead 15 and ground wire 16 can
For silver wire or copper wire or other wires.Chip 12 can be fixed on the front on base island 11 by elargol 18.
Wherein, the purpose for forming silver-colored ring 17 in 11 front of base island is welding ground 16, in the ground terminal and silver of chip 12
Welding ground between ring 17 is essential.But silver and the binding force between encapsulating material such as resin be not it is fine, two
It is easy to be invaded by steam between person;And the binding force of silver and copper is then preferable, will not be invaded between the two by steam.Therefore, this hair
In bright scheme, the width of silver-colored ring can be given and limited, to achieve a better balance.On the one hand, excellent in order to ensure welding needs
The width a1 of the silver-colored ring is selected to be not less than 100 microns.On the other hand, in order to improve the binding force with encapsulating material, silver should be reduced
The width of the area of ring, the preferably described silver-colored ring a1 is not more than 300 microns.
In the present invention program, isolated area 22 is formed between the outer and the edges Ji Dao of the silver ring 17, is in order to anti-
The edge on the islands Zhi Ji forms steam and invades point, to ensure that the realization of the purpose, the width a2 of the isolated area are micro- not less than 10
Meter Wei Yi.Preferably, the width a2 of the isolated area is between 10 microns to 200 microns.
The binding force of resin-encapsulated material and copper surface in order to further increase, it is preferred that the front of the Ji Dao, including
The surface of the bottom of the settlement 21 and the isolated area 22 and silver-colored ring 17, the copper plate formed with electrochemical method.
Further, the thickness of the copper plate is between 0.125 to 0.25 micron.Further, the copper plate has been subjected to
Anti- copper-stripping chemical liquids processing, to further increase binding force.
As described above, the present invention program forms the silver-colored ring for bonding wire in base island front, and the edge 10 of distance Ji Dao is micro-
Meter or more, but it is no more than the half of equidirectional base island width, typically 10 microns to 200 microns;The width of silver-plated ring
At 100 microns or more, typically between 100 microns to 300 microns, but no more than the half of equidirectional base island width;With true
It protects:Silver-colored ring has enough width for welding, and silver-colored ring circle zone has enough areas for disposing chip, and silver-colored anchor ring
Product is small as possible to avoid reducing the binding force with encapsulating material.The knot of resin-encapsulated material and copper surface in order to further increase
With joint efforts, the method for using electrochemistry again on copper surface plates one layer of copper, and thickness makes copper surface more smooth, so in 0.125um ∽ 0.25um
It carries out anti-copper-stripping chemical liquids processing again afterwards, increases the combination force with silver-colored ring below, while increasing resin and base island front
Binding force.
In this way, the present invention can reduce steam intrusion integrated circuit package structure from source.
Referring to FIG. 3, the embodiment of the present invention also provides a kind of processing side of integrated circuit package structure as described above
Method, the method includes:
31, lead frame is made, the lead frame includes Ji Dao and outer pin;
32, in the copper coating of the lead frame, copper plate of the thickness between 0.125 to 0.25 micron is formed;
33, silver-plated in the positive face ring of the Ji Dao, a silver medal ring is formed, the interior edge of the silver ring is enclosed for disposing the core
The settlement of piece forms isolated area between the outer and the edges Ji Dao of the silver ring, and the width of the isolated area is not less than
10 microns;
34, load glue fixed chip, the welding lead between the chip and the outer pin, with envelope are utilized in the settlement
Package material encapsulates the chip and the outer pin and lead, forms defined shape.
Optionally, after step 32, before step 33, further include:The copper plate is carried out at anti-copper-stripping chemical liquids
Reason.
As described above, in some embodiments, the specific embodiment of the present embodiment method can be:
A) machine die method is used, lead frame Ji Dao and lead frame outer pin construction in generating mechanism etc.;
B) one layer of copper is plated in mechanism surface, thickness makes copper surface more smooth in 0.125um ∽ 0.25um, then carries out anti-copper again
Chemical liquids processing is removed, increases the combination with silver-colored ring below, while increasing resin and base island front binding force;
C) the place progress ring at 10 microns from base island edge-plated or more is silver-plated, since the silver ring is only used for soldered wires, no
It is contacted with conducting resinl, therefore, removes common anti-load glue diffusion chemical treatment;D) order load glue in base island front;
e)Semiconductor chip is pressed on load glue, and carries out the hinge reaction of glue in high temperature oven;
f)Metal lead wire welding is carried out between semiconductor chip and terminal pin;
g)Ji Dao, chip, outer pin are encapsulated with resin inside mold;
H) make mechanism at defined shape with mold etc..
Since Ji Dao has to the lead i.e. ground wire of welding ground connection, and the place of ground wire bonding must be silver-plated, but tie
The binding force of resin and silver-plated surface in structure is little, is easy steam intrusion, causes resin and base island skin lamination, serious
Words layering can be diffused into chip surface, and when circuit works, the steam of layering can expand, and on the one hand cause Product jointing point off
It opens;On the other hand pressure is generated in encapsulating structure, the operating voltage of circuit is made to change.And the resin in encapsulating structure and
The surface binding force of base island copper is better than the binding force with silver surface.Therefore, under conditions of meeting welding, one is to try to reduce
The area of silver increases the area on copper surface;Second is that the interface in mechanism between resin, air, Metal Substrate island does not go out as possible
Existing silvering, increases the binding force at interface, to control the intrusion of steam on source.
To sum up, the embodiment of the invention discloses a kind of integrated circuit package structure and its processing methods, by using above-mentioned
Technical solution achieves following technique effect:
It is electroplated to form silver-colored ring in base island front, for ground wire bonding, and the copper material on positive other regions islands Reng Weiji in base island itself
Matter, encapsulating material such as resin and base island contact portion in such encapsulating structure only have pole be partially it is silver-plated, it is most of
Be with copper surface contact, and the binding force of copper and resin be better than silver and resin combination, it can thus be avoided steam invade,
Improve the reliability of encapsulating structure.
If being appreciated that the outer of silver-colored ring, the side of Ji Dao and air overlap, due to the knot of resin and silver contact
It is bad with joint efforts, then edge can become steam point of entry, when encountering the region of copper surface contact of resin and Ji Dao,
The speed promoted to the inside can just be reduced, but steam still comes into encapsulating structure, just slow down after being into
The speed of interior diffusion still cannot preferably solve the problems, such as that steam is invaded.
And in technical solution of the present invention, isolated area is formed between silver-colored ring outer and the edges Ji Dao, and isolated area is still copper
Material and resin-encapsulated material tool are well bonded, and can prevent that steam is invaded from the edge of Ji Dao, thus from source
On solve the problems, such as steam invasion, it is ensured that the high reliability of encapsulating structure.
As it can be seen that technical solution of the present invention, on the one hand, replace full electroplate by setting silver-colored ring in base island front, reduce silver
With the contact area of encapsulating material, increase the contact area of the copper material and encapsulating material of Ji Dao itself, to reduce entering for steam
It invades, improves reliability;On the other hand, silver-colored ring is located at the inner region in base island front edge, one is reserved between the edges Ji Dao
Isolated area prevents that steam is invaded, solves water from source using the copper material of the isolated area and combining closely for encapsulating material
The problem of vapour is invaded;To realize and improve Ji Dao and encapsulating material binding force, steam is avoided to invade, improving encapsulating structure can
By property the technical issues of.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, is not described in some embodiment
Part, may refer to the associated description of other embodiments.
Above-described embodiment is merely illustrative of the technical solution of the present invention, rather than its limitations;The ordinary skill people of this field
Member should understand that:It can still modify to the technical solution recorded in the various embodiments described above, or to which part skill
Art feature carries out equivalent replacement;And these modifications or replacements, each reality of the present invention that it does not separate the essence of the corresponding technical solution
Apply the spirit and scope of a technical solution.
Claims (10)
1. a kind of integrated circuit package structure, including Ji Dao, chip and encapsulating material, which is characterized in that
The front of the Ji Dao is formed with silver-colored ring, and edge is enclosed the settlement for disposing the chip, institute in the silver ring
It states and forms isolated area between the outer of silver-colored ring and the edges Ji Dao.
2. integrated circuit package structure according to claim 1, which is characterized in that
The width of the isolated area is not less than 10 microns.
3. integrated circuit package structure according to claim 2, which is characterized in that
The width of the isolated area is between 10 microns to 200 microns.
4. integrated circuit package structure according to claim 1, which is characterized in that
The width of the silver ring is not less than 100 microns.
5. integrated circuit package structure according to claim 4, which is characterized in that
The width of the silver ring is not more than 300 microns.
6. integrated circuit package structure according to claim 1, which is characterized in that
The settlement, the isolated area, other regions of lead frame and silver-colored ring the surface of bottom there is electrochemical method
The copper plate of formation.
7. wanting the integrated circuit package structure described in 6 according to right, which is characterized in that
The thickness of the copper plate is between 0.125 to 0.25 micron.
8. integrated circuit package structure according to claim 7, which is characterized in that
The copper plate has been subjected to anti-copper-stripping chemical liquids processing.
9. a kind of processing method of integrated circuit package structure as described in claim 1, which is characterized in that the method packet
It includes:
Lead frame is made, the lead frame includes Ji Dao and outer pin;
In the copper coating of the lead frame, copper plate of the thickness between 0.125 to 0.25 micron is formed;
It is silver-plated in the positive face ring of the Ji Dao, a silver medal ring is formed, the interior edge of the silver ring is enclosed for disposing the chip
Settlement, form isolated area between the outer and the edges Ji Dao of the silver ring, the width of the isolated area is not less than 10
Micron;
Load glue fixed chip, the welding lead between the chip and the outer pin, with encapsulation are utilized in the settlement
Chip described in material package and the outer pin and lead form defined shape.
10. according to the method described in claim 9, it is characterized in that, before the positive face ring of the Ji Dao is silver-plated, further include:
Anti- copper-stripping chemical liquids processing is carried out to the copper plate.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114190009A (en) * | 2021-11-19 | 2022-03-15 | 气派科技股份有限公司 | Surface-mounted device packaging structure and upper plate welding method thereof |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6034422A (en) * | 1995-09-29 | 2000-03-07 | Dai Nippon Printing Co., Ltd. | Lead frame, method for partial noble plating of said lead frame and semiconductor device having said lead frame |
US6396129B1 (en) * | 2001-03-05 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package |
US6667073B1 (en) * | 2002-05-07 | 2003-12-23 | Quality Platers Limited | Leadframe for enhanced downbond registration during automatic wire bond process |
KR20060111936A (en) * | 2005-04-25 | 2006-10-31 | 앰코 테크놀로지 코리아 주식회사 | Leadframe structure for semiconductor package |
US20080111218A1 (en) * | 2006-11-09 | 2008-05-15 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
KR20100050640A (en) * | 2008-11-06 | 2010-05-14 | 앰코 테크놀로지 코리아 주식회사 | Lead frame for manufacturing semiconductor package and method for plating the same |
US20110140253A1 (en) * | 2009-12-14 | 2011-06-16 | National Semiconductor Corporation | Dap ground bond enhancement |
CN202651105U (en) * | 2012-06-21 | 2013-01-02 | 常州银河世纪微电子有限公司 | Surface-mount-type bridge-type lead frame |
CN108831874A (en) * | 2018-08-07 | 2018-11-16 | 广东气派科技有限公司 | The encapsulating structure of integrated circuit |
-
2018
- 2018-04-11 CN CN201810320806.7A patent/CN108364928A/en active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6034422A (en) * | 1995-09-29 | 2000-03-07 | Dai Nippon Printing Co., Ltd. | Lead frame, method for partial noble plating of said lead frame and semiconductor device having said lead frame |
US6396129B1 (en) * | 2001-03-05 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package |
US6667073B1 (en) * | 2002-05-07 | 2003-12-23 | Quality Platers Limited | Leadframe for enhanced downbond registration during automatic wire bond process |
KR20060111936A (en) * | 2005-04-25 | 2006-10-31 | 앰코 테크놀로지 코리아 주식회사 | Leadframe structure for semiconductor package |
US20080111218A1 (en) * | 2006-11-09 | 2008-05-15 | Stats Chippac Ltd. | Integrated circuit package system with encapsulation lock |
KR20100050640A (en) * | 2008-11-06 | 2010-05-14 | 앰코 테크놀로지 코리아 주식회사 | Lead frame for manufacturing semiconductor package and method for plating the same |
US20110140253A1 (en) * | 2009-12-14 | 2011-06-16 | National Semiconductor Corporation | Dap ground bond enhancement |
CN202651105U (en) * | 2012-06-21 | 2013-01-02 | 常州银河世纪微电子有限公司 | Surface-mount-type bridge-type lead frame |
CN108831874A (en) * | 2018-08-07 | 2018-11-16 | 广东气派科技有限公司 | The encapsulating structure of integrated circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114190009A (en) * | 2021-11-19 | 2022-03-15 | 气派科技股份有限公司 | Surface-mounted device packaging structure and upper plate welding method thereof |
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