CN108364881A - A kind of method of dielectric layer hole link on detection wafer - Google Patents
A kind of method of dielectric layer hole link on detection wafer Download PDFInfo
- Publication number
- CN108364881A CN108364881A CN201810153103.XA CN201810153103A CN108364881A CN 108364881 A CN108364881 A CN 108364881A CN 201810153103 A CN201810153103 A CN 201810153103A CN 108364881 A CN108364881 A CN 108364881A
- Authority
- CN
- China
- Prior art keywords
- metal interconnection
- interconnection structure
- preset distance
- metal
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of method detecting dielectric layer hole link on wafer, one wafer is provided, crystal column surface is covered with dielectric layer and dielectric barrier successively, wherein, multiple metal interconnection structures are preset in dielectric layer, both sides are provided with a sealing structure, and sealing structure uses manufacturing process identical with metal interconnection structure, metal interconnection structure is also connected with a pin configuration, further comprising the steps of：Cutting line is done in length and width direction to be parallel to metal interconnection structure, is cut to wafer, is obtained multigroup sample to be tested；Conductive structure and a pedestal are attached by an aluminum steel；Under a predetermined condition, resistance test is carried out to each sample to be tested by a tester table；Resistance data is collected, resistor time relation curve is drawn；And calculate hole link parameter；Advantageous effect：Can in situ measurement easily be carried out to the hole link of rear end porous medium layer, complete quantitatively evaluating, foundation is provided for the assessment and improvement of technique.
Description
Technical field
The present invention relates to a kind of sides of dielectric layer hole link in field of semiconductor manufacture more particularly to detection wafer
Method.
Background technology
With the continuous large-scale of component being increasingly miniaturized with integrated circuit, the RC retardation ratio of rear end, which becomes, to be influenced to collect
An important factor at circuit signal processing speed.RC retardation ratio is to be generated between conductor resistance and interlayer sneak capacitance on integrated circuit
Delay.In order to which the RC retardation ratio of terminal interconnection after reducing often is led in current high-tech node (such as 28nm and 55nm) technique
The porosity of filled media between increasing metal interconnecting wires is crossed to reduce the dielectric constant of filled media, to reduce RC retardation ratio.
But after increasing medium porosity some detrimental effects can be caused to performance, the yield etc. of integrated circuit, such as it is situated between
The mechanical strength of matter declines, it is easier to influenced by plasma bombardment in manufacturing process, medium and interconnection line be easier by
The influence etc. of the diffusion of metal ion and steam.Obviously, the either reduction of dielectric constant or above-mentioned adverse effect, all with
The connectivity in duct is related.For example, under same porosity, structure mutually isolated is more than interconnected structure between hole
Metal ion, steam diffusion can more be inhibited, while also there is better medium and interconnection line reliability.
So, if it is possible to it realizes the in-situ monitoring to porous medium layer hole link, is beneficial to disclose technique, hole
Contact between structure and performance, reliability provides foundation to give the optimization of technique and improve.
Include in the prior art gas adsorption method for the measurement method of film porous medium layer hole link, ellipse inclined
Instrument method, X-ray or neutron small angle scattering method and positronium bury in oblivion method etc..
Gas adsorption method needs to measure the weight change of the front and back porous media of absorption.But for by thicker substrate branch
Support and contain a large amount of metal interconnecting wires rear end porous membrane for, this method lacks accuracy.
Ellipsometry method is a kind of optical means, and measurement porous medium layer is needed to be reflected before and after filling certain non-wetting fluid
The variation of rate and polarization situation.But it due to being difficult to know containing the true refractive index of medium after metal wire, also can not accurately calculate
Its pore structure.
X-ray or neutron small angle scattering method are also required to relatively porous dielectric layer and are scattered before and after filling certain non-wetting fluid
The variation of spectrum, and it also needs to multilayer thin film stack gather into folds to increase thickness to increase scattering strength and detectivity.
Since the propagation of light, X-ray or neutron in the medium can be interfered by a large amount of metal interconnecting wires, it equally can not be accurately calculated
Pore structure
It is to characterize pore structure by measuring the annihilation lifetime spectroscopy of positronium that positronium, which buries in oblivion method, due to positive electron
Element is all more sensitive to the defect (vacancy, hole, impurity etc.) of various sizes, it is also easy by medium the detection of hole
Metal wire and medium/metal boundary defect interference, cause to underestimate its hole link.
In addition, existing several method is complicated for operation, and is required for the instrument of accurate costliness, cost is higher.So it
Not in carry out wafer on porous medium layer hole connectivity in situ measurement.
Invention content
In view of the above-mentioned problems, the present invention provides a kind of method detecting dielectric layer hole link on wafer, a crystalline substance is provided
Circle, the crystal column surface are covered with a dielectric layer and a dielectric barrier successively, which is characterized in that are preset in the dielectric layer
A plurality of metal interconnection structures, each metal interconnection structure both sides are provided with a sealing structure, and the sealing structure uses
Manufacturing process identical with the metal interconnection structure, the metal interconnection structure are also connected with a preset pin configuration, also wrap
Include following steps：
Step S1 presets one group of second preset distance value, and it is current second predetermined therefrom to choose one second preset distance
Distance；
Step S2, to be parallel to the length direction of the metal interconnection structure, and away from the edge of the metal interconnection structure
The straight line of one first preset distance is the first cutting line, to be parallel to the width direction of the metal interconnection structure, and away from described
The straight line of current second preset distance described in the edge of metal interconnection structure is the second cutting line, is interconnected to a plurality of metals
At least two in structure is cut, and one group of sample to be tested is obtained；
Step S3 judges whether there is not used second preset distance,
If so, choosing not used second preset distance as the current second preset distance value, walked
Rapid S2；
If nothing, step S4 is carried out；
The pin configuration and a pedestal are attached by step S4 by aluminum steel；
Step S5 carries out resistance test by a tester table under a predetermined condition to each sample to be tested；
Step S6 collects the resistance data of each sample to be tested, draws the resistivity-time of each sample to be tested
Relation curve；
Step S7 calculates hole link according to the resistivity-time relation curve with corresponding second preset distance
Property parameter.
Wherein, the metal interconnection structure is the metal interconnecting wires with a predetermined length.
Wherein, the metal interconnection structure is isolated by a metal barrier with the dielectric layer.
Wherein, the conductive structure includes four metal pads, and metal pad passes through lead connection institute described in each two
State one end of metal interconnection structure.
Wherein, the predetermined length is 5 μm.
Wherein, the pedestal is a pedestal for carrying pin, and the resistance test is carried out by the pin.
Wherein, the sealing structure and the spacing of the metal interconnection structure are the minimum spacing that technique allows.
Wherein, ten times of second preset distance more than the predetermined length.
Wherein, in the step S3, the predetermined condition includes that temperature is not less than 300 DEG C, and atmosphere is air or contains steam
Atmosphere.
Wherein, in the step S5, the hole link parameter is tortuous fractal dimension, the tortuous fractal dimension
Computational methods are：
In formula,For the resistance variations rate of the test sample, DtFor tortuous fractal dimension, l is the second preset distance.
Advantageous effect：This method can conveniently realize the quantitatively evaluating of the hole link of rear end dielectric layer, be technique
Assessment and improve provide foundation.By in situ measurement, eliminate using other disturbing factors that may be introduced when other methods；
It avoids being specifically manufactured the waste caused by sky piece, test result can reflect influence of all technical process to medium.Meanwhile nothing
The complex operations such as grinding, stripping need to be carried out to the dielectric layer on wafer, can effectively reduce experiment difficulty and cost.
Description of the drawings
Fig. 1 is the step flow of the method specific embodiment of dielectric layer hole link on a kind of detection wafer of the present invention
Figure；
Fig. 2 is that metal mutually links in the method specific embodiment of dielectric layer hole link on a kind of detection wafer of the present invention
The schematic layout pattern of structure；
Fig. 3 is that metal mutually links in the method specific embodiment of dielectric layer hole link on a kind of detection wafer of the present invention
The schematic cross-section of structure；
Fig. 4 is that sample to be tested is electric in the method specific embodiment of dielectric layer hole link on a kind of detection wafer of the present invention
Hinder the schematic diagram of measurement method.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of not making creative work it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
As shown in Figure 1, Figure 2, Figure 3 and Figure 4, it proposes a kind of method detecting dielectric layer hole link on wafer, provides
One wafer, the crystal column surface are covered with a dielectric layer 23 and a dielectric barrier 21 successively, wherein pre- in the dielectric layer 23
Equipped with a metal interconnection structure 11,11 both sides of the metal interconnection structure are provided with a sealing structure 12, the sealing structure 12
Using manufacturing process identical with the metal interconnection structure 11, the metal interconnection structure 11 is also connected with a preset conductive knot
Structure, it is further comprising the steps of：
Step S1 presets one group of second preset distance value, and it is current second predetermined therefrom to choose one second preset distance
Distance；
Step S2, to be parallel to the length direction of the metal interconnection structure 11, and away from the metal interconnection structure 11
The straight line of one first preset distance of edge is the first cutting line 142, to be parallel to the width direction of the metal interconnection structure 11,
And the straight line of current second preset distance in edge away from the metal interconnection structure 11 13 is the second cutting line 141, to a plurality of
At least two in the metal interconnection structure 11 is cut, and one group of sample to be tested is obtained；
Step S3 judges whether there is not used second preset distance,
If so, choosing not used second preset distance as the current second preset distance value, walked
Rapid S2；
If nothing, step S4 is carried out；
The pin configuration and a pedestal are attached by step S4 by an aluminum steel；
Step S5 carries out resistance test by a tester table under a predetermined condition to each sample to be tested；
Step S6 collects the resistance data of each sample to be tested, draws the resistivity-time of each sample to be tested
Relation curve；
Step S7 calculates duct with corresponding second preset distance 13 according to the resistivity-time relation curve and connects
General character parameter.
In above-mentioned technical proposal, dielectric layer 23 is a porous medium layer.It is waited for through the above technical solutions, being cut from wafer
Sample easily can carry out in situ measurement to the hole link of porous media, and the quantization of duct connectivity is commented in realization
Valence provides foundation for subsequent technological evaluation and improvement.
In a preferred embodiment, the metal interconnection structure 11 is that a metal with a predetermined length interconnects
Line.
Specifically, the length of metal interconnecting wires can be 5 μm.
In above-mentioned technical proposal, 5 μm of long metal interconnecting wires can inhibit the electromigration during resistance detection.
In a preferred embodiment, the metal interconnection structure 11 passes through a metal barrier 22 and the dielectric layer
23 are isolated.
In above-mentioned technical proposal, this is isolated into dielectric layer 23 using metal barrier 22 as metal interconnection structure 11
Technique known to field technology personnel, therefore repeat no more, it should be noted that in the embodiment only using metal barrier 22
Feasibility for illustrating technical solution, not limits protection scope of the present invention.
In a preferred embodiment, the pin configuration includes four metal pads, metal pad described in each two
One end of the metal interconnection structure is connected by a lead.
Specifically, as shown in figure 4, metal pad includes two external pads 31 and two internal pads 32.Wherein, external
Pad 31 is as the port for applying electric current, and internal pads 32 are as the port for measuring voltage.After obtaining measurement result, voltage is removed
The resistance value of test structure can be obtained with electric current.
In a preferred embodiment, the sealing structure 12 and the spacing of the metal interconnection structure 11 permit for technique
Perhaps minimum spacing.
In above-mentioned technical proposal, sealing structure 12 can limit the steam in measurement process, make steam along close
The length direction for being seemingly parallel to metal interconnection structure 11 is diffused.
In a preferred embodiment, ten times of second preset distance 13 more than the predetermined length.
Specifically, the size of the second preset distance 13 can take 50~400 μm.
In above-mentioned technical proposal, take the second preset distance as big as possible that can improve the accuracy of test result.
In a preferred embodiment, pedestal can be a 24Pin ceramic bases.By metal pad by aluminum steel with
After the pin connection of 24Pin ceramic bases, the measurement of sample to be tested resistance value can be carried out by four-end method.
In a preferred embodiment, in the step S3, the predetermined condition includes temperature condition and atmospheric condition.
Specifically, temperature is not less than 300 DEG C when test, atmosphere can be air or the atmosphere containing steam.
In above-mentioned technical proposal, during carrying out high temperature resistance monitoring to sample to be tested, the steam in atmosphere can lead to
It crosses dielectric layer 23 to spread to metal interconnection structure 11, and the metal barrier 22 around oxidized metal interconnection structure 11, this meeting
The effective thickness of metal barrier 22 is caused to be thinned, so as to cause conduction electrons dissipating in metal wire/metal barrier interface
Probability reduction is penetrated, the resistance of metal interconnection structure 11 also just increases with the time of high-temperature baking and reduced.At 300 DEG C or more,
This process is controlled by absorption of the steam in the duct of dielectric layer 23/diffusion, and absorption/diffusion of steam then with the company in duct
The general character is related.It therefore, can be by monitoring resistance variations rate of the metal interconnection structure 11 in high temperature and water vapour environment come between
The hole link of earthmeter dielectric layer 23.
Specifically, temperature can take 325 DEG C when test, atmosphere can be air, and humidity can be 40%~60%.
In above-mentioned technical proposal, a period of time is being measured, such as after 100 hours, the resistivity-time for extracting sample to be tested closes
It is slope of a curve, using the slope average value of more samples to be tested of same size as the electricity under corresponding second preset distance 13
Resistive rate.
Specifically, the electricity of the sample to be tested of at least three kinds of different second preset distances 13 can be monitored at that same temperature
Resistive rate.Wherein, the sample to be tested of same second preset distance 13 should at least monitor 15 or more.
In a preferred embodiment, in the step S5, the hole link parameter is tortuous fractal dimension, institute
The computational methods for stating tortuous fractal dimension are：
In formula,For the resistance variations rate of the test sample, DtFor tortuous fractal dimension, l is current second predetermined
Distance, "~" symbolic indication are proportional.
In above-mentioned technical proposal, the relationship of resistance change rate and corresponding second preset distance 13 is drawn under logarithmic coordinates,
And fitting a straight line is carried out, the absolute value of the slope for the straight line being fitted is tortuous point of the duct of same layer medium around test structure
Shape dimension.
In above-mentioned technical proposal, due to ranging from the 1~3 of the value of tortuous fractal dimension, and tortuous fractal dimension is closer
3, illustrate that duct is more tortuous, it is small that probability is connected between adjacent holes；Tortuous fractal dimension illustrates duct closer to straight closer to 1
Form of tubes, adjacent holes connection probability is big, and the connectivity of porous medium layer is high.So being measured according under different technology conditions
The value of the tortuous fractal dimension of the test structure arrived can judge the variation tendency of porous medium layer hole link.
In conclusion using above-mentioned technical proposal, survey in situ can be carried out to the hole link of dielectric layer on wafer 23
Amount, eliminates using other disturbing factors that may be introduced when other methods；It avoids being specifically manufactured the waste caused by sky piece, it can
Directly to test the product manufactured with complete process, test result can reflect shadow of all technical process to medium
It rings；Without on wafer dielectric layer carry out grinding, stripping etc. complex operations, can effectively reduce experiment difficulty and at
This；The manufacture of sample to be tested and the intrinsic equipment that the test apparatus needed for test is IC manufacturing enterprise, so there is no need to be examination
It tests and increases new equipment.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (9)
1. the method for dielectric layer hole link, provides a wafer, the crystal column surface is covered with successively on a kind of detection wafer
One dielectric layer and a dielectric barrier, which is characterized in that a plurality of metal interconnection structures, Mei Gesuo are preset in the dielectric layer
It states metal interconnection structure both sides and is provided with a sealing structure, the sealing structure uses system identical with the metal interconnection structure
Technique is made, the metal interconnection structure is also connected with a preset pin configuration, further comprising the steps of：
Step S1 presets one group of second preset distance value, and it is current second preset distance therefrom to choose one second preset distance；
Step S2, to be parallel to the length direction of the metal interconnection structure, and away from the edge of the metal interconnection structure 1
The straight line of one preset distance is the first cutting line, to be parallel to the width direction of the metal interconnection structure, and away from the metal
The straight line of current second preset distance described in the edge of interconnection structure is the second cutting line, to a plurality of metal interconnection structures
In at least two cut, obtain one group of sample to be tested；
Step S3 judges whether there is not used second preset distance,
If so, choosing not used second preset distance as the current second preset distance value, step S2 is carried out；
If nothing, step S4 is carried out；
The pin configuration and a pedestal are attached by step S4 by aluminum steel；
Step S5 carries out resistance test by a tester table under a predetermined condition to each sample to be tested；
Step S6 collects the resistance data of each sample to be tested, draws the resistivity-time relationship of each sample to be tested
Curve；
Step S7 calculates hole link ginseng according to the resistivity-time relation curve with corresponding second preset distance
Number.
2. according to the method described in claim 1, it is characterized in that, the metal interconnection structure has a predetermined length for one
Metal interconnecting wires.
3. according to the method described in claim 1, it is characterized in that, the metal interconnection structure passes through a metal barrier and institute
Dielectric layer is stated to be isolated.
4. according to the method described in claim 1, it is characterized in that, the pin configuration includes four metal pads, each two
The metal pad connects one end of the metal interconnection structure by a lead.
5. according to the method described in claim 2, it is characterized in that, the predetermined length is 5 μm.
6. according to the method described in claim 1, it is characterized in that, the spacing of the sealing structure and the metal interconnection structure
The minimum spacing allowed for technique.
7. according to the method described in claim 2, it is characterized in that, second preset distance is more than the ten of the predetermined length
Times.
8. according to the method described in claim 1, it is characterized in that, in the step S3, the predetermined condition include temperature not
Less than 300 DEG C, atmosphere is air or the atmosphere containing steam.
9. according to the method described in claim 1, it is characterized in that, in the step S5, the hole link parameter is circuitous
Bent fractal dimension, the tortuous fractal dimension calculate according to the following formula：
In formula,For the resistance variations rate of the test sample, DtFor tortuous fractal dimension, l is current second preset distance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810153103.XA CN108364881B (en) | 2018-02-11 | 2018-02-11 | Method for detecting connectivity of medium layer pore on wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810153103.XA CN108364881B (en) | 2018-02-11 | 2018-02-11 | Method for detecting connectivity of medium layer pore on wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108364881A true CN108364881A (en) | 2018-08-03 |
| CN108364881B CN108364881B (en) | 2020-08-21 |
Family
ID=63002917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810153103.XA Active CN108364881B (en) | 2018-02-11 | 2018-02-11 | Method for detecting connectivity of medium layer pore on wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108364881B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113286421A (en) * | 2021-04-16 | 2021-08-20 | 珠海杰赛科技有限公司 | Dense BGA conductor structure, printed circuit board and manufacturing method |
| CN117250067A (en) * | 2023-11-20 | 2023-12-19 | 南京泛铨电子科技有限公司 | Sample preparation method and system capable of filling and protecting semiconductor test piece material analysis |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002520597A (en) * | 1998-07-13 | 2002-07-09 | アセンブリオン エヌ ヴィ | Method and apparatus for distinguishing regions where a substance is present on a surface |
| US20080224134A1 (en) * | 2007-03-12 | 2008-09-18 | Samsung Electronics Co., Ltd. | Test Structures for Identifying an Allowable Process Margin for Integrated Circuits and Related Methods |
| CN103187403A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor failure analysis structure, forming method of semiconductor failure analysis structure and failure time detection method thereof |
| CN104239711A (en) * | 2014-09-09 | 2014-12-24 | 同济大学 | Method for determining joint roughness |
-
2018
- 2018-02-11 CN CN201810153103.XA patent/CN108364881B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002520597A (en) * | 1998-07-13 | 2002-07-09 | アセンブリオン エヌ ヴィ | Method and apparatus for distinguishing regions where a substance is present on a surface |
| US20080224134A1 (en) * | 2007-03-12 | 2008-09-18 | Samsung Electronics Co., Ltd. | Test Structures for Identifying an Allowable Process Margin for Integrated Circuits and Related Methods |
| CN103187403A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor failure analysis structure, forming method of semiconductor failure analysis structure and failure time detection method thereof |
| CN104239711A (en) * | 2014-09-09 | 2014-12-24 | 同济大学 | Method for determining joint roughness |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113286421A (en) * | 2021-04-16 | 2021-08-20 | 珠海杰赛科技有限公司 | Dense BGA conductor structure, printed circuit board and manufacturing method |
| CN117250067A (en) * | 2023-11-20 | 2023-12-19 | 南京泛铨电子科技有限公司 | Sample preparation method and system capable of filling and protecting semiconductor test piece material analysis |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108364881B (en) | 2020-08-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0281227B1 (en) | Apparatus and method for detecting spot defects in integrated circuits | |
| US5057441A (en) | Method for reliability testing integrated circuit metal films | |
| CN100547398C (en) | A kind of device of measuring semiconductor film material Seebeck coefficient and resistivity | |
| US6290388B1 (en) | Multi-purpose integrated intensive variable sensor | |
| CN203133171U (en) | Testing device for testing wafer of electronic circuit | |
| CN107527661B (en) | Word line resistance testing method and three-dimensional memory failure analysis method | |
| CN108573890B (en) | Copper metal interconnection electromigration test structure and test method thereof | |
| CN108364881A (en) | A kind of method of dielectric layer hole link on detection wafer | |
| CN107993955A (en) | A kind of method for detecting defects of wafer edge | |
| Glang | Defect size distribution in VLSI chips | |
| US20020186036A1 (en) | Combination optical and electrical metrology apparatus | |
| US7487064B2 (en) | Method for detecting and monitoring defects | |
| CN102788911B (en) | Thermosensitive film noise testing method | |
| CN104124235B (en) | Testing structure and testing method implemented by same | |
| CN106526322B (en) | Can trace to the source in piece high value resistor measuring system and its source tracing method | |
| US10700013B2 (en) | IC wafer for identification of circuit dies after dicing | |
| CN111916364A (en) | Method for detecting metal content of film layer on surface of wafer | |
| US4440799A (en) | Monitor for impurity levels in aluminum deposition | |
| US10768206B2 (en) | Loop-back probe test and verification method | |
| TW200402816A (en) | Zoom in pin nest structure, test vehicle having the structure, and method of fabricating the structure | |
| US20070069760A1 (en) | System and method for characterizing silicon wafers | |
| CN104835803A (en) | Device and method for testing integrated circuit plate and integrated circuit metal layer | |
| JP2990471B2 (en) | Inspection monitoring method of conductive pattern | |
| CN113471173B (en) | Test structure and test method | |
| CN103887204A (en) | Silicon wafer quality factor eliminating method related to problems of laser annealing process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |