CN108364850A - A kind of preparation method of upright GaAs nano wires - Google Patents

A kind of preparation method of upright GaAs nano wires Download PDF

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Publication number
CN108364850A
CN108364850A CN201810032745.4A CN201810032745A CN108364850A CN 108364850 A CN108364850 A CN 108364850A CN 201810032745 A CN201810032745 A CN 201810032745A CN 108364850 A CN108364850 A CN 108364850A
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substrate surfaces
gaas
growth
nano wires
gaas nano
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方铉
魏志鹏
贾慧民
唐吉龙
牛守柱
楚学影
李金华
王晓华
马晓辉
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Changchun University of Science and Technology
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00Nanotechnology for materials or surface science, e.g. nanocomposites
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/02428Structure
    • H01L21/0243Surface structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/02546Arsenides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02603Nanowires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Abstract

The invention discloses a kind of preparation methods of upright GaAs nano wires.The relationship of Ga drops catalyst and Si substrate surface contacts angle and substrate surface oxidated layer thickness is obtained according to YoungShi formula,The present invention is handled Si substrate surfaces using HF acid,Keep Si substrate surfaces roughening,And the oxide layer of Si substrate surfaces is partially removed,This method realizes the processing of Si substrate surfaces by using HF acid the control to surface oxide layer thickness,Regulate and control the contact angle of Ga catalyst droplets and substrate surface by adjusting oxidated layer thickness and coarse surface topography,Ga catalyst droplets and substrate surface are made to have suitable contact angle,It realizes and inhibits multiple twin growth,Enable GaAs nano wire vertical growths,There are multiple twins when solving existing self-catalysis epitaxial growth GaAs nano wires,The direction of growth of nano wire is difficult to control,There are a large amount of inclination nano wires,The problem that limitation GaAs nano wires are applied in the devices,To realize high quality,High-performance GaAs nano-wire devices establish material foundation.

Description

A kind of preparation method of upright GaAs nano wires
Technical field
The present invention relates to field of semiconductor materials, more particularly to upright in Group III-V semiconductor field of nano material preparation A kind of preparation method of GaAs nano wires.
Background technology
Nano wire be it is a kind of be limited in nanometer scale in the horizontal, and it is longitudinal there is no limit one-dimentional structure, due to Two dimension energy level splittings of cross-wise direction, this makes it be shown completely in mechanics, electricity, optics etc. relative to body material Different property.Meanwhile the axial hetero-junctions with radial direction can be formed in structure design, it itself can also be used as one solely Vertical device so that this nanostructure becomes a kind of constructing module of very promising nanoscale devices, and becomes and grinds The hot spot studied carefully.Group III-V semiconductor nano material has in terms of nano-device wide due to unique physical property Application potential and receive the concern of people.GaAs is one of III-V compound semiconductor material, is direct band-gap semicondictor Material has the characteristics that the electrical and optical properties that high carrier mobility, effective mass are small, excellent, this makes GaAs nanometers Line becomes a kind of ideal material for preparing electronic device and opto-electronic device, and GaAs nano wires are in LED, laser, detection at present Device, solar cell, thermo-electric device etc. obtain extensive research.
GaAs nano wires have developed a series of preparation methods in terms of growth, including chemical vapor deposition (CVD), metal have Machine object vapor deposition (MOVPE), molecular beam epitaxy (MBE) etc..The preparation of nano-material can generally be divided into from top to bottom and Two kinds from bottom to top, wherein being to go to array structure institute with allowing constituent atoms automatic order by way of material epitaxy from bottom to top The low dimensionality of nano-wires structure needed limits so as to avoid technique, and carries out nano-material growth by self-catalysis method and belong to In one kind from bottom to top.For the GaAs nano wires of self-catalysis growth, basic principle is to deposit Ga elements in substrate surface, So that substrate surface forms Ga drop beads, and as the collection center of Ga atoms and As atoms, it is further passed through Ga and As, With the increase of As components in Ga-As alloys and over-saturation state is progressivelyed reach, GaAs is precipitated in interface and forms GaAs and receives Rice noodles.This self-catalysis mode avoids dissimilar metal pollution nano wire, meanwhile, it is more excellent in terms of the defect for reducing nano wire Gesture is best suited for the application of extensive nano wire electronics device, is one of nano wire preparation method of most Research Prospects.
Currently, the growth of GaAs nano-materials may be implemented by different growing technologies, in GaAs nano-materials It is in the majority with self-catalysis growth pattern in technology of preparing, but realize that GaAs nano wires are grown with substrate transverse on substrate, it obtains straight Vertical GaAs nano wires are a problems existing for self-catalysis epitaxy technology, and self-catalysis grows GaAs nano wires since there are multiple Twin so that the direction of growth of nano wire is difficult to control, and then a large amount of inclined nano wires occurs, limits nano wire in device In application.Therefore, the GaAs nano wires for how realizing vertical growth realize that the application of upright GaAs nano wires in the devices is Primarily solve the problems, such as.
Invention content
The present invention proposes a kind of preparation method of upright GaAs nano wires, this method by with HF acid solutions to Si substrate tables The natural oxidizing layer in face performs etching, and Si substrates is made to obtain coarse surface topography, is carved to the oxide layer of Si substrate surfaces Erosion, by handling the control realized to Si substrate surface oxidated layer thickness with HF acid etches, by changing the thickness of oxide layer, and The contact angle for regulating and controlling Ga catalyst droplets and substrate in conjunction with coarse surface topography makes Ga catalyst droplets and substrate surface It is final to realize the growth for inhibiting multiple twin with suitable contact angle, make GaAs nano wires perpendicular to substrate vertical growth, There are multiple twins, the direction of growth of nano wire to be difficult to control when solving existing self-catalysis epitaxy technology growth GaAs nano wires, There is a large amount of inclined nano wires, the problem that limitation GaAs nano wires are applied in the devices, to realize high quality, high-performance GaAs Nano-wire devices establish material foundation.
The present invention proposes a kind of preparation method of upright GaAs nano wires, and this method is by controlling Si substrate surface oxide layers Contact angle with substrate of thickness and coarse surface topography regulation and control Ga catalyst droplets, according to YoungShi formula it is found that lining Bottom is related with substrate surface oxidated layer thickness with catalyst contact angle, by changing Si liner oxidation layer thickness, by Si substrate oxygen Change layer to be handled with HF acid etches, it is 0.8nm to make Si surface oxide layer thickness, obtains the GaAs nano wires of vertical-growth.
The present invention proposes a kind of preparation method of upright GaAs nano wires, utilizes HF acid to Si substrate surface oxygen in this method Change layer processing the specific steps are:1, by HF:H2O is with 1:10 ratio prepares etching liquid, and etching condition is room temperature, in fluorescent lamp It is performed etching under the environmental condition of irradiation;2, Si substrates are put into prepared etching liquid to the autoxidation of Si substrate surfaces Layer performs etching, etch period 2s;3, Si substrates are taken out from etching liquid, utilizes ellipsometer measurement surface oxidation tunic Thickness, when oxidated layer thickness is thicker, etch period is less, when not reaching expected and requiring, Si substrates is put into etching liquid and are continued Etching, until Si surface oxide layer thickness reaches the present invention and realizes that the 0.8nm thickness required by upright GaAs nanowire growths is wanted It asks;4, the Si substrates of etching processing are put into the growth that upright GaAs nano wires are carried out in growth apparatus.
The present invention proposes that a kind of preparation method of upright GaAs nano wires, this method grow GaAs with molecular beam epitaxy technique Nano wire, growth mechanism use the growth pattern of self-catalysis, and catalyst is Ga drops, when Ga drops catalyst is in Si substrate surfaces When generation, pause 80s keeps Ga drops fully dispersed, to ensure droplet size, to make Ga drops catalyst and pass through HF For the Si substrate surfaces of acid etch processing there are one suitable surface contact angle, the present invention passes through the natural oxygen to Si substrate surfaces Changing layer etching keeps Si substrate surfaces roughening, and the thickness of control Si substrate surface oxide layers, realization pair are handled by HF acid etches The regulation and control of Ga drops and Si substrate surface contacts angle, it is final to realize the GaAs nano wires in molecular beam epitaxial growth GaAs nano wires The purpose of vertical growth reaches the advantageous effect for preparing upright GaAs nano wires proposed by the invention.
Description of the drawings
Fig. 1 is the technical solution figure that the present invention realizes upright GaAs nanowire preparation methods.
Fig. 2 is upright GaAs nano-materials SEM figures prepared by the present invention.
Specific implementation mode
Below by the drawings and specific embodiments, to the upright GaAs nano-material systems of this realization proposed by the invention Standby method is described in further detail, and can be prepared and Si substrate transverses using this method proposed by the invention Upright GaAs nano-materials, prepared upright GaAs nano wires SEM figures are as shown in Fig. 2.
The present invention proposes a kind of preparation method of upright GaAs nano wires, this method by with HF acid solutions to Si substrate tables The natural oxidizing layer in face performs etching, and keeps Si substrate surfaces roughening, meanwhile, realize the control to Si substrate surface oxidated layer thickness System, thickness combination Si substrates by changing oxide layer coarse surface topography regulation and control Ga catalyst droplets and substrate surface connect Feeler degree makes Ga catalyst droplets and substrate surface have suitable contact angle, is finally reached the growth for inhibiting multiple twin, The vertical-growth for realizing GaAs nano wires, there are multiple twin when solving existing self-catalysis epitaxy technology growth GaAs nano wires, The direction of growth of nano wire is difficult to control, and a large amount of inclined nano wires, the difficulty that limitation GaAs nano wires are applied in the devices occurs Topic, to realize that high quality, high-performance GaAs nano-wire devices establish material foundation.It is below Si (111) substrate with substrate, growth Technology is molecular beam epitaxy technique, and source material used is the sources Ga, the sources As, solution used in etching processing Si substrates be HF acid solutions, Institute's growth material is GaAs nano wires, and such embodiment carries out specific detailed description.
Fig. 1 show the technical solution figure that the present invention realizes upright GaAs nanowire preparation methods, and Si substrates (1) surface has Natural oxidizing layer (2) performs etching Si substrate surface natural oxidizing layers with HF acid, obtains coarse surface and oxide layer is suitable The Si substrate surfaces (3) of thickness, making Ga drops catalyst, there are one suitable surfaces with the Si substrate surfaces by the processing of HF acid Contact angle obtains upright GaAs nano wires (5) when carrying out GaAs nanowire growths.
Fig. 2 show the upright GaAs nano wires SEM figures that epitaxial growth of the present invention obtains, and can see the present invention in figure Realize the preparation of upright GaAs nano wires.
Realize that the specific implementation step that in the present embodiment prepared by upright GaAs nano-materials is as follows:
Step 1:Si (111) substrate cleaning treatment, first, by HF:H2O is with 1:10 ratio prepares etching liquid, etches item Part is room temperature, is etched under daylight light irradiation environment, and then, Si substrates are put into prepared etching liquid to Si substrate surfaces Natural oxidizing layer perform etching, etch period 2s takes out Si substrates after the HF acid etches of 2s from etching liquid, profit It, will when the thicker etch period of oxidated layer thickness is less not reached expected and require with ellipsometer measurement surface oxide layer film thickness Si substrates, which are put into etching liquid, to be continued to etch, until Si substrate surface oxidated layer thickness reaches the present invention and realizes upright GaAs nanometers The required 0.8nm thickness requirements of line growth are finally ultrasonically treated 5min with absolute ethyl alcohol to the Si substrates after HF acid etches, It is rinsed well with deionized water (DI) after ultrasonic cleaning processing and is dried up with nitrogen, complete the processing work to Si (111) substrate Skill can carry out the growth of upright GaAs nano wires;
Step 2:The Si of cleaning treatment (111) substrate is handled in molecular beam epitaxy system, after preliminary treatment Si (111) substrate be put on the sample carrier of molecular beam epitaxy (MBE) system Sample Room guide rail trolley, Sample Room take out true Vacancy is managed, when Sample Room vacuum environment is better than 10-8When Torr, the baking temperature of Si substrates is set as 200 DEG C, baking time 2 is small When, sample is sent into surge chamber by the preliminary aqueous vapor and foreign gas for removing Si substrate surfaces after Sample Room preliminary treatment (Buffer) in, 350 DEG C of bakings are carried out to Si substrates, baking time 2 hours further removes the gas of Si substrate surface difficulties removal Body impurity, finally by treated, Si substrates are sent into the growth rooms MBE, wait for GaAs nanowire growths parameter setting and growth source stove The epitaxial growth of GaAs nano-materials is carried out after parameter stability;
Step 3:The growth of upright GaAs nano wires, growth flow are:First, energetic reflection electron diffraction instrument is opened (RHEED) in-situ monitoring is carried out to substrate surface, underlayer temperature is added to 620 DEG C, open Ga source valve 10s, deposition Ga catalysis Agent, subsequent intermediate hold 80s, keeps Ga drops fully dispersed, to ensure droplet size, to make Ga drops catalyst and warp The Si substrate surfaces of HF acid etches processing are crossed there are one suitable surface contact angle, this suitable surface contact angle can be with Realize that the vertical growth of GaAs nano wires, GaAs nanowire growth temperatures are 620 DEG C, Ga source oven temperature degree is 995 DEG C, corresponding Ga Line equivalent pressure is 6.2 × 10-8Torr, As source oven temperature degree are 600 DEG C, and corresponding As lines equivalent pressure is 1.6 × 10- 6Torr, As/Ga line ratio are 25.8, growth time 10min, and epitaxial growth with this condition obtains GaAs nano-materials;
Step 4:After the growth for completing GaAs nano wires, the sources Ga, the sources As flapper closure, source oven temperature degree cooling, when substrate temperature Degree closes the sources As after being less than 400 DEG C, and after waiting for epitaxial device parameter to reach arrange parameter, growth is had upright GaAs nano wires Si substrates are transmitted and are taken out by guide rail trolley, to grow sample surface topography and GaAs nano-materials crystal quality into Row test characterization, completes the preparation of upright GaAs nano-materials.
A kind of the application preparation method of upright GaAs nano-materials claimed is realized by above step, it should Method makes Si substrates obtain coarse surface shape by being performed etching to the natural oxidizing layer of Si substrate surfaces with HF acid solutions Looks perform etching the oxide layer of Si substrate surfaces, are handled by HF acid etches, realize the control to Si surface oxide layer thickness System regulates and controls Ga catalyst droplets and substrate table by the coarse surface topography of the thickness combination Si substrate surfaces of change oxide layer The contact angle in face makes Ga catalyst droplets and substrate surface have suitable contact angle, this suitably contacts angle can To realize the growth for inhibiting multiple twin, the vertical-growth of GaAs nano wires is realized, solve existing self-catalysis epitaxy technology growth There are multiple twins, the direction of growth of nano wire to be difficult to control when GaAs nano wires, a large amount of inclined nano wires, limitation occurs The problem that GaAs nano wires are applied in the devices, to realize that high quality, high-performance GaAs nano-wire devices establish material foundation.

Claims (5)

1. a kind of preparation method of upright GaAs nano wires, which is characterized in that this method is by using HF acid to Si substrate surfaces It is handled, keeps Si substrate surfaces roughening, and the oxide layer of Si substrate surfaces is partially removed, Si is being served as a contrast by HF acid Bottom surface etching processing realizes the purpose controlled Si substrate surface oxidated layer thickness, adjusts Si substrate surface oxidated layer thickness And the roughness of Si substrate surfaces makes to realize the adjusting of the contact angle to Ga catalyst droplets Yu Si substrate surfaces indirectly Ga catalyst droplets have suitable contact angle with Si substrate surfaces, realize the growth for inhibiting multiple twin, make GaAs nano wires Can vertical growth, there are multiple twin, the directions of growth of nano wire when solving existing self-catalysis epitaxial growth GaAs nano wires It is difficult to control, a large amount of inclination nano wires, the problem that limitation GaAs nano wires are applied in the devices, the Ga drops catalyst occurs The growth that upright GaAs nano wires may be implemented in angle is suitably contacted between Si substrate surfaces, HF acid described in this method is right The processing of Si substrate surface natural oxidizing layers completes Si substrate surfaces when the oxidated layer thickness of Si substrate surfaces is 0.8nm certainly The HF acid etches processing of right oxide layer, the Si substrate surfaces natural oxidizing layer can make Ga liquid when being etched to 0.8nm thickness Drop catalyst has suitable contact angle with Si substrate surfaces, when carrying out the growth of GaAs nano-materials, Ga catalyst droplets The growth that angle keeps GaAs nano wires upright is suitably contacted with Si substrate surfaces, the Ga drops catalyst is in Si substrate surfaces After formation, the 80s of pause 80s, the pause can enable Ga drops fully dispersed, ensure the suitable size of drop, make Ga There are one suitable surface contact angle, this described conjunctions with the Si substrate surfaces by the processing of HF acid etches for drop catalyst Suitable surface contact angle realizes the upright growth of GaAs nano wires.
2. a kind of preparation method of upright GaAs nano wires as described in claim 1, which is characterized in that this method utilizes Ga liquid Drop is used as catalyst, the growth mechanism of self-catalysis to be grown, and Si substrate surfaces are handled using HF acid, makes Si substrate surfaces oneself Right oxide layer is etched, and the thickness of oxide layer is 0.8nm, Ga liquid after the natural oxidizing layer of Si substrate surfaces is etched in this method Catalyst is dripped with the Si substrate surfaces of the oxidated layer thickness there are one contact angle, this described contact angle is suitble to GaAs to receive The upright growth of rice noodles.
3. a kind of preparation method of upright GaAs nano wires as described in claim 1, which is characterized in that served as a contrast to Si using HF acid Bottom surface oxide layer processing the specific steps are:1, by HF:H2O is with 1:10 ratio prepares etching liquid, and etching condition is room temperature, It is performed etching under daylight light irradiation environmental condition;2, by Si substrates be put into prepared etching liquid to Si substrate surfaces from Right oxide layer performs etching, etch period 2s;3, Si substrates are taken out from etching liquid, utilizes ellipsometer measurement Si substrate tables The oxide layer film thickness in face, when oxidated layer thickness is thicker, etch period is less, and Si substrate surfaces oxidated layer thickness does not reach expected It is required that when, Si substrates are put into etching liquid and continue to etch, until Si substrate surface oxidated layer thickness reaches realization of the present invention 0.8nm thickness requirements required by GaAs nano wire vertical growths.
4. a kind of preparation method of upright GaAs nano wires as described in claim 1, which is characterized in that carrying out GaAs nanometers When line is grown, when Ga drops catalyst is when Si substrate surfaces generate, the 80s of pause 80s, pause can enable Ga drops Enough fully to spread and be in stable state, it is suitable size to make Ga drops, realizes Ga drops catalyst and passes through HF acid etches There are one suitable surface contact angle, the suitable surface contact angles may be implemented to instruct GaAs for the Si substrate surfaces of processing Nano wire vertical growth.
5. a kind of preparation method of upright GaAs nano wires as described in claim 1, which is characterized in that by using the present invention This method proposed, first, performing etching processing to Si substrate surface natural oxidizing layers enables Ga drops catalyst to be served as a contrast with Si Bottom surface has suitable contact angle, then, when growing GaAs nano wires, stops 80s when Ga drop formations, makes Ga drops It fully spreads and is in stable state with the contact of Si substrates, finally, carry out nanowire growth, obtain upright GaAs nano wires Material, when solving existing self-catalysis epitaxial growth GaAs nano wires, there are the directions of growth of multiple twin, nano wire to be difficult to control System, occur it is a large amount of tilt nano wires, the problem of limitation GaAs nano wires are applied in the devices, method proposed by the invention can be with Upright high quality GaAs nano-materials are realized, to pushing the improvement of GaAs nano-wire devices performances to establish material foundation.
CN201810032745.4A 2018-01-17 2018-01-17 A kind of preparation method of upright GaAs nano wires Pending CN108364850A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109801835A (en) * 2018-12-14 2019-05-24 华南理工大学 A kind of method of grown at low temperature GaAs nano wire
CN109767972B (en) * 2018-12-13 2021-05-14 华南理工大学 Method for growing GaAs nanowire on Si substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367588A (en) * 2013-07-11 2013-10-23 中国科学院半导体研究所 Method for developing quantum dot on side wall of GaAs nanowire by utilizing nanoring as mask
CN103531679A (en) * 2013-10-23 2014-01-22 中国科学院半导体研究所 Method for preparing quantum-dot single photon source in hexagonal-prism nano microcavity

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367588A (en) * 2013-07-11 2013-10-23 中国科学院半导体研究所 Method for developing quantum dot on side wall of GaAs nanowire by utilizing nanoring as mask
CN103531679A (en) * 2013-10-23 2014-01-22 中国科学院半导体研究所 Method for preparing quantum-dot single photon source in hexagonal-prism nano microcavity

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
FEDERICO MATTEINI ET AL: "Ga-assisted growth of GaAs nanowires on silicon, comparison of surface SiOx of different nature", 《JOURNAL OF CRYSTAL GROWTH》 *
MADSEN ET AL: "Influence of the oxide layer for growth of self-assisted InAs nanowires on Si(111)", 《NANOSCALE RESEARCH LETTERS》 *
MATTEINI ET AL: "Impact of the Ga droplet wetting, morphology, and pinholes on the orientation of GaAs nanowires", 《CRYSTAL GROWTH DESIGN》 *
MATTEINI ET AL: "Wetting of Ga on SiOx and Its Impact on GaAs Nanowire Growth", 《CRYSTAL GROWTH DESIGN》 *
SIEW LI TAN ET AL: "Highly uniform zinc blende GaAs nanowires on Si(111) using a controlled chemical oxide template", 《NANOTECHNOLOGY》 *
戴遐明: "《纳米陶瓷材料及其应用》", 30 June 2005 *
陈永: "《纳米材料制备与改性》", 31 July 2008 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109767972B (en) * 2018-12-13 2021-05-14 华南理工大学 Method for growing GaAs nanowire on Si substrate
CN109801835A (en) * 2018-12-14 2019-05-24 华南理工大学 A kind of method of grown at low temperature GaAs nano wire

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Application publication date: 20180803