CN108364671B - Parity check device of semiconductor memory and semiconductor memory - Google Patents
Parity check device of semiconductor memory and semiconductor memory Download PDFInfo
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- CN108364671B CN108364671B CN201810362508.4A CN201810362508A CN108364671B CN 108364671 B CN108364671 B CN 108364671B CN 201810362508 A CN201810362508 A CN 201810362508A CN 108364671 B CN108364671 B CN 108364671B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The embodiment of the invention discloses a parity check device of a semiconductor memory and the semiconductor memory. The parity check device comprises a memory controller for providing a first signal and generating a first parity check bit; a check circuit connected with the memory controller to receive the second signal and the first parity bit formed by the first signal; the checking circuit generates a parity check result; an output control circuit connected with the memory controller to receive the second signal and the first clock signal synchronized with the first signal, and generate an output instruction and the second clock signal; the buffer circuit is connected with the check circuit and the output control circuit and outputs a parity check result according to the output instruction; and the output circuit is connected with the buffer circuit and the output control circuit, receives the parity check result, and outputs the parity check result according to the second clock signal so that the clock cycle number of the parity check result, which is delayed relative to the first signal at the moment of outputting the parity check result from the output circuit, is a preset value, and the preset value is a positive integer larger than 1.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a parity check device for a semiconductor memory and a semiconductor memory.
Background
The parity check result of the traditional dynamic random access memory aiming at the command and address buses is asynchronous, when the parity check result shows errors, only the time period of which command signal or address bus signal is in error in transmission can be known, so that the controller of the dynamic random access memory needs to execute all command signals or address bus signals in the time period again, the error correction efficiency of the dynamic random access memory is lower, and the development requirement of the dynamic random access memory cannot be met.
Therefore, how to improve the error correction efficiency of the parity check result for the command and address buses of the dynamic random access memory is a technical problem that the skilled person is urgent to solve.
The above information disclosed in the background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a parity check device of a semiconductor memory and the semiconductor memory, so as to at least solve the technical problems in the background art.
The technical solution of the embodiment of the present invention is achieved by providing, according to one embodiment of the present invention, a parity check device of a semiconductor memory, including:
a memory controller for providing a first signal and generating a first parity bit according to the first signal;
a check circuit connected with the memory controller to receive the first signal and the first parity bit formed by the first signal transmitted to the check circuit; the check circuit is used for generating a second parity check bit according to the second signal and generating a parity check result according to the first parity check bit and the second parity check bit;
an output control circuit connected with the memory controller to receive a second signal and a first clock signal synchronized with the first signal, for generating an output instruction and a second clock signal according to the second signal and the second signal, respectively;
the buffer circuit is connected with the check circuit and the output control circuit and is used for storing the parity check result and outputting the parity check result according to the output instruction; and
and the output circuit is connected with the buffer circuit and the output control circuit, is used for receiving the parity check result output by the buffer circuit, is used for receiving the second clock signal output by the output control circuit, and is used for outputting the parity check result according to the second clock signal so that the clock cycle number of the moment of outputting the parity check result from the output circuit relative to the first signal is a preset value, and the preset value is a positive integer greater than 1.
As an alternative, the output control circuit includes:
a delay phase-locked loop circuit connected with the memory controller to receive a first clock signal synchronized with the first signal and generate a third clock signal, and connected with the output circuit through a delay line to delay the third clock signal to generate the second clock signal;
the third clock signal is advanced by a first time than the first clock signal, and the first time is equal to the time when the third clock signal is transmitted to the output end of the output circuit through the delay line.
As an alternative, the delay locked loop circuit is further configured to synchronize the second signal using the third clock signal to form a third signal;
the output control circuit further includes:
the delay circuit is connected with the delay phase-locked loop circuit to receive the third signal and is used for delaying the third signal for a second time according to the preset value to generate a fourth signal; and
an output instruction generating circuit connected to the delay circuit to receive the fourth signal, and connected to the buffer circuit; the output instruction generating circuit is used for generating the output instruction according to the received fourth signal and outputting the output instruction to the buffer circuit;
wherein the second time is (preset value-1/K) clock cycles, K is a natural number greater than 1 and 1/K clock cycles are greater than a time difference between outputting the fourth signal from the delay circuit and receiving the parity check result by the output circuit.
According to still another embodiment of the present invention, there is provided a semiconductor memory including any one of the parity check devices described above.
The parity check device of the semiconductor memory and the semiconductor memory of the embodiment of the invention. When the parity check result output by the output circuit shows that the second signal is different from the first signal at a certain moment, the first signal is wrong in the process of being transmitted to the check circuit, and the wrong first signal is a first signal of a preset value for a clock period before the moment, so that the wrong first signal can be accurately found, and therefore, the semiconductor memory only needs to execute the wrong first signal again. The parity check device of the semiconductor memory can accurately find the first error signal, has high error correction efficiency, and can adapt to the development requirement of the semiconductor memory.
The foregoing summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will become apparent by reference to the drawings and the following detailed description.
Drawings
In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not therefore to be considered limiting of its scope.
FIG. 1 is a schematic diagram of a parity check device of a semiconductor memory according to an embodiment of the present invention;
fig. 2 is a timing diagram of an example of a parity check device of the semiconductor memory shown in fig. 1.
Reference numerals illustrate:
100. the memory controller is configured to store the data,
200. the verification circuitry is configured to verify that the circuit,
210. a parity bit generation circuit that generates a parity bit,
220. the comparison circuit is used for comparing the data of the data,
300. the output control circuit is used for controlling the output of the control circuit,
310. a delay locked loop circuit is provided which,
311. the delay line is used to delay the time of the signal,
320. the delay circuit is provided with a delay circuit,
330. an output instruction generating circuit for generating an output instruction,
340. the register circuitry is configured to store the data,
400. the cache circuit is used for storing the data,
500. the output circuit is provided with a voltage-limiting circuit,
510. the output end of the output circuit is provided with a control circuit,
520. the output driving circuit is provided with a driving circuit,
600. an input instruction generating circuit.
Detailed Description
Hereinafter, only certain exemplary embodiments are briefly described. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
Example 1
An embodiment of the present invention provides a parity check device of a semiconductor memory, as shown in fig. 1 and 2, including:
a memory controller 100 for providing a first signal and generating a first parity bit according to the first signal;
a check circuit 200 connected to the memory controller 100 to receive the first signal and the first parity bit formed by the first signal transmitted to the check circuit 200; the check circuit 200 is configured to generate a second parity bit according to the second signal, and generate a parity result according to the first parity bit and the second parity bit;
an output control circuit 300 connected to the memory controller 100 to receive the second signal and a first clock signal synchronized with the first signal, for generating an output instruction and a second clock signal according to the second signal and the first clock signal, respectively;
the buffer circuit 400 is connected with the check circuit 200 and the output control circuit 300, and is used for storing the parity check result and outputting the parity check result according to the output instruction; and
the output circuit 500 is connected to the buffer circuit 400 and the output control circuit 300, and is configured to receive the parity result output by the buffer circuit, and is configured to receive the second clock signal output by the output control circuit 300, and is configured to output the parity result according to the second clock signal, so that the number of clock cycles at which the timing of outputting the parity result from the output circuit 500 is delayed with respect to the first signal is a preset value, and the preset value is a positive integer greater than 1.
The parity check device of the semiconductor memory of the embodiment of the invention comprises a memory controller, a check circuit, a buffer circuit, an output circuit and an output control circuit. The check circuit is respectively connected with the storage controller and the buffer circuit, the storage controller provides a first signal and generates a first parity check bit according to the first signal, so that the check circuit generates a second parity check bit according to a second signal formed by transmitting the first signal to the check circuit, and generates a parity check result according to the first parity check bit and the second parity check bit, and the buffer circuit stores the parity check result. Thus, the parity result is stored in the buffer circuit. The output control circuit is connected with the buffer circuit and the output circuit respectively, and is connected with the storage controller to receive a second signal and a first clock signal synchronous with the first signal, and is used for generating an output instruction and a second clock signal respectively according to the first clock signal and the second signal, the buffer circuit stores a parity check result and outputs the parity check result according to the output instruction, the output circuit receives the parity check result and the second clock signal and outputs the parity check result according to the second clock signal, so that the clock cycle number of the moment of outputting the parity check result from the output circuit relative to the first signal is a preset value, and the preset value is a positive integer larger than 1. In this way, when the parity check result output by the output circuit shows that the second signal is different from the first signal at a certain moment, it is indicated that the first signal is wrong in the process of being transmitted to the check circuit, and the wrong first signal is the first signal of a preset value for a clock period before the moment, so that the wrong first signal can be found accurately, and therefore, the semiconductor memory only needs to execute the wrong first signal again. The parity check device of the semiconductor memory can accurately find the first error signal, has high error correction efficiency, and can adapt to the development requirement of the semiconductor memory.
With respect to the first signal, at least one of a command signal and a bus address signal is included. In fig. 2, the preset value is 10, the first signal is a command signal, and the clock cycle number of the parity result delayed with respect to the first signal at the time of output from the output circuit is the preset value.
In order to achieve a predetermined number of clock cycles delayed with respect to the first signal at the time when the parity result is output from the output circuit. As shown in fig. 1 and 2, the output control circuit 300 needs to include:
a delay locked loop circuit 310 connected to the memory controller 100 to receive the first clock signal synchronized with the first signal and generate a third clock signal, and connected to the output circuit 500 through a delay line 311 to delay the third clock signal to generate a second clock signal;
the third clock signal is advanced by a first time period, which is equal to the time period when the third clock signal is transmitted to the output terminal 510 of the output circuit through the delay line 311.
Defining the clock period of the first clock signal where the first signal is located as the first clock period of the first clock signal, wherein the preset value is represented by m, and the delay time of the delay line is represented by t 1 Time t representing delay of output circuit 2 In the case of representation, the third clock signal is advanced by a time t from the first clock signal 1 +t 2 Further, the (m+1) th clock cycle of the third clock signal is delayed by the delay line to generate the (m+1) th clock cycle of the second clock signal, and the (m+1) th clock cycle of the second clock signal is advanced by t relative to the (m+1) th clock cycle of the first clock signal 2 The time reaches the output circuit, the second clock signal controls the parity check result in the output circuit to start outputting, and the time required by the output circuit to output the parity check result is t 2 The clock cycle number of the time parity check result output by the parity check result output circuit relative to the first clock signal is m, and the clock cycle number of the time parity check result output by the parity check result output circuit relative to the first signal is a preset value because the first signal and the first clock signal are synchronous. In fig. 2, the third clock signal is advanced by 1/4 clock period from the first clock signal.
In order to achieve that the number of clock cycles at which the parity result is delayed relative to the first signal is a preset value at the time when the parity result is output from the output circuit, it is necessary to ensure that the parity result is already in the output circuit when the m+1th clock cycle of the second clock signal arrives at the output circuit, and therefore it is necessary to control the time when the buffer circuit outputs the parity result to the output circuit.
It is therefore necessary that the delay locked loop circuit 310 is also connected to the verification circuit 200 to receive the second signal, as shown in fig. 1; wherein the delay locked loop circuit 310 is further configured to synchronize the second signal using the third clock signal to form a third signal;
the output control circuit further includes a delay circuit 320 and an output instruction generation circuit 330;
the delay circuit 320 is connected to the delay phase-locked loop circuit 310 to receive the third signal, delay the third signal by a second time according to a preset value to generate a fourth signal, and output the fourth signal to the output instruction generating circuit 330;
an output instruction generating circuit 330 connected to the delay circuit 320 to receive the fourth signal, and connected to the buffer circuit 400; the output instruction generating circuit 330 is configured to generate an output instruction after receiving the fourth signal, and output the output instruction to the buffer circuit 400;
wherein the second time is (preset value-1/K) clock cycles, K is a natural number greater than 1 and 1/K clock cycles are greater than a time difference between outputting the fourth signal from the delay circuit and receiving the parity check result from the output circuit. In FIG. 2, 1/K clock cycles are 1/2 clock cycles.
Because the third signal is synchronous with the third clock signal, the delay time of the fourth signal relative to the third clock signal is (preset value-1/K) clock cycles, and the effect that 1/K clock cycles are less than the preset value clock cycles is that the 1/K clock cycles are reserved as delay circuits to output the fourth signal to the output instruction generating circuit, the output instruction generating circuit generates an output instruction and outputs the output instruction to the buffer circuit, and the buffer circuit receives the output instruction and then outputs the parity check result to the output circuit; at the same time, the third clock signal is advanced from the first clock signal, so that the parity check result reaches the output circuit at a time earlier than the m+1th clock period of the second clock signal.
To achieve that the output control circuit obtains a preset value, as shown in fig. 1, the output control circuit 300 further includes a register circuit 340, and the delay circuit 320 is connected to the register circuit 340 to receive the preset value provided by the register circuit 340.
In order to realize the work when the output circuit needs to output the parity check result, the output circuit does not work when the output circuit does not need to output the parity check result, so as to achieve the purpose of energy saving. As shown in fig. 1, delay circuit 320 also requires a connection to output circuit 500; the delay circuit 320 is further configured to generate an output enable signal according to the third signal and output the output enable signal to the output circuit 500, where the output enable signal is at an active level within a preset time, the output enable signal is delayed (preset value-1/L) by a clock period compared with the third signal, L is a natural number greater than 1, and L is less than K. In fig. 2, the output enable signal is advanced to the output instruction, so that the output instruction can be guaranteed to be capable of controlling the buffer circuit to output the parity check result.
As to the specific structure of the output circuit, as shown in fig. 1, the output circuit 500 includes an output driving circuit 520 and an output pin 510 connected to the output driving circuit, the output pin serving as an output terminal 510 of the output circuit;
the output driving circuit 520 is connected to the delay line 311 to receive the second clock signal, the output driving circuit is connected to the delay circuit 320 to receive the output enable signal, and the output driving circuit is connected to the buffer circuit 400 to receive the parity result, wherein the output driving circuit 520 is configured to drive the parity result to be output from the output pin according to the control of the output enable signal and the second clock signal.
The specific structure of the verification circuit is as follows: as shown in fig. 1, the check circuit 200 includes a parity bit generation circuit 210 and a comparison circuit 220, the parity bit generation circuit 210 being connected to the memory controller 100 to receive the second signal and generate a second parity bit;
a comparison circuit 220 connected to the memory controller 100 to receive the first parity bit, and connected to the parity bit generation circuit 210 to receive the second parity bit, and connected to the buffer circuit 400; wherein the comparing circuit 220 is configured to generate a parity result according to the first parity bit and the second parity bit and output the parity result to the buffer circuit 400.
The check circuit takes a certain time to generate the parity result.
The parity check device of the semiconductor memory stores the parity check result in the buffer circuit for realizing. As shown in fig. 1, the parity check device of the semiconductor memory further needs to include:
an input instruction generating circuit 600 connected to the checking circuit 200 to receive the second signal and connected to the buffer circuit 600; the input instruction generating circuit 600 is configured to generate an input instruction according to the second signal and output the input instruction to the buffer circuit 400, where the input instruction is configured to control the buffer circuit 400 to store the parity check result.
After the parity result is generated, the parity result is stored in the buffer circuit by the input instruction.
Specifically, the buffer circuit is a first-in first-out buffer circuit, and the input instruction generating circuit is a first-in first-out input instruction generating circuit correspondingly, and the output instruction generating circuit is a first-in first-out input instruction output instruction generating circuit.
Example two
The embodiment of the invention provides a semiconductor memory, which comprises a parity check device in the first embodiment.
In describing the present invention and its embodiments, it should be understood that the orientation or positional relationship indicated by the terms "top", "bottom", "height", etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description and simplification of the description, and are not indicative or implying that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
In the present invention and its embodiments, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," "secured," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrated; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention and its embodiments, unless explicitly specified and limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include both the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.
The above disclosure provides many different embodiments, or examples, for implementing different structures of the invention. The foregoing description of specific example components and arrangements has been presented to simplify the present disclosure. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that various changes and substitutions are possible within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (11)
1. A parity check device for a semiconductor memory, comprising:
a memory controller for providing a first signal and generating a first parity bit according to the first signal;
a check circuit connected with the memory controller to receive the first signal and the first parity bit formed by the first signal transmitted to the check circuit; the check circuit is used for generating a second parity check bit according to the second signal and generating a parity check result according to the first parity check bit and the second parity check bit;
an output control circuit connected with the memory controller to receive a second signal and a first clock signal synchronized with the first signal, for generating an output instruction and a second clock signal according to the second signal and the first clock signal, respectively;
the buffer circuit is connected with the check circuit and the output control circuit and is used for storing the parity check result and outputting the parity check result according to the output instruction; and
the output circuit is connected with the buffer circuit and the output control circuit, and is used for receiving the parity check result output by the buffer circuit, receiving the second clock signal output by the output control circuit, and outputting the parity check result according to the second clock signal so that the clock cycle number of the parity check result delayed relative to the first signal at the moment of outputting from the output circuit is a preset value, and the preset value is a positive integer greater than 1; wherein the parity check result reaches the output circuit a predetermined value +1 clock cycle earlier than the second clock signal reaches the output circuit.
2. The parity check device of a semiconductor memory according to claim 1, wherein the output control circuit comprises:
a delay phase-locked loop circuit connected with the memory controller to receive a first clock signal synchronized with the first signal and generate a third clock signal, and connected with the output circuit through a delay line to delay the third clock signal to generate the second clock signal;
the third clock signal is advanced by a first time than the first clock signal, and the first time is equal to the time when the third clock signal is transmitted to the output end of the output circuit through the delay line.
3. The parity check device of claim 2 wherein the delay locked loop circuit is further configured to synchronize the second signal using the third clock signal to form a third signal; the output control circuit further includes:
the delay circuit is connected with the delay phase-locked loop circuit to receive the third signal and is used for delaying the third signal for a second time according to the preset value to generate a fourth signal; and
an output instruction generating circuit connected to the delay circuit to receive the fourth signal, and connected to the buffer circuit; the output instruction generating circuit is used for generating the output instruction according to the received fourth signal and outputting the output instruction to the buffer circuit;
wherein the second time is (preset value-1/K) clock cycles, K is a natural number greater than 1 and 1/K clock cycles are greater than a time difference between outputting the fourth signal from the delay circuit and receiving the parity check result by the output circuit.
4. A parity check device for a semiconductor memory according to claim 3, wherein the output control circuit further comprises a register circuit, the delay circuit being connected to the register circuit to receive the preset value provided by the register circuit.
5. The parity check device of claim 3 wherein the delay circuit is further configured to generate an output enable signal from the third signal and output the output enable signal to the output circuit, the output enable signal being at an active level for a preset time, wherein the output enable signal is delayed (preset value-1/L) by a clock cycle from the third signal, L is a natural number greater than 1 and L is less than K.
6. The parity check device of a semiconductor memory according to claim 5, wherein the output circuit includes an output driving circuit and an output pin connected to the output driving circuit, the output pin serving as an output terminal of the output circuit;
the output driving circuit is connected with the delay line to receive the second clock signal, is connected with the delay circuit to receive the output enabling signal, is connected with the buffer circuit to receive the parity check result, and is used for driving the parity check result to be output from the output pin according to control of the output enabling signal and the second clock signal.
7. The parity check device of a semiconductor memory according to claim 1, wherein the check circuit comprises:
a parity generating circuit coupled to the memory controller to receive the second signal and generate the second parity;
a comparison circuit connected with the memory controller to receive the first parity bit, and connected with the parity bit generation circuit to receive the second parity bit; the comparison circuit is used for generating the parity check result according to the first parity check bit and the second parity check bit and outputting the parity check result to the buffer circuit.
8. The parity check device of a semiconductor memory according to claim 1, further comprising:
an input instruction generating circuit connected with the checking circuit for receiving the second signal; the input instruction generating circuit is used for generating an input instruction according to the second signal and outputting the input instruction to the buffer circuit, and the input instruction is used for controlling the buffer circuit to store the parity check result.
9. The parity check device of claim 8 wherein the buffer circuit is a first-in first-out buffer circuit and the input instruction generating circuit is a first-in first-out input instruction generating circuit.
10. The parity check device of claim 1 wherein the first signal comprises at least one of a command signal and a bus address signal.
11. A semiconductor memory comprising the parity check device of any one of claims 1 to 10.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008192206A (en) * | 2007-02-01 | 2008-08-21 | Matsushita Electric Ind Co Ltd | Semiconductor memory device |
| CN102315902A (en) * | 2010-07-07 | 2012-01-11 | 中国科学院微电子研究所 | Universal addressing device and method of quasi-cyclic low-density parity check code |
| KR20160068369A (en) * | 2014-12-05 | 2016-06-15 | 에스케이하이닉스 주식회사 | Circuit for checking parity and memory including the same |
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| US8806316B2 (en) * | 2012-01-11 | 2014-08-12 | Micron Technology, Inc. | Circuits, integrated circuits, and methods for interleaved parity computation |
| US9389953B2 (en) * | 2013-03-04 | 2016-07-12 | Samsung Electronics Co., Ltd. | Semiconductor memory device and system conducting parity check and operating method of semiconductor memory device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008192206A (en) * | 2007-02-01 | 2008-08-21 | Matsushita Electric Ind Co Ltd | Semiconductor memory device |
| CN102315902A (en) * | 2010-07-07 | 2012-01-11 | 中国科学院微电子研究所 | Universal addressing device and method of quasi-cyclic low-density parity check code |
| KR20160068369A (en) * | 2014-12-05 | 2016-06-15 | 에스케이하이닉스 주식회사 | Circuit for checking parity and memory including the same |
| CN106205728A (en) * | 2014-12-05 | 2016-12-07 | 爱思开海力士有限公司 | Parity checker and include the storage arrangement of this parity checker |
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