CN108363839A - The optimal pin of extensive BGA package based on priori is distributed generation method - Google Patents
The optimal pin of extensive BGA package based on priori is distributed generation method Download PDFInfo
- Publication number
- CN108363839A CN108363839A CN201810065483.1A CN201810065483A CN108363839A CN 108363839 A CN108363839 A CN 108363839A CN 201810065483 A CN201810065483 A CN 201810065483A CN 108363839 A CN108363839 A CN 108363839A
- Authority
- CN
- China
- Prior art keywords
- pin
- matrix
- optimal
- return path
- extensive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2113/00—Details relating to the application field
- G06F2113/18—Chip packaging
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Architecture (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The optimal pin of extensive BGA package that the invention discloses a kind of based on priori is distributed generation method,The design of encapsulated circuit progress pin distribution is replaced with matrix,The element of wherein internal matrix includes signal pins,Power pins,Ground pin,By this three classes pin with 0,1,2 replace and are filled into the first column vector of matrix,It is to start with the element of the first column vector,It is shifted to obtain next column element successively,Finally obtain complete matrix,Then multiple and different matrixes can be obtained by changing the distance of displacement,Optimal matrix can be obtained according to the total inductance of each matrix and return path quality,The corresponding pin distribution of the matrix is that optimal pin is distributed,The method of the present invention need not carry out time-consuming iterative search,It highly shortened and solve the time,And the optimal solution constructed under identical parameter is more stable,The signal integrity of encapsulated circuit is also relatively strong.
Description
Technical field
The present invention relates to lsi package field, especially a kind of extensive BGA envelopes based on priori
Fill optimal pin distribution generation method.
Background technology
With the development of semiconductor technology and Information technology, the function that single integrated circuit has also becomes more and more multiple
It is miscellaneous so that the input and output pin number on integrated antenna package sharply increases, and power problems and electromagnetic compatibility problem are also increasingly
Highlight, to encapsulation technology, more stringent requirements are proposed, in order to meet these requirements, baii grid array (BGA) encapsulation meet the tendency of and
It is raw, welded ball array is made as the electrical connection between chip and printed circuit board in the bottom of package substrate, can be provided than it
It encapsulates more number of pins.
Although BGA package can provide good switching performance, number of pins drastically increases so that under BGA package
Signal integrity gradually degrades, and is distributed by rational pin, and the mutual inductance that direction can be made opposite is cancelled out each other, to significantly
The influence to signal integrity is reduced, therefore how to find an optimal pin distribution to seem very heavy in a chip design
It wants, there are some pin distribution generation methods based on Stochastic Optimization Algorithms to be suggested recently, they can efficiently solve this kind of
Problem, but longer time is required for be iterated search, and also these algorithms are unstable, it is difficult to accomplish to search every time
Same solution, which prevent it to apply to industrial production.
Invention content
To solve the above problems, the purpose of the present invention is to provide a kind of extensive BGA package based on priori is most
Excellent pin is distributed generation method, can construct optimal solution or approximate optimal solution, need not carry out time-consuming iterative search, greatly
Ground, which shortens, solves the time, and the optimal solution constructed under identical parameter is more stable.
Technical solution is used by the present invention solves the problems, such as it：
A kind of optimal pin of extensive BGA package based on priori is distributed generation method, includes the following steps：
A, determine that the ratio of the sum of ic power pin and ground pin and the upper total pin number of encapsulation, scale parameter are set
It is set to 1：R, while perpendicular separation parameter vi and horizontal interval parameter hi are set, and vi*hi=R；
B, the identical matrix of a dimensional values is arranged according to the package dimension M*N of integrated circuit；
C, the vectorial col that a length is M is generated, it, will after the compensating length comp for calculating outgoing vector col according to M and vi
Vectorial col extends comp unit；
D, by signal pins, power pins, pin respectively with 0,1,2 element representations, filled out in the vectorial col after extending
Enter 0,1,2 elements, wherein non-zero element discontinuously occurs, and is separated by vi-1 0 between non-zero element；
E, the element in vectorial col will be filled in as the first row of matrix, next column is by the element of previous column vertical
Square upward displacement obtains, and complete matrix is obtained after the element of comp unit of all row lowermost ends is removed, wherein next
The distance of row and the unit of previous column horizontal interval hi, displacement is d；
F, change translocation distance d, obtain multiple and different matrixes, calculate separately each matrix total inductance and return path matter
Amount, obtains optimal matrix, corresponding member in the matrix according to the data of the total inductance of all matrixes and return path quality
Element is that optimal pin is distributed.
Further, perpendicular separation parameter vi and horizontal interval parameter hi is arranged simultaneously in the step A, wherein perpendicular separation
Parameter vi is the spacing distance between each two element in same row, horizontal interval parameter hi be with each two element in a line it
Between spacing distance.
Further, vi*hi=R in the step A, if vi and hi have multigroup product, every group of product to carry out respectively subsequent
The total inductance of all matrixes of every group of obtained product and return path quality are compared, are obtained optimal by all steps
Pin distribution.By the setting of different vi and hi, multigroup matrix can be calculated, so as in the square of different products
Optimal pin distribution is found in battle array.
Further, according to M and vi in the step C, after the compensating length comp for calculating outgoing vector col, vectorial col is prolonged
Long comp unit, the calculation formula of wherein compensating length comp are：
Comp=2*vi-mod (M, 2*vi)
Mod is to take the remainder operation.Compensating length, which can play, maintains vector shift to be distributed constant effect.
Further, the element in vectorial col will be filled in the step E as the first row of matrix, next column is by upper
The element of one row shifts in vertical direction to be obtained, and in displacement, element is moved down as unit of translocation distance d, each
The element of row bottom is moved to the top of the row.
Further, each matrix total inductance and return path quality, the wherein meter of total inductance are calculated separately in the step F
Calculating formula is：
Wherein aijFor mutual inductance, it is 1 when i-th of pin is identical as j-th of pin current direction, is -1 when different, works as i=
When j, aij=0；Mutual inductance value between a pair of pins, wherein dijFor the Euclidean between i-th of pin and j-th of pin
Distance；dmaxMaximum Euclidean distance of the minimum value between all pins pair.
Further, each matrix total inductance and return path quality, wherein return path matter are calculated separately in the step F
The calculation formula of amount is：
Dsum=D (dmin)-E(dmin)
Wherein dminFor each power supply or ground pin to the collection of the Euclidean distance of its another nearest power supply or ground pin
It closes, D (dmin) be the set variance, E (dmin) be the set mean value.
Further, it is obtained according to the total inductance of all matrixes and the data of return path quality in the step F optimal
Matrix, corresponding element is that optimal pin is distributed in the matrix, from multigroup total inductance and the data of return path quality
In obtain the value and its corresponding total inductance of return path quality minimum, the pin of matrix corresponding to this group of data is distributed as most
Excellent pin distribution, corresponding translocation distance are optimal shift distance.Return path quality minimum and total inductance also have close
When the value of minimum, the mutual inductance between encapsulated circuit pin is smaller, and the influence to signal integrity is also smaller.
Further, if the data of return path quality minimum and its corresponding total inductance have multigroup same case, choosing
It is Optimal matrix to take the matrix of translocation distance minimum, and the corresponding pin of the matrix is distributed as optimal pin distribution.
The beneficial effects of the invention are as follows：A kind of extensive BGA package based on priori that the present invention uses is optimal to draw
Foot is distributed generation method, replaces encapsulated circuit to carry out the design of pin distribution with matrix, the wherein element of internal matrix includes letter
Number pin, power pins, pin, this three classes pin is replaced with 0,1,2 and is filled into the first column vector of matrix, with the
One column vector be start, shifted to obtain next column vector successively, finally obtain complete matrix, then change displacement away from
From multiple and different matrixes can be obtained, optimal square can be obtained according to the total inductance of each matrix and return path quality
Battle array, the corresponding pin distribution of the matrix are that optimal pin is distributed, and method of the invention need not carry out time-consuming iteration and search
Rope, highly shortened solve the time, and the optimal solution constructed under identical parameter be it is more stable, encapsulated circuit
Signal integrity is also relatively strong.
Description of the drawings
The invention will be further described with example below in conjunction with the accompanying drawings.
Fig. 1 is a kind of flow of the optimal pin distribution generation method of extensive BGA package based on priori of the invention
Block diagram；
Fig. 2 is the composition schematic diagram of vectorial col；
Fig. 3 is the shifting process schematic diagram of vectorial col；
Fig. 4 is the schematic diagram after the completion of matrix B structure；
Fig. 5 is the curve graph of the total inductance obtained under the different shift amount d of input；
Fig. 6 is the curve graph of the return path quality obtained under the different shift amount d of input.
Specific implementation mode
Referring to Fig.1, a kind of optimal pin of extensive BGA package based on priori of the invention is distributed generation method,
Include the following steps：The ratio for determining the sum of ic power pin and ground pin and the upper total pin number of encapsulation first, will
Scale parameter is set as 1：R, while perpendicular separation parameter vi and horizontal interval parameter hi are set, and make vi*hi=R, root
The identical matrix of one dimensional values is set according to the package dimension M*N of integrated circuit, generates the vectorial col that a length is M, root
According to M and vi, after the compensating length comp for calculating outgoing vector col, vectorial col is extended into comp unit, is distinguished with 0,1,2 elements
Indicate signal pins, power pins, pin, then toward extend after vectorial col in filling 0,1,2 elements, wherein non-zero element
It is discontinuous to occur, and separated by vi-1 0 between non-zero element, the element in vectorial col will be filled in as the first of matrix
Row, next column hereafter all shift by the element of previous column in vertical direction to be obtained, and the distance of displacement is d, is being owned
Row after, will comp unit of all row lowermost ends element remove after obtain complete matrix, finally change translocation distance
D obtains multiple and different matrixes, calculates separately each matrix total inductance and return path quality, according to total electricity of all matrixes
The data of sense and return path quality obtain optimal matrix, and corresponding element is that optimal pin is distributed in the matrix, this
The method of invention need not carry out time-consuming iterative search, and optimal pin distribution can be calculated in a relatively short period of time,
It is distributed influence of the entanglement to signal integrity from pin is reduced.
Specifically, perpendicular separation parameter vi be to be configured as unit of the distance between two elements in vertical direction,
Horizontal interval parameter hi is to be configured as unit of the distance between two elements in horizontal direction.
The specific steps of the present invention are illustrated with design parameter below, the wherein package dimension of integrated circuit is 21*21, institute
With the positive matrices that the matrix of setting is 21 rows 21 row, the ratio of the summation and total pin that determine power pins and ground pin is 1：4,
So vi=4, hi=1, and vi*hi=4 can be arranged, vectorial translocation distance d is set as 2.
Then vector can be calculated according to formula as shown in Figure 2 a by firstly generating the vectorial col that a length is 21
The compensating length comp of col, wherein formula are：
Comp=2*vi-mod (M, 2*vi)
Vi=4, M=21 are brought into above formula, wherein mod is to take the remainder operation, and compensating length can be calculated
Comp=3, i.e. vector col extend downwards 3 units, obtain 24 bit vectors in Fig. 2 b, are then filled into element 0,1,2 and prolong
In vector after length, and non-zero element discontinuously occurs, between non-zero element between be divided into 4 units, i.e. between two elements between
Every 30, as shown in Figure 2 c, 0 element color is most shallow in figure, and 1 element takes second place, and 2 element colors are most deep.
Using all elements of the vectorial col of populated element as the first column vector, the second column element is by the first column element
Displacement obtains, and all elements of vectorial col is moved down two units in vertical direction, the element of lowermost end is moved to most
Top, you can obtain the second column element, as shown in Fig. 3 d and Fig. 3 e, Fig. 3 d are the first column element, and Fig. 3 e move for the first column element
The second column element obtained behind position；Third column element can be obtained after carrying out same shifting function by the second column element again, repeat
21 column elements can be obtained after shifting function, and finally the element in the compensating length of 21 column element bottom ends is removed, that is, removes institute
Complete matrix can be obtained after 3 elements of directed quantity bottom, as shown in Figure 4.
Then the size of translocation distance d can be changed, and obtains multiple and different matrixes, calculates separately the total of different matrixes
Inductance and return path quality, the calculation formula of wherein total inductance are：
A in formulaijFor mutual inductance, it is 1 when i-th of pin is identical as j-th of pin current direction, is -1 when different, works as i=
When j, aij=0；Mutual inductance value between a pair of pins, wherein dijFor the Euclidean between i-th of pin and j-th of pin
Distance；To ensure the Xiang Weizheng, dmaxMinimum value should be the maximum Euclidean distance between all pins pair.
The calculation formula of return path quality is：
Dsum=D (dmin)-E(dmin)
D in formulaminFor each power supply or ground pin to the collection of the Euclidean distance of its another nearest power supply or ground pin
It closes, D (dmin) be the set variance, E (dmin) be the set mean value.Pass through the meter of above-mentioned total inductance and return path quality
The data under different translocation distances can be calculated by calculating formula, by the data of total inductance and return path quality with line chart
Form embodies, and as shown in Fig. 5 the datagram of the total inductance under difference translocation distance, Fig. 6 are under different translocation distances
Return path quality datagram.
Multi-group data when return path quality is minimum and total inductance is also relatively small can be found from Fig. 5 and Fig. 6,
Corresponding matrix when being translocation distance d=2,6,10,14 respectively, when translocation distance d takes any one in 2,6,10,14
When, obtained total inductance is identical with the numerical value of return path quality, therefore can choose translocation distance minimum, i.e. when d=2 is corresponding
Matrix, the arrangement of elements of the internal matrix is optimal pin distribution.
If vi and hi have multigroup product, for example, vi=2, hi=2, and vi*hi=4, then with vi=2, hi=2, this group multiplies
Product carries out subsequent all steps, when by the total inductance of obtained all matrixes and return path quality with vi=4, hi=1
The total inductance and return path quality of obtained all matrixes are compared, and it is minimum and total therefrom to search out return path quality
The inductance also matrix corresponding to relatively small value, the corresponding pin distribution of the matrix are optimal pin distribution
The method of the present invention need not carry out time-consuming iterative search, highly shortened and solve the time, can construct
Optimal solution or approximate optimal solution, and the optimal solution constructed under identical parameter is more stable, optimal pin distribution,
The mutual inductance that direction can be made opposite is cancelled out each other, and the influence to signal integrity is greatly reduced.
The above, only presently preferred embodiments of the present invention, the invention is not limited in the above embodiments, as long as
It reaches the technique effect of the present invention with identical means, should all belong to the scope of protection of the present invention.
Claims (9)
1. a kind of optimal pin of extensive BGA package based on priori is distributed generation method, it is characterised in that：Including following
Step：
A, determine that the ratio of the sum of ic power pin and ground pin and the upper total pin number of encapsulation, scale parameter are set as
1：R, while perpendicular separation parameter vi and horizontal interval parameter hi are set, and vi*hi=R；
B, the identical matrix of a dimensional values is arranged according to the package dimension M*N of integrated circuit；
C, the vectorial col that a length is M is generated, it, will be vectorial after the compensating length comp for calculating outgoing vector col according to M and vi
Col extends comp unit；
D, by signal pins, power pins, pin respectively with 0,1,2 element representations, filling 0 in the vectorial col after extending,
1,2 element wherein non-zero element discontinuously occurs, and is separated between non-zero element by vi-1 0；
E, the element in vectorial col will be filled in as the first row of matrix, next column is by the element of previous column in vertical direction
Upper displacement obtains, will comp unit of all row lowermost ends element remove after obtain complete matrix, wherein next column with
The distance of the unit of previous column horizontal interval hi, displacement is d；
F, change translocation distance d, obtain multiple and different matrixes, calculate separately each matrix total inductance and return path quality,
Optimal matrix is obtained according to the data of the total inductance of all matrixes and return path quality, corresponding element is in the matrix
Optimal pin distribution.
2. the optimal pin of a kind of extensive BGA package based on priori according to claim 1 is distributed generation method,
It is characterized in that：Perpendicular separation parameter vi and horizontal interval parameter hi is arranged simultaneously in the step A, wherein perpendicular separation parameter
Vi is the spacing distance between each two element in same row, and horizontal interval parameter hi is between each two element in a line
Spacing distance.
3. the optimal pin of a kind of extensive BGA package based on priori according to claim 1 is distributed generation method,
It is characterized in that：Vi*hi=R in the step A, if vi and hi have multigroup product, every group of product to carry out respectively subsequent all
Step compares the total inductance of all matrixes of every group of obtained product and return path quality, obtains optimal draw
Foot is distributed.
4. the optimal pin of a kind of extensive BGA package based on priori according to claim 1 is distributed generation method,
It is characterized in that：According to M and vi in the step C, after the compensating length comp for calculating outgoing vector col, vectorial col is extended
The calculation formula of comp unit, wherein compensating length comp is：
Comp=2*vi-mod (M, 2*vi)
Mod is to take the remainder operation.
5. the optimal pin of a kind of extensive BGA package based on priori according to claim 1 is distributed generation method,
It is characterized in that：The element in vectorial col will be filled in the step E as the first row of matrix, next column is by previous column
Element shift obtain in vertical direction, in displacement, element is moved down as unit of translocation distance d, each row most
The element of lower section is moved to the top of the row.
6. the optimal pin of a kind of extensive BGA package based on priori according to claim 1 is distributed generation method,
It is characterized in that：Each matrix total inductance and return path quality are calculated separately in the step F, the wherein calculating of total inductance is public
Formula is：
Wherein aijFor mutual inductance, it is 1 when i-th of pin is identical as j-th of pin current direction, is -1 when different, as i=j,
aij=0；Mutual inductance value between a pair of pins, wherein dijFor the Euclidean distance between i-th of pin and j-th of pin；
dmaxMaximum Euclidean distance of the minimum value between all pins pair.
7. the optimal pin of a kind of extensive BGA package based on priori according to claim 1 is distributed generation method,
It is characterized in that：Calculate separately each matrix total inductance and return path quality in the step F, wherein return path quality
Calculation formula is：
Dsum=D (dmin)-E(dmin)
Wherein dminFor each power supply or ground pin to the set of the Euclidean distance of its another nearest power supply or ground pin, D
(dmin) be the set variance, E (dmin) be the set mean value.
8. the optimal pin of a kind of extensive BGA package based on priori according to claim 1 is distributed generation method,
It is characterized in that：In the step F optimal square is obtained according to the data of the total inductance of all matrixes and return path quality
Gust, corresponding element is that optimal pin is distributed in the matrix, is obtained from the data of multigroup total inductance and return path quality
To the value and its corresponding total inductance of return path quality minimum, the pin of matrix corresponding to this group of data is distributed as optimal draw
Foot is distributed, and corresponding translocation distance is optimal shift distance.
9. the optimal pin of a kind of extensive BGA package based on priori according to claim 8 is distributed generation method,
It is characterized in that：If the data of return path quality minimum and its corresponding total inductance have multigroup same case, chooses and move
Distance minimum matrix in position is Optimal matrix, and the corresponding pin of the matrix is distributed as optimal pin distribution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810065483.1A CN108363839B (en) | 2018-01-23 | 2018-01-23 | Priori knowledge based optimal pin distribution generation method for large-scale BGA package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810065483.1A CN108363839B (en) | 2018-01-23 | 2018-01-23 | Priori knowledge based optimal pin distribution generation method for large-scale BGA package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108363839A true CN108363839A (en) | 2018-08-03 |
| CN108363839B CN108363839B (en) | 2022-03-08 |
Family
ID=63006958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810065483.1A Active CN108363839B (en) | 2018-01-23 | 2018-01-23 | Priori knowledge based optimal pin distribution generation method for large-scale BGA package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108363839B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109600911A (en) * | 2018-12-05 | 2019-04-09 | 郑州云海信息技术有限公司 | A kind of arrangement method and relevant apparatus of PCB connector signal pin |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003001415A1 (en) * | 2001-06-22 | 2003-01-03 | Cadence Design Systems, Inc. | Topological global routing for automated ic package interconnect |
| US8302067B2 (en) * | 2009-10-19 | 2012-10-30 | National Chiao Tung University | Pin-out designation method for package-board codesign |
| CN103560097A (en) * | 2013-11-20 | 2014-02-05 | 中国科学院深圳先进技术研究院 | Wiring path optimization method for three-dimensional chip |
| CN104904122A (en) * | 2013-12-31 | 2015-09-09 | 华为技术有限公司 | Compressed sensing-based signal reconstruction method and device |
| CN105574237A (en) * | 2015-12-10 | 2016-05-11 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Particle swarm based system-in-package BGA power ground pin distribution optimization method |
| CN105608257A (en) * | 2015-12-15 | 2016-05-25 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Method for generating large-scale optimal pinouts in BGA package based on genetic algorithm |
| CN107203489A (en) * | 2017-03-27 | 2017-09-26 | 中国科学院信息工程研究所 | A kind of feature selection approach based on optimal reconstruct |
-
2018
- 2018-01-23 CN CN201810065483.1A patent/CN108363839B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003001415A1 (en) * | 2001-06-22 | 2003-01-03 | Cadence Design Systems, Inc. | Topological global routing for automated ic package interconnect |
| US8302067B2 (en) * | 2009-10-19 | 2012-10-30 | National Chiao Tung University | Pin-out designation method for package-board codesign |
| CN103560097A (en) * | 2013-11-20 | 2014-02-05 | 中国科学院深圳先进技术研究院 | Wiring path optimization method for three-dimensional chip |
| CN104904122A (en) * | 2013-12-31 | 2015-09-09 | 华为技术有限公司 | Compressed sensing-based signal reconstruction method and device |
| CN105574237A (en) * | 2015-12-10 | 2016-05-11 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Particle swarm based system-in-package BGA power ground pin distribution optimization method |
| CN105608257A (en) * | 2015-12-15 | 2016-05-25 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Method for generating large-scale optimal pinouts in BGA package based on genetic algorithm |
| CN107203489A (en) * | 2017-03-27 | 2017-09-26 | 中国科学院信息工程研究所 | A kind of feature selection approach based on optimal reconstruct |
Non-Patent Citations (1)
| Title |
|---|
| 杨兵 等: "BGA封装技术", 《电子与封装》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109600911A (en) * | 2018-12-05 | 2019-04-09 | 郑州云海信息技术有限公司 | A kind of arrangement method and relevant apparatus of PCB connector signal pin |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108363839B (en) | 2022-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Pak et al. | Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation | |
| CN103717007B (en) | Multiple-suction-nozzle chip mounter mounting process optimization method based on clustering analysis and genetic algorithm | |
| CN102883548B (en) | Component mounting and dispatching optimization method for chip mounter on basis of quantum neural network | |
| CN100505987C (en) | Method for improving the line precision in the etching technology | |
| CN201867789U (en) | Self-adaptive graphical user interface building device | |
| CN108363839A (en) | The optimal pin of extensive BGA package based on priori is distributed generation method | |
| CN107742885A (en) | Distribution network voltage power sensitivity method of estimation based on canonical match tracing | |
| CN105516540B (en) | The compression method and device of bianry image | |
| EP2534675A2 (en) | Interconnect pattern for high performance interfaces | |
| US7454723B2 (en) | Validation of electrical performance of an electronic package prior to fabrication | |
| CN108701684A (en) | The ground plane for being guided through the horizontal data signal transmission line of packaging is isolated vertically, ground path is coaxially isolated and impedance-tumed | |
| CN104064657B (en) | Method and system for manufacturing LED display module based on COB packaging technology | |
| CN105187051A (en) | Power and area optimization method of incomplete certain Reed-Muller circuit based on NSGA-II | |
| CN110083969A (en) | Digital integrated electronic circuit layout method and terminal device based on discrete optimization | |
| US8863062B2 (en) | Methods and apparatus for floorplanning and routing co-design | |
| CN103369415B (en) | Based on the full network on mating plate of micro-ring resonator | |
| CN103886148B (en) | Automatic layout method and system for positions of heat through holes in 3D integrated circuit | |
| CN106055744B (en) | A kind of voltage drop analysis method of the three dimensional integrated circuits of the cell level based on lattice point | |
| Li et al. | Pin assignment optimization for large-scale high-pin-count BGA packages using genetic algorithm | |
| CN104809284B (en) | Method for planning interconnected micro-bump matrix among stacked three-dimensional integrated chip chips | |
| CN108510441B (en) | Image multi-resolution display method based on staggered grids | |
| Yeh et al. | Circuit clustering using a stochastic flow injection method | |
| Ozdal et al. | Algorithms for simultaneous escape routing and layer assignment of dense PCBs | |
| CN204465503U (en) | General digital logical integrated circuit replacement module | |
| CN101826123B (en) | Method for promoting chip finished product rate through increasing standard cell through hole |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |