CN108363839B - Priori knowledge based optimal pin distribution generation method for large-scale BGA package - Google Patents
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Abstract
The invention discloses a large-scale BGA package optimal pin distribution generation method based on prior knowledge, which is characterized in that a matrix replaces a package circuit to design pin distribution, wherein elements in the matrix comprise signal pins, power supply pins and ground pins, the three types of pins are replaced by 0, 1 and 2 and filled in a first column vector of the matrix, the elements in the first column vector are used as the beginning, the displacement is sequentially carried out to obtain a next column of elements, finally, a complete matrix is obtained, then, the displacement distance is changed to obtain a plurality of different matrices, the optimal matrix can be obtained according to the total inductance and the return path quality of each matrix, the pin distribution corresponding to the matrix is the optimal pin distribution, the method of the invention does not need to carry out time-consuming iterative search, greatly shortens the solving time, and the optimal solution constructed under the same parameters is relatively stable, the signal integrity of the packaged circuit is also strong.
Description
Technical Field
The invention relates to the field of large-scale integrated circuit packaging, in particular to a priori knowledge-based method for generating optimal pin distribution of large-scale BGA packaging.
Background
With the development of semiconductor technology and information technology, the functions of a single integrated circuit become more and more complex, so that the number of input/output pins on an integrated circuit package increases sharply, the power consumption problem and the electromagnetic compatibility problem become more and more prominent, and higher requirements are put forward on the package technology.
Although BGA packages can provide good connection performance, the number of pins is increased sharply, so that the signal integrity under BGA packages is gradually degraded, and mutual inductances in opposite directions can be cancelled by reasonable pin distribution, thereby greatly reducing the influence on the signal integrity, so that it is very important how to find an optimal pin distribution in chip design.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a method for generating an optimal pin distribution of a large-scale BGA package based on a priori knowledge, which can construct an optimal solution or an approximately optimal solution, and does not need to perform time-consuming iterative search, thereby greatly shortening the solution time, and the optimal solution constructed under the same parameters is relatively stable.
The technical scheme adopted by the invention for solving the problems is as follows:
a large-scale BGA package optimal pin distribution generation method based on prior knowledge comprises the following steps:
A. determining the proportion of the sum of the power supply pins and the ground pins of the integrated circuit to the total number of pins on the package, and setting the proportion parameters as 1: r, setting a vertical interval parameter vi and a horizontal interval parameter hi simultaneously, and setting vi & lthi & gt R;
B. setting a matrix with the same size and numerical value according to the packaging size M x N of the integrated circuit;
C. generating a vector col with the length of M, calculating the compensation length comp of the vector col according to M and vi, and then prolonging the vector col by comp units;
D. respectively representing a signal pin, a power supply pin and a ground pin by 0, 1 and 2 elements, and filling 0, 1 and 2 elements into an extended vector col, wherein non-0 elements are not continuously appeared, and the non-0 elements are separated by vi-1 0 elements;
E. taking the elements filled in the vector col as a first column of the matrix, wherein the next column is obtained by shifting the elements of the previous column in the vertical direction, and removing the comp units of the bottommost elements of all the columns to obtain a complete matrix, wherein the next column is horizontally separated from the previous column by hi units, and the shifting distance is d;
F. and changing the shift distance d to obtain a plurality of different matrixes, respectively calculating the total inductance and the return path quality of each matrix, and obtaining an optimal matrix according to the data of the total inductance and the return path quality of all the matrixes, wherein corresponding elements in the matrix are optimal pin distribution.
Further, the step a simultaneously sets a vertical interval parameter vi and a horizontal interval parameter hi, where the vertical interval parameter vi is an interval distance between every two elements in the same column, and the horizontal interval parameter hi is an interval distance between every two elements in the same row.
Further, in the step a, vi × hi ═ R, if there are multiple groups of products of vi and hi, each group of products respectively performs all subsequent steps, and compares the total inductance of all matrices of each group of products obtained with the quality of the return path to obtain the optimal pin distribution. Through the setting of different vi and hi, a plurality of groups of matrixes can be obtained through calculation, so that the optimal pin distribution can be found in the matrixes with different products.
Further, in the step C, after calculating the compensation length comp of the vector col according to M and vi, extending the vector col by comp units, wherein the calculation formula of the compensation length comp is as follows:
comp＝2*vi-mod(M,2*vi)
mod is the remainder taking operation. The compensation length may serve to maintain the vector shift distribution constant.
Further, in step E, the elements filled in the vector col are used as the first column of the matrix, and the next column is obtained by shifting the elements of the previous column in the vertical direction, and when the elements are shifted, the elements are shifted downward by the shift distance d, and the lowermost element in each column is shifted to the uppermost element in the column.
Further, in the step F, the total inductance and the quality of the return path of each matrix are calculated respectively, wherein a calculation formula of the total inductance is as follows:
wherein a isijFor mutual inductance, the current direction of the ith pin is 1 when the current direction of the ith pin is the same as that of the jth pin, the current direction of the ith pin is not-1 when the current direction of the jth pin is not the same as that of the jth pin, and a is equal to j when i is equal to jij＝0；
Is the mutual inductance between a pair of pins, where dijThe Euclidean distance between the ith pin and the jth pin is set; dmaxIs the maximum euclidean distance between all pin pairs.
Further, in the step F, the total inductance and the return path quality of each matrix are calculated respectively, wherein the calculation formula of the return path quality is as follows:
Dsum＝D(dmin)-E(dmin)
wherein d isminSet of Euclidean distances for each power or ground pin to its nearest other power or ground pin, D (D)min) Is the variance of the set, E (d)min) Is the mean of the set.
Further, in the step F, an optimal matrix is obtained according to the total inductance of all the matrices and the data of the quality of the return path, the corresponding elements in the matrix are the optimal pin distribution, the value with the minimum quality of the return path and the corresponding total inductance are obtained from the sets of the total inductance and the data of the quality of the return path, the pin distribution of the matrix corresponding to the set of data is the optimal pin distribution, and the corresponding shift distance is the optimal shift distance. When the quality of the return path is minimum and the total inductance also has a value close to the minimum, the mutual inductance between the pins of the packaging circuit is small, and the influence on the integrity of the signal is small.
Further, if the quality of the return path is minimum and the data of the total inductance corresponding to the return path has multiple groups of same conditions, selecting the matrix with the minimum shift distance as an optimal matrix, and distributing the pins corresponding to the matrix as optimal pin distribution.
The invention has the beneficial effects that: the invention adopts a large-scale BGA package optimal pin distribution generation method based on prior knowledge, a matrix replaces a package circuit to design pin distribution, wherein elements in the matrix comprise signal pins, power supply pins and ground pins, the three types of pins are replaced by 0, 1 and 2 and filled in a first column vector of the matrix, the first column vector is used as a start, the displacement is sequentially carried out to obtain a next column vector, finally, a complete matrix is obtained, then, the displacement distance is changed to obtain a plurality of different matrices, the optimal matrix can be obtained according to the total inductance and the return path quality of each matrix, the pin distribution corresponding to the matrix is the optimal pin distribution, the method of the invention does not need to carry out time-consuming iterative search, greatly shortens the solving time, and the optimal solution constructed under the same parameters is relatively stable, the signal integrity of the packaged circuit is also strong.
Drawings
The invention is further illustrated with reference to the following figures and examples.
FIG. 1 is a block flow diagram of a method for generating an optimal pin distribution for a large-scale BGA package based on prior knowledge according to the present invention;
FIG. 2 is a schematic diagram of the composition of a vector col;
FIG. 3 is a schematic diagram of the shifting process of the vector col;
FIG. 4 is a schematic representation of the matrix B after it has been constructed;
FIG. 5 is a graph of the total inductance obtained with different amounts of displacement d input;
fig. 6 is a graph of the resulting return path quality with different amounts of shift d input.
Detailed Description
Referring to fig. 1, the method for generating the optimal pin distribution of the large-scale BGA package based on the priori knowledge of the present invention includes the following steps: firstly, determining the proportion of the sum of power pins and ground pins of the integrated circuit to the total number of pins on the package, and setting the proportion parameters as 1: r, setting a vertical spacing parameter vi and a horizontal spacing parameter hi simultaneously, setting vi & lthi & gt to R, setting a matrix with the same dimension value according to the packaging dimension M & ltN & gt of the integrated circuit, generating a vector col with the length of M, calculating the compensation length comp of the vector col according to M and vi, extending the vector col by comp units, respectively representing a signal pin, a power supply pin and a ground pin by 0, 1 and 2 elements, then filling 0, 1 and 2 elements into the extended vector col, wherein the elements other than 0 are not continuously appeared, and the elements other than 0 are separated by vi-1 0 elements, taking the elements filled in the vector col as a first column of the matrix, and then taking the next column as a column after the next column is obtained by shifting the elements of the previous column in the vertical direction, wherein the shifting distance is d, and after all columns are obtained, removing the elements of the comp units at the bottommost of all columns to obtain a complete matrix, and finally, changing the shift distance d to obtain a plurality of different matrixes, respectively calculating the total inductance and the return path quality of each matrix, and obtaining an optimal matrix according to the data of the total inductance and the return path quality of all the matrixes, wherein the corresponding elements in the matrix are optimal pin distribution.
Specifically, the vertical interval parameter vi is set in units of a distance between two elements in the vertical direction, and the horizontal interval parameter hi is set in units of a distance between two elements in the horizontal direction.
Specific steps of the present invention are described below with specific parameters, wherein the package size of the integrated circuit is 21 × 21, so the matrix is set as a positive matrix of 21 rows and 21 columns, and the ratio of the sum of the power supply pins and the ground pins to the total pins is determined to be 1: 4, so vi ═ 4, hi ═ 1, and vi ═ hi ═ 4 can be set, setting the displacement distance d of the vector to 2.
First, a vector col with a length of 21 is generated, as shown in fig. 2a, and then a compensation length comp of the vector col can be calculated according to a formula, where the formula is:
comp＝2*vi-mod(M,2*vi)
substituting vi to 4, M to 21 into the above equation, where mod is the operation of taking the remainder, the compensation length comp to 3 can be calculated, that is, the vector col is extended downward by 3 units to obtain the 24-bit vector in fig. 2b, then the elements 0, 1, and 2 are filled into the extended vector, and the non-0 elements do not appear continuously, and the interval between the non-0 elements is 4 units, that is, the interval between two elements is 3 0, as shown in fig. 2c, where 0 element is lightest in color, 1 element is second, and 2 elements are darkest in color.
Taking all elements of the vector col filled with the elements as a first column vector, shifting a second column element by the first column element, moving all elements of the vector col downward by two units in the vertical direction, and moving the bottommost element to the top to obtain the second column element, as shown in fig. 3d and 3e, where fig. 3d is the first column element, and fig. 3e is the second column element obtained after shifting the first column element; and then, the second column elements are subjected to the same shift operation to obtain a third column elements, the shift operation is repeated to obtain 21 columns of elements, and finally, the elements in the compensation length at the bottom ends of the 21 columns of elements are removed, that is, 3 elements at the bottoms of all vectors are removed to obtain a complete matrix, as shown in fig. 4.
Then, the size of the shift distance d can be changed, a plurality of different matrixes are obtained, and the total inductance and the quality of the return path of the different matrixes are respectively calculated, wherein the calculation formula of the total inductance is as follows:
in the formula aijFor mutual inductance, the current direction of the ith pin is 1 when the current direction of the ith pin is the same as that of the jth pin, the current direction of the ith pin is not-1 when the current direction of the jth pin is not the same as that of the jth pin, and a is equal to j when i is equal to jij＝0；
Is the mutual inductance between a pair of pins, where dijThe Euclidean distance between the ith pin and the jth pin is set; to ensure that the term is positive, dmaxThe minimum value of (c) should be the maximum euclidean distance between all pin pairs.
The calculation formula of the return path quality is as follows:
Dsum＝D(dmin)-E(dmin)
in the formula dminSet of Euclidean distances for each power or ground pin to its nearest other power or ground pin, D (D)min) Is the variance of the set, E (d)min) Is the mean of the set. Data under different shift distances can be calculated through the calculation formula of the total inductance and the return path quality, and the data of the total inductance and the return path quality are represented in a form of a line graph, for example, fig. 5 is a data graph of the total inductance under different shift distances, and fig. 6 is a data graph of the return path quality under different shift distances.
From fig. 5 and 6, it is possible to find out a plurality of sets of data in which the quality of the return path is the minimum and the total inductance is relatively small, each set is a matrix corresponding to a shift distance d of 2, 6, 10, or 14, and when the shift distance d is any one of 2, 6, 10, or 14, the obtained total inductance and the return path quality are the same, so that the matrix corresponding to a shift distance d of the minimum, that is, d of 2, may be selected, and the arrangement of elements in the matrix is the optimal pin distribution.
If vi and hi have multiple groups of products, for example, vi is 2, hi is 2, and vi is 4, then the subsequent steps are performed by using the product of vi is 2 and hi is 2, the obtained total inductance and return path quality of all the matrices are compared with those obtained when vi is 4 and hi is 1, and a matrix corresponding to the value with the minimum return path quality and relatively small total inductance is found, and the pin distribution corresponding to the matrix is the optimal pin distribution
According to the method, time-consuming iterative search is not needed, the solving time is greatly shortened, the optimal solution or the approximate optimal solution can be constructed, the constructed optimal solution is stable under the same parameters, the optimal pin distribution can enable mutual inductance in opposite directions to mutually offset, and the influence on the signal integrity is greatly reduced.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and the present invention shall fall within the protection scope of the present invention as long as the technical effects of the present invention are achieved by the same means.
Claims (9)
1. A large-scale BGA package optimal pin distribution generation method based on prior knowledge is characterized in that: the method comprises the following steps:
A. determining the proportion of the sum of power pins and ground pins of the integrated circuit to the total number of pins on the package, setting the proportion parameter to be 1: R, and simultaneously setting a vertical interval parameter vi and a horizontal interval parameter hi, wherein vi is equal to R;
B. setting a matrix with the same size and numerical value according to the packaging size M x N of the integrated circuit;
C. generating a vector col with the length of M, calculating the compensation length comp of the vector col according to M and vi, and then prolonging the vector col by comp units;
D. respectively representing a signal pin, a power supply pin and a ground pin by 0, 1 and 2 elements, and filling 0, 1 and 2 elements into an extended vector col, wherein non-0 elements are not continuously appeared, and the non-0 elements are separated by vi-1 0 elements;
E. taking all elements filled in the vector col as a first column of the matrix, wherein the next column is obtained by shifting the elements of the previous column in the vertical direction, and removing the comp units of the bottommost elements of all columns to obtain a complete matrix, wherein the next column is horizontally separated from the previous column by hi units, and the shifting distance is d;
F. and changing the shift distance d to obtain a plurality of different matrixes, respectively calculating the total inductance and the return path quality of each matrix, and obtaining an optimal matrix according to the data of the total inductance and the return path quality of all the matrixes, wherein corresponding elements in the matrix are optimal pin distribution.
2. The method of claim 1, wherein the method for generating the optimal pin distribution of the large-scale BGA package based on the priori knowledge comprises: and step A, simultaneously setting a vertical interval parameter vi and a horizontal interval parameter hi, wherein the vertical interval parameter vi is the interval distance between every two elements in the same column, and the horizontal interval parameter hi is the interval distance between every two elements in the same row.
3. The method of claim 1, wherein the method for generating the optimal pin distribution of the large-scale BGA package based on the priori knowledge comprises: and in the step A, if the vi and the hi have multiple groups of products, each group of products respectively carries out all the subsequent steps, and the total inductance of all matrixes of each group of products and the quality of a return path are compared to obtain the optimal pin distribution.
4. The method of claim 1, wherein the method for generating the optimal pin distribution of the large-scale BGA package based on the priori knowledge comprises: in the step C, after the compensation length comp of the vector col is calculated according to M and vi, the vector col is extended by comp units, wherein the calculation formula of the compensation length comp is as follows:
comp＝2*vi-mod(M,2*vi)
mod is the remainder taking operation.
5. The method of claim 1, wherein the method for generating the optimal pin distribution of the large-scale BGA package based on the priori knowledge comprises: in step E, the elements filled in the vector col are used as the first column of the matrix, and the next column is obtained by shifting the elements in the previous column in the vertical direction.
6. The method of claim 1, wherein the method for generating the optimal pin distribution of the large-scale BGA package based on the priori knowledge comprises: and step F, respectively calculating the total inductance and the return path quality of each matrix, wherein the calculation formula of the total inductance is as follows:
wherein a isijFor mutual inductance, the current direction of the ith pin is 1 when the current direction of the ith pin is the same as that of the jth pin, the current direction of the ith pin is not-1 when the current direction of the jth pin is not the same as that of the jth pin, and a is equal to j when i is equal to jij＝0；
Is the mutual inductance between a pair of pins, where dijThe Euclidean distance between the ith pin and the jth pin is set; dmaxIs the maximum euclidean distance between all pin pairs.
7. The method of claim 1, wherein the method for generating the optimal pin distribution of the large-scale BGA package based on the priori knowledge comprises: and step F, respectively calculating the total inductance and the return path quality of each matrix, wherein the calculation formula of the return path quality is as follows:
Dsum＝D(dmin)-E(dmin)
wherein d isminSet of Euclidean distances for each power or ground pin to its nearest other power or ground pin, D (D)min) Is the variance of the set, E (d)min) Is the mean of the set.
8. The method of claim 1, wherein the method for generating the optimal pin distribution of the large-scale BGA package based on the priori knowledge comprises: and F, obtaining an optimal matrix according to the total inductance of all the matrixes and the data of the quality of the return path, wherein the corresponding elements in the matrix are optimal pin distribution, obtaining the value with the minimum quality of the return path and the corresponding total inductance from the data of the quality of the return path and the data of the total inductance, the pin distribution of the matrix corresponding to the group of data is optimal pin distribution, and the corresponding shift distance is the optimal shift distance.
9. The method of claim 8, wherein the method for generating the optimal pin distribution of the large-scale BGA package based on the prior knowledge comprises: and if the quality of the return path is minimum and the data of the total inductance corresponding to the return path has multiple groups of same conditions, selecting the matrix with the minimum shift distance as an optimal matrix, and distributing the pins corresponding to the matrix as optimal pin distribution.
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