CN108346673B

CN108346673B - Backside-illuminated image sensor, manufacturing method thereof and electronic device

Info

Publication number: CN108346673B
Application number: CN201710059033.7A
Authority: CN
Inventors: 姚国峰; 陆珏; 张海芳; 刘煊杰
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-01-23
Filing date: 2017-01-23
Publication date: 2021-11-12
Anticipated expiration: 2037-01-23
Also published as: CN108346673A

Abstract

The invention relates to a back-illuminated image sensor, a method of manufacturing the same, and an electronic apparatus. The method comprises the following steps: providing a first wafer comprising a pixel area, wherein the first wafer comprises a first surface and a second surface which are oppositely arranged; providing a second wafer and bonding the second wafer to the first surface of the first wafer; forming a number of spaced deep trenches in the second surface opposite the pixel region; an antireflective layer is formed in the deep trench. According to the method, a deep groove is formed in the back surface of the first wafer, and an anti-reflection layer is formed in the deep groove, so that crosstalk and dark current can be reduced.

Description

Backside-illuminated image sensor, manufacturing method thereof and electronic device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a back-illuminated image sensor, a manufacturing method thereof and an electronic device.

Background

Generally, an image sensor is a back-illuminated image sensor that converts an optical image into an electrical signal. The image sensor includes a Charge Coupled Device (CCD) and a Complementary Metal Oxide Semiconductor (CMOS) image sensor.

Since a CMOS Image Sensor (CIS) has improved manufacturing technology and characteristics, various aspects of semiconductor manufacturing technology have focused on developing CMOS image sensors. CMOS image sensors are manufactured using CMOS technology, and have lower power consumption, are easier to realize high integration, and manufacture devices having smaller sizes, and thus, CMOS image sensors are widely used in various products such as digital cameras and digital camcorders.

Background of the inventionbackground illumination CMOS image sensors (BSI CIS) are widely used in multifunctional electronic devices, wherein a device wafer (device wafer) and a carrier wafer (carrier wafer) are bonded together by a Fusion bonding (Fusion bonding) method.

As the pixel size decreases, noise such as crosstalk increases. For better image quality, the crosstalk problem needs to be improved. There are three types of crosstalk in current devices: spectral crosstalk (spectral crosstalk), optical crosstalk (optical crosstalk), and electrical crosstalk (electrical crosstalk). Among them, spectral crosstalk (spectral crosstalk) is caused by misalignment of a Color Filter (CF). The optical crosstalk (optical crosstalk) is caused by photons penetrating to an adjacent photodiode. Electrical crosstalk (electrical crosstalk) is caused by electrons drifting to the wrong pixel area.

Spectral crosstalk (spectral crosstalk) and optical crosstalk (optical crosstalk) can be addressed by embedding color filters into a metal layer grid structure. A Deep Trench Isolation (DTI) structure may suppress optical crosstalk (optical crosstalk) and electrical crosstalk (electrical crosstalk), but isolation of a photodiode by a separate ion implantation is difficult as the thickness of a silicon substrate increases. Therefore, a Deep Trench Isolation (DTI) structure on the back side can effectively enhance pixel isolation.

For back side illuminated image sensors, it is acceptable that the back side structure has no Deep Trench Isolation (DTI) structure, but the back side illuminated image sensor is limited by Si/ARC/insulating layer/back side passivation layer structure in the pixel region and logic region.

Therefore, in order to solve the above technical problems in the prior art, it is necessary to provide a new backside illuminated image sensor, a method for manufacturing the same, and an electronic device.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In order to overcome the problems existing at present, an embodiment of the present invention provides a method for manufacturing a back-illuminated image sensor, the method including:

providing a first wafer comprising a pixel area, wherein the first wafer comprises a first surface and a second surface which are oppositely arranged;

providing a second wafer and bonding the second wafer to the first surface of the first wafer;

forming a number of spaced deep trenches in the second surface opposite the pixel region;

an antireflective layer is formed in the deep trench.

Optionally, the antireflective layer has a decreasing refractive index in a direction radially inward of the deep trench.

Optionally, the anti-reflective layer comprises one material having a different refractive index or a plurality of materials having different refractive indices.

Optionally, the first wafer includes a substrate, the deep trench is formed in the substrate, the deep trench has a depth at least greater than half of the thickness of the substrate, and the deep trench has an aspect ratio at least greater than 5.

Optionally, the antireflective layer is formed at a temperature of less than 400 ℃.

Optionally, the anti-reflection layer covers the second surface and fills the deep trench, the method further comprising, after forming the anti-reflection layer:

and forming a grid structure on the anti-reflection layer, wherein the grid structure comprises a main body layer and a plurality of grid openings arranged in the main body layer, and the grid openings expose the anti-reflection layer.

Optionally, wherein a color filter is embedded in the grid openings of the grid structure.

Optionally, the first wafer further includes a logic region located at one side of the pixel region, and a metal interconnection layer and a pad layer embedded in the dielectric layer are formed in the logic region.

Optionally, the first wafer includes a substrate, and the method further includes, after forming the anti-reflection layer on the substrate surface and in the deep trench and before forming the mesh structure:

patterning the substrate opposite the logic region and the anti-reflection layer on the substrate to form an opening and expose the dielectric layer;

forming an insulating layer on the anti-reflection layer and the surface of the opening;

patterning the insulating layer and the dielectric layer in the opening to form a groove and expose the metal interconnection layer;

and forming a metal layer on the insulating layer to cover the insulating layer, and filling the groove to form connection with the metal interconnection layer.

Optionally, the method of forming the opening includes:

forming a photoresist layer on the substrate and the anti-reflection layer on the second surface;

patterning the photoresist layer to remove the photoresist layer over the logic region;

baking the first wafer, the second wafer and the photoresist layer;

etching the substrate on the baked first wafer to form the opening.

Optionally, the baking temperature is 150 ℃ to 240 ℃ and the baking time is 60 seconds to 300 seconds.

Optionally, the side wall of the opening is inclined at an angle of less than 50 °, and the width of the opening is greater than 50 μm.

Optionally, after forming the metal layer, the method further includes:

forming a patterned mask layer on the metal layer;

and etching the metal layer by taking the mask layer as a mask so as to form the metal grid structure above the pixel area, and simultaneously removing the metal layer above the insulating layer outside the metal interconnection layer so as to expose the insulating layer.

Optionally, after exposing the insulating layer, the method further includes:

and patterning the insulating layer and the dielectric layer above the pad layer in the logic area to form a pad opening and expose the pad layer.

Optionally, the first wafer is a device wafer, and the second wafer is a support wafer.

The present invention also provides a back-illuminated image sensor, including:

the first wafer comprises a pixel area, and the first wafer comprises a first surface and a second surface which are oppositely arranged;

a second wafer bonded to the first surface of the first wafer;

a deep trench located on the second surface of the first wafer and above the pixel region;

and the anti-reflection layer is filled in the deep groove.

Optionally, a substrate is formed on the first wafer, the deep trench is formed in the substrate, the depth of the deep trench is at least greater than half of the thickness of the substrate, and the aspect ratio of the deep trench is at least greater than 5.

Optionally, the anti-reflection layer covers the second surface and fills the deep trench, the back-illuminated image sensor further comprising:

the grid structure is arranged above the anti-reflection layer and comprises a main body layer and a plurality of grid openings arranged in the main body layer, and the grid openings expose the anti-reflection layer.

Optionally, the back-illuminated image sensor further comprises:

a color filter embedded in the grid opening of the grid structure.

Optionally, the first wafer further includes a logic region located at one side of the pixel region, and a metal interconnect layer and a pad layer embedded in a dielectric layer are formed in the logic region.

Optionally, an opening penetrating through a thickness of the dielectric layer is formed in the logic region, an insulating layer and a metal layer located above the insulating layer are formed on a surface of the opening, and the metal layer is connected with the metal interconnection layer.

Optionally, a pad opening is formed in the dielectric layer in the logic region, the pad opening exposing the pad layer.

The invention also provides an electronic device which comprises the back-illuminated image sensor.

In summary, the present invention provides a method for manufacturing a back side illuminated image sensor, in which a deep trench is formed on the back side of the first wafer, and an anti-reflection layer is formed in the deep trench, so as to solve the problems in the prior art.

As a preferable mode, a mesh structure is further formed in the pixel region, which can enhance image performance by suppressing optical crosstalk (optical crosstalk), and in addition, the mesh structure can implement a camera function of Phase Detection Auto Focus (PDAF).

Further, embedding the color filter into the metal grid, the color filter vendor does not need very precise patterning, and can enhance quantum efficiency (quantum efficiency).

The back side illuminated image sensor of the invention has the advantages as well as the manufacturing method. The electronic device of the invention also has the advantages because the back-illuminated image sensor is adopted.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1 is a schematic flow chart of a method of manufacturing a back-illuminated image sensor according to an embodiment of the present invention;

FIGS. 2A-2F are cross-sectional views of structures formed by the steps associated with a method of fabricating a backside illuminated image sensor in another embodiment of the present invention, wherein the right side of FIG. 2E is a top view of the circled portion of the left side;

fig. 3 shows a schematic view of an electronic device according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Example one

Next, detailed steps of an exemplary method of a method of manufacturing a back-illuminated image sensor according to an embodiment of the present invention will be described with reference to fig. 1 and fig. 2A to 2F. Fig. 1 is a schematic flow chart of a method for manufacturing a back-illuminated image sensor according to an embodiment of the present invention, and fig. 2A to 2F are cross-sectional views of structures formed in the steps related to the method for manufacturing a back-illuminated image sensor according to an embodiment of the present invention.

As shown in fig. 1, the manufacturing method specifically includes the steps of:

step S1: providing a first wafer comprising a pixel area, wherein the first wafer comprises a first surface and a second surface which are oppositely arranged;

step S2: providing a second wafer and bonding the second wafer to the first surface of the first wafer;

step S3: forming a number of spaced deep trenches in the second surface opposite the pixel region;

step S4: an antireflective layer is formed in the deep trench.

The method for manufacturing the backside illuminated image sensor of the embodiment specifically includes the following steps:

firstly, a first step is executed, a first wafer is provided, the first wafer comprises a first surface and a second surface which are oppositely arranged, and the first surface at least comprises a pixel area.

Specifically, as shown in fig. 2A, at least a substrate 203 is formed on a first wafer, the substrate 203 is formed on a first surface of the first wafer, and the substrate 203 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.

The first surface of the first wafer comprises a pixel area and a logic area, wherein the pixel area is used for forming various elements of an image sensor and interconnection structures, and the logic area is used for forming various interconnection structures and packaging structures, for example, a metal interconnection layer 2022 and a pad layer 2021 embedded in a dielectric layer are formed in the logic area.

An interconnect structure 2023 is also formed in the pixel region, wherein the interconnect structure 2023 includes a metal layer (e.g., a copper layer or an aluminum layer), a metal plug, or a metal via, and wherein a bottom metal layer of the interconnect structure is located above the surface of the first wafer.

The formation method of the interconnect structure may be a conventional manufacturing method, such as forming a dielectric layer 202, then patterning the dielectric layer to form an opening and filling the opening with a conductive material, sequentially forming metal layers and a via hole to form the interconnect structure, and further depositing a dielectric layer after forming the top metal layer to cover the top metal layer and planarize, as shown in fig. 2A.

The top metal layer is made of a metal material Al, and the deposition method of the metal material Al may be one of low-pressure chemical vapor deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) formed by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD) method, and the like, and in the present invention, the Physical Vapor Deposition (PVD) method is preferred.

Optionally, other devices, such as passive devices and radio frequency devices, may also be formed in the first wafer.

Alternatively, the passive device may include a metal-insulator-metal capacitor (MIM), a spiral inductor, or the like. As an example, a radio frequency device is also formed on the first surface of the first wafer. In this embodiment, transistors are used to form various circuits, rf devices are used to form rf components or modules, and interconnect structures are used to connect the transistors, rf devices, and other components in the front-end device.

The specific structure and the forming method of each component formed in the first wafer may be selected by those skilled in the art according to actual needs by referring to the prior art, and are not described herein again.

Next, step two is performed, a second wafer 201 is provided and the second wafer is bonded to the first surface of the first wafer.

As shown in fig. 2A, a second wafer 201 is provided, and in this embodiment, the second wafer 201 is a carrier wafer (carrier wafer) for carrying and protecting front-end devices in a subsequent process of thinning the first wafer and other subsequent processes.

Alternatively, the second wafer 201 may be a common silicon substrate or other suitable substrate, which is not limited herein.

A trap layer (high trap layer) is formed on a bonding surface of the second wafer 201 and the first wafer to improve bonding performance between the second wafer 201 and the first wafer.

Optionally, the trapping layer comprises polysilicon or amorphous silicon.

One side of the second wafer is bonded to the side of the first wafer on which the front-end devices are formed (i.e., the first surface) by a bonding process, as shown in fig. 2A. The bonding process may be performed by any method known to those skilled in the art, such as an oxide fusion bonding process, and the like.

Optionally, in the method, a bonding material layer is formed on the first wafer, then a capture layer is formed on the second wafer, and the bonding material layer is bonded with the capture layer during bonding, so that the first wafer and the second wafer are bonded, and the capture layer and the bonding material layer have good bonding performance, so that the bonding performance of the first wafer and the second wafer is further improved, and the performance and yield of devices are improved.

Wherein the first surface of the first wafer is bonded to the second wafer in this step, and the wafer is inverted after bonding, resulting in the structure shown in fig. 2A, such that the second surface of the first wafer is facing upward.

Then, thinning processing is carried out on the first wafer from the side of a second surface, opposite to the first surface, of the first wafer.

Specifically, as shown in fig. 2A, the first wafer is thinned from a side of a second surface of the first wafer opposite to the first surface.

Illustratively, the thinning process may be CMP (chemical mechanical polishing) or other suitable method.

And step three is executed, and a plurality of spaced deep grooves are formed in the second surface opposite to the pixel region.

Specifically, as shown in fig. 2A, a hard mask layer is formed on the second surface of the first wafer, i.e., the back surface of the first wafer in this step.

The hard mask layer can be a nitride hard mask layer and/or an oxide hard mask layer.

Then, the hard mask layer is patterned, for example, a patterned photoresist layer is formed on the hard mask layer, and the hard mask layer is etched by using the photoresist layer as a mask, so that an opening is formed in the hard mask layer.

And finally, etching the back surface of the substrate in the first wafer by taking the hard mask layer as a mask, and forming the deep groove in the substrate.

Wherein the deep trench has a depth at least greater than half the thickness of the substrate, and the deep trench has an aspect ratio at least greater than 5.

In which the substrate is etched using a Bosch process of reactive ions to form the deep trench.

Alternatively, the etching process of the Bosch process is divided into two steps of etching and passivation, for example, a passivation film is firstly deposited on the side wall, and C is introduced₄F₈Gas, C₄F₈Decomposed into ionic CF in plasma state₂Radicals and reactive F radicals, in which CF is₂The radicals react with the Si surface to form (CF)₂) And n high-molecular passivation film.

Then etching is carried out, and gas SF is introduced₆To increase F ion dissociation, the passivation film is etched away, and then the Si substrate is etched. In the etching step, the part of the sidewall polymer attached on the previous attached layer moves away from the sidewall again under the influence of the non-vertical ion impact sidewall, and is attached on the deeper sidewall again. Thus, the polymer film on the sidewall is continuously driven down to form a locally anisotropic etch.

The Bosch technique is selected in this application to achieve the Si deep trench etch by alternating passivation/etch (TMDE).

Wherein, the sidewall profile of the deep trench can be vertical or inclined, and is not limited.

Optionally, in order to control the deep trench to have a large opening to obtain sufficient over-etching, the pulse function is turned off during this process, while the etching time is controlled to be slightly longer than the time of the passivation step.

Through the etching of the process steps, the deep groove with a narrow upper part and a wide lower part can be obtained, and an included angle formed between the side wall of the deep groove and the horizontal surface of the substrate is smaller than 85 degrees.

Because the deep groove is in a shape with a wide upper part and a narrow lower part and has enough over-etching amount, a larger opening is formed, so that the polymer can not be gathered at the bottom of the deep groove in the etching process, and simultaneously the anti-reflection layer can be better filled in the subsequent process.

Wherein the number of the deep trenches is several, and the deep trenches are disposed around each pixel in the pixel region, but not limited to the arrangement.

And step four is executed, and an antireflection layer is formed in the deep groove.

Specifically, after the deep trench is formed, the hard mask layer is removed first, and the hard mask layer may be removed by a method having a larger etching selection ratio with respect to the substrate, so as to expose the substrate.

A wet chemical treatment step is then performed after the formation of the removal of the hard mask layer to eliminate damage on the second surface.

Optionally, the wet chemical treatment step selects two or more of hydrofluoric acid, nitric acid, acetic acid and hydrogen peroxide.

The method further includes performing an oxidation step on the second surface and the surface of the deep trench after the wet chemical treatment step to form an oxide layer on the second surface and the surface of the deep trench to facilitate filling of the anti-reflection layer.

In this step, the oxide layer is formed through a wet process or a steam ambient process.

Wherein the thickness of the oxide layer is thin, only for changing the surface properties, e.g. around 5 angstroms.

An antireflective layer 205 is then filled in the deep trench and covers the substrate, as shown in FIG. 2B.

Wherein a refractive index of the anti-reflection layer decreases in a radially inward direction of the deep trench. Wherein the radial direction refers to a direction from outside to inside of the sidewall of the deep trench, as indicated by the arrow in FIG. 2A. For example, the refractive index of the anti-reflection layer decreases from the outside to the inside of the sidewall of the deep trench. For example, the antireflective layer has a graded decreasing index of refraction from the outside to the inside of the sidewalls of the deep trench.

Optionally, the anti-reflective layer comprises high refractive index zirconia, titania, tantalum oxide, silicon nitride, hafnium oxide, germanium oxide, alumina, silicon oxynitride, silicon rich oxides and doped silicon oxides, and low refractive index silicon oxide and air.

In which a step of planarizing the anti-reflection layer is further included after the anti-reflection layer is deposited.

And forming a deep groove on the back surface of the first wafer, and forming an antireflection layer in the deep groove, wherein crosstalk and dark current can be reduced through the arrangement.

Step five is executed, the substrate opposite to the logic area and the antireflection layer on the substrate are patterned to form an opening 20 and expose the dielectric layer 202.

Specifically, as shown in fig. 2C, the method of forming the opening 20 includes:

step 1: patterning the substrate 203 and the anti-reflective layer 205 on a second surface opposite the logic region to form an opening 20 and expose the dielectric layer 202;

step 2: and forming an insulating layer on the antireflection layer and the surface of the opening.

The method for forming the opening comprises the steps of forming photoresist, exposing, developing, etching and the like.

Optionally, the opening is a tapered opening with a narrow top and a wide bottom.

In order to form the tapered opening, the following steps are performed:

baking the first wafer, the second wafer and the photoresist layer;

etching the substrate on the baked first wafer to form the opening.

Wherein the baking temperature is 150 ℃ to 240 ℃, and the baking time is 60 seconds to 300 seconds.

The formation of the tapered opening is important for removing the metal remaining on the sidewall, which can ensure that no metal remains, and avoid causing short circuit of the circuit.

The insulating layer may be SiN, but is not limited to the material.

And step six is executed, a grid structure is formed on the anti-reflection layer, the grid structure comprises a main body layer and a plurality of grid openings arranged in the main body layer, and the grid openings expose the anti-reflection layer.

Specifically, as shown in fig. 2D, after the forming the anti-reflection layer and before the forming the mesh structure, the method further includes:

patterning the insulating layer and the dielectric layer in the opening to form a groove and expose the metal interconnection layer 2022;

and forming a metal layer 207 on the insulating layer to cover the insulating layer, and filling the groove to form connection with the metal interconnection layer.

Wherein, the metal layer 207 may be made of tungsten (W), nickel (Ni) or titanium (Ti); the conductive metal nitride layer may include a titanium nitride (TiN) layer; the conductive metal oxide layer may include iridium oxide (IrO)₂) A layer; the metal silicide layer may include a titanium silicide (TiSi) layer.

The metal layer 207 may be deposited by one of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG).

The metal layer 207 is then patterned to form a metal mesh structure 2071 on the pixel area, specifically:

forming a patterned mask layer on the metal layer;

and etching the metal layer by taking the mask layer as a mask to form a plurality of grid openings in the metal layer, further forming the metal grid structure above the pixel area, and simultaneously removing the metal layer above the insulating layer on the outer side of the metal interconnection layer to expose the insulating layer.

The metal mesh structure 2071 comprises a main body layer and a plurality of mesh openings arranged in the main body layer, as shown in fig. 2E, wherein the right side of fig. 2E is a top view of a circle portion of the left side of the figure.

The metal mesh structure formed in the pixel region may enhance image performance by suppressing optical crosstalk (optical crosstalk), and in addition, the metal mesh structure may implement a camera function of Phase Detection Auto Focus (PDAF).

The grid structure is not limited to a metal grid structure, and the solid material constituting the grid structure must be capable of absorbing light and having good electrical conductivity, and the energy band structure of the material is required to have a large number of freely movable electrons, so that the metal material is preferable, but may be a partially non-metal solid material (such as graphite) or the like.

In this step, the metal layer above the insulating layer outside the metal interconnection layer is removed while leaving a portion connected to the metal interconnection layer.

Finally, as shown in fig. 2F, after exposing the anti-reflective layer, the method further includes:

the anti-reflection layer and the dielectric layer over the pad layer in the logic region are patterned to form a pad opening 30 and expose the pad layer 2021.

Furthermore, a color filter is embedded in the metal mesh, for example, the color filter is embedded in the mesh opening of the mesh structure. The color filter vendor does not need very precise patterning in the metal grid, and can enhance quantum efficiency (quantum efficiency).

The method further includes the step of forming a backside passivation layer after forming the pad opening 30, the passivation layer being formed in an area outside the pad opening.

The passivation layer is one or more selected from a PESIN layer, a PETEOS layer, a SiN layer, and a TEOS layer, and the thickness thereof is not limited to a certain range.

Thus, the description of the key steps of the method of manufacturing the back-illuminated image sensor of the present embodiment is completed. Through the above steps, a double-sided thin SOI (silicon on insulator) structure is formed. The fabrication of the entire back-illuminated image sensor can then also be done according to various methods known in the art.

As a preferable mode, a metal mesh structure is further formed in the pixel region, which can enhance image performance by suppressing optical crosstalk (optical crosstalk), and in addition, the metal mesh structure can implement a camera function of Phase Detection Auto Focus (PDAF).

Example two

Embodiments of the present invention provide a backside illuminated image sensor, which is prepared by the manufacturing method in the first embodiment. The back-illuminated image sensor may be an integrated circuit or an integrated circuit intermediate product including a Radio Frequency (RF) device.

Next, a structure of a back-illuminated image sensor proposed by an embodiment of the present invention is described with reference to fig. 2F. Fig. 2F is a cross-sectional view of a structure of a back-illuminated image sensor according to an embodiment of the present invention.

As shown in fig. 2F, the back-illuminated image sensor of the present embodiment includes:

a second wafer 203 bonded to the first surface of the first wafer;

and the anti-reflection layer 205 is filled in the deep groove.

Specifically, at least a substrate 203 is formed on a first wafer, the substrate 203 is formed on a first surface of the first wafer, and the substrate 203 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.

Wherein an interconnect structure is also formed in the pixel region, the interconnect structure including a metal layer (e.g., a copper layer or an aluminum layer), a metal plug, or a metal via, wherein an underlying metal layer of the interconnect structure is located above the first wafer surface.

The second wafer 201 is a carrier wafer (carrier wafer) for carrying and protecting front-end devices in a subsequent process of thinning the first wafer and other subsequent processes.

The second wafer 201 may be a common silicon substrate or other suitable substrate, and is not limited herein.

Optionally, the trapping layer comprises polysilicon or amorphous silicon.

Deep trenches are formed in the substrate of the first wafer.

The deep groove is in a shape with a wide upper part and a narrow lower part, and has enough over-etching amount, so that a larger opening is formed, and therefore, polymers can not be gathered at the bottom of the deep groove in the etching process, and meanwhile, the anti-reflection layer can be better filled in the subsequent process.

An opening extending to the dielectric layer is formed in the logic area, an insulating layer and a metal layer located above the insulating layer are formed on the surface of the opening, and the metal layer is connected with the metal interconnection layer.

A grid structure is formed on the anti-reflection layer in an isolated manner, wherein a color filter is embedded in the grid structure. The grid structure comprises a main body layer and a plurality of grid openings arranged in the main body layer, and the grid openings expose the anti-reflection layer.

In the present invention, the lattice structure is a metal lattice structure 2071. Wherein, the constituent material of the metal grid structure can be tungsten (W), nickel (Ni) or titanium (Ti); the conductive metal nitride layer may include a titanium nitride (TiN) layer; the conductive metal oxide layer may include iridium oxide (IrO)₂) A layer; the metal silicide layer may include a titanium silicide (TiSi) layer.

The image sensor further includes a backside passivation layer formed in an area outside the pad opening.

The backside illuminated image sensor of the present embodiment may be other circuits or modules. The performance of the back-illuminated image sensor is improved, so that the requirements on the device performance under more application environments can be met.

EXAMPLE III

An embodiment of the invention provides an electronic device, which comprises an electronic component and a back-illuminated image sensor electrically connected with the electronic component. The back-illuminated image sensor comprises the back-illuminated image sensor manufactured according to the manufacturing method of the back-illuminated image sensor in the first embodiment, or comprises the back-illuminated image sensor in the second embodiment.

The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, or an intermediate product having the above-mentioned back-illuminated image sensor, for example: a mobile phone mainboard with the integrated circuit, and the like.

Wherein figure 3 shows an example of a mobile telephone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.

Wherein the mobile phone handset comprises the aforementioned backside illuminated image sensor, or the backside illuminated image sensor manufactured by the method for manufacturing a backside illuminated image sensor according to the first embodiment, the backside illuminated image sensor comprises: the first wafer comprises a pixel area, and the first wafer comprises a first surface and a second surface which are oppositely arranged; a second wafer bonded to the first surface of the first wafer; a deep trench located on the second surface of the first wafer and above the pixel region; and the anti-reflection layer is filled in the deep groove.

The electronic device of the invention also has the advantages because the back-illuminated image sensor is adopted.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of fabricating a back-illuminated image sensor, the method comprising:

forming an anti-reflection layer in the deep trench;

the method further includes, after forming the anti-reflective layer:

forming a grid structure on the anti-reflection layer, wherein the grid structure comprises a main body layer and a plurality of grid openings arranged in the main body layer, and the grid openings expose the anti-reflection layer;

embedding a color filter into the grid openings of the grid structure.

2. The method of claim 1, wherein the antireflective layer has a decreasing index of refraction in a direction radially inward of the deep trench.

3. The method of claim 2, wherein the anti-reflective layer comprises one material having a different refractive index or a plurality of materials having different refractive indices.

4. The method of claim 1, wherein the first wafer comprises a substrate, wherein the deep trench is formed in the substrate, wherein the deep trench has a depth at least greater than half of a thickness of the substrate, and wherein the deep trench has an aspect ratio at least greater than 5.

5. The method of claim 1, wherein the antireflective layer is formed at a temperature of less than 400 ℃.

6. The method of claim 1, wherein the first wafer further comprises a logic region on one side of the pixel region, and wherein a metal interconnect layer and a pad layer embedded in a dielectric layer are formed in the logic region.

7. The method of claim 6, wherein the first wafer comprises a substrate, the method further comprising, after forming the antireflective layer in the substrate surface and the deep trenches, and before forming the mesh structure:

8. The method of claim 7, wherein forming the opening comprises:

baking the first wafer, the second wafer and the photoresist layer;

etching the substrate on the baked first wafer to form the opening.

9. The method according to claim 8, wherein the baking temperature is 150 ℃ to 240 ℃ and the baking time is 60 seconds to 300 seconds.

10. The method of claim 7, wherein the side walls of the opening are inclined at an angle of less than 50 °, and the width of the opening is greater than 50 μm.

11. The method of claim 7, wherein after forming the metal layer, the method further comprises:

forming a patterned mask layer on the metal layer;

12. The method of claim 11, wherein after exposing the insulating layer, the method further comprises:

13. The method of claim 1, wherein the first wafer is a device wafer and the second wafer is a support wafer.

14. A back-illuminated image sensor, comprising:

a second wafer bonded to the first surface of the first wafer;

the anti-reflection layer is filled in the deep groove;

the grid structure is arranged above the anti-reflection layer and comprises a main body layer and a plurality of grid openings arranged in the main body layer, and the grid openings expose the anti-reflection layer;

a color filter embedded in the grid opening of the grid structure.

15. The back-illuminated image sensor of claim 14, wherein the anti-reflective layer has a refractive index that decreases in a direction radially inward of the deep trench.

16. The back-illuminated image sensor of claim 15, wherein the anti-reflection layer comprises one material or a plurality of materials having different refractive indices.

17. The back-illuminated image sensor of claim 14, wherein at least a substrate is formed on the first wafer, the deep trench is formed in the substrate, the deep trench has a depth at least greater than half the thickness of the substrate, and the deep trench has an aspect ratio at least greater than 5.

18. The back-illuminated image sensor of claim 14, wherein the first wafer further comprises at least a logic region on one side of the pixel region, wherein a metal interconnect layer and a pad layer embedded in a dielectric layer are formed in the logic region.

19. The back-illuminated image sensor of claim 18, wherein an opening is formed in the logic region through a thickness of the dielectric layer portion, an insulating layer and a metal layer over the insulating layer are formed on a surface of the opening, and the metal layer is connected to the metal interconnect.

20. The back-illuminated image sensor of claim 19, wherein the side walls of the opening are inclined at an angle of less than 50 °, and the width of the opening is greater than 50 μ ι η.

21. The back-illuminated image sensor of claim 19, wherein a pad opening is formed in the dielectric layer in the logic region, the pad opening exposing the pad layer.

22. An electronic device, characterized in that the electronic device comprises a back-illuminated image sensor as claimed in one of claims 14 to 21.