CN108346669B

CN108346669B - Switch array substrate and manufacturing method thereof

Info

Publication number: CN108346669B
Application number: CN201810100662.4A
Authority: CN
Inventors: 黄北洲
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2018-02-01
Filing date: 2018-02-01
Publication date: 2021-04-09
Anticipated expiration: 2038-02-01
Also published as: CN108346669A

Abstract

The application discloses a switch array substrate and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a patterned first conductive layer, wherein the patterned first conductive layer forms at least one gate line and at least one gate electrode, the gate line is electrically connected with the gate electrode and respectively comprises a first sub-layer and a second sub-layer positioned on the first sub-layer, the first sub-layer protrudes out of the second sub-layer in a direction parallel to the substrate, and the second sub-layer has an inclined side wall; patterning a semiconductor material layer to be disposed corresponding to the gate electrode; patterning a second conductive layer to form a source electrode and a drain electrode on the semiconductor material layer respectively, wherein the gate electrode enables the source electrode and the drain electrode to be overlapped in a self-alignment mode respectively; and forming a patterned transparent conductive layer on the gate dielectric layer corresponding to the gate line.

Description

Switch array substrate and manufacturing method thereof

Technical Field

The present disclosure relates to a switch array substrate, and more particularly, to a switch array substrate for self-aligned manufacturing of thin film transistors and a method for manufacturing the same.

Background

Thin liquid crystal transistors (TFTs) are used in liquid crystal displays and imagers to control or sense the state of each pixel of the display or image. In a thin film transistor display or sensor system, the operating characteristics of the system are optimized by having each pixel or cell have substantially the same operating characteristics. The operating characteristics of the thin film transistor may include, among others, switching speed, capacitive loading of the drive and sense lines, and gain of the transistor.

One of the problems in the prior art that leads to variations in the characteristics of different pixels or cells of the switch array substrate is the inability to precisely align the mask locations that define the source and drain electrodes of the thin film transistor, thereby ensuring accurate alignment of the source/drain electrodes with respect to the gate electrode. Misalignment of the source/drain electrodes with respect to the gate electrode will result in an increased overlap between the gate electrode and either the source or drain electrode, while the overlap between the gate electrode and the other is reduced. Since the parasitic capacitance between the gate electrode and the source or drain electrode is a direct function of the overlap between them, this change in the position of the overlap can cause a change in the capacitance of the device, thereby changing the switching speed and load of other circuits.

Additionally, if the source/drain electrodes are misaligned relative to the gate electrode, it may be necessary to increase the size of the gate electrode to ensure that all devices have an acceptable overlap position between the gate electrode and the source/drain electrodes, and increasing the size of the gate electrode increases the size of the device, thereby increasing the overall capacitance per device. The capacitance of the device is important because it controls the charging time of the gate electrode, the capacitive coupling between the gate electrode and the source/drain electrode nodes, and the noise introduced by defects at the amorphous silicon or amorphous silicon dielectric interface. Therefore, there is a need to provide self-alignment between the source/drain electrodes and the gate electrode in order to maintain a fixed and predictable overlapping position between the gate electrode and each of the source and drain electrodes across the entire chip to ensure the operating characteristics of the switch array substrate.

Disclosure of Invention

An object of the present invention is to provide a self-aligned switch array substrate and a method for manufacturing the same, which can maintain a fixed and predictable overlapping position between a gate electrode and source and drain electrodes of a thin film transistor, thereby controlling an overlapping influence of the gate electrode and the source and drain electrodes to ensure an operation characteristic thereof. In addition, the present application can form an auxiliary capacitor by designing the gate line, the gate dielectric layer and the transparent conductive layer corresponding to the gate line.

The application provides a manufacturing method of a switch array substrate, which comprises the following steps: forming a buffer layer on a substrate; forming a patterned first conductive layer on the buffer layer, wherein the patterned first conductive layer forms at least one gate line and at least one gate electrode, the gate line is electrically connected with the gate electrode and respectively comprises a first sub-layer and a second sub-layer positioned on the first sub-layer, the first sub-layer protrudes out of the second sub-layer in a direction parallel to the substrate, and the second sub-layer has an inclined side wall; forming a gate dielectric layer on the gate line, the gate electrode and the buffer layer; forming a semiconductor material layer on the gate dielectric layer and patterning the semiconductor material layer to make the semiconductor material layer arranged corresponding to the gate electrode; forming a second conductive layer on the semiconductor material layer and the gate dielectric layer, and patterning the second conductive layer to form a source electrode and a drain electrode on the semiconductor material layer, wherein the source electrode and the drain electrode are respectively in contact with the semiconductor material layer, and the gate electrode respectively enables the source electrode and the drain electrode to be overlapped in a self-alignment manner; and forming a patterned transparent conductive layer on the gate dielectric layer corresponding to the gate line.

The present application further provides a switch array substrate, which includes a substrate, a buffer layer, a gate line, a gate electrode, a gate dielectric layer, a semiconductor material layer, a source electrode, a drain electrode, and a transparent conductive layer. The buffer layer is arranged on the substrate. The gate line and the gate electrode are arranged on the buffer layer, the gate line and the gate electrode are electrically connected and respectively comprise a first sub-layer and a second sub-layer positioned on the first sub-layer, the first sub-layer protrudes out of the second sub-layer in the direction parallel to the substrate, and the second sub-layer is provided with an inclined side wall. The gate dielectric layer is disposed on the gate line, the gate electrode and the buffer layer. The semiconductor material layer is arranged on the gate dielectric layer and is arranged corresponding to the gate electrode. The source electrode and the drain electrode are respectively arranged on the semiconductor material layer, the source electrode and the drain electrode are respectively contacted with the semiconductor material layer, and the gate electrode is respectively overlapped with the source electrode and the drain electrode in a self-alignment manner. The transparent conductive layer is disposed on the gate dielectric layer corresponding to the gate line.

In one embodiment, the first sub-layer has two sidewalls having a selected overlap distance corresponding to a peripheral portion of the first sub-layer, and the patterned second conductive layer is self-aligned and overlapped with the gate electrode by disposing the source electrode and the drain electrode at least over the gate electrode by the selected overlap distance.

In one embodiment, the edge of the transparent conductive layer extends from the outside of the gate line to above the second sub-layer.

In one embodiment, the transparent conductive layer at least partially overlaps the sloped sidewalls of the second sub-layer in a direction perpendicular to the substrate.

In one embodiment, the first sub-layer, the gate dielectric layer and the transparent conductive layer form an auxiliary capacitor.

In one embodiment, the topography of the gate electrode is propagated upward through each layer covering the gate electrode.

The present application also provides a method for manufacturing a switch array substrate, including: forming a buffer layer on a substrate;

forming a patterned first conductive layer on the buffer layer, wherein the patterned first conductive layer forms at least one gate line and at least one gate electrode, the gate line is electrically connected with the gate electrode and respectively comprises a first sub-layer and a second sub-layer positioned on the first sub-layer, the first sub-layer protrudes out of the second sub-layer in a direction parallel to the substrate, and the second sub-layer has an inclined side wall; forming a gate dielectric layer on the gate line, the gate electrode and the buffer layer; forming a semiconductor material layer on the gate dielectric layer and patterning the semiconductor material layer to make the semiconductor material layer arranged corresponding to the gate electrode; forming a second conductive layer on the semiconductor material layer and the gate dielectric layer, and patterning the second conductive layer to form a source electrode and a drain electrode on the semiconductor material layer, wherein the source electrode and the drain electrode are respectively in contact with the semiconductor material layer, and the gate electrode respectively enables the source electrode and the drain electrode to be overlapped in a self-alignment manner; and forming a patterned transparent conductive layer on the gate dielectric layer corresponding to the gate line, wherein the edge of the transparent conductive layer extends from the outside of the gate line to the top of the second sub-layer, the transparent conductive layer and the inclined sidewall of the second sub-layer are at least partially overlapped in the direction vertical to the substrate, and the first sub-layer, the gate dielectric layer and the transparent conductive layer form an auxiliary capacitor.

In summary, in the switch array substrate and the method for manufacturing the same of the present application, the gate electrode with the double-layer structure is disposed on the buffer layer, and the source electrode and the drain electrode are disposed on the semiconductor material layer respectively and can contact the semiconductor material layer respectively, so that the source electrode and the drain electrode can be overlapped with the gate electrode in a self-aligned manner. Therefore, the switch array substrate of the present application can maintain a fixed and predictable overlapping position between the gate electrode and the source and drain electrodes of the thin film transistor, thereby controlling the overlapping influence of the gate electrode and the source and drain electrodes of the thin film transistor to ensure the operating characteristics of the switch array substrate. In addition, the present application can form an auxiliary capacitor by designing a gate line having a double-layer structure, a gate dielectric layer and a transparent conductive layer corresponding to the gate line.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

fig. 1 is a flowchart illustrating a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

Fig. 2A to fig. 2H are schematic diagrams illustrating a manufacturing process of a thin film transistor according to an embodiment of the present disclosure.

Fig. 3 is a schematic view illustrating a manufacturing process of a thin film transistor according to another embodiment of the present application.

Fig. 4 is a flowchart illustrating a method of fabricating a thin film transistor according to another embodiment of the present application.

Fig. 5A to fig. 5I are schematic views illustrating a manufacturing process of a thin film transistor according to another embodiment of the present application.

Fig. 6 is a schematic view illustrating a manufacturing process of a thin film transistor according to another embodiment of the present application.

Fig. 7 is a flowchart illustrating a method of manufacturing a switch array substrate according to an embodiment of the present application.

Fig. 8A to 8G are schematic views illustrating a manufacturing process of a switch array substrate according to an embodiment of the present application.

Detailed Description

Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present application. This application may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, it is to be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced device or assembly must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and therefore should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Hereinafter, a method of manufacturing a switch array substrate according to some embodiments of the present application will be described with reference to the accompanying drawings, in which like elements will be described with like reference numerals.

Fig. 1 is a flowchart illustrating a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. As shown in fig. 1, the method of manufacturing a thin film transistor may include: forming a first conductive layer on a substrate and patterning the first conductive layer to form a gate electrode (step S01); forming an insulating layer on the substrate and the gate electrode (step S02); using the gate electrode as a photo mask, using negative photoresist lithography to remove a portion of the insulating layer above the gate electrode, so that the height of the gate electrode is lower than the height of the two side insulating layers (step S03); forming a gate dielectric layer on the gate electrode and the insulating layer (step S04); forming a semiconductor material layer on the gate dielectric layer and patterning the semiconductor material layer such that the semiconductor material layer is disposed corresponding to the gate electrode (step S05); forming a second conductive layer on the semiconductor material layer and the gate dielectric layer (step S06); and patterning the second conductive layer to form a source electrode and a drain electrode on the semiconductor material layer, wherein the source electrode and the drain electrode contact the semiconductor material layer respectively, and the gate electrode overlaps the source electrode and the drain electrode in a self-aligned manner, respectively (step S07).

Hereinafter, please refer to fig. 2A to fig. 2H to describe the details of the steps S01 to S07. Fig. 2A to fig. 2H are schematic diagrams illustrating a manufacturing process of a thin film transistor according to an embodiment of the present application.

First, step S01 is: a first conductive layer M1 is formed on a substrate S1, and the first conductive layer M1 is patterned to form a gate electrode G. The substrate S1 may be a transparent material for transmissive display devices, such as glass, quartz or the like, plastic, rubber, fiberglass or other polymeric material, and in some embodiments may be a borate alkali-free glass substrate; alternatively, the substrate S1 may be an opaque material for self-emissive or reflective display devices, such as metal-glass fiber composite panels, metal-ceramic composite panels.

In step S01, as shown in fig. 2A, a first conductive layer M1 may be deposited on the substrate S1 by, for example, a Physical Vapor Deposition (PVD) method, a Chemical Vapor Deposition (CVD) method, or other suitable methods, and the first conductive layer M1 is patterned by using a photolithography technique to define the shape of the gate electrode G of the tft. Patterning the film layer by photolithography can be achieved by processes such as photoresist coating, exposure, development, etching and photoresist removal, which are well known in the art and are not important in the present application, and can be obtained from published literature data or networks by those skilled in the art, and will not be described herein. The material of the first conductive layer M1 (or the gate electrode G) in this embodiment is a single-layer or multi-layer structure made of opaque metal (such as aluminum, copper, silver, molybdenum, chromium, or titanium) or an alloy thereof, and is not limited. However, in this embodiment, before step S01, the manufacturing method may further include: after a buffer layer B is formed on the substrate S1, step S01 is performed to locate the gate electrode G on the buffer layer B. In addition, in some embodiments of fabricating the tft substrate, portions of the conductive lines for transmitting driving signals may be electrically connected to each other using a structure that is the same layer and the same process as the gate electrode G (the first conductive layer M1), such as a gate line (gate line).

Step S02 is performed: an insulating layer I is formed on the substrate S1 and the gate electrode G. As shown in fig. 2B, in the present embodiment, an insulating layer I may be deposited on the buffer layer B and the gate electrode G by using a Physical Vapor Deposition (PVD) method or a Chemical Vapor Deposition (CVD) method, for example, to cover the buffer layer B and the gate electrode G. The insulating layer I can be, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure of the above materials, but is not limited thereto.

Thereafter, step S03 is performed: using the gate electrode G as a photo mask, and using negative photoresist lithography to remove part of the insulating layer I above the gate electrode G, so that the height of the gate electrode G is lower than the height of the two side insulating layers I. In this step, as shown in fig. 2C, it may include: after a Negative photoresist (Negative Photo Resist) N is coated on a surface of the substrate S1 opposite to the gate electrode G, exposure, development and etching processes are performed to remove a portion of the insulating layer I on the gate electrode G. After the negative photoresist N is coated on the lower surface S12 of the substrate S1, the negative photoresist N is irradiated upward from the lower part of the negative photoresist N, so that light can sequentially pass through the negative photoresist N and the lower surface S12 of the substrate S1 and irradiate the insulating layer I, because the gate electrode G is made of opaque metal material, the insulating layer I above the gate electrode G is not irradiated by the light, the insulating layer I above the gate electrode G can be removed after development and etching, the insulating layers I at two sides of the gate electrode G are remained, and after the negative photoresist N is removed, the height of the gate electrode G itself can be lower than the height of the insulating layers I at two sides, as shown in FIG. 2D. The "height" is the shortest distance between the surface of the film layer away from the substrate S1 and the upper surface S11 of the substrate S1, based on the upper surface S11 of the substrate S1.

Thereafter, step S04 is performed: a gate dielectric layer GI is formed on the gate electrode G and the insulation layer I. As shown in FIG. 2E, a gate dielectric layer GI is formed on the gate electrode G and the insulating layer I by deposition, for example, so that the gate dielectric layer GI covers the gate electrode G and the insulating layer I. The gate dielectric layer GI may be an organic material such as an organosilicone compound, or an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure thereof. Since the height of the gate electrode G is lower than the height of the two side insulating layers I, a groove can be formed between the gate electrode G and the two side insulating layers I, and the gate dielectric layer GI is filled into the groove to form a step structure with the same height when the gate dielectric layer GI is formed.

Thereafter, step S05 is performed: forming a semiconductor material layer C on the gate dielectric layer GI and patterning the semiconductor material layer C so that the semiconductor material layer C is disposed corresponding to the gate electrode G. As shown in fig. 2F, after forming the semiconductor material layer C, the semiconductor material layer C is patterned by photolithography, so that the semiconductor material layer C is formed on the gate dielectric layer GI at a position opposite to the gate electrode G. Since the gate dielectric layer GI has a step structure, the semiconductor material layer C can have a step structure. In some embodiments, the semiconductor material layer C may be made of amorphous silicon (a-Si) material, and may for example include an amorphous silicon layer and a doped layer, and the amorphous silicon layer may be located between the doped layer and the gate dielectric layer GI. In some embodiments, the doped layer may be an n-type semiconductor layer.

Subsequently, as shown in fig. 2G, step S06 is further performed: a second conductive layer M2 is formed on the semiconductor material layer C and the gate dielectric layer GI. Here, the second conductive layer M2 can be formed on the semiconductor material layer C by, for example, deposition, such that the second conductive layer M2 contacts and covers the semiconductor material layer C. The gate electrode G and the insulating layers I on two sides form a step structure with high and low heights, so that the appearance of the gate electrode G is upwards transmitted through each film layer. The second conductive layer M2 is made of a single-layer or multi-layer structure of opaque metal (e.g., aluminum, copper, silver, molybdenum, chromium, or titanium) or an alloy thereof, but is not limited thereto. In addition, in some embodiments of manufacturing the tft substrate, a portion of the conductive lines for transmitting the driving signals may be electrically connected to each other using a structure that is the same layer as the second conductive layer M2 and manufactured in the same process, such as a data line (data line).

Finally, step S07 is performed: the second conductive layer M2 is patterned to form a source electrode S and a drain electrode D on the semiconductor material layer C, wherein the source electrode S and the drain electrode D contact the semiconductor material layer C, and the gate electrode G overlaps the source electrode S and the drain electrode D in a self-aligned manner. In some embodiments, the source electrode S and the drain electrode D may be formed in a self-aligned manner by performing an exposure process using, for example, a multi-Tone mask htm (half Tone mask), followed by an etching process to pattern the second conductive layer M2. In fig. 2H, the source electrode S and the drain electrode D are respectively located on the semiconductor material layer C, and the source electrode S and the drain electrode D are respectively in contact with the semiconductor material layer C, so that when the semiconductor material layer C of the thin film transistor is not turned on, the source electrode S and the drain electrode D are electrically separated.

Therefore, in the thin film transistor of the present embodiment, the buffer layer B is disposed on the substrate S1, the gate electrode G is disposed on the buffer layer B, the insulating layer I is disposed on the buffer layer B and on both sides of the gate electrode G, the height of the gate electrode G is lower than that of the insulating layer I on both sides, the gate dielectric layer GI is disposed on the gate electrode G and the insulating layer I, the semiconductor material layer C is disposed on the gate dielectric layer GI, and the semiconductor material layer C is disposed corresponding to the gate electrode G. In addition, the source electrode S and the drain electrode D are respectively disposed on the semiconductor material layer C and can respectively contact the semiconductor material layer C, so that the gate electrode G can respectively overlap the source electrode S and the drain electrode D in a self-aligned manner. Other technical features of the thin film transistor can be referred to above, and are not described herein.

Since the height of the gate electrode G is lower than the height of the insulating layers I on both sides, the gate electrode G and the insulating layers I on both sides can form a groove, and the gate dielectric layer GI can be filled in the groove, so that the region of the semiconductor material layer C as the source electrode S and the drain electrode D is higher than the middle region (i.e. the channel region) of the semiconductor material layer C, and therefore, the gate electrode G is closer to the middle portion (the channel region) of the semiconductor material layer C, and the gate electrode G is farther from the source electrode S, the gate electrode G and the drain electrode D, so as to control the overlapping effect of the gate electrode and the source/drain electrodes to ensure the operating characteristics thereof.

In some embodiments, as shown in fig. 3, the method for manufacturing a thin film transistor further includes: a passivation layer P is formed to cover the source electrode S, the drain electrode D and the semiconductor material layer C to protect them from being damaged by the intrusion of moisture or foreign matters. The passivation layer P may be formed by deposition, for example, and may be an organic material such as an organosilicone compound, or an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure thereof. This passivation layer P may be referred to as a back channel passivation layer to maintain the stability of the characteristics of the thin film transistor.

Fig. 4 is a flowchart illustrating a method of fabricating a thin film transistor according to another embodiment of the present application. As shown in fig. 4, the method of manufacturing a thin film transistor may include: forming a buffer layer on a substrate, and patterning the buffer layer to form a recess (step T01); forming a first conductive layer on the buffer layer (step T02); forming a photoresist corresponding to a gate electrode pattern on the first conductive layer corresponding to the recess (step T03); patterning the first conductive layer to form a gate electrode corresponding to the photoresist in the recess, so that the periphery of the gate electrode has a slope and a plane connected to each other, and removing the photoresist (step T04); forming a gate dielectric layer on the gate electrode and the buffer layer (step T05); forming a semiconductor material layer on the gate dielectric layer and patterning the semiconductor material layer such that the semiconductor material layer is disposed corresponding to the gate electrode (step T06); and forming a second conductive layer on the semiconductor material layer and the gate dielectric layer, and patterning the second conductive layer to form a source electrode and a drain electrode on the semiconductor material layer, wherein the source electrode and the drain electrode contact the semiconductor material layer, respectively, and the gate electrode overlaps the source electrode and the drain electrode in a self-aligned manner, respectively (step T07).

Please refer to fig. 5A to 5I to describe the details of the steps T01 to T07. Fig. 5A to 5I are schematic views illustrating a manufacturing process of a thin film transistor according to another embodiment of the present application.

First, step T01 is: a buffer layer B is formed on a substrate S1, and the buffer layer B is patterned to form a recess U. The substrate S1 may be a transparent material for transmissive display devices, such as glass, quartz or the like, plastic, rubber, fiberglass or other polymeric material, and in some embodiments may be a borate alkali-free glass substrate; alternatively, the substrate S1 may be an opaque material for self-emissive or reflective display devices, such as metal-glass fiber composite panels, metal-ceramic composite panels.

In step T01, as shown in fig. 5A, the buffer layer B may be deposited on the substrate S1, for example, by Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD), or other suitable method, and patterned by using photolithography technique, thereby patterning the buffer layer B to form the recess U. Here, the shape of the recess U can be defined by photolithography using a photomask (mask). Patterning the film layer by photolithography can be achieved by processes such as photoresist coating, exposure, development, etching and photoresist removal, which are well known in the art and are not important in the present application, and can be obtained from published literature data or networks by those skilled in the art, and will not be described herein. The buffer layer B may be, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure of the above materials, but is not limited thereto.

Next, step T02 is: a first conductive layer M1 is formed on the buffer layer B. As shown in fig. 5B, the first conductive layer M1 can be deposited on the buffer layer B by, for example, Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD), or other suitable methods, and since the buffer layer B has a recess U, the first conductive layer M1 will also fill the recess U to form another recess. The first conductive layer M1 is made of an opaque metal (e.g., aluminum, copper, silver, molybdenum, chromium, or titanium) or an alloy thereof. In addition, in some embodiments of manufacturing the tft substrate, some of the conductive lines for transmitting driving signals may be electrically connected to each other using a structure that is the same layer as the first conductive layer M1 and is manufactured in the same process, for example, a gate line (gate line).

To define the gate electrode pattern, the following steps T03 and T04 are performed. Wherein, the step T03 is: a photoresist P corresponding to a gate electrode pattern is formed on the first conductive layer M1 corresponding to the recess U. Here, in order to obtain a self-aligned gate electrode pattern, as shown in fig. 5C, a photoresist P corresponding to a desired gate electrode pattern is formed on another recess of the first conductive layer M1 in this embodiment.

In addition, step T04 is: the first conductive layer M1 is patterned to form a gate electrode G corresponding to the photoresist P in the recess U, so that the gate electrode G has a slope G21 and a plane G11 at its periphery, and the photoresist P is removed. As shown in fig. 5D and 5E, the gate electrode G can be formed by photolithography through the photoresist P corresponding to the gate electrode pattern, wherein the first conductive layer M1 except the gate electrode G is etched away, and the first conductive layer M1 is etched a little more, so that a portion of the first conductive layer M1 under the photoresist P is also removed, thereby obtaining the pattern of the gate electrode G having a planar lower layer and a sloped upper layer. In the present embodiment, the gate electrode G can be subdivided to include a first sub-layer G1 and a second sub-layer G, the first sub-layer G1 is located on the recess U of the buffer layer B, and the second sub-layer G2 is located on the first sub-layer G1. The plane G11 at the periphery of the gate electrode G is the surface of the first sub-layer G1 away from the buffer layer B, and the inclined plane G21 is the inclined sidewall of the second sub-layer G2. Here, when the second sub-layer G2 is removed (etched), the outer portion of the first sub-layer G1 is exposed in a self-aligned manner, thereby forming the gate electrode G having a gate electrode pattern. In addition, the first sub-layer G1 also has two (upstanding) side walls having a selected overlap distance d corresponding to the peripheral portion of the first sub-layer G1. The first sub-layer G1 of the present embodiment is quite thin, and the material of the first sub-layer G1 is the same as that of the second sub-layer G2. In other words, in the step T02 of forming the first conductive layer M1 (gate electrode G), the first conductive layer M1 is formed by a single process and a single material, so that after the step T04, the first sub-layer G1 and the second sub-layer G2 of the gate electrode G are made of the same material. Therefore, compared with the gate electrode G made of two materials, the process of the present embodiment is simpler and the cost is lower. In addition, it is to be noted that the gate electrode G is divided into the first sub-layer G1 and the second sub-layer G2 for illustration purpose only, and the first conductive layer M1 (gate electrode G) is not formed by two different materials and processes.

Thereafter, step T05 is performed: a gate dielectric layer GI is formed on the gate G and the buffer layer B. As shown in fig. 5F, a gate dielectric layer GI is formed on the gate electrode G and the buffer layer B, for example, by deposition, so that the gate dielectric layer GI covers the gate electrode G and the buffer layer B. The gate dielectric layer GI may be an organic material such as an organosilicone compound, or an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure thereof. Since the gate electrode G is a structure protruding from the recess U, and the periphery of the gate electrode G has the interconnection slope G21 and the plane G11, the topography of the gate electrode G can be propagated upward through each film layer formed later and covering the gate electrode G.

Next, step T06 is: forming a semiconductor material layer C on the gate dielectric layer GI and patterning the semiconductor material layer C so that the semiconductor material layer C is disposed corresponding to the gate electrode G. As shown in fig. 5G, a semiconductor material layer C is formed on the gate dielectric layer GI and then patterned by photolithography, so that the semiconductor material layer C is formed on the gate dielectric layer GI at a position opposite to the gate electrode G. Since the gate dielectric layer GI has a step structure formed according to the gate electrode G pattern, the semiconductor material layer C can have a step structure. In some embodiments, the semiconductor material layer C may be made of amorphous silicon (a-Si) material, and may for example include an amorphous silicon layer and a doped layer, and the amorphous silicon layer may be located between the doped layer and the gate dielectric layer GI. In some embodiments, the doped layer may be an n-type semiconductor layer.

Next, as shown in fig. 5H, step T07 is performed: forming a second conductive layer M2 on the semiconductor material layer C and the gate dielectric layer GI, and patterning the second conductive layer M2 to form a source electrode S and a drain electrode D on the semiconductor material layer C, wherein the source electrode S and the drain electrode D contact the semiconductor material layer C, respectively, and the gate electrode G makes the source electrode S and the drain electrode D overlap each other in a self-aligned manner. Here, the second conductive layer M2 may be formed on the semiconductor material layer C by, for example, deposition, such that the second conductive layer M2 contacts and covers the semiconductor material layer C. Here, the topography of the gate electrode G is propagated upward through each film layer as well, so that the second conductive layer M2 has a topography similar to that of the gate electrode G. The second conductive layer M2 is made of a single-layer or multi-layer structure of opaque metal (e.g., aluminum, copper, silver, molybdenum, chromium, or titanium) or an alloy thereof, but is not limited thereto. In addition, in some embodiments of manufacturing the tft substrate, a portion of the conductive lines for transmitting the driving signals may be electrically connected to each other using a structure that is the same layer as the second conductive layer M2 and manufactured in the same process, such as a data line (data line).

Thereafter, as shown in fig. 5I, the second conductive layer M2 is patterned such that the source electrode S and the drain electrode D are disposed above the gate electrode G at least by the selected overlap distance D to overlap the gate electrode G in a self-aligned manner. In some embodiments, the source electrode S and the drain electrode D may be formed in a self-aligned manner by performing an exposure process using, for example, a multi-Tone mask htm (half Tone mask), followed by an etching process to pattern the second conductive layer M2. In fig. 5I, the source electrode S and the drain electrode D are respectively located on the semiconductor material layer C, and the source electrode S and the drain electrode D are respectively in contact with the semiconductor material layer C, when the semiconductor material layer C of the thin film transistor is not turned on, the source electrode S and the drain electrode D are electrically separated.

Therefore, in the tft of this embodiment, the buffer layer B is disposed on the substrate and has a recess, the gate electrode G is disposed in the recess U of the buffer layer B, and has an inclined plane G21 and a plane G11 connected to each other at the periphery thereof, the gate dielectric layer GI is disposed on the gate electrode G and the buffer layer B, the semiconductor material layer C is disposed on the gate dielectric layer GI, and the semiconductor material layer C is disposed corresponding to the gate electrode G. In addition, the source electrode S and the drain electrode D are respectively disposed on the semiconductor material layer C and can respectively contact the semiconductor material layer C, so that the gate electrode G can respectively overlap the source electrode S and the drain electrode D in a self-aligned manner. Other technical features of the thin film transistor can be referred to above, and are not described herein.

Since the gate electrode G is disposed in the recess U of the buffer layer B and has an outer periphery with an interconnecting inclined plane G21 and a plane G11, the source electrode S and the drain electrode D are respectively disposed on the semiconductor material layer C and can respectively contact the semiconductor material layer C, such that the source electrode S and the drain electrode D are self-aligned and overlapped with the gate electrode G at least by a selected overlap distance D disposed above the gate electrode G. Therefore, the thin film transistor of the present embodiment can manufacture the gate electrode G that overlaps the source electrode S and the drain electrode D in self-alignment by using the first conductive layer M1 made of the same material, so that the overlapping position between the gate electrode G and the source electrode S and the drain electrode D can be kept fixed and predictable, thereby controlling the overlapping effect of the gate electrode and the source electrode and the drain electrode to ensure the operating characteristics thereof.

In some embodiments, as shown in fig. 6, a schematic view of a manufacturing process of a thin film transistor according to another embodiment of the present application is shown. The method for manufacturing a thin film transistor may further include: a passivation layer P is formed to cover the source electrode S, the drain electrode D and the semiconductor material layer C to protect them from being damaged by the intrusion of moisture or foreign matters. The passivation layer P may be formed by deposition, for example, and may be an organic material such as an organosilicone compound, or an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure thereof. This passivation layer P may be referred to as a back channel passivation layer to maintain the stability of the characteristics of the thin film transistor.

In addition, in some embodiments, a plurality of thin film transistors may be formed on the substrate S1 in an array arrangement to form a thin film transistor substrate.

Fig. 7 is a flowchart illustrating a method of manufacturing a switch array substrate according to an embodiment of the present application. As shown in fig. 7, the method for manufacturing the switch array substrate may include: forming a buffer layer on a substrate (step U01); forming a patterned first conductive layer on the buffer layer, wherein the patterned first conductive layer forms at least one gate line and at least one gate electrode, the gate line is electrically connected to the gate electrode and respectively includes a first sub-layer and a second sub-layer on the first sub-layer, the first sub-layer protrudes from the second sub-layer in a direction parallel to the substrate, and the second sub-layer has an inclined sidewall (step U02); forming a gate dielectric layer on the gate line, the gate electrode and the buffer layer (step U03); forming a semiconductor material layer on the gate dielectric layer and patterning the semiconductor material layer such that the semiconductor material layer is disposed corresponding to the gate electrode (step U04); forming a second conductive layer on the semiconductor material layer and the gate dielectric layer, and patterning the second conductive layer to form a source electrode and a drain electrode on the semiconductor material layer, wherein the source electrode and the drain electrode contact the semiconductor material layer, respectively, and the gate electrode overlaps the source electrode and the drain electrode in a self-aligned manner, respectively (step U05); and forming a transparent conductive layer patterned corresponding to the gate line on the gate dielectric layer (step U06).

Please refer to fig. 8A to 8G to describe the details of the steps U01 to U06. Fig. 8A to 8G are schematic views illustrating a manufacturing process of a switch array substrate according to an embodiment of the present application.

First, step U01 is: a buffer layer B is formed on a substrate S1. The substrate S1 may be a transparent material for transmissive display devices, such as glass, quartz or the like, plastic, rubber, fiberglass or other polymeric material, and in some embodiments may be a borate alkali-free glass substrate; alternatively, the substrate S1 may be an opaque material for self-emissive or reflective display devices, such as metal-glass fiber composite panels, metal-ceramic composite panels.

In step U01, as shown in fig. 8A, the buffer layer B may be formed on the substrate S1 by, for example, a Physical Vapor Deposition (PVD) method, a Chemical Vapor Deposition (CVD) method, or other suitable method. The buffer layer B may be, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a single-layer or multi-layer structure of the above materials, but is not limited thereto.

Next, step U02 is: a patterned first conductive layer M1 is formed on the buffer layer B, wherein the patterned first conductive layer M1 forms at least one gate line GL and at least one gate electrode G, the gate line GL is electrically connected to the gate electrode G and respectively includes a first sub-layer G1 and a second sub-layer G2 located on the first sub-layer G1, the first sub-layer G1 protrudes from the second sub-layer G2 in a direction parallel to the substrate S1, and the second sub-layer G2 has an inclined sidewall G21. Here, the first conductive layer M1 may be deposited on the buffer layer B by, for example, a Physical Vapor Deposition (PVD) method or a Chemical Vapor Deposition (CVD) method, or other suitable methods, and the gate lines GL and G may be defined by using a photomask (mask) and using a photolithography technique to form the gate electrodes G of the thin film transistors and the gate lines GL electrically connected to the gate electrodes G. Here, the gate lines GL and the gate electrodes G have the same shape and structure. In other words, the gate electrode G of the thin film transistor and the gate line GL electrically connected to the gate electrode G are formed by the same process and material. In some embodiments of the switch array substrate, the patterned first conductive layer M1 may form a plurality of gate lines GL and a plurality of gate electrodes G, and each gate line GL may be electrically connected to the plurality of gate electrodes G arranged in rows and form a matrix arranged in rows and columns. Patterning the film layer by photolithography can be achieved by processes such as photoresist coating, exposure, development, etching and photoresist removal, which are well known in the art and are not important in the present application, and can be obtained from published literature data or networks by those skilled in the art, and will not be described herein. The material of the first conductive layer M1 is a multilayer structure made of opaque metal (e.g., aluminum, copper, silver, molybdenum, chromium, or titanium) or an alloy thereof.

As shown in fig. 8B, the gate line GL and the gate electrode G formed by the patterned first conductive layer M1 of the present embodiment may respectively include a first sub-layer G1 and a second sub-layer G2. The first sub-layer G1 is disposed on the buffer layer B, and the second sub-layer G2 is stacked on the first sub-layer G1. The first sub-layer G1 of the present embodiment is different from the second sub-layer G2 in material, and in some embodiments, the first sub-layer G1 is, for example but not limited to, titanium (Ti), and the second sub-layer G2 is, for example but not limited to, molybdenum (Mo) or aluminum (Al). In addition, the first sub-layer G1 protrudes from the second sub-layer G2 in a direction parallel to the substrate S1 to have a plane G11, and the periphery of the second sub-layer G2 has an inclined sidewall G21. Here, when the second sub-layer G2 is removed (etched), the outer portion of the first sub-layer G1 is exposed in a self-aligned manner, thereby forming the gate electrode G (and the gate line GL) having a gate electrode pattern. In addition, the first sub-layer G1 has two sidewalls opposite to the second sub-layer G2, the two sidewalls have a selected overlapping distance d, and the selected overlapping distance d corresponds to the peripheral portion of the first sub-layer G1.

Then, step U03 is performed: a gate dielectric layer GI is formed on the gate line GL, the gate electrode G and the buffer layer B. As shown in fig. 8C, a gate dielectric layer GI is formed on the gate electrode G and the buffer layer B, for example, by deposition, so that the gate dielectric layer GI covers the gate electrode G and the buffer layer B, and the gate dielectric layer GI is also formed on the gate line GL and covers the gate line GL. The gate dielectric layer GI may be an organic material such as an organo-silicon oxide, or an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure thereof. Since the periphery of the gate electrode G has a stepped structure of the inclined sidewall G21 of the second sub-layer G2 and the plane G11 of the first sub-layer G1 connected to each other, the topography of the gate electrode G can be propagated upward through the gate dielectric layer GI formed later and covering the gate electrode G.

Next, step U04 is: forming a semiconductor material layer C on the gate dielectric layer GI and patterning the semiconductor material layer C so that the semiconductor material layer C is disposed corresponding to the gate electrode G. As shown in fig. 8D, a semiconductor material layer C is formed on the gate dielectric layer GI and then patterned by photolithography, for example, so that the semiconductor material layer C is formed on the gate dielectric layer GI at a position opposite to the gate electrode G. Since the gate dielectric layer GI has a step structure formed according to the gate electrode G pattern, the semiconductor material layer C can have a step structure. In some embodiments, the semiconductor material layer C may be made of amorphous silicon (a-Si) material, and may for example include an amorphous silicon layer and a doped layer, and the amorphous silicon layer may be located between the doped layer and the gate dielectric layer GI. In some embodiments, the doped layer may be a layer of n-type semiconductor material.

As shown in fig. 8E, step U05 is performed: forming a second conductive layer M2 on the semiconductor material layer C and the gate dielectric layer GI, and patterning the second conductive layer M2 to form a source electrode S and a drain electrode D on the semiconductor material layer C, wherein the source electrode S and the drain electrode D contact the semiconductor material layer C, respectively, and the gate electrode G makes the source electrode S and the drain electrode D overlap each other in a self-aligned manner. Here, the second conductive layer M2 may be formed on the semiconductor material layer C by, for example, deposition, such that the second conductive layer M2 contacts and covers the semiconductor material layer C. Wherein the topography of the gate electrode G is propagated upward through each film layer covering the gate electrode G as well, so that the second conductive layer M2 has a topography similar to the gate electrode G. The second conductive layer M2 is made of a single-layer or multi-layer structure of opaque metal (e.g., aluminum, copper, silver, molybdenum, chromium, or titanium) or an alloy thereof, but is not limited thereto.

In addition, the patterned second conductive layer M2 is formed by disposing the source electrode S and the drain electrode D above the gate electrode G at least by the selected overlap distance D, so as to overlap the gate electrode G in a self-aligned manner. In some embodiments, the source electrode S and the drain electrode D may be formed in a self-aligned manner by performing an exposure process using, for example, a multi-Tone mask htm (half Tone mask), followed by an etching process to pattern the second conductive layer M2. In fig. 8E, the source electrode S and the drain electrode D are respectively located on the semiconductor material layer C, and the source electrode S and the drain electrode D are respectively in contact with the semiconductor material layer C, when the semiconductor material layer C of the thin film transistor is not turned on, the source electrode S and the drain electrode D are electrically separated. In addition, in some embodiments of the switch array substrate, the patterned second conductive layer M2 may form a plurality of data lines (data lines) and a plurality of source electrodes S or drain electrodes D electrically connected to the data lines, respectively, to form thin film transistors of a plurality of pixels, and the gate electrodes G corresponding to the thin film transistors are electrically connected to the gate lines GL, respectively.

In some embodiments of the method for manufacturing a switch array substrate, the method may further include: forming a passivation layer P to cover the source electrode S and the drain electrode D, and forming a through hole H on the passivation layer P to expose a portion of the source electrode S or the drain electrode D. As shown in fig. 8F, after a passivation layer P is formed on the tft by deposition, a through hole H is formed on the passivation layer P by photolithography to expose a portion of the drain electrode D. The passivation layer P may be an organic material such as an organosilicone compound, or an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a multi-layer structure thereof. The passivation layer P may be referred to as a back channel passivation layer, which may maintain stability of the thin film transistor.

In addition, in some embodiments of the method for manufacturing a switch array substrate, the method may further include: and forming a patterned transparent conductive layer E on the passivation layer P, wherein the transparent conductive layer E fills the through hole H and contacts the source electrode S or the drain electrode D. As shown in fig. 8F, a patterned transparent conductive layer E may be formed, for example, by deposition and photolithography techniques, covering the passivation layer P, and filling the via hole H to contact and electrically connect with the drain electrode D. The transparent conductive layer E may be a pixel electrode of a pixel, and may be made of, but not limited to, a transparent conductive material such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Aluminum Zinc Oxide (AZO), Cadmium Tin Oxide (CTO), tin oxide (SnO2), or zinc oxide (ZnO), for example. In this embodiment, the transparent conductive layer E can be pixel electrodes arranged in an array on the switch array substrate and can extend to the corresponding gate lines GL.

Referring to fig. 7, in the above process of forming the transparent conductive layer E, a patterned transparent conductive layer E may be formed on the gate dielectric layer GI corresponding to the gate line GL (step U06). As shown in fig. 8G, the (two) edges E1 of the patterned transparent conductive layer E extend from the outside of the gate line GL to the top of the second sub-layer G2 of the gate line GL, and the transparent conductive layer E at least partially overlaps the inclined sidewall G21 of the second sub-layer G2 in the direction perpendicular to the substrate S1, so that the first sub-layer G1, the gate dielectric layer GI and the transparent conductive layer E can form an auxiliary capacitor. Here, one auxiliary capacitor is formed on each of both sides of the gate line GL. Therefore, in the switch array substrate of the present embodiment, in addition to controlling the overlapping effect of the source electrode S/drain electrode D by the gate electrode G of the two-layer structure (the first sub-layer G1 and the second sub-layer G2), the gate line GL formed by the same first conductive layer M1 can be used to form the auxiliary capacitance between the protruding portion of the first sub-layer G1 and the transparent conductive layer E (pixel electrode).

In the switch array substrate of the present embodiment, the buffer layer B is disposed on the substrate S1, the gate line GL and the gate electrode G are disposed on the buffer layer B, wherein the gate line GL is electrically connected to the gate electrode G and respectively includes a first sub-layer G1 and a second sub-layer G2 on the first sub-layer G1, the first sub-layer G1 protrudes from the second sub-layer G2 in a direction parallel to the substrate S1, the second sub-layer G2 has an inclined sidewall G21, the gate dielectric layer GI is disposed on the gate line GL, the gate electrode G and the buffer layer B, the semiconductor material layer C is disposed on the gate dielectric layer GI, and the semiconductor material layer C is disposed corresponding to the gate electrode G. The source electrode S and the drain electrode D are respectively arranged on the semiconductor material layer C, the source electrode S and the drain electrode D are respectively contacted with the semiconductor material layer C, and the gate electrode G is respectively overlapped with the source electrode S and the drain electrode D in a self-alignment mode. In addition, a transparent conductive layer E is disposed on the gate dielectric layer GI corresponding to the gate line GL. The edge of the transparent conductive layer E extends from the outside of the gate line GL to the top of the second sub-layer G2, and the transparent conductive layer E at least partially overlaps the inclined sidewall G21 of the second sub-layer G2 in the direction perpendicular to the substrate S1, so that the first sub-layer G1, the gate dielectric layer GI and the transparent conductive layer E form an auxiliary capacitor. For the technical features of other components of the switch array substrate, reference may be made to the same components and descriptions thereof, which are not described herein again.

In summary, in the switch array substrate and the manufacturing method thereof of the present application, the gate electrode with the double-layer structure is disposed on the buffer layer, and the source electrode and the drain electrode are disposed on the semiconductor material layer respectively and can contact the semiconductor material layer respectively, so that the source electrode and the drain electrode can be overlapped with the gate electrode in a self-aligned manner. Therefore, the switch array substrate of the present application can maintain a fixed and predictable overlapping position between the gate electrode and the source and drain electrodes of the thin film transistor, thereby controlling the overlapping influence of the gate electrode and the source and drain electrodes of the thin film transistor to ensure the operating characteristics of the switch array substrate. In addition, the present application can form an auxiliary capacitor by designing a gate line having a double-layer structure, a gate dielectric layer and a transparent conductive layer corresponding to the gate line.

The foregoing is by way of example only, and not limiting. Any equivalent modifications or variations without departing from the spirit and scope of the present application should be included in the scope of the claims.

Claims

1. A method for manufacturing a switch array substrate includes:

forming a buffer layer on a substrate;

forming a patterned first conductive layer on the buffer layer, wherein the patterned first conductive layer forms at least one gate line and at least one gate electrode, the gate line is electrically connected to the gate electrode and respectively includes a first sub-layer and a second sub-layer located on the first sub-layer, the first sub-layer protrudes from the second sub-layer in a direction parallel to the substrate and has a plane, the first sub-layer has two sidewalls, the two sidewalls have a selected overlapping distance, the selected overlapping distance corresponds to a peripheral portion of the first sub-layer, and the second sub-layer has an inclined sidewall;

forming a gate dielectric layer on the gate line, the gate electrode and the buffer layer;

forming a semiconductor material layer on the gate dielectric layer and patterning the semiconductor material layer to make the semiconductor material layer arranged corresponding to the gate electrode;

forming a second conductive layer over the semiconductor material layer and the gate dielectric layer, and patterning the second conductive layer to form a source electrode and a drain electrode, respectively, on the semiconductor material layer, wherein the source electrode and the drain electrode contact the semiconductor material layer, respectively, and the gate electrode self-aligns and overlaps the source electrode and the drain electrode, respectively, wherein patterning the second conductive layer is such that the source electrode and the drain electrode are disposed over the gate electrode, at least by the selected overlap distance, self-aligned and overlap the gate electrode; and

forming a patterned transparent conductive layer on the gate dielectric layer corresponding to the gate line, wherein the edge of the transparent conductive layer extends from the outside of the gate line to the top of the second sub-layer, the transparent conductive layer at least partially overlaps the inclined sidewall of the second sub-layer in the direction perpendicular to the substrate, and the first sub-layer, the gate dielectric layer and the transparent conductive layer form an auxiliary capacitor.

2. The method of manufacturing of claim 1, wherein the topography of the gate electrode propagates upward through each film layer covering the gate electrode.

3. A switch array substrate, comprising:

a substrate;

the buffer layer is arranged on the base material;

a gate line and a gate electrode disposed on the buffer layer, the gate line electrically connected to the gate electrode and respectively including a first sub-layer and a second sub-layer disposed on the first sub-layer, the first sub-layer protruding from the second sub-layer in a direction parallel to the substrate and having a plane, the first sub-layer having two sidewalls, the two sidewalls having a selected overlap distance, the selected overlap distance corresponding to a peripheral portion of the first sub-layer, the second sub-layer having an inclined sidewall;

a gate dielectric layer disposed on the gate line, the gate electrode and the buffer layer;

a semiconductor material layer disposed on the gate dielectric layer, the semiconductor material layer corresponding to the gate electrode;

a source electrode and a drain electrode respectively disposed on the layer of semiconductor material, the source electrode and the drain electrode respectively contacting the layer of semiconductor material, and the gate electrode respectively self-aligningly overlapping the source electrode and the drain electrode, wherein the source electrode and the drain electrode are disposed over the gate electrode at least by the selected overlap distance and self-aligningly overlap the gate electrode; and

a transparent conductive layer disposed on the gate dielectric layer corresponding to the gate line, wherein an edge of the transparent conductive layer extends from an outer side of the gate line to above the second sub-layer, the transparent conductive layer at least partially overlaps the inclined sidewall of the second sub-layer in a direction perpendicular to the substrate, and the first sub-layer, the gate dielectric layer and the transparent conductive layer form an auxiliary capacitor.

4. The switch array substrate of claim 3, wherein the topography of the gate electrode propagates upward through each film layer covering the gate electrode.