CN108346664B - Memory device with cell-on-periphery structure and memory package including same - Google Patents

Abstract

The present disclosure provides a memory device having a peripheral on cell structure and a memory package including the same. A memory device includes a substrate and peripheral circuitry disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. The memory device further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power supply wiring configured to supply a first voltage, a second power supply wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to either the first power wiring or the second power wiring.

Description

Memory device with cell-on-periphery structure and memory package including same

technical field

Example embodiments of inventive concepts relate generally to memory devices, and more particularly, to memory devices having a cell over periphery (COP) structure and memory packages including the same.

Background technique

A vertical memory device, commonly referred to as a three-dimensional (3D) memory device, is a memory device including a plurality of memory cells repeatedly stacked on a surface of a substrate. These memory devices are capable of very high storage capacities in very small structures. For example, in a vertical memory device, a channel may protrude from a surface of a substrate or may extend vertically from the surface of the substrate, and gate lines and insulating layers surrounding the vertical channel may be repeatedly stacked.

However, reduction in size of vertical memory devices is limited because the memory devices must still include interfaces to electrically connect the memory devices to peripheral circuits for communicating with and being driven by external devices.

Contents of the invention

According to an exemplary embodiment of the inventive concept, a memory device includes a substrate and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. The memory device further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power wiring configured to supply a first voltage, a second power wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring.

According to an exemplary embodiment of the inventive concept, a memory package includes a base substrate and a plurality of memory chips stacked on the base substrate. Each of the plurality of memory chips includes a substrate and peripheral circuits disposed on the first surface of the substrate. The peripheral circuit includes a first transistor. Each memory chip further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array . The second wiring layer includes a first power wiring configured to supply a first voltage, a second power wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring.

According to an exemplary embodiment of the inventive concept, a memory device includes a substrate and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor and a second transistor, a lower wiring layer provided on the peripheral circuit, a base layer provided on the lower wiring layer, and a memory cell array provided on the base layer. The memory cell array includes a plurality of channels. The memory device also includes an upper wiring layer disposed on the memory cell array. The upper wiring layer includes at least two power wirings. A first power supply wiring of the at least two power supply wirings is configured to supply a first voltage, and a second power supply wiring of the at least two power supply wirings is configured to supply a second voltage. The upper wiring layer also includes a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring. The upper wiring layer also includes a second wiring electrically connected to the second transistor. The second wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring.

Description of drawings

The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

FIG. 1 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept;

2 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

3 is a cross-sectional view taken along line II' of FIG. 2 according to an exemplary embodiment of the present inventive concept;

4 is a circuit diagram illustrating an example of a memory cell array that may be disposed in the memory cell region in FIG. 3 according to an exemplary embodiment of the inventive concept;

5, 6, 7, 8, and 9 are cross-sectional views for describing a process of manufacturing a memory device according to an exemplary embodiment of the present inventive concept;

FIG. 10 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

11 is a cross-sectional view taken along line II' of FIG. 10 according to an exemplary embodiment of the present inventive concept;

12 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

13 is a cross-sectional view taken along line II-II' of FIG. 12 according to an exemplary embodiment of the present inventive concept;

14 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

15 is a cross-sectional view taken along line III-III' of FIG. 14 according to an exemplary embodiment of the present inventive concept;

16 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept;

17 and 18 are diagrams illustrating a memory package according to an exemplary embodiment of the inventive concept;

19 is a block diagram illustrating a solid state disk or a solid state drive (SSD) according to an exemplary embodiment of the present inventive concept;

20 is a block diagram illustrating an embedded multimedia card (eMMC) according to an exemplary embodiment of the present inventive concept;

21 is a block diagram illustrating a universal flash memory (UFS) according to an exemplary embodiment of the inventive concept; and

FIG. 22 is a block diagram illustrating a mobile device according to an exemplary embodiment of the inventive concept.

Detailed ways

Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. FIG. 1 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept.

In FIG. 1 , a direction substantially perpendicular to a first surface (eg, a top surface) of a substrate is referred to as a first direction D1 (eg, a Z-axis direction). Also, two directions substantially parallel to the first surface of the substrate and intersecting each other are referred to as a second direction D2 (eg, X-axis direction) and a third direction D3 (eg, Y-axis direction). For example, the second direction D2 and the third direction D3 may be substantially perpendicular to each other. In addition, the first direction D1 (eg, the Z-axis direction) is substantially perpendicular to both the second direction D2 (eg, the X-axis direction) and the third direction D3 (eg, the Y-axis direction).

Referring to FIG. 1 , the memory device 10 includes a peripheral circuit region PCR in which peripheral circuits are disposed. The memory device 10 also includes a memory cell region MCR in which the memory cell array MCA is disposed. The memory device 10 may further include a plurality of input/output (I/O) pads IOPAD disposed on a top surface thereof.

The peripheral circuit region PCR includes the semiconductor substrate 20, the peripheral circuit may be on a first surface (eg, top surface) of the semiconductor substrate 20, and the first wiring layer 30 may be disposed on the peripheral circuit. In addition, the peripheral circuit may include a first transistor TR disposed on the first surface of the semiconductor substrate 20 . The memory cell region MCR includes a base layer 40 that may be disposed on the first wiring layer 30 , a memory cell array MCA that may be disposed on the base layer 40 , and a second wiring layer 50 that may be disposed on the memory cell array MCA. The plurality of I/O pads IOPAD may be disposed on the second wiring layer 50 .

The second wiring layer 50 may include a first power wiring 52 , a second power wiring 54 and a first wiring 56 . The second wiring layer 50 may further include a first connection wiring 58 .

The first power wiring 52 may be configured to supply a first voltage to the memory device 10 , and the second power wiring 54 may be configured to supply a second voltage to the memory device 10 . Furthermore, the second voltage may be different from the first voltage. For example, the first voltage may be a power supply voltage (such as Vcc), and the second voltage may be a ground voltage (such as Vss).

The first wiring 56 may be electrically connected to the first transistor TR. For example, as will be described with reference to FIG. 3 , the first wiring 56 may be electrically connected to the gate electrode of the first transistor TR through at least one contact provided through the first wiring layer 30 and the second wiring layer 50 .

The first wiring 56 may be configured to be electrically connectable to one of the first power wiring 52 and the second power wiring 54 . For example, as shown in FIG. 1 , the first wiring 56 may be electrically connected to the first power supply wiring 52 through a first connection wiring 58 . The first transistor TR may receive a first voltage. In another example, the first wiring 56 may be electrically connected to the second power wiring 54 through a second connection wiring. Furthermore, the first transistor TR may then receive the second voltage.

The memory device 10 according to an exemplary embodiment of the inventive concept may have a relatively small size by employing a cell on periphery (COP) structure. By adopting this structure, the peripheral circuit is provided on the semiconductor substrate 20 and the memory cell array MCA is stacked on the peripheral circuit. In addition, in the memory device 10 according to an exemplary embodiment of the present inventive concept, the first wiring 56 electrically connected to the first transistor TR in the peripheral circuit may be disposed in the second wiring layer 50 disposed in the second wiring layer 50 On the memory cell array MCA. In addition, the first wiring 56 may be electrically connectable to the first power wiring 52 or the second power wiring 54 . Therefore, the design of the memory device 10 can be easily modified, and thus the time for manufacturing the memory device 10 can be reduced even if the design of the memory device 10 is modified.

FIG. 2 is a top view of a memory device according to an exemplary embodiment of the inventive concept. FIG. 3 is a cross-sectional view taken along line II' of FIG. 2 according to an exemplary embodiment of the present inventive concept.

Referring to FIGS. 2 and 3 , the memory device may include a peripheral circuit region PCR and a memory cell region MCR. The peripheral circuit region PCR includes a peripheral circuit structure disposed on the substrate 100. The memory cell region MCR includes memory cells disposed on the peripheral circuit structure. cell structure.

In some exemplary embodiments of the inventive concept, the memory device may be a nonvolatile memory device. For example, a nonvolatile memory device may have a COP structure in which a memory cell structure is stacked on a peripheral circuit structure. The memory cell structure may have a vertical NAND flash memory structure in which a plurality of NAND flash memory cells are arranged vertically. For example, NAND flash memory cells may be stacked in a first direction D1 with respect to a first surface (eg, a top surface) of the substrate 100 .

In addition, FIG. 2 shows the base layer 201 , the pad 240 , the mold protection layer 212 , the first power supply wiring 310 , the second power supply wiring 320 , the first wiring 330 , and the first connection wiring 332 .

The peripheral circuit structure may, for example, include a gate structure 130 , source/drain regions 103 , insulating layers 140 and 160 , contacts 145 , wiring 150 , etc., which may be disposed on the substrate 100 . The insulating layers 140 and 160, the contact 145, and the wiring 150 may form a first wiring layer (eg, the first wiring layer 30 in FIG. 1). Also, the first wiring layer may be referred to as a lower wiring layer. The insulating layers 140 and 160 may be referred to as lower insulating layers. The contact 145 may be called a lower contact or a first contact, and the wiring 150 may be called a lower wiring or a second wiring.

The substrate 100 may include a semiconductor material such as crystalline silicon formed from a single crystal or crystalline germanium formed from a single crystal. The gate structure 130 may include a gate insulating layer pattern 110 and a gate electrode 120 stacked on the substrate 100 . In addition, a gate electrode 120 is disposed on the gate insulating layer pattern 110 .

The gate insulating layer pattern 110 may include, for example, silicon oxide or metal oxide. The gate electrode 120 may include, for example, metal, metal nitride, or doped polysilicon. The source/drain regions 103 may include n-type or p-type impurities. A transistor (eg, the first transistor TR in FIG. 1 ) including a gate structure 130 and a source/drain region 103 may be disposed on the substrate 100 .

The first lower insulating layer 140 may be disposed on the substrate 100 to cover structures such as the transistors that may be disposed on the substrate 100 . The first lower contact 145 may extend through a portion of the first lower insulating layer 140 and may be electrically connected to the gate electrode 120 .

The first lower wiring 150 may be disposed on the upper surface of the first lower insulating layer 140 and may be electrically connected to the first lower contact 145 . The second lower insulating layer 160 may be disposed on the first lower insulating layer 140 to cover the first lower wiring 150 . Although FIG. 3 shows an exemplary embodiment of the inventive concept (wherein the lower wiring layer includes a single lower wiring 150), as will be described with reference to FIGS. 11 and 13, the lower wiring layer may include multiple down the wiring.

The first lower insulating layer 140 and the second lower insulating layer 160 may include an insulating material such as silicon oxide. The first lower contact 145 and the first lower wiring 150 may include, for example, metal, metal nitride, or doped polysilicon.

The memory cell structure may include a base layer 201 which may be disposed on a lower wiring layer (for example, disposed on the second lower insulating layer 160), a channel 225, gate lines 260a, 260b, 260c, 260d, 260e, and 260f, bit lines 285, The insulating layers 275 and 290, the contact 248a, and the wirings 310, 320, 330, and 332, and the like. The insulating layers 275 and 290, the contact 248a, and the wirings 310, 320, 330, and 332 may form a second wiring layer (eg, the second wiring layer 50 in FIG. 1). The second wiring layer may be referred to as an upper wiring layer, and the insulating layers 275 and 290 may be referred to as an upper insulating layer, wherein, for example, the second upper insulating layer 290 may be disposed on the first upper insulating layer 275 . Also, the contact 248a may be referred to as an upper contact, and the wirings 310, 320, 330, and 332 may be referred to as upper wirings.

The base layer 201 may include, for example, polysilicon or crystalline silicon formed of a single crystal. In some exemplary embodiments of the inventive concept, the base layer 201 may further include p-type impurities such as boron (B), and in this case, the base layer 201 may serve as a p-type well.

The channel 225 may be disposed on the base layer 201 and may extend from a first surface (eg, top surface) of the base layer 201 in a first direction D1 (eg, Z-axis direction). The channel 225 may have a hollow cylindrical shape or a cup shape. The channel 225 may include polysilicon or crystalline silicon formed of a single crystal, and may include an impurity region doped with, for example, a p-type impurity such as boron.

A plurality of channels 225 may be arranged in a second direction D2 (eg, an X-axis direction) to form channel rows, and a plurality of channel rows may be arranged in a third direction D3 (eg, a Y-axis direction). In addition, the plurality of channels 225 extend in a first direction (eg, Z-axis direction) substantially perpendicular to the first surface.

A filling layer pattern 230 may be disposed in an inner space of the trench 225 . The filling layer pattern 230 may have a pillar shape or a solid cylindrical shape. The filling layer pattern 230 may include an insulating layer pattern such as silicon oxide.

In some exemplary embodiments of the inventive concept, the channel 225 may have a pillar shape or a solid cylindrical shape, and in this case, the filling layer pattern 230 may be omitted.

The dielectric layer structure 220 may be disposed on the outer sidewall of the trench 225 . The dielectric layer structure 220 may have a cup shape whose central bottom is opened, a straw shape, or a shape substantially similar to a hollow cylindrical shape.

The dielectric layer structure 220 may include, for example, a tunnel insulating layer, a charge storage layer, and a blocking layer, which may be sequentially stacked from the outer sidewall of the channel 225 . The barrier layer may comprise, for example, silicon oxide or a metal oxide such as hafnium oxide or aluminum oxide. The charge storage layer may include, for example, a nitride such as silicon nitride or a metal oxide, and the tunnel insulating layer may include, for example, an oxide such as silicon oxide. For example, the dielectric layer structure 220 may have oxide-nitride-oxide (ONO) layers stacked to form the dielectric layer structure 220 .

The pad 240 may be disposed on the filling layer pattern 230 , the trench 225 and the dielectric layer structure 220 . For example, the filling layer pattern 230 , the trench 225 and the dielectric layer structure 220 may be covered or closed by the pad 240 . The pad 240 may include, for example, polysilicon or crystalline silicon formed of a single crystal. The pad 240 may also include, for example, n-type impurities such as phosphorus (P) or arsenic (As).

As shown in FIG. 2 , a plurality of pads 240 may be arranged in a second direction D2 (eg, an X-axis direction) to form pad rows substantially comparable to channel rows. A plurality of pad rows may be arranged in a third direction D3 (eg, Y-axis direction).

The gate lines 260a-260f may be disposed on the outer sidewall of the dielectric layer structure 220 and may be spaced apart from each other in the first direction D1 (eg, Z-axis direction). In some exemplary embodiments of the inventive concepts, each of the gate lines 260a-260f may surround the channel 225 of at least one channel row and may extend in the second direction D2 (eg, the X-axis direction). For example, as shown in FIGS. 2 and 3, each of the gate lines 260a-260f may surround four channel rows; however, the number of channel rows surrounded by each of the gate lines 260a-260f is not limited thereto.

The gate lines 260a-260f may include, for example, metal and/or its nitride having low resistance. For example, the gate lines 260a-260f may include tungsten (W), tungsten nitride, titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, platinum (Pt), and the like. In some exemplary embodiments of the inventive concepts, the gate lines 260a-260f may have a multi-layer structure including a barrier layer including a metal nitride and a metal layer.

In some exemplary embodiments of the present invention concept, the lowermost gate line 260a (for example, the first one from the base layer 201) can be used as a ground selection line (GSL), and the uppermost gate line 260f (for example, the closest The first upper insulating layer 275) may serve as a string selection line (SSL). The other gate lines 260b, 260c, 260d and 260e between the GSL and the SSL may be used as word lines.

According to an exemplary embodiment of the inventive concept, the GSL, the word line, and the SSL may be formed in a single level, four levels, and a single level, respectively. However, the respective numbers of levels of GSL, word lines, and SSL are not limited thereto. In some exemplary embodiments of the present inventive concept, GSL and SSL can be formed in two levels respectively, word lines can be formed in 2 ⁿ levels, where n is a positive integer, for example, word lines can have 4, 8 or 16 levels. The stacked number of gate lines 260a-260f may be determined in consideration of the degree of integration and circuit design of the memory device.

The insulating interlayers 202a, 202b, 202c, 202d, 202e, 202f, and 202g may be alternately stacked with the gate lines 260a-260f in the first direction D1 (eg, Z-axis direction). The insulating interlayers 202a-202g may include a silicon oxide-based material, such as silicon dioxide (SiO ₂ ), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF). The gate lines 260a-260f may be insulated from each other along the first direction D1 (eg, Z-axis direction) by insulating interlayers 202a-202g.

A first upper insulating layer 275 may be disposed on the uppermost insulating interlayer 202g, the pad 240 and the first upper contact 248a.

A bit line contact 280 may be disposed through the first upper insulating layer 275 to contact the pad 240 . A plurality of bitline contacts 280 may be formed in an array defining an arrangement similar to channels 225 or pads 240 .

A bit line 285 may be disposed on the first upper insulating layer 275 and may be electrically connected to the bit line contact 280 . For example, the bitline 285 may extend in a third direction D3 (eg, the Y-axis direction) and may be electrically connected to the plurality of bitline contacts 280 .

In some exemplary embodiments of the present inventive concepts, the mold protection layer 212 may be disposed on a lateral portion of the base layer 201 . The first upper contact 248 a may extend through the mold protection layer 212 , the base layer 201 , and a portion of the second lower insulating layer 160 , and may make contact with the first lower wiring 150 . The first insulating layer pattern 241a may be disposed on a sidewall of the first upper contact 248a.

The first plug 291 may extend through the first upper insulating layer 275 and may make contact with the first upper contact 248a. The first upper wiring 330 may be disposed on the first upper insulating layer 275 (eg, an upper surface of the first upper insulating layer 275 ) and may electrically connect the first plug 291 and the first upper contact 248a, respectively. The second upper insulating layer 290 may be disposed on the first upper insulating layer 275 and may cover the first upper wiring 330 .

In the memory device according to an exemplary embodiment of the inventive concept, the first transistor included in the peripheral circuit region PCR may be used to implement a logic circuit. For example, the peripheral circuit region PCR may include various elements for driving the memory device. In addition, each element may include various logic circuits such as OR gates, AND gates, NOR gates, NAND gates, etc., and each logic circuit may include at least one transistor. For example, a first transistor may be included in a first logic circuit and may be connected to a first input terminal of the first logic circuit. The first transistor may be electrically connected to the first upper wiring 330 through the contacts 145 and 248 a, the first lower wiring 150 and the first plug 291 .

In some exemplary embodiments of the present inventive concepts, the first power wiring 310 , the second power wiring 320 , the first upper wiring 330 and the first connection wiring 332 may be disposed on the same layer on the first upper insulating layer 275 (e.g. set on the same plane in plan view). For example, the first power supply wiring 310 and the second power supply wiring 320 may be disposed on the same layer on the memory cell array. For example, each of the first power supply wiring 310 and the second power supply wiring 320 may extend in the second direction D2 (for example, the X-axis direction). In addition, the first power wiring 310 and the second power wiring 320 may be spaced apart from each other. The first upper wiring 330 may be disposed between the first power wiring 310 and the second power wiring 320 . The first connection wiring 332 may electrically connect the first power wiring 310 and the first upper wiring 330 . Also, the first connection wiring 332 may be replaced with a second connection wiring that connects the second power supply wiring 320 with the first upper wiring 330 .

Thus, in the memory device according to an exemplary embodiment of the present inventive concept, the first upper wiring 330 electrically connected to the first transistor in the peripheral circuit may be disposed on an upper wiring layer (eg, the second wiring layer 50 in FIG. 1 ). )middle. Then, a power option for the first transistor can be efficiently and easily selected based on the first upper wiring 330 by changing the arrangement of the connection wiring connecting the first upper wiring 330 with one of the power supply wirings 310 and 320. choose. For example, the first upper wiring 330 may be electrically connectable to one of the power supply wirings 310 and 320, and one of a first voltage (such as a power supply voltage) and a second voltage (such as a ground voltage) may be selected to be supplied to the first transistors without excessive design changes. Therefore, the design of the memory device can be easily modified, and thus the time for manufacturing the memory device can be reduced even if the design of the memory device is modified.

FIG. 4 is a circuit diagram illustrating an example of a memory cell array that may be disposed in the memory cell region in FIG. 3 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 4, the memory cell array 400 may include a plurality of strings 410 each having a vertical structure. The plurality of strings 410 may be arranged in a second direction D2 (for example, the X-axis direction) to define a series. Furthermore, a plurality of strings may be arranged in a third direction D3 (eg, Y-axis direction) to define a string array. Each string may include a string selection transistor SSTV, a ground selection transistor GSTV, and a plurality of memory cells MC arranged in a first direction D1 (eg, Z-axis direction) and connected in series between the string selection transistor SSTV and the ground selection transistor GSTV. .

The string selection transistor SSTV may be connected to the bit lines BL(1), . . . , BL(m), and the ground selection transistor GSTV may be connected to the common source line CSL. The string selection transistor SSTV can be connected to the string selection lines SSL11, SSL12, . . . , SSLi1, SSLi2, and the ground selection transistor GSTV can be connected to the ground selection lines GSL11, GSL12, . Memory cells in the same layer may be connected to the same one of word lines WL(1), WL(2), . . . WL(n-1), WL(n). Each string selection line and each ground selection line may extend in the second direction D2 (for example, the X-axis direction), and the string selection lines SSL11-SSLi2 and the ground selection lines GSL11-GSLi2 may extend in the third direction D3 (for example, the Y-axis direction). direction) layout. Each word line may extend in the second direction D2 (for example, the X-axis direction), and the word lines WL(1)-WL(n) may extend along the first direction D1 (for example, the Z-axis direction) and the third direction D3 (for example, Y-axis direction) arrangement. Each bit line (eg BL(1)) may extend in a third direction D3 (eg Y-axis direction), and the bit lines BL(1)-BL(m) may extend in a second direction D2 (eg X-axis direction) layout. Memory cell MC can be controlled by voltages on word lines WL(1)-WL(n).

Like a two-dimensional (2D) flash memory device, a vertical or three-dimensional (3D) flash memory device including the memory cell array 400 can perform a program operation and a read operation in units of a page (page), and perform an erase operation in units of a block (block). operate.

Also, according to exemplary embodiments of the inventive concept, two string selection transistors included in a single string may be connected to a single string selection line, and two ground selection transistors included in a single string may be connected to a single ground selection line. According to an exemplary embodiment of the inventive concept, a single string may include one string selection transistor and one ground selection transistor.

5 , 6 , 7 , 8 and 9 are cross-sectional views for describing a process of manufacturing a memory device according to an exemplary embodiment of the inventive concept.

Referring to FIG. 5 , a gate structure 130 and source/drain regions 103 may be disposed on a substrate 100 .

A semiconductor substrate including crystalline silicon formed from a single crystal and/or crystalline germanium formed from a single crystal may be used as the substrate 100 . For example, substrate 100 may be obtained from a silicon wafer.

A gate insulating layer and a gate electrode layer may be disposed on the substrate 100 and then may be etched to form a gate insulating layer pattern 110 and a gate electrode 120 . Accordingly, a gate structure 130 including the gate insulating layer pattern 110 and the gate electrode 120 sequentially stacked on the substrate 100 may be formed.

An ion implantation process may be performed using the gate structure 130 as an implantation mask to form source/drain regions 103 at an upper portion of the substrate 100 adjacent to the gate structure 130 (eg, the upper surface of the substrate 100 ). Accordingly, the source/drain region 103 may be disposed at an upper portion of the substrate 100 adjacent to the gate structure 130 . Accordingly, a first transistor may be defined and disposed on the substrate 100 .

The gate insulating layer may be formed of silicon oxide or metal oxide through, for example, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a spin coating process, an atomic layer deposition (ALD) process, or the like. In addition, the gate insulating layer may be formed through a thermal oxidation process on the top surface of the substrate 100 . The gate electrode layer may include metal, metal nitride, or doped polysilicon by, for example, an ALD process or a sputtering process.

A first lower insulating layer 140 covering the gate structure 130 may be disposed on the substrate 100 . The first lower contact 145 may be disposed through the first lower insulating layer 140 and may make contact with the first transistor by contacting the gate electrode 120 included in the gate structure 130 . In addition, the first lower contact 145 may be in contact with the source/drain region 103 .

A first lower wiring 150 electrically connected to the lower contact 145 may be disposed on the first lower insulating layer 140 . A second lower insulating layer 160 covering the first lower wiring 150 may be disposed on the first lower insulating layer 140 .

The first lower insulating layer 140 and the second lower insulating layer 160 may include an insulating material such as silicon oxide through, for example, a CVD process or a spin coating process. The first lower contact 145 and the first lower wiring 150 may include metal or metal nitride through, for example, an ALD process or a sputtering process.

A single-level lower wiring is shown in FIG. 5 ; however, as will be described with reference to FIGS. 11 and 13 , additional lower insulating layers and lower wiring may be stacked.

The base layer 201 may be disposed on the second lower insulating layer 160 .

In an exemplary embodiment of the present inventive concept, the base layer 201 may include a polysilicon material and may be made through a sputtering process, a CVD process, an ALD process, a physical vapor deposition (PVD) process, or the like. The base layer 201 may include polysilicon doped with, for example, p-type impurities such as boron (B). Here, the base layer 201 may serve as a p-type well.

In an exemplary embodiment of the present inventive concept, an amorphous silicon layer may be disposed on the upper surface of the second lower insulating layer 160 (for example, disposed on the second lower insulating layer 160 in the first direction D1), and then may Heat treatment or laser irradiation is performed to convert the amorphous silicon layer into the base layer 201 including single crystal crystalline silicon. Here, defects in the base layer 201 can be substantially repaired so that the functional characteristics of the base layer 201 as a p-type well can be improved.

In an exemplary embodiment of the present inventive concept, the base layer 201 may be formed through a wafer bonding process. Here, a wafer such as crystalline silicon formed of a single crystal wafer may be attached on the second lower insulating layer 160 . The upper portion of the wafer may be removed or planarized to form base layer 201 .

Referring to FIG. 6, insulating interlayers 202 (eg, 202a-202g) and sacrificial layers 204 (eg, 204a-204f) may be alternately and repeatedly disposed on the base layer 201 in a first direction D1 (eg, Z-axis direction) to form a mold. system structure. For example, the first insulating interlayer 202a can be disposed on the base layer 201, the first sacrificial layer 204a can be disposed on the first insulating interlayer 202a, the second insulating interlayer 202b can be disposed on the first sacrificial layer 204a, and so on.

In an exemplary embodiment of the present inventive concept, the insulating interlayer 202 may include a silicon oxide-based material, such as silicon dioxide, silicon oxycarbide, and/or silicon oxyfluoride. The sacrificial layer 204 may include a material that may have etch selectivity with respect to the insulating interlayer 202 and may be easily removed through a wet etching process. For example, the sacrificial layer 204 may include silicon nitride (SiN) and/or silicon boron nitride (SiBN).

The insulating interlayer 202 and the sacrificial layer 204 can be formed by CVD process, PECVD process, spin coating process, ALD process and so on.

The sacrificial layer 204 may be removed in a subsequent process to provide space for the GSL, word lines and SSL. For example, each of GSL and SSL may be formed in a single level, and word lines may be formed in 4 levels. In this example, as shown in FIG. 6, the sacrificial layer 204 may be formed in 6 levels, and the insulating interlayer 202 may be formed in 7 levels. However, the stacked numbers of GSLs, SSLs, and word lines may not be limited to the examples provided here.

Referring to FIG. 7 , lateral portions of the molded structure may be removed, and an insulating layer covering the molded structure may be disposed on the base layer 201 . In addition, to form the mold protection layer 212, the upper portion of the insulating layer may be planarized until the uppermost insulating interlayer 202g is exposed.

Referring to FIG. 8, channel holes may be disposed through the mold structure, and a dielectric layer structure 220, a channel 225, and a filling layer pattern 230 may be disposed in each of the channel holes. A pad 240 covering the channel hole may be disposed on the dielectric layer structure 220 , the channel 225 and the filling layer pattern 230 .

A first upper contact 248a may be formed. For example, a portion of the mold protection layer 212, the base layer 201, and the second lower insulating layer 160 may be etched to form a first contact hole through which the top surface of the first lower wiring 150 is exposed. The first insulating layer pattern 241a may be disposed on a sidewall of the first contact hole. Then, a first upper contact 248a may be formed to fill the remaining portion of the first contact hole.

Upper gridline cutting regions (eg, element 250 in FIG. 15 ) and gridline cutting regions (eg, element 256 in FIG. 15 ) may be formed. The sacrificial layer 204 exposed by the gate line cut region may be removed, and the gate lines 260 a - 260 f may be disposed at spaces from which the sacrificial layer 204 is removed.

Referring to FIG. 9, a first upper insulating layer 275 may be disposed on the uppermost insulating interlayer 202g, the pad 240, and the first upper contact 248a. The first upper insulating layer 275 may be formed of, for example, silicon oxide through a CVD process.

The first plug 291 and the bit line contact 280 may be disposed through the first upper insulating layer 275 and may make contact with the first upper contact 248 a and the pad 240 , respectively.

A bit line 285 may be disposed on the first upper insulating layer 275 and may be electrically connected to the bit line contact 280 . The bit line 285 may extend in a third direction D3 (eg, the Y-axis direction) and may be electrically connected to the plurality of bit line contacts 280 .

The first upper wiring 330 may be electrically connected to the first plug 291 . In addition, the first upper wiring 330 may be disposed on the first upper insulating layer 275 . The first power wiring 310 , the second power wiring 320 and the first connection wiring 332 may also be disposed on the first upper insulating layer 275 . The first upper wiring 330 may be electrically connectable to one of the first power wiring 310 and the second power wiring 320 . The first transistor including the gate structure 130 and the source/drain region 103 may receive the first voltage and the second voltage through the first upper wiring 330 (which is electrically connected to one of the first power wiring 310 and the second power wiring 320). One of the voltages (such as one of the supply voltage and the ground voltage).

For example, an upper conductive layer may be disposed on the first upper insulating layer 275 using metal or metal nitride, and then may be patterned to form bit lines 285 and wirings 310 , 320 , 330 and 332 . The bit line 285 and the wirings 310, 320, 330, and 332 may be provided through substantially the same etching process.

A second upper insulating layer 290 covering the bit line 285 and the wirings 310 , 320 , 330 and 332 may be disposed on the first upper insulating layer 275 .

5 , 6 , 7 , 8 , and 9 illustrate processes in which the wirings 310 , 320 , 330 , and 332 are formed after forming the memory cell array; however, the process order is not particularly limited here. For example, a process for a peripheral circuit region PCR may be performed, wirings 310, 320, 330, and 332 may be formed, and then a process for a memory cell region MCR may be performed.

FIG. 10 is a top view of a memory device according to an exemplary embodiment of the inventive concept. FIG. 11 is a cross-sectional view taken along line II' of FIG. 10 according to an exemplary embodiment of the present inventive concept.

Referring to FIG. 10 and FIG. 11 , the memory device may include a peripheral circuit region PCR and a memory cell region MCR, the peripheral circuit region PCR includes a peripheral circuit structure disposed on the substrate 100, and the memory cell region MCR includes memory cells disposed on the peripheral circuit structure. cell structure.

10 and FIG. 11 may be substantially the same as the memory device in FIG. 2 and FIG. 3, except that the memory device in FIG. 10 and FIG. The element connecting the second transistor to the second wiring 340 and the lower wiring layer (for example, the first wiring layer 30 in FIG. 1 ) in the memory device of FIGS. 10 and 11 are implemented with a plurality of layers.

The peripheral circuit structure may, for example, include gate structures 130 and 132, source/drain regions 103 and 104, insulating layers 140, 160, 162 and 164, contacts 145, 147a, 147b and 147c, wiring 150 disposed on the substrate 100. , 152a, 152b and 152c etc.

A gate structure 132 of a transistor (eg, a second transistor) may include a gate insulating layer pattern 112 and a gate electrode 122 stacked on the substrate 100 . The source/drain regions 104 may include n-type or p-type impurities. A transistor (eg, a second transistor) including a gate structure 132 and a source/drain region 104 may be provided and defined on the substrate 100 .

A first lower insulating layer 140 may be disposed on the substrate 100 to cover structures such as transistors (eg, first and second transistors). The first lower contact 145 may extend through a portion of the first lower insulating layer 140 and may be electrically connected to the gate electrode 120 of the gate structure 130 .

The first lower wiring 150 may be disposed on the first lower insulating layer 140 and may be electrically connected to the first lower contact 145 .

The second lower insulating layer 160 may be disposed on the first lower insulating layer 140 to cover the lower wirings 150 and 152a. A third lower insulating layer 162 may be disposed on the second lower insulating layer 160 to cover the lower wiring 152b. A fourth lower insulating layer 164 may be disposed on the third lower insulating pattern 162 to cover the lower wiring 152c. The gate electrode 122 may be electrically connected to lower wirings 152a, 152b, and 152c through lower contacts 147a, 147b, and 147c, respectively. The connection between the lower wiring and the lower contact may vary according to the routing of the signal line.

The memory cell structure may include a base layer 201, a channel 225, gate lines 260a-260f, a bit line 285, insulating layers 275 and 290, a contact 248a, which may be disposed on a lower wiring layer (for example, disposed on a fourth lower insulating layer 164). and 248b and wires 310, 320, 330, 332, 340, and 342, etc.

Similar to the first upper contact 248 a , the second upper contact 248 b may extend through the mold protection layer 212 , the base layer 201 , and a portion of the fourth lower insulating layer 164 . However, the difference between the contacts 248a and 248b is that the second upper contact 248b may be in contact with the lower wiring 152c. Similar to how the first insulating layer pattern 241a may be disposed with respect to the first upper contact 248a, the second insulating layer pattern 241b may be disposed on a sidewall of the second upper contact 248b.

Similar to the first plug 291, the second plug 293 may extend through the first upper insulating layer 275 and may make contact with the second upper contact 248b. The second upper wiring 340 may be disposed on the first upper insulating layer 275 to electrically connect the second plug 293 and the second upper contact 248b, respectively.

The second transistor may be electrically connected to the second upper wiring 340 through the contacts 147 a , 147 b , 147 c and 248 b , the lower wirings 152 a , 152 b and 152 c , and the second plug 293 .

In an exemplary embodiment of the present inventive concept, the wirings 310, 320, 330, 332, 340, and 342 may be disposed on the same layer on the first upper insulating layer 275 (for example, disposed on the same plane in plan view) . For example, each of the first power wiring 310 and the second power wiring 320 may extend in the second direction D2 (eg, the X-axis direction), and the first power wiring 310 and the second power wiring 320 may be spaced apart from each other. The first upper wiring 330 and the second upper wiring 340 may be arranged between the first power wiring 310 and the second power wiring 320 . The first connection wiring 332 may electrically connect the first power wiring 310 and the first upper wiring 330 . The second connection wiring 342 may electrically connect the second power wiring 320 and the second upper wiring 340 . Like the first upper wiring 330 , the second upper wiring 340 may be one of the power wirings 310 and 320 electrically connectable. Then, a power supply option for the second transistor can be efficiently and easily selected based on the second upper wiring 340 by changing the arrangement of the connection wiring connecting the second upper wiring 340 with one of the power supply wirings 310 and 320 .

FIG. 12 is a top view of a memory device according to an exemplary embodiment of the inventive concept. FIG. 13 is a cross-sectional view taken along line II-II' of FIG. 12 according to an exemplary embodiment of the present inventive concept.

Referring to FIG. 12 and FIG. 13 , the memory device may include a peripheral circuit region PCR and a memory cell region MCR, the peripheral circuit region PCR includes a peripheral circuit structure disposed on the substrate 100, and the memory cell region MCR includes a memory cell disposed on the peripheral circuit structure. cell structure.

The memory device of FIG. 12 and FIG. 13 may be substantially the same as the memory device of FIG. 2 and FIG. 3, except that the memory device of FIG. 12 and FIG. The connection wiring 362 and the elements for connecting the third transistor to the third wiring 360 and the lower wiring layer (for example, the first wiring layer) in the memory device of FIGS. 12 and 13 are realized with a plurality of layers.

Similar to the first power supply wiring 310, the third power supply wiring 350 may supply a first voltage which may be a power supply voltage.

The peripheral circuit structure may include, for example, gate structures 130 and 134, source/drain regions 103 and 105, insulating layers 140, 160, 162 and 164, contacts 145, 149a, 149b and 149c, wiring 150, 154a, 154b and 154c, etc.

A gate structure 134 of a transistor (eg, a third transistor) may include a gate insulating layer pattern 114 and a gate electrode 124 stacked on the substrate 100 . The source/drain regions 105 may include n-type or p-type impurities. A transistor (eg, a third transistor) including a gate structure 134 and a source/drain region 105 may be provided and defined on the substrate 100 .

A first lower insulating layer 140 may be disposed on the substrate 100 to cover structures such as transistors (eg, third transistors). The first lower contact 145 may extend through a portion of the first lower insulating layer 140 and may be electrically connected to the gate electrode 120 of the gate structure 130 .

The first lower wiring 150 may be disposed on the first lower insulating layer 140 and may be electrically connected to the first lower contact 145 .

The second lower insulating layer 160 may be disposed on the first lower insulating layer 140 to cover the lower wirings 150 and 154a. A third lower insulating layer 162 may be disposed on the second lower insulating layer 160 to cover the lower wiring 154b. A fourth lower insulating layer 164 may be disposed on the third lower insulating pattern 162 to cover the lower wiring 154c. The gate electrode 124 may be electrically connected to lower wirings 154a, 154b, and 154c through lower contacts 149a, 149b, and 149c, respectively. The connection between the lower wiring and the lower contact may vary according to the wiring of the signal line.

The memory cell structure may include a base layer 201, a channel 225, gate lines 260a-260f, a bit line 285, insulating layers 275 and 290, a contact 248a, which may be disposed on a lower wiring layer (for example, disposed on a fourth lower insulating layer 164). and 248c, and wires 310, 320, 330, 332, 350, 360, and 362, and the like.

Similar to the first upper contact 248 a , the third upper contact 248 c may extend through the mold protection layer 212 , the base layer 201 , and a portion of the fourth lower insulating layer 164 . However, the difference between the contacts 248a and 248c is that the second upper contact 248c may be in contact with the lower wiring 154c. Similar to how the first insulating layer pattern 241a may be disposed with respect to the first upper contact 248a, the third insulating layer pattern 241c may be disposed on a sidewall of the third upper contact 248c.

Similar to the first plug 291, the third plug 295 may extend through the first upper insulating layer 275 and may make contact with the third upper contact 248c. The third upper wiring 360 may be disposed on the first upper insulating layer 275 to electrically connect the third plug 295 and the third upper contact 248c, respectively.

The third transistor may be electrically connected to the third upper wiring 360 through the contacts 149 a , 149 b , 149 c and 248 c , the lower wirings 154 a , 154 b and 154 c , and the third plug 295 .

In an exemplary embodiment of the present inventive concept, the wirings 310, 320, 330, 332, 350, 360, and 362 may be disposed on the same layer on the first upper insulating layer 275 (for example, disposed on the same plane in plan view). superior). For example, each of the first power supply wiring 310, the second power supply wiring 320, and the third power supply wiring 350 may extend in the second direction D2 (for example, the X-axis direction), and the first power supply wiring 310, the second power supply wiring 320 and the third power wiring 350 may be spaced apart from each other. The first upper wiring 330 may be disposed between the first power wiring 310 and the second power wiring 320 . The third upper wiring 360 may be disposed between the second power wiring 320 and the third power wiring 350 . The first connection wiring 332 may electrically connect the first power wiring 310 and the first upper wiring 330 . The third connection wiring 362 may electrically connect the third power wiring 350 and the third upper wiring 360 . Like the first upper wiring 330 , the third upper wiring 360 may be electrically connectable to one of the power wirings 320 and 350 . Then, a power supply option for the third transistor can be efficiently and easily selected based on the third upper wiring 360 by changing the arrangement of the connection wiring connecting the third upper wiring 360 with one of the power supply wirings 320 and 350 .

Although FIGS. 2 , 10 , and 12 show examples of upper wiring and power wiring, the number, arrangement, and configuration of the upper wiring and power wiring are not limited thereto. In addition, the upper wiring and the power supply wiring shown are included in an upper wiring layer (for example, a second wiring layer) on the memory cell array and are electrically connected to transistors in the peripheral circuit. For example, the upper wiring layer of the memory device may include any number of power supply wirings extending in any direction and spaced apart from each other, and elements (such as transistors) electrically connected to peripheral circuits and configured to be electrically connectable between the power supply wirings. Any number of upper wires for one.

FIG. 14 is a top view of a memory device according to an exemplary embodiment of the inventive concepts. FIG. 15 is a cross-sectional view taken along line III-III' of FIG. 14 according to an exemplary embodiment of the present inventive concept.

14 and 15, the memory device may include a peripheral circuit region PCR and a memory cell region MCR, the peripheral circuit region PCR includes a peripheral circuit structure disposed on the substrate 100, and the memory cell region MCR includes a memory cell disposed on the peripheral circuit structure cell structure.

The memory devices of FIGS. 14 and 15 may be substantially the same as the memory devices of FIGS. 2 and 3, except that the base layer in the memory devices of FIGS. 14 and 15 is physically divided into a plurality of base layer patterns and the channels 225 and The arrangement of the pads 240 is changed in the memory devices of FIGS. 14 and 15 .

Some elements of the memory device are not shown in FIG. 14 for clarity and conciseness of description. For example, FIG. 14 shows base layer patterns 201a, 201b, and 201c, separation layer patterns 206, impurity regions 266, pads 240, mold protection layer 212, first power supply wiring 310, second power supply wiring 320, first wiring 330 and the first connection wiring 332, other elements than the above are omitted.

The memory cell structure may include a first base layer pattern 201a, a second base layer pattern 201b, and a third base layer pattern 201c, a channel 225, a gate, and The lines 260a, 260b, 260c, 260d, 260e and 260f, the bit line 285, the insulating layers 275 and 290, the wirings 310, 320, 330 and 332, and the like.

The separation layer pattern 206 may extend in the second direction D2 (eg, the X-axis direction), and the plurality of separation layer patterns 206 may be arranged along the third direction D3 (eg, the Y-axis direction). Accordingly, the base layer may be physically divided into first to third base layer patterns 201a-201c. 14 and 15 illustrate three base layer patterns 201a-201c; however, the number of base layer patterns is not limited thereto. The separation layer pattern 206 may include an insulating layer pattern, such as silicon oxide.

In an exemplary embodiment of the present inventive concept, the lowermost insulating interlayer 202 a may be substantially integrated or integrated with the separation layer pattern 206 . In an exemplary embodiment of the present inventive concept, the formation of the spacer layer may be omitted, and the lowermost insulating interlayer 202a may fill the opening corresponding to the spacer layer pattern 206 and cover the base layer patterns 201a-201c.

The base layer patterns 201a-201c may include, for example, polysilicon or crystalline silicon formed of a single crystal. In an exemplary embodiment of the inventive concept, the base layer patterns 201a-201c may further include p-type impurities such as boron (B). In this exemplary embodiment, the base layer patterns 201a-201c may serve as p-type wells.

The channel 225 may be disposed on the base layer patterns 201a-201c, and may extend from the top surfaces of the base layer patterns 201a-201c in the first direction D1 (eg, the Z-axis direction). In an exemplary embodiment of the present inventive concept, a plurality of channels 225 may be arranged in the second direction D2 (for example, the X-axis direction) to form a channel row, and the channels 225 included in adjacent channel rows may be formed in Arranged in a zigzag manner facing each other. Accordingly, the density of the channels 225 in a unit area of the base layer patterns 201a-201c may be increased.

The gate line cutting region 256 may be disposed along the first direction D1 (eg, the Z-axis direction) through the gate lines 260 a - 260 f and the insulating interlayers 202 a - 202 g. The gate line cutting area 256 may have a groove shape or a ditch shape extending in the second direction D2 (eg, the X-axis direction).

A gate line cutting pattern 270 extending in the second direction D2 (eg, the X-axis direction) may be disposed on the impurity region 266 . A plurality of impurity regions 266 and a plurality of gate line cutting patterns 270 may be arranged along a third direction D3 (eg, a Y-axis direction). In an exemplary embodiment of the inventive concept, the impurity region 266 may include n-type impurities such as phosphorus (P) or arsenic (As). The gate line cutting pattern 270 may include an insulating layer pattern, such as silicon oxide. A metal silicide pattern such as a cobalt silicide pattern and/or a nickel silicide pattern may be further disposed on the impurity region 266 .

In an exemplary embodiment of the inventive concept, one of the impurity regions 266 and one of the gate line cutting patterns 270 may be provided for each of the base layer patterns 201a-201c. As shown in FIG. 15, for example, the gate line cutting area 256 may be disposed in the central area of the second base layer pattern 201b. The impurity region 266 may be disposed in an upper portion of the second base layer pattern 201b exposed by the gate line cut region 256, and the gate line cut pattern 270 filling the gate line cut region 256 may be in the first direction D1 (eg, the Z-axis direction). on the impurity region 266 .

In an exemplary embodiment of the inventive concept, the cell blocks sharing the gate lines 260 a - 260 f may be defined by the gate line cutting pattern 270 . The unit block may be divided into sub-unit blocks by the separation layer pattern 206 . Therefore, the size or size of a single block can be reduced, so that segmented operational control can be realized. For example, the unit block may be further divided or divided by the separation layer pattern 206, and thus signal interference or disturbance occurring when the size or size of the unit block becomes increased may be prevented. Therefore, the operational reliability of the memory device can be improved.

An upper gate line cutting pattern 252 may be disposed in the upper gate line cutting region 250 . The upper gate line cutting pattern 252 may include an insulating material such as silicon oxide.

In an exemplary embodiment of the present inventive concept, an upper gate line cut region 250 or an upper gate line cut pattern 252 may be provided for separation of SSLs in each cell block. In this exemplary embodiment of the present inventive concept, the upper gate line cutting region 250 or the upper gate line cutting pattern 252 may extend through the uppermost insulating interlayer 202g and the SSL 260f, and may partially extend through the uppermost insulating interlayer 202g and the SSL 260f. The lower insulating interlayer 202f.

In an exemplary embodiment of the inventive concept, the upper wires 310, 320, 330, and 332 may correspond to each arrangement of the base layer patterns 201a-201c.

In an exemplary embodiment of the inventive concept, the number, arrangement, and configuration of upper wirings and power wirings included in an upper wiring layer (for example, the second wiring layer 50 of FIG. 1 ) of the memory device of FIGS. 14 and 15 may be Change. In an exemplary embodiment of the inventive concept, the lower wiring layer (eg, the first wiring layer 30 in FIG. 1 ) of the memory device of FIGS. 14 and 15 may be implemented with a plurality of layers.

FIG. 16 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept.

Referring to FIG. 16 , the memory device 500 may include a memory cell array 510 , an address decoder 520 , a read/write unit 530 , a data input/output (I/O) unit 540 , a voltage generation unit 550 and control logic 560 .

In the memory device 500 according to the exemplary embodiment of the inventive concept, the memory cell array 510 may be disposed in the memory cell region MCR in FIG. The (I/O) unit 540 , the voltage generating unit 550 and the control logic 560 may be disposed in the peripheral circuit region PCR in FIG. 1 .

The memory cell array 510 may be connected to an address decoder 520 through a word line WL and a selection line. For example, the selection lines may include a string selection line SSL and a ground selection line GSL. The memory cell array 510 may be connected to a read/write unit 530 through a bit line BL.

The memory cell array 510 may include a plurality of memory cells. For example, the memory cell array 510 may include memory cells arranged in a row direction and a column direction. For example, memory cell array 510 may include a plurality of memory cells, each storing one or more bits of data. For example, the memory cell array 510 may have a vertical NAND flash memory structure as shown in FIG. 4 .

The address decoder 520 may be connected to the memory cell array 510 through a word line WL, a string selection line SSL, and a ground selection line GSL. Address decoder 520 may operate in response to control of control logic 560 . The address decoder 520 may receive an address ADDR from an external device such as a memory controller.

The address decoder 520 may decode a row address in the received address ADDR. The address decoder 520 may select at least one word line corresponding to the decoded row address among the word lines WL. The address decoder 520 may select at least one selection line corresponding to the decoded row address among selection lines including a string selection line SSL and a ground selection line GSL.

The address decoder 520 may transmit various voltages received from the voltage generating unit 550 to selected word lines, unselected word lines, selected selection lines, and unselected selection lines.

The address decoder 520 may decode a column address in the received address ADDR. In addition, the address decoder 520 may transmit the decoded column address DCA to the read and write unit 530 .

In an exemplary embodiment of the inventive concept, the address decoder 520 may include a row decoder decoding a row address, a column decoder decoding a column address, and an address buffer storing a received address ADDR.

The read/write unit 530 may be connected to the memory cell array 510 through the bit line BL, and may be connected to the data I/O unit 540 through the data line DL. The read-write unit 530 may operate in response to the control of the control logic 560 . The read-write unit 530 may receive the decoded column address DCA from the address decoder 520 . Based on the decoded column address DCA, the read/write unit 530 may select at least one bit line among the bit lines BL.

In an exemplary embodiment of the present inventive concept, the read-write unit 530 may receive data from the data I/O unit 540 and may write the received data into the memory cell array 510 . The read-write unit 530 can read data from the memory cell array 510 and transmit the read data to the data I/O unit 540 . The read-write unit 530 can read data from the first storage area of the memory cell array 510 , and can write the read data into the second storage area of the memory cell array 510 . For example, the read-write unit 530 may perform a copy-back operation.

In an exemplary embodiment of the inventive concept, the read and write unit 530 may include components such as a page buffer (or page register) and a column selection circuit. In an exemplary embodiment of the inventive concept, the read and write unit 530 may include components such as a sense amplifier, a write driver, and a column selection circuit.

The data I/O unit 540 may be connected to the read/write unit 530 through a data line DL. The data I/O unit 540 may operate in response to the control of the control logic 560 . The data I/O unit 540 may exchange data DATA with external devices. The data I/O unit 540 can transmit data DATA from an external device to the read/write unit 530 through the data line DL. The data I/O unit 540 may output data DATA transferred from the read/write unit 530 through the data line DL to an external device. In an exemplary embodiment of the inventive concept, the data I/O unit 540 may include components such as a data buffer.

The voltage generating unit 550 is connected to the memory cell array 510 , the address decoder 520 and the control logic 560 . The voltage generation unit 550 may receive power from an external device. In an exemplary embodiment of the inventive concept, the voltage generating unit 550 may receive a power voltage Vcc and a ground voltage Vss from an external device. Based on the control of the control logic 560, the voltage generation unit 550 may generate voltages having various levels from the power supply voltage Vcc and the ground voltage Vss. In an exemplary embodiment of the inventive concept, the voltage generating unit 550 may generate various voltages, such as a high voltage Vpp, a program voltage Vpgm, a pass voltage Vpass, a read voltage Vread, and an erase voltage Vers.

The voltage generated by the voltage generating unit 550 may be supplied to the address decoder 520 and the memory cell array 510 based on the control of the control logic 560 . For example, a program voltage Vpgm and a pass voltage Vpass may be supplied to the address decoder 520 during a program operation. The read voltage Vread may be supplied to the address decoder 520 during a read operation. An erase voltage Vers may be supplied to the memory cell array 510 during an erase operation.

The voltage generated by the voltage generating unit 550 is not limited to the above-mentioned voltage.

The control logic 560 may be connected to the address decoder 520 , the read/write unit 530 and the data I/O unit 540 . The control logic 560 may control general operations of the memory device 500 . The control logic 560 may operate in response to a control signal CTRL transmitted from an external device.

17 and 18 are diagrams illustrating a memory package according to an exemplary embodiment of the inventive concept.

Referring to FIG. 17 , the memory package 700 includes a base substrate 710 and a plurality of memory chips CHP1 , CHP2 and CHP3 stacked on the base substrate 710 .

Each of the memory chips CHP1-CHP3 may include a peripheral circuit region PCR and a memory cell region MCR, and may further include a plurality of I/O pads IOPAD. The peripheral circuit region PCR may include a semiconductor substrate, a peripheral circuit disposed on a first surface (eg, a top surface) of the semiconductor substrate, and a first wiring layer disposed on the peripheral circuit. Furthermore, the peripheral circuit may include at least one transistor. The memory cell region MCR may include a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer on the memory cell array. The plurality of I/O pads IOPAD may be disposed on the second wiring layer.

Each of the memory chips CHP1-CHP3 may be implemented with a memory device according to an exemplary embodiment of the inventive concept. For example, a second wiring layer (for example, an upper wiring layer) in each of the memory chips CHP1-CHP3 may include at least one upper wiring electrically connected to at least one transistor in the peripheral circuit. The at least one upper wiring may be electrically connectable to one of the power supply wirings, whereby a power supply option for the at least one transistor may be enabled based on the at least one upper wiring by changing a connection between one of the power supply wirings and the upper wiring. Choose easily and easily.

In an exemplary embodiment of the inventive concept, the memory chips CHP1 - CHP3 may be stacked on the base substrate 710 such that a surface on which the plurality of I/O pads IOPAD may be disposed faces upward. For example, the memory chips CHP1-CHP3 may be stacked in a downside-down state such that the second surface (eg, bottom surface) of the semiconductor substrate 730 of each memory chip faces down. In other words, the memory cell region MCR may be located on the peripheral circuit region PCR with respect to each of the memory chips CHP1-CHP3.

In an exemplary embodiment of the inventive concept, the plurality of I/O pads IOPAD may be arranged near one side of the semiconductor substrate with respect to each of the memory chips CHP1-CHP3. Thus, the memory chips CHP1-CHP3 can be stacked in steps, that is, stacked in a step shape, so that the plurality of I/O pads IOPAD of each memory chip can be exposed (for example, the plurality of I/O pads IOPAD may be exposed on the edge of each step). In such a stacked state, the memory chips CHP1-CHP3 may be electrically connected to the base substrate 710 through a plurality of bonding wires BW.

The stacked memory chips CHP1-CHP3 and the bonding wires BW may be fixed by a sealing member 740, and an adhesive member 730 may be interposed between the base substrate 710 and the memory chips CHP1-CHP3. Conductive bumps 720 may be disposed on the bottom surface of the base substrate 710 for electrical connection to external devices.

Referring to FIG. 18 , a memory package 700 a includes a base substrate 710 and a plurality of memory chips CHP1 ′, CHP2 ′, and CHP3 ′ stacked on the base substrate 710 .

The memory package 700a of FIG. 18 may be substantially the same as the memory package 700 of FIG. 17, except that the arrangement of the plurality of I/O pads IOPAD' and the stacked structure of the memory chips CHP1'-CHP3' are changed in the memory package 700a of FIG. outside.

Each of the memory chips CHP1'-CHP3' may include a peripheral circuit region PCR and a memory cell region MCR, and may further include the plurality of I/O pads IOPAD'. The peripheral circuit region PCR may include a semiconductor substrate, a peripheral circuit disposed on a first surface (eg, a top surface or an upper surface) of the semiconductor substrate, and a first wiring layer disposed on the peripheral circuit. The peripheral circuit may include at least one transistor. The memory cell region MCR may include a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer on the memory cell array.

The plurality of I/O pads IOPAD' may be disposed on a second surface (eg, a bottom surface) of the semiconductor substrate opposite to the first surface of the semiconductor substrate. The I/O pad IOPAD′ may cover a through-substrate via TSV disposed in the peripheral circuit region PCR. Then, the I/O pad IOPAD' may be electrically connected to at least one lower wiring included in the first wiring layer (eg, lower wiring layer) of the peripheral circuit region PCR.

The plurality of I/O pads IOPAD' may vertically overlap a portion of the memory cell region MCR in which the memory cell array is disposed, with respect to each of the memory chips CHP1'-CHP3'.

In some exemplary embodiments of the inventive concepts, the memory chips CHP1 ′-CHP3 ′ may be stacked on the base substrate 710 such that a surface on which the plurality of I/O pads IOPAD′ may be disposed faces upward. For example, the memory chips CHP1'-CHP3' may be stacked in an inverted state such that the second surface (eg, bottom surface) of the semiconductor substrate of each memory chip faces upward. In other words, the memory cell region MCR may be located under the peripheral circuit region PCR with respect to each of the memory chips CHP1'-CHP3'.

FIG. 19 is a block diagram illustrating a solid state disk or a solid state drive (SSD) according to an exemplary embodiment of the inventive concept.

Referring to FIG. 19 , an SSD 1000 may include a plurality of nonvolatile memory devices 1100 and an SSD controller 1200 .

Alternatively, the nonvolatile memory device 1100 may be supplied with an external high voltage VPP. Each of the nonvolatile memory devices 1100 may include the above-mentioned vertical NAND flash memory device. The nonvolatile memory device 1100 may have a COP structure according to an exemplary embodiment of the inventive concept and an upper wiring layer including an upper wiring, as described with reference to FIGS. 1 to 18 .

The SSD controller 1200 may be connected to the nonvolatile memory device 1100 through a plurality of channels CH1, CH2, CH3 . . . CHi. SSD controller 1200 may include one or more processors 1210 , buffer memory 1220 , error correction code (ECC) block 1230 , host interface 1250 and nonvolatile memory interface 1260 .

The buffer memory 1220 may store data for driving the SSD controller 1200 . Cache memory 1220 may include multiple memory lines each storing data or instructions. Although FIG. 19 illustrates an exemplary embodiment of the inventive concept in which the cache memory 1220 is included in the SSD controller 1200, the inventive concept is not limited thereto. For example, the cache memory 1220 may be located outside the SSD controller 1200 .

The ECC block 1230 may calculate an error correction code value of data and may be programmed during a program operation, and may correct errors of read data using the error correction code value during a read operation. In a data recovery operation, the ECC block 1230 may correct errors of data recovered from the nonvolatile memory device 1100 . In addition, a code memory may also be included to store code data required to drive the SSD controller 1200 . Code memory can be implemented by non-volatile memory devices.

The host interface 1250 may provide an interface with external devices. A non-volatile memory (NVM) interface 1260 may provide an interface with the non-volatile memory device 1100 .

FIG. 20 is a block diagram illustrating an embedded multimedia card (eMMC) according to an exemplary embodiment of the inventive concept.

Referring to FIG. 20 , an eMMC 2000 may include one or more NAND flash memory devices 2100 and a controller 2200 .

As described with reference to FIGS. 1 to 18 , according to an exemplary embodiment of the inventive concept, the NAND flash memory device 2100 may have a COP structure and an upper wiring layer including an upper wiring.

The controller 2200 may be connected with the NAND flash memory device 2100 via a plurality of channels. The controller 2200 may include one or more controller cores 2210 , a host interface 2250 and a NAND interface 2260 . The controller core 2210 can control the entire operation of the eMMC2000. The host interface 2250 may provide an interface between the controller 2200 and the host 2010 . The NAND interface 2260 may provide an interface between the NAND flash memory device 2100 and the controller 2200 .

In an exemplary embodiment of the inventive concept, the host interface 2250 may be a parallel interface (eg, an MMC interface). In other exemplary embodiments of the present inventive concepts, the host interface 2250 may be a serial interface (eg, UHS-II, UFS, etc.).

The eMMC 2000 may receive power supply voltages VCC and VCCq from the host 2010 . For example, a power supply voltage VCC (eg, about 3.3V) may be supplied to the NAND flash memory device 2100 and the NAND interface 2260 , and a power supply voltage VCCq (eg, about 1.8V/3.3V) may be supplied to the controller 2200 . In an exemplary embodiment of the inventive concept, optionally, the eMMC 2000 may be supplied with an external high voltage VPP. Also, optionally, an external high voltage VPP may be supplied to the NAND flash memory device 2100 .

FIG. 21 is a block diagram illustrating a universal flash memory (UFS) according to an exemplary embodiment mode of the inventive concept.

Referring to FIG. 21 , a UFS system 3000 may include a UFS host 3100 , UFS devices 3200 and 3300 , an embedded UFS device 3400 , and a removable UFS card 3500 .

UFS host 3100 may be an application processor of a mobile device. Each of the UFS host 3100, the UFS devices 3200 and 3300, the embedded UFS device 3400, and the removable UFS card 3500 may communicate with external devices through the UFS protocol. At least one of the UFS devices 3200 and 3300, the embedded UFS device 3400, and the removable UFS card 3500 may be implemented by a nonvolatile memory device. As described with reference to FIGS. 1 to 18 , according to an exemplary embodiment of the inventive concept, a nonvolatile memory device may have a COP structure and an upper wiring layer including an upper wiring.

Embedded UFS device 3400 and removable UFS card 3500 may communicate using a protocol other than the UFS protocol. The UFS host 3100 and the removable UFS card 3500 can communicate through various card protocols (eg, UFD, MMC, Secure Digital (SD), mini SD, micro SD, etc.).

FIG. 22 is a block diagram illustrating a mobile device according to an exemplary embodiment of the inventive concept.

Referring to FIG. 22 , a mobile device 4000 may include an application processor 4100 , a communication module 4200 , a display/touch module 4300 , a storage device 4400 , and a mobile random access memory (RAM) (eg, buffer RAM) 4500 .

The application processor 4100 may control operations of the mobile device 4000 . The communication module 4200 may be implemented to perform wireless or wired communication with external devices. The display/touch module 4300 may be implemented to display data processed by the application processor 4100 or to receive data through a touch panel. The storage device 4400 may be implemented to store user data. The mobile RAM (eg buffer RAM) 4500 may temporarily store data for processing operations of the mobile device 4000 .

In an exemplary embodiment of the inventive concept, the storage device 4400 may be, for example, eMMC, SSD, UFS device, or the like. The memory device 4400 may include a nonvolatile memory device. As described with reference to FIGS. 1 to 18 , according to an exemplary embodiment of the inventive concept, a nonvolatile memory device may have a COP structure and an upper wiring layer including an upper wiring.

A memory device or a memory device according to an exemplary embodiment of the present inventive concept may be packaged using various package types or package configurations, such as package on package (PoP), ball grid array (BGA), chip scale package (CSP), leaded Plastic chip carrier (PLCC), plastic dual in-line package (PDIP), waffle die package (Die in Waffle Pack), wafer die (Die in Wafer form), chip on board (COB), Ceramic Dual Inline Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Narrow Pitch Small Outline Package (SSOP), Thin Small Outline Package (TSOP) ), System-in-Package (SIP), Multi-Chip Package (MCP), Wafer-Level Manufacturing Package (WFP), Wafer-Level Processing Stacked Package (WSP), etc.

The present disclosure can be applied to various devices and systems. For example, the present disclosure can be applied to systems such as mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video cameras, personal computers (PCs), server computers, workstations, laptop computers , digital TV, set-top boxes, portable game consoles, navigation systems, etc.

The foregoing is a description of exemplary embodiments of the present inventive concept and should not be construed as limiting the same. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. Accordingly, it is to be understood that the foregoing is a description of various exemplary embodiments, and that it is not to be construed as limited to the particular exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as additional exemplary Embodiments are intended to be included within the scope of the claims.

Claims (19)

1. A storage device, comprising: Substrate; peripheral circuitry disposed on the first surface of the substrate, wherein the peripheral circuitry includes a first transistor; a first wiring layer disposed on the peripheral circuit; a base layer disposed on the first wiring layer; an array of memory cells disposed on the base layer; and A second wiring layer disposed on the memory cell array, wherein the second wiring layer includes: a first power wiring configured to supply a first voltage; a second power supply wiring configured to supply a second voltage; a first wiring electrically connected to the first transistor, wherein the first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring; and a first connection wiring electrically connecting the first wiring to the first power supply wiring or the second power supply wiring, wherein each of the first power supply wiring and the second power supply wiring extends in a first direction, and the first power supply wiring and the second power supply wiring are spaced apart from each other, wherein the first wiring is provided between the first power supply wiring and the second power supply wiring, and in a case where the first wiring is electrically connected to the first power supply wiring through the first connection wiring, the first voltage is supplied to the first transistor through the first wiring, and In a case where the first wiring is electrically connected to the second power supply wiring through the first connection wiring, the second voltage is supplied to the first transistor through the first wiring. 2. The memory device according to claim 1, wherein the first power supply wiring and the second power supply wiring, the first wiring and the first connection wiring are arranged on the same plane. 3. The memory device according to claim 1, wherein the first wiring is electrically connected to a gate electrode of the first transistor. 4. The memory device of claim 3, further comprising: The first contact and the second contact are provided through a part of the insulating layer included in the first wiring layer. 5. The memory device according to claim 4, wherein the first contact electrically connects the gate electrode of the first transistor with a second wiring included in the first wiring layer, Wherein the second contact electrically connects the first wiring and the second wiring. 6. The memory device of claim 1, wherein the peripheral circuit further comprises a second transistor, The second wiring layer further includes a second wiring electrically connected to the second transistor, wherein the second wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring. 7. The memory device of claim 1, wherein the peripheral circuit further comprises a second transistor, Wherein the second wiring layer also includes: a third power wiring configured to supply the first voltage; a second wiring electrically connected to the second transistor, the second wiring being configured to be electrically connectable to the second power supply wiring or the third power supply wiring; and A second connection wiring electrically connects the second wiring to the second power supply wiring or the third power supply wiring. 8. The memory device according to claim 7, wherein each of the first power supply wiring, the second power supply wiring, and the third power supply wiring extends in a first direction, and the first power supply wiring , the second power supply wiring and the third power supply wiring are spaced apart from each other, The second wiring is arranged between the second power supply wiring and the third power supply wiring. 9. The memory device of claim 1, wherein the first voltage is a power supply voltage, and the second voltage is a ground voltage. 10. The memory device of claim 1, wherein the base layer comprises polysilicon or single crystal silicon. 11. The memory device of claim 10, wherein the base layer is divided into a plurality of base layer patterns, and each of the plurality of base layer patterns functions as a p-type well. 12. The memory device of claim 1, wherein the array of memory cells comprises a plurality of vertical NAND flash memory cells. 13. The memory device of claim 1, wherein the memory cell array comprises: a plurality of channels extending in a first direction perpendicular to the first surface; and A plurality of gate lines surrounds the outer sidewall of the trench, the plurality of gate lines are stacked in the first direction and spaced apart from each other. 14. A memory package comprising: base substrate; and a plurality of memory chips stacked on the base substrate, each of the plurality of memory chips comprising: Substrate; peripheral circuitry disposed on the first surface of the substrate, wherein the peripheral circuitry includes a first transistor; a first wiring layer disposed on the peripheral circuit; a base layer disposed on the first wiring layer; an array of memory cells disposed on the base layer; and A second wiring layer disposed on the memory cell array, wherein the second wiring layer includes: a first power wiring configured to supply a first voltage; a second power supply wiring configured to supply a second voltage; a first wiring electrically connected to the first transistor, wherein the first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring; and a first connection wiring electrically connecting the first wiring to the first power supply wiring or the second power supply wiring, wherein each of the first power supply wiring and the second power supply wiring extends in a first direction, and the first power supply wiring and the second power supply wiring are spaced apart from each other, wherein the first wiring is provided between the first power supply wiring and the second power supply wiring, and in a case where the first wiring is electrically connected to the first power supply wiring through the first connection wiring, the first voltage is supplied to the first transistor through the first wiring, and In a case where the first wiring is electrically connected to the second power supply wiring through the first connection wiring, the second voltage is supplied to the first transistor through the first wiring. 15. A memory device comprising: Substrate; a peripheral circuit disposed on the first surface of the substrate, the peripheral circuit including a first transistor and a second transistor; a lower wiring layer disposed on the peripheral circuit; a base layer disposed on the lower wiring layer; a memory cell array disposed on the base layer, wherein the memory cell array includes a plurality of channels; and The upper wiring layer is arranged on the memory cell array, wherein the upper wiring layer includes: at least two power supply wirings, wherein a first of the at least two power supply wirings is configured to supply a first voltage and a second of the at least two power supply wirings is configured to supply a second voltage; a first wiring electrically connected to the first transistor, wherein the first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring; a second wiring electrically connected to the second transistor, wherein the second wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring; a first connection wiring electrically connecting the first wiring to the first power supply wiring or the second power supply wiring; and second connection wiring electrically connecting the second wiring to the first power supply wiring or the second power supply wiring, wherein each of the first power supply wiring and the second power supply wiring extends in a first direction, and the first power supply wiring and the second power supply wiring are spaced apart from each other, wherein the first wiring and the second wiring are provided between the first power wiring and the second power wiring, In a case where the first wiring is electrically connected to the first power supply wiring through the first connection wiring, the first voltage is supplied to the first transistor through the first wiring, and In a case where the first wiring is electrically connected to the second power supply wiring through the first connection wiring, the second voltage is supplied to the first transistor through the first wiring. 16. The memory device according to claim 15 , wherein the plurality of channels are arranged in the second direction to form at least one channel row, and among the plurality of channels disposed in adjacent channel rows The roads are arranged in a zigzag manner. 17. The memory device of claim 15, wherein the base layer is divided into a plurality of base layer patterns by a plurality of separation layer patterns. 18. The memory device of claim 15, wherein the plurality of channels extend in a first direction perpendicular to the first surface of the substrate. 19. The memory device according to claim 18, wherein the memory cell array comprises a plurality of gate lines surrounding outer sidewalls of the trenches, wherein the plurality of gate lines are stacked in the first direction, mutually spaced apart and shared by the plurality of channels.