CN108346664B - Memory device with cell-on-periphery structure and memory package including same - Google Patents

Memory device with cell-on-periphery structure and memory package including same Download PDF

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CN108346664B
CN108346664B CN201710060999.2A CN201710060999A CN108346664B CN 108346664 B CN108346664 B CN 108346664B CN 201710060999 A CN201710060999 A CN 201710060999A CN 108346664 B CN108346664 B CN 108346664B
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wiring
power supply
layer
disposed
transistor
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CN108346664A (en
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金昶汎
金成勋
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Samsung Electronics Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

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Abstract

The present disclosure provides a memory device having a peripheral on cell structure and a memory package including the same. A memory device includes a substrate and peripheral circuitry disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. The memory device further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power supply wiring configured to supply a first voltage, a second power supply wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to either the first power wiring or the second power wiring.

Description

具有外围上单元结构的存储器件和包括其的存储器封装Memory device with cell-on-periphery structure and memory package including same

技术领域technical field

本发明构思的示例实施方式总体上涉及存储器件,更具体地,涉及具有外围上单元(cell over periphery,COP)结构的存储器件以及包括该存储器件的存储器封装。Example embodiments of inventive concepts relate generally to memory devices, and more particularly, to memory devices having a cell over periphery (COP) structure and memory packages including the same.

背景技术Background technique

垂直存储器件(通常所说的三维(3D)存储器件)是包括重复堆叠在衬底的表面上的多个存储单元的存储器件。这些存储器件能够在非常小的结构内具有非常高的存储容量。例如,在垂直存储器件中,沟道可以从衬底的表面突出或者可以从衬底的表面垂直地延伸,并且围绕垂直沟道的栅线和绝缘层可以被重复地堆叠。A vertical memory device, commonly referred to as a three-dimensional (3D) memory device, is a memory device including a plurality of memory cells repeatedly stacked on a surface of a substrate. These memory devices are capable of very high storage capacities in very small structures. For example, in a vertical memory device, a channel may protrude from a surface of a substrate or may extend vertically from the surface of the substrate, and gate lines and insulating layers surrounding the vertical channel may be repeatedly stacked.

然而,垂直存储器件的尺寸的减小受限制,因为存储器件必须仍然包括接口以将存储器件电连接到外围电路用于与外部设备通信并由外部设备驱动。However, reduction in size of vertical memory devices is limited because the memory devices must still include interfaces to electrically connect the memory devices to peripheral circuits for communicating with and being driven by external devices.

发明内容Contents of the invention

根据本发明构思的示范性实施方式,一种存储器件包括衬底和设置在衬底的第一表面上的外围电路。外围电路包括第一晶体管。存储器件还包括设置在外围电路上的第一布线层、设置在第一布线层上的基底层、设置在基底层上的存储单元阵列、以及设置在存储单元阵列上的第二布线层。第二布线层包括配置为供应第一电压的第一电源布线、配置为供应第二电压的第二电源布线、以及电连接到第一晶体管的第一布线。第一布线配置为可电连接到第一电源布线或第二电源布线。According to an exemplary embodiment of the inventive concept, a memory device includes a substrate and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. The memory device further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power wiring configured to supply a first voltage, a second power wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring.

根据本发明构思的示范性实施方式,一种存储器封装包括基底基板和堆叠在基底基板上的多个存储芯片。所述多个存储芯片的每个包括衬底和设置在衬底的第一表面上的外围电路。外围电路包括第一晶体管。每个存储芯片还包括设置在外围电路上的第一布线层、设置在第一布线层上的基底层、设置在基底层上的存储单元阵列、以及设置在存储单元阵列上的第二布线层。第二布线层包括配置为供应第一电压的第一电源布线、配置为供应第二电压的第二电源布线、以及电连接到第一晶体管的第一布线。第一布线配置为可电连接到第一电源布线或第二电源布线。According to an exemplary embodiment of the inventive concept, a memory package includes a base substrate and a plurality of memory chips stacked on the base substrate. Each of the plurality of memory chips includes a substrate and peripheral circuits disposed on the first surface of the substrate. The peripheral circuit includes a first transistor. Each memory chip further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array . The second wiring layer includes a first power wiring configured to supply a first voltage, a second power wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring.

根据本发明构思的示范性实施方式,一种存储器件包括衬底和设置在衬底的第一表面上的外围电路。外围电路包括第一晶体管和第二晶体管、设置在外围电路上的下布线层、设置在下布线层上的基底层、以及设置在基底层上的存储单元阵列。存储单元阵列包括多个沟道。存储器件还包括设置在存储单元阵列上的上布线层。上布线层包括至少两个电源布线。所述至少两个电源布线中的第一电源布线配置为供应第一电压,所述至少两个电源布线中的第二电源布线配置为供应第二电压。上布线层还包括电连接到第一晶体管的第一布线。第一布线配置为可电连接到第一电源布线或第二电源布线。上布线层还包括电连接到第二晶体管的第二布线。第二布线配置为可电连接到第一电源布线或第二电源布线。According to an exemplary embodiment of the inventive concept, a memory device includes a substrate and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor and a second transistor, a lower wiring layer provided on the peripheral circuit, a base layer provided on the lower wiring layer, and a memory cell array provided on the base layer. The memory cell array includes a plurality of channels. The memory device also includes an upper wiring layer disposed on the memory cell array. The upper wiring layer includes at least two power wirings. A first power supply wiring of the at least two power supply wirings is configured to supply a first voltage, and a second power supply wiring of the at least two power supply wirings is configured to supply a second voltage. The upper wiring layer also includes a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring. The upper wiring layer also includes a second wiring electrically connected to the second transistor. The second wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring.

附图说明Description of drawings

通过参照附图详细描述本发明构思的示范性实施方式,本发明构思的以上和其它的特征将变得更加明显,附图中:The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

图1是根据本发明构思的示范性实施方式的存储器件的透视图;FIG. 1 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept;

图2是根据本发明构思的示范性实施方式的存储器件的俯视图;2 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

图3是根据本发明构思的示范性实施方式的沿图2的线I-I'截取的剖面图;3 is a cross-sectional view taken along line II' of FIG. 2 according to an exemplary embodiment of the present inventive concept;

图4是示出根据本发明构思的示范性实施方式的可设置在图3中的存储单元区域中的存储单元阵列的示例的电路图;4 is a circuit diagram illustrating an example of a memory cell array that may be disposed in the memory cell region in FIG. 3 according to an exemplary embodiment of the inventive concept;

图5、图6、图7、图8和图9是用于描述根据本发明构思的示范性实施方式的制造存储器件的工艺的剖面图;5, 6, 7, 8, and 9 are cross-sectional views for describing a process of manufacturing a memory device according to an exemplary embodiment of the present inventive concept;

图10是根据本发明构思的示范性实施方式的存储器件的俯视图;FIG. 10 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

图11是根据本发明构思的示范性实施方式的沿图10的线I-I'截取的剖面图;11 is a cross-sectional view taken along line II' of FIG. 10 according to an exemplary embodiment of the present inventive concept;

图12是根据本发明构思的示范性实施方式的存储器件的俯视图;12 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

图13是根据本发明构思的示范性实施方式的沿图12的线II-II'截取的剖面图;13 is a cross-sectional view taken along line II-II' of FIG. 12 according to an exemplary embodiment of the present inventive concept;

图14是根据本发明构思的示范性实施方式的存储器件的俯视图;14 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

图15是根据本发明构思的示范性实施方式的沿图14的线III-III'截取的剖面图;15 is a cross-sectional view taken along line III-III' of FIG. 14 according to an exemplary embodiment of the present inventive concept;

图16是示出根据本发明构思的示范性实施方式的存储器件的方框图;16 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept;

图17和图18是示出根据本发明构思的示范性实施方式的存储器封装的图;17 and 18 are diagrams illustrating a memory package according to an exemplary embodiment of the inventive concept;

图19是示出根据本发明构思的示范性实施方式的固态盘或固态硬盘(SSD)的方框图;19 is a block diagram illustrating a solid state disk or a solid state drive (SSD) according to an exemplary embodiment of the present inventive concept;

图20是示出根据本发明构思的示范性实施方式的嵌入式多媒体卡(eMMC)的方框图;20 is a block diagram illustrating an embedded multimedia card (eMMC) according to an exemplary embodiment of the present inventive concept;

图21是示出根据本发明构思的示范性实施方式的通用闪速存储器(UFS)的方框图;以及21 is a block diagram illustrating a universal flash memory (UFS) according to an exemplary embodiment of the inventive concept; and

图22是示出根据本发明构思的示范性实施方式的移动设备的方框图。FIG. 22 is a block diagram illustrating a mobile device according to an exemplary embodiment of the inventive concept.

具体实施方式Detailed ways

在下文将参照附图更充分地描述本发明构思的示范性实施方式。然而,本公开可以以许多不同的形式实施,而不应被解释为限于这里阐述的实施方式。Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

将理解,当一元件被称为“连接”或“联接”到另一元件时,它可以直接连接或直接联接到该另一元件,或者可以存在居间的元件。图1是根据本发明构思的示范性实施方式的存储器件的透视图。It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. FIG. 1 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept.

在图1中,基本上垂直于衬底的第一表面(例如顶表面)的方向被称为第一方向D1(例如Z轴方向)。此外,基本上平行于衬底的第一表面并且彼此交叉的两个方向被称为第二方向D2(例如X轴方向)和第三方向D3(例如Y轴方向)。例如,第二方向D2和第三方向D3可以基本上彼此垂直。此外,第一方向D1(例如Z轴方向)基本上垂直于第二方向D2(例如X轴方向)和第三方向D3(例如Y轴方向)两者。In FIG. 1 , a direction substantially perpendicular to a first surface (eg, a top surface) of a substrate is referred to as a first direction D1 (eg, a Z-axis direction). Also, two directions substantially parallel to the first surface of the substrate and intersecting each other are referred to as a second direction D2 (eg, X-axis direction) and a third direction D3 (eg, Y-axis direction). For example, the second direction D2 and the third direction D3 may be substantially perpendicular to each other. In addition, the first direction D1 (eg, the Z-axis direction) is substantially perpendicular to both the second direction D2 (eg, the X-axis direction) and the third direction D3 (eg, the Y-axis direction).

参照图1,存储器件10包括其中设置外围电路的外围电路区域PCR。存储器件10还包括其中设置存储单元阵列MCA的存储单元区域MCR。存储器件10还可以包括设置在其顶表面上的多个输入/输出(I/O)焊盘IOPAD。Referring to FIG. 1 , the memory device 10 includes a peripheral circuit region PCR in which peripheral circuits are disposed. The memory device 10 also includes a memory cell region MCR in which the memory cell array MCA is disposed. The memory device 10 may further include a plurality of input/output (I/O) pads IOPAD disposed on a top surface thereof.

外围电路区域PCR包括半导体衬底20,外围电路可以在半导体衬底20的第一表面(例如顶表面)上,并且第一布线层30可以设置在外围电路上。此外,外围电路可以包括设置在半导体衬底20的第一表面上的第一晶体管TR。存储单元区域MCR包括可设置在第一布线层30上的基底层40、可设置在基底层40上的存储单元阵列MCA、以及可设置在存储单元阵列MCA上的第二布线层50。所述多个I/O焊盘IOPAD可以设置在第二布线层50上。The peripheral circuit region PCR includes the semiconductor substrate 20, the peripheral circuit may be on a first surface (eg, top surface) of the semiconductor substrate 20, and the first wiring layer 30 may be disposed on the peripheral circuit. In addition, the peripheral circuit may include a first transistor TR disposed on the first surface of the semiconductor substrate 20 . The memory cell region MCR includes a base layer 40 that may be disposed on the first wiring layer 30 , a memory cell array MCA that may be disposed on the base layer 40 , and a second wiring layer 50 that may be disposed on the memory cell array MCA. The plurality of I/O pads IOPAD may be disposed on the second wiring layer 50 .

第二布线层50可以包括第一电源布线52、第二电源布线54和第一布线56。第二布线层50还可以包括第一连接布线58。The second wiring layer 50 may include a first power wiring 52 , a second power wiring 54 and a first wiring 56 . The second wiring layer 50 may further include a first connection wiring 58 .

第一电源布线52可以配置为向存储器件10供应第一电压,第二电源布线54可以配置为向存储器件10供应第二电压。此外,第二电压可以不同于第一电压。例如,第一电压可以是电源电压(例如Vcc),第二电压可以是接地电压(例如Vss)。The first power wiring 52 may be configured to supply a first voltage to the memory device 10 , and the second power wiring 54 may be configured to supply a second voltage to the memory device 10 . Furthermore, the second voltage may be different from the first voltage. For example, the first voltage may be a power supply voltage (such as Vcc), and the second voltage may be a ground voltage (such as Vss).

第一布线56可以电连接到第一晶体管TR。例如,如将参照图3描述的,第一布线56可以通过穿过第一布线层30和第二布线层50设置的至少一个接触而电连接到第一晶体管TR的栅电极。The first wiring 56 may be electrically connected to the first transistor TR. For example, as will be described with reference to FIG. 3 , the first wiring 56 may be electrically connected to the gate electrode of the first transistor TR through at least one contact provided through the first wiring layer 30 and the second wiring layer 50 .

第一布线56可以配置为可电连接到第一电源布线52和第二电源布线54中的一个。例如,如图1所示,第一布线56可以通过第一连接布线58电连接到第一电源布线52。第一晶体管TR可以接收第一电压。在另一示例中,第一布线56可以通过第二连接布线电连接到第二电源布线54。此外,第一晶体管TR可以于是接收第二电压。The first wiring 56 may be configured to be electrically connectable to one of the first power wiring 52 and the second power wiring 54 . For example, as shown in FIG. 1 , the first wiring 56 may be electrically connected to the first power supply wiring 52 through a first connection wiring 58 . The first transistor TR may receive a first voltage. In another example, the first wiring 56 may be electrically connected to the second power wiring 54 through a second connection wiring. Furthermore, the first transistor TR may then receive the second voltage.

根据本发明构思的示范性实施方式的存储器件10可以通过采用外围上单元(COP)结构而具有相对小的尺寸。通过采用该结构,外围电路设置在半导体衬底20上并且存储单元阵列MCA堆叠在外围电路上。此外,在根据本发明构思的示范性实施方式的存储器件10中,电连接到外围电路中的第一晶体管TR的第一布线56可以设置在第二布线层50中,第二布线层50设置在存储单元阵列MCA上。此外,第一布线56可以可电连接到第一电源布线52或第二电源布线54。因此,可以容易地修改存储器件10的设计,因而即使存储器件10的设计被修改,也可以减少用于制造存储器件10的时间。The memory device 10 according to an exemplary embodiment of the inventive concept may have a relatively small size by employing a cell on periphery (COP) structure. By adopting this structure, the peripheral circuit is provided on the semiconductor substrate 20 and the memory cell array MCA is stacked on the peripheral circuit. In addition, in the memory device 10 according to an exemplary embodiment of the present inventive concept, the first wiring 56 electrically connected to the first transistor TR in the peripheral circuit may be disposed in the second wiring layer 50 disposed in the second wiring layer 50 On the memory cell array MCA. In addition, the first wiring 56 may be electrically connectable to the first power wiring 52 or the second power wiring 54 . Therefore, the design of the memory device 10 can be easily modified, and thus the time for manufacturing the memory device 10 can be reduced even if the design of the memory device 10 is modified.

图2是根据本发明构思的示范性实施方式的存储器件的俯视图。图3是根据本发明构思的示范性实施方式的沿图2的线I-I'截取的剖面图。FIG. 2 is a top view of a memory device according to an exemplary embodiment of the inventive concept. FIG. 3 is a cross-sectional view taken along line II' of FIG. 2 according to an exemplary embodiment of the present inventive concept.

参照图2和图3,存储器件可以包括外围电路区域PCR和存储单元区域MCR,外围电路区域PCR包括设置在衬底100上的外围电路结构,存储单元区域MCR包括设置在外围电路结构上的存储单元结构。Referring to FIGS. 2 and 3 , the memory device may include a peripheral circuit region PCR and a memory cell region MCR. The peripheral circuit region PCR includes a peripheral circuit structure disposed on the substrate 100. The memory cell region MCR includes memory cells disposed on the peripheral circuit structure. cell structure.

在本发明构思的一些示范性实施方式中,存储器件可以是非易失性存储器件。例如,非易失性存储器件可以具有其中存储单元结构堆叠在外围电路结构上的COP结构。存储单元结构可以具有其中多个NAND闪存单元被垂直地设置的垂直NAND闪存结构。例如,NAND闪存单元可以相对于衬底100的第一表面(例如顶表面)堆叠在第一方向D1上。In some exemplary embodiments of the inventive concept, the memory device may be a nonvolatile memory device. For example, a nonvolatile memory device may have a COP structure in which a memory cell structure is stacked on a peripheral circuit structure. The memory cell structure may have a vertical NAND flash memory structure in which a plurality of NAND flash memory cells are arranged vertically. For example, NAND flash memory cells may be stacked in a first direction D1 with respect to a first surface (eg, a top surface) of the substrate 100 .

此外,图2示出基底层201、焊盘240、模制保护层212、第一电源布线310、第二电源布线320、第一布线330和第一连接布线332。In addition, FIG. 2 shows the base layer 201 , the pad 240 , the mold protection layer 212 , the first power supply wiring 310 , the second power supply wiring 320 , the first wiring 330 , and the first connection wiring 332 .

外围电路结构可以例如包括可设置在衬底100上的栅结构130、源极/漏极区103、绝缘层140和160、接触145、布线150等。绝缘层140和160、接触145和布线150可以形成第一布线层(例如图1中的第一布线层30)。此外,第一布线层可以被称为下布线层。绝缘层140和160可以被称为下绝缘层。接触145可以被称为下接触或第一接触,布线150可以被称为下布线或第二布线。The peripheral circuit structure may, for example, include a gate structure 130 , source/drain regions 103 , insulating layers 140 and 160 , contacts 145 , wiring 150 , etc., which may be disposed on the substrate 100 . The insulating layers 140 and 160, the contact 145, and the wiring 150 may form a first wiring layer (eg, the first wiring layer 30 in FIG. 1). Also, the first wiring layer may be referred to as a lower wiring layer. The insulating layers 140 and 160 may be referred to as lower insulating layers. The contact 145 may be called a lower contact or a first contact, and the wiring 150 may be called a lower wiring or a second wiring.

衬底100可以包括半导体材料,例如由单晶形成的晶体硅或由单晶形成的晶体锗。栅结构130可以包括堆叠在衬底100上的栅绝缘层图案110和栅电极120。此外,栅电极120设置在栅绝缘层图案110上。The substrate 100 may include a semiconductor material such as crystalline silicon formed from a single crystal or crystalline germanium formed from a single crystal. The gate structure 130 may include a gate insulating layer pattern 110 and a gate electrode 120 stacked on the substrate 100 . In addition, a gate electrode 120 is disposed on the gate insulating layer pattern 110 .

栅绝缘层图案110可以包括例如硅氧化物或金属氧化物。栅电极120可以包括例如金属、金属氮化物或掺杂的多晶硅。源极/漏极区103可以包括n型或p型杂质。包括栅结构130和源极/漏极区103的晶体管(例如图1中的第一晶体管TR)可以设置在衬底100上。The gate insulating layer pattern 110 may include, for example, silicon oxide or metal oxide. The gate electrode 120 may include, for example, metal, metal nitride, or doped polysilicon. The source/drain regions 103 may include n-type or p-type impurities. A transistor (eg, the first transistor TR in FIG. 1 ) including a gate structure 130 and a source/drain region 103 may be disposed on the substrate 100 .

第一下绝缘层140可以设置在衬底100上以覆盖可设置在衬底100上的结构诸如所述晶体管。第一下接触145可以延伸穿过第一下绝缘层140的一部分并可以电连接到栅电极120。The first lower insulating layer 140 may be disposed on the substrate 100 to cover structures such as the transistors that may be disposed on the substrate 100 . The first lower contact 145 may extend through a portion of the first lower insulating layer 140 and may be electrically connected to the gate electrode 120 .

第一下布线150可以设置在第一下绝缘层140的上表面上,并可以电连接到第一下接触145。第二下绝缘层160可以设置在第一下绝缘层140上以覆盖第一下布线150。尽管图3示出本发明构思的示范性实施方式(其中下布线层包括单个下布线150),但是如将参照图11和图13描述的,下布线层可以包括分布在不同的层中的多个下布线。The first lower wiring 150 may be disposed on the upper surface of the first lower insulating layer 140 and may be electrically connected to the first lower contact 145 . The second lower insulating layer 160 may be disposed on the first lower insulating layer 140 to cover the first lower wiring 150 . Although FIG. 3 shows an exemplary embodiment of the inventive concept (wherein the lower wiring layer includes a single lower wiring 150), as will be described with reference to FIGS. 11 and 13, the lower wiring layer may include multiple down the wiring.

第一下绝缘层140和第二下绝缘层160可以包括绝缘材料,例如硅氧化物。第一下接触145和第一下布线150可以包括例如金属、金属氮化物或掺杂的多晶硅。The first lower insulating layer 140 and the second lower insulating layer 160 may include an insulating material such as silicon oxide. The first lower contact 145 and the first lower wiring 150 may include, for example, metal, metal nitride, or doped polysilicon.

存储单元结构可以包括可设置在下布线层上(例如设置在第二下绝缘层160上)的基底层201、沟道225、栅线260a、260b、260c、260d、260e和260f、位线285、绝缘层275和290、接触248a以及布线310、320、330和332等。绝缘层275和290、接触248a以及布线310、320、330和332可以形成第二布线层(例如图1中的第二布线层50)。第二布线层可以被称为上布线层,绝缘层275和290可以被称为上绝缘层,其中例如第二上绝缘层290可以设置在第一上绝缘层275上。此外,接触248a可以被称为上接触,布线310、320、330和332可以被称为上布线。The memory cell structure may include a base layer 201 which may be disposed on a lower wiring layer (for example, disposed on the second lower insulating layer 160), a channel 225, gate lines 260a, 260b, 260c, 260d, 260e, and 260f, bit lines 285, The insulating layers 275 and 290, the contact 248a, and the wirings 310, 320, 330, and 332, and the like. The insulating layers 275 and 290, the contact 248a, and the wirings 310, 320, 330, and 332 may form a second wiring layer (eg, the second wiring layer 50 in FIG. 1). The second wiring layer may be referred to as an upper wiring layer, and the insulating layers 275 and 290 may be referred to as an upper insulating layer, wherein, for example, the second upper insulating layer 290 may be disposed on the first upper insulating layer 275 . Also, the contact 248a may be referred to as an upper contact, and the wirings 310, 320, 330, and 332 may be referred to as upper wirings.

基底层201可以包括例如多晶硅或由单晶形成的晶体硅。在本发明构思的一些示范性实施方式中,基底层201还可以包括p型杂质诸如硼(B),并且在这样的情况下,基底层201可以用作p型阱。The base layer 201 may include, for example, polysilicon or crystalline silicon formed of a single crystal. In some exemplary embodiments of the inventive concept, the base layer 201 may further include p-type impurities such as boron (B), and in this case, the base layer 201 may serve as a p-type well.

沟道225可以设置在基底层201上,并可以在第一方向D1(例如Z轴方向)上从基底层201的第一表面(例如顶表面)延伸。沟道225可以具有空心的圆柱形形状或杯子形状。沟道225可以包括多晶硅或由单晶形成的晶体硅,并可以包括用例如p型杂质诸如硼掺杂的杂质区域。The channel 225 may be disposed on the base layer 201 and may extend from a first surface (eg, top surface) of the base layer 201 in a first direction D1 (eg, Z-axis direction). The channel 225 may have a hollow cylindrical shape or a cup shape. The channel 225 may include polysilicon or crystalline silicon formed of a single crystal, and may include an impurity region doped with, for example, a p-type impurity such as boron.

多个沟道225可以布置在第二方向D2(例如X轴方向)上以形成沟道行,多个沟道行可以布置在第三方向D3(例如Y轴方向)上。此外,所述多个沟道225在基本上垂直于第一表面的第一方向(例如Z轴方向)上延伸。A plurality of channels 225 may be arranged in a second direction D2 (eg, an X-axis direction) to form channel rows, and a plurality of channel rows may be arranged in a third direction D3 (eg, a Y-axis direction). In addition, the plurality of channels 225 extend in a first direction (eg, Z-axis direction) substantially perpendicular to the first surface.

填充层图案230可以设置在沟道225的内部空间中。填充层图案230可以具有柱子形状或实心的圆柱形形状。填充层图案230可以包括绝缘层图案例如硅氧化物。A filling layer pattern 230 may be disposed in an inner space of the trench 225 . The filling layer pattern 230 may have a pillar shape or a solid cylindrical shape. The filling layer pattern 230 may include an insulating layer pattern such as silicon oxide.

在本发明构思的一些示范性实施方式中,沟道225可以具有柱子形状或实心的圆柱形形状,并且在这样的情况下,填充层图案230可以被省略。In some exemplary embodiments of the inventive concept, the channel 225 may have a pillar shape or a solid cylindrical shape, and in this case, the filling layer pattern 230 may be omitted.

电介质层结构220可以设置在沟道225的外侧壁上。电介质层结构220可以具有其中央底部敞开的杯子形状、吸管形状或基本上类似于空心的圆柱形形状的形状。The dielectric layer structure 220 may be disposed on the outer sidewall of the trench 225 . The dielectric layer structure 220 may have a cup shape whose central bottom is opened, a straw shape, or a shape substantially similar to a hollow cylindrical shape.

电介质层结构220可以包括例如可从沟道225的外侧壁顺序地堆叠的隧道绝缘层、电荷存储层和阻挡层。阻挡层可以包括例如硅氧化物或金属氧化物诸如铪氧化物或铝氧化物。电荷存储层可以包括例如氮化物(诸如硅氮化物)或金属氧化物,隧道绝缘层可以包括例如氧化物,诸如硅氧化物。例如,电介质层结构220可以具有堆叠而形成电介质层结构220的氧化物-氮化物-氧化物(ONO)层。The dielectric layer structure 220 may include, for example, a tunnel insulating layer, a charge storage layer, and a blocking layer, which may be sequentially stacked from the outer sidewall of the channel 225 . The barrier layer may comprise, for example, silicon oxide or a metal oxide such as hafnium oxide or aluminum oxide. The charge storage layer may include, for example, a nitride such as silicon nitride or a metal oxide, and the tunnel insulating layer may include, for example, an oxide such as silicon oxide. For example, the dielectric layer structure 220 may have oxide-nitride-oxide (ONO) layers stacked to form the dielectric layer structure 220 .

焊盘240可以设置在填充层图案230、沟道225和电介质层结构220上。例如,填充层图案230、沟道225和电介质层结构220可以被焊盘240覆盖或封闭。焊盘240可以包括例如多晶硅或由单晶形成的晶体硅。焊盘240还可以包括例如n型杂质,例如磷(P)或砷(As)。The pad 240 may be disposed on the filling layer pattern 230 , the trench 225 and the dielectric layer structure 220 . For example, the filling layer pattern 230 , the trench 225 and the dielectric layer structure 220 may be covered or closed by the pad 240 . The pad 240 may include, for example, polysilicon or crystalline silicon formed of a single crystal. The pad 240 may also include, for example, n-type impurities such as phosphorus (P) or arsenic (As).

如图2所示,多个焊盘240可以布置在第二方向D2(例如X轴方向)上以形成基本上可与沟道行相比较的焊盘行。多个焊盘行可以布置在第三方向D3(例如Y轴方向)上。As shown in FIG. 2 , a plurality of pads 240 may be arranged in a second direction D2 (eg, an X-axis direction) to form pad rows substantially comparable to channel rows. A plurality of pad rows may be arranged in a third direction D3 (eg, Y-axis direction).

栅线260a-260f可以设置在电介质层结构220的外侧壁上并可以在第一方向D1(例如Z轴方向)上彼此间隔开。在本发明构思的一些示范性实施方式中,栅线260a-260f的每条可以围绕至少一个沟道行的沟道225并可以在第二方向D2(例如X轴方向)上延伸。例如,如图2和图3所示,栅线260a-260f的每条可以围绕四个沟道行;然而,由栅线260a-260f的每条围绕的沟道行的数目不限于此。The gate lines 260a-260f may be disposed on the outer sidewall of the dielectric layer structure 220 and may be spaced apart from each other in the first direction D1 (eg, Z-axis direction). In some exemplary embodiments of the inventive concepts, each of the gate lines 260a-260f may surround the channel 225 of at least one channel row and may extend in the second direction D2 (eg, the X-axis direction). For example, as shown in FIGS. 2 and 3, each of the gate lines 260a-260f may surround four channel rows; however, the number of channel rows surrounded by each of the gate lines 260a-260f is not limited thereto.

栅线260a-260f可以包括例如具有低电阻的金属和/或其氮化物。例如,栅线260a-260f可以包括钨(W)、钨氮化物、钛(Ti)、钛氮化物、钽(Ta)、钽氮化物、铂(Pt)等。在本发明构思的一些示范性实施方式中,栅线260a-260f可以具有多层结构,该多层结构包括包含金属氮化物的阻挡层和金属层。The gate lines 260a-260f may include, for example, metal and/or its nitride having low resistance. For example, the gate lines 260a-260f may include tungsten (W), tungsten nitride, titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, platinum (Pt), and the like. In some exemplary embodiments of the inventive concepts, the gate lines 260a-260f may have a multi-layer structure including a barrier layer including a metal nitride and a metal layer.

在本发明构思的一些示范性实施方式中,最下面的栅线260a(例如从基底层201起的第一个)可以用作接地选择线(GSL),最上面的栅线260f(例如最接近第一上绝缘层275)可以用作串选择线(SSL)。在GSL与SSL之间的其它的栅线260b、260c、260d和260e可以用作字线。In some exemplary embodiments of the present invention concept, the lowermost gate line 260a (for example, the first one from the base layer 201) can be used as a ground selection line (GSL), and the uppermost gate line 260f (for example, the closest The first upper insulating layer 275) may serve as a string selection line (SSL). The other gate lines 260b, 260c, 260d and 260e between the GSL and the SSL may be used as word lines.

根据本发明构思的示范性实施方式,GSL、字线和SSL可以分别形成在单个层级、四个级别和单个层级中。然而,GSL、字线和SSL的层级的各自的数目不限于此。在本发明构思的一些示范性实施方式中,GSL和SSL可以分别形成在两个层级中,字线可以形成在2n个层级中,其中n是正整数,例如字线可以具有4、8或16个层级。栅线260a-260f的堆叠数目可以考虑存储器件的集成度和电路设计来确定。According to an exemplary embodiment of the inventive concept, the GSL, the word line, and the SSL may be formed in a single level, four levels, and a single level, respectively. However, the respective numbers of levels of GSL, word lines, and SSL are not limited thereto. In some exemplary embodiments of the present inventive concept, GSL and SSL can be formed in two levels respectively, word lines can be formed in 2 n levels, where n is a positive integer, for example, word lines can have 4, 8 or 16 levels. The stacked number of gate lines 260a-260f may be determined in consideration of the degree of integration and circuit design of the memory device.

绝缘夹层202a、202b、202c、202d、202e、202f和202g可以与栅线260a-260f在第一方向D1(例如Z轴方向)上交替地堆叠。绝缘夹层202a-202g可以包括基于硅氧化物的材料,例如二氧化硅(SiO2)、硅碳氧化物(SiOC)或硅氟氧化物(SiOF)。栅线260a-260f可以通过绝缘夹层202a-202g而沿着第一方向D1(例如Z轴方向)彼此绝缘。The insulating interlayers 202a, 202b, 202c, 202d, 202e, 202f, and 202g may be alternately stacked with the gate lines 260a-260f in the first direction D1 (eg, Z-axis direction). The insulating interlayers 202a-202g may include a silicon oxide-based material, such as silicon dioxide (SiO 2 ), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF). The gate lines 260a-260f may be insulated from each other along the first direction D1 (eg, Z-axis direction) by insulating interlayers 202a-202g.

第一上绝缘层275可以设置在最上面的绝缘夹层202g、焊盘240和第一上接触248a上。A first upper insulating layer 275 may be disposed on the uppermost insulating interlayer 202g, the pad 240 and the first upper contact 248a.

位线接触280可以穿过第一上绝缘层275设置以与焊盘240接触。多个位线接触280可以形成为限定类似于沟道225或焊盘240的布置的阵列。A bit line contact 280 may be disposed through the first upper insulating layer 275 to contact the pad 240 . A plurality of bitline contacts 280 may be formed in an array defining an arrangement similar to channels 225 or pads 240 .

位线285可以设置在第一上绝缘层275上并可以电连接到位线接触280。例如,位线285可以在第三方向D3(例如Y轴方向)上延伸并可以电连接到多个位线接触280。A bit line 285 may be disposed on the first upper insulating layer 275 and may be electrically connected to the bit line contact 280 . For example, the bitline 285 may extend in a third direction D3 (eg, the Y-axis direction) and may be electrically connected to the plurality of bitline contacts 280 .

在本发明构思的一些示范性实施方式中,模制保护层212可以设置在基底层201的侧向部分(lateral portion)上。第一上接触248a可以延伸穿过模制保护层212、基底层201以及第二下绝缘层160的一部分,并可以与第一下布线150接触。第一绝缘层图案241a可以设置在第一上接触248a的侧壁上。In some exemplary embodiments of the present inventive concepts, the mold protection layer 212 may be disposed on a lateral portion of the base layer 201 . The first upper contact 248 a may extend through the mold protection layer 212 , the base layer 201 , and a portion of the second lower insulating layer 160 , and may make contact with the first lower wiring 150 . The first insulating layer pattern 241a may be disposed on a sidewall of the first upper contact 248a.

第一插塞291可以延伸穿过第一上绝缘层275并可以与第一上接触248a接触。第一上布线330可以设置在第一上绝缘层275(例如第一上绝缘层275的上表面)上并可以分别电连接第一插塞291和第一上接触248a。第二上绝缘层290可以设置在第一上绝缘层275上并可以覆盖第一上布线330。The first plug 291 may extend through the first upper insulating layer 275 and may make contact with the first upper contact 248a. The first upper wiring 330 may be disposed on the first upper insulating layer 275 (eg, an upper surface of the first upper insulating layer 275 ) and may electrically connect the first plug 291 and the first upper contact 248a, respectively. The second upper insulating layer 290 may be disposed on the first upper insulating layer 275 and may cover the first upper wiring 330 .

在根据本发明构思的示范性实施方式的存储器件中,包括在外围电路区域PCR中的第一晶体管可以用于实现逻辑电路。例如,外围电路区域PCR可以包括用于驱动存储器件的各种元件。此外,每个元件可以包括各种逻辑电路诸如或门(OR gate)、与门(AND gate)、或非门(NOR gate)、与非门(NAND gate)等,并且每个逻辑电路可以包括至少一个晶体管。例如,第一晶体管可以被包括在第一逻辑电路中并可以连接到第一逻辑电路的第一输入端子。第一晶体管可以通过接触145和248a、第一下布线150和第一插塞291电连接到第一上布线330。In the memory device according to an exemplary embodiment of the inventive concept, the first transistor included in the peripheral circuit region PCR may be used to implement a logic circuit. For example, the peripheral circuit region PCR may include various elements for driving the memory device. In addition, each element may include various logic circuits such as OR gates, AND gates, NOR gates, NAND gates, etc., and each logic circuit may include at least one transistor. For example, a first transistor may be included in a first logic circuit and may be connected to a first input terminal of the first logic circuit. The first transistor may be electrically connected to the first upper wiring 330 through the contacts 145 and 248 a, the first lower wiring 150 and the first plug 291 .

在本发明构思的一些示范性实施方式中,第一电源布线310、第二电源布线320、第一上布线330和第一连接布线332可以设置在第一上绝缘层275上的相同的层上(例如设置在俯视图中的相同的平面上)。例如,第一电源布线310和第二电源布线320可以设置在存储单元阵列上的相同的层上。例如,第一电源布线310和第二电源布线320的每个可以在第二方向D2(例如X轴方向)上延伸。此外,第一电源布线310和第二电源布线320可以彼此间隔开。第一上布线330可以布置在第一电源布线310和第二电源布线320之间。第一连接布线332可以将第一电源布线310与第一上布线330电连接。此外,第一连接布线332可以用将第二电源布线320与第一上布线330连接的第二连接布线代替。In some exemplary embodiments of the present inventive concepts, the first power wiring 310 , the second power wiring 320 , the first upper wiring 330 and the first connection wiring 332 may be disposed on the same layer on the first upper insulating layer 275 (e.g. set on the same plane in plan view). For example, the first power supply wiring 310 and the second power supply wiring 320 may be disposed on the same layer on the memory cell array. For example, each of the first power supply wiring 310 and the second power supply wiring 320 may extend in the second direction D2 (for example, the X-axis direction). In addition, the first power wiring 310 and the second power wiring 320 may be spaced apart from each other. The first upper wiring 330 may be disposed between the first power wiring 310 and the second power wiring 320 . The first connection wiring 332 may electrically connect the first power wiring 310 and the first upper wiring 330 . Also, the first connection wiring 332 may be replaced with a second connection wiring that connects the second power supply wiring 320 with the first upper wiring 330 .

因而,在根据本发明构思的示范性实施方式的存储器件中,电连接到外围电路中的第一晶体管的第一上布线330可以设置在上布线层(例如图1中的第二布线层50)中。于是,用于第一晶体管的电源选项(power option)可以通过改变将第一上布线330与电源布线310和320之一连接的连接布线的布置而基于第一上布线330被有效地且容易地选择。例如,第一上布线330可以可电连接到电源布线310和320中的一个,并且第一电压(例如电源电压)和第二电压(例如接地电压)中的一个可以被选择以提供到第一晶体管而没有过多的设计变化。因此,可以容易地修改存储器件的设计,因而即使存储器件的设计被修改,也可以减少用于制造存储器件的时间。Thus, in the memory device according to an exemplary embodiment of the present inventive concept, the first upper wiring 330 electrically connected to the first transistor in the peripheral circuit may be disposed on an upper wiring layer (eg, the second wiring layer 50 in FIG. 1 ). )middle. Then, a power option for the first transistor can be efficiently and easily selected based on the first upper wiring 330 by changing the arrangement of the connection wiring connecting the first upper wiring 330 with one of the power supply wirings 310 and 320. choose. For example, the first upper wiring 330 may be electrically connectable to one of the power supply wirings 310 and 320, and one of a first voltage (such as a power supply voltage) and a second voltage (such as a ground voltage) may be selected to be supplied to the first transistors without excessive design changes. Therefore, the design of the memory device can be easily modified, and thus the time for manufacturing the memory device can be reduced even if the design of the memory device is modified.

图4是示出根据本发明构思的示范性实施方式的可设置在图3中的存储单元区域中的存储单元阵列的示例的电路图。FIG. 4 is a circuit diagram illustrating an example of a memory cell array that may be disposed in the memory cell region in FIG. 3 according to an exemplary embodiment of the inventive concept.

参照图4,存储单元阵列400可以包括多个串410,每个串410具有垂直结构。所述多个串410可以布置在第二方向D2(例如X轴方向)上以限定串列。此外,多个串列可以布置在第三方向D3(例如Y轴方向)上以限定串阵列。每个串可以包括串选择晶体管SSTV、接地选择晶体管GSTV、以及布置在第一方向D1(例如Z轴方向)上且串联连接在串选择晶体管SSTV与接地选择晶体管GSTV之间的多个存储单元MC。Referring to FIG. 4, the memory cell array 400 may include a plurality of strings 410 each having a vertical structure. The plurality of strings 410 may be arranged in a second direction D2 (for example, the X-axis direction) to define a series. Furthermore, a plurality of strings may be arranged in a third direction D3 (eg, Y-axis direction) to define a string array. Each string may include a string selection transistor SSTV, a ground selection transistor GSTV, and a plurality of memory cells MC arranged in a first direction D1 (eg, Z-axis direction) and connected in series between the string selection transistor SSTV and the ground selection transistor GSTV. .

串选择晶体管SSTV可以连接到位线BL(1)、...、BL(m),接地选择晶体管GSTV可以连接到公共源极线CSL。串选择晶体管SSTV可以连接到串选择线SSL11、SSL12、...、SSLi1、SSLi2,接地选择晶体管GSTV可以连接到接地选择线GSL11、GSL12、...、GSLi1、GSLi2。相同的层中的存储单元可以连接到字线WL(1)、WL(2)、...WL(n-1)、WL(n)中的同一字线。每条串选择线和每条接地选择线可以在第二方向D2(例如X轴方向)上延伸,并且串选择线SSL11-SSLi2和接地选择线GSL11-GSLi2可以沿第三方向D3(例如Y轴方向)布置。每条字线可以在第二方向D2(例如X轴方向)上延伸,并且字线WL(1)-WL(n)可以沿第一方向D1(例如Z轴方向)和第三方向D3(例如Y轴方向)布置。每条位线(例如BL(1))可以在第三方向D3(例如Y轴方向)上延伸,并且位线BL(1)-BL(m)可以沿第二方向D2(例如X轴方向)布置。存储单元MC可以由字线WL(1)-WL(n)上的电压控制。The string selection transistor SSTV may be connected to the bit lines BL(1), . . . , BL(m), and the ground selection transistor GSTV may be connected to the common source line CSL. The string selection transistor SSTV can be connected to the string selection lines SSL11, SSL12, . . . , SSLi1, SSLi2, and the ground selection transistor GSTV can be connected to the ground selection lines GSL11, GSL12, . Memory cells in the same layer may be connected to the same one of word lines WL(1), WL(2), . . . WL(n-1), WL(n). Each string selection line and each ground selection line may extend in the second direction D2 (for example, the X-axis direction), and the string selection lines SSL11-SSLi2 and the ground selection lines GSL11-GSLi2 may extend in the third direction D3 (for example, the Y-axis direction). direction) layout. Each word line may extend in the second direction D2 (for example, the X-axis direction), and the word lines WL(1)-WL(n) may extend along the first direction D1 (for example, the Z-axis direction) and the third direction D3 (for example, Y-axis direction) arrangement. Each bit line (eg BL(1)) may extend in a third direction D3 (eg Y-axis direction), and the bit lines BL(1)-BL(m) may extend in a second direction D2 (eg X-axis direction) layout. Memory cell MC can be controlled by voltages on word lines WL(1)-WL(n).

如同二维(2D)闪存器件一样,包括存储单元阵列400的垂直或三维(3D)闪存器件可以以页(page)为单位执行编程操作和读操作,并以块(block)为单位执行擦除操作。Like a two-dimensional (2D) flash memory device, a vertical or three-dimensional (3D) flash memory device including the memory cell array 400 can perform a program operation and a read operation in units of a page (page), and perform an erase operation in units of a block (block). operate.

此外,根据本发明构思的示范性实施方式,包括在单个串中的两个串选择晶体管可以连接到单条串选择线,包括在单个串中的两个接地选择晶体管可以连接到单条接地选择线。根据本发明构思的示范性实施方式,单个串可以包括一个串选择晶体管和一个接地选择晶体管。Also, according to exemplary embodiments of the inventive concept, two string selection transistors included in a single string may be connected to a single string selection line, and two ground selection transistors included in a single string may be connected to a single ground selection line. According to an exemplary embodiment of the inventive concept, a single string may include one string selection transistor and one ground selection transistor.

图5、图6、图7、图8和图9是用于描述根据本发明构思的示范性实施方式的制造存储器件的工艺的剖面图。5 , 6 , 7 , 8 and 9 are cross-sectional views for describing a process of manufacturing a memory device according to an exemplary embodiment of the inventive concept.

参照图5,栅结构130和源极/漏极区103可以设置在衬底100上。Referring to FIG. 5 , a gate structure 130 and source/drain regions 103 may be disposed on a substrate 100 .

包括由单晶形成的晶体硅和/或由单晶形成的晶体锗的半导体衬底可以用作衬底100。例如,衬底100可以从硅晶片获得。A semiconductor substrate including crystalline silicon formed from a single crystal and/or crystalline germanium formed from a single crystal may be used as the substrate 100 . For example, substrate 100 may be obtained from a silicon wafer.

栅绝缘层和栅电极层可以设置在衬底100上,然后可以被蚀刻以形成栅绝缘层图案110和栅电极120。因此,可以形成栅结构130,栅结构130包括顺序堆叠在衬底100上的栅绝缘层图案110和栅电极120。A gate insulating layer and a gate electrode layer may be disposed on the substrate 100 and then may be etched to form a gate insulating layer pattern 110 and a gate electrode 120 . Accordingly, a gate structure 130 including the gate insulating layer pattern 110 and the gate electrode 120 sequentially stacked on the substrate 100 may be formed.

可以利用栅结构130作为注入掩模执行离子注入工艺以在衬底100的邻近栅结构130的上部(例如衬底100的上表面)处形成源极/漏极区103。因此,源极/漏极区103可以设置在衬底100的邻近栅结构130的上部处。因此,第一晶体管可以被限定并设置在衬底100上。An ion implantation process may be performed using the gate structure 130 as an implantation mask to form source/drain regions 103 at an upper portion of the substrate 100 adjacent to the gate structure 130 (eg, the upper surface of the substrate 100 ). Accordingly, the source/drain region 103 may be disposed at an upper portion of the substrate 100 adjacent to the gate structure 130 . Accordingly, a first transistor may be defined and disposed on the substrate 100 .

栅绝缘层可以通过例如化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、旋涂工艺、原子层沉积(ALD)工艺等由硅氧化物或金属氧化物形成。此外,栅绝缘层可以通过对衬底100的顶表面的热氧化工艺形成。栅电极层可以通过例如ALD工艺或溅射工艺而包括金属、金属氮化物或掺杂的多晶硅。The gate insulating layer may be formed of silicon oxide or metal oxide through, for example, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a spin coating process, an atomic layer deposition (ALD) process, or the like. In addition, the gate insulating layer may be formed through a thermal oxidation process on the top surface of the substrate 100 . The gate electrode layer may include metal, metal nitride, or doped polysilicon by, for example, an ALD process or a sputtering process.

覆盖栅结构130的第一下绝缘层140可以设置在衬底100上。第一下接触145可以穿过第一下绝缘层140设置并可以通过接触包括在栅结构130中的栅电极120而与第一晶体管接触。此外,第一下接触145可以与源极/漏极区103接触。A first lower insulating layer 140 covering the gate structure 130 may be disposed on the substrate 100 . The first lower contact 145 may be disposed through the first lower insulating layer 140 and may make contact with the first transistor by contacting the gate electrode 120 included in the gate structure 130 . In addition, the first lower contact 145 may be in contact with the source/drain region 103 .

电连接到下接触145的第一下布线150可以设置在第一下绝缘层140上。覆盖第一下布线150的第二下绝缘层160可以设置在第一下绝缘层140上。A first lower wiring 150 electrically connected to the lower contact 145 may be disposed on the first lower insulating layer 140 . A second lower insulating layer 160 covering the first lower wiring 150 may be disposed on the first lower insulating layer 140 .

第一下绝缘层140和第二下绝缘层160可以通过例如CVD工艺或旋涂工艺而包括绝缘材料例如硅氧化物。第一下接触145和第一下布线150可以通过例如ALD工艺或溅射工艺而包括金属或金属氮化物。The first lower insulating layer 140 and the second lower insulating layer 160 may include an insulating material such as silicon oxide through, for example, a CVD process or a spin coating process. The first lower contact 145 and the first lower wiring 150 may include metal or metal nitride through, for example, an ALD process or a sputtering process.

图5中示出单层级的下布线;然而,如将参照图11和图13描述的,可以堆叠额外的下绝缘层和下布线。A single-level lower wiring is shown in FIG. 5 ; however, as will be described with reference to FIGS. 11 and 13 , additional lower insulating layers and lower wiring may be stacked.

基底层201可以设置在第二下绝缘层160上。The base layer 201 may be disposed on the second lower insulating layer 160 .

在本发明构思的一示范性实施方式中,基底层201可以包括多晶硅材料并可以通过溅射工艺、CVD工艺、ALD工艺、物理气相沉积(PVD)工艺等制成。基底层201可以包括用例如p型杂质诸如硼(B)掺杂的多晶硅。这里,基底层201可以用作p型阱。In an exemplary embodiment of the present inventive concept, the base layer 201 may include a polysilicon material and may be made through a sputtering process, a CVD process, an ALD process, a physical vapor deposition (PVD) process, or the like. The base layer 201 may include polysilicon doped with, for example, p-type impurities such as boron (B). Here, the base layer 201 may serve as a p-type well.

在本发明构思的一示范性实施方式中,非晶硅层可以设置在第二下绝缘层160的上表面上(例如在第一方向D1上设置在第二下绝缘层160上),然后可以执行热处理或激光辐照以将非晶硅层转变成包括单晶的晶体硅的基底层201。这里,基底层201中的缺陷可以基本上被修复从而可以提高作为p型阱的基底层201的功能特性。In an exemplary embodiment of the present inventive concept, an amorphous silicon layer may be disposed on the upper surface of the second lower insulating layer 160 (for example, disposed on the second lower insulating layer 160 in the first direction D1), and then may Heat treatment or laser irradiation is performed to convert the amorphous silicon layer into the base layer 201 including single crystal crystalline silicon. Here, defects in the base layer 201 can be substantially repaired so that the functional characteristics of the base layer 201 as a p-type well can be improved.

在本发明构思的一示范性实施方式中,基底层201可以通过晶片接合工艺形成。这里,晶片(例如由单晶晶片形成的晶体硅)可以附接在第二下绝缘层160上。晶片的上部可以被去除或平坦化以形成基底层201。In an exemplary embodiment of the present inventive concept, the base layer 201 may be formed through a wafer bonding process. Here, a wafer such as crystalline silicon formed of a single crystal wafer may be attached on the second lower insulating layer 160 . The upper portion of the wafer may be removed or planarized to form base layer 201 .

参照图6,绝缘夹层202(例如202a-202g)和牺牲层204(例如204a-204f)可以在第一方向D1(例如Z轴方向)上交替地且重复地设置在基底层201上以形成模制结构。例如,第一绝缘夹层202a可以设置在基底层201上,第一牺牲层204a可以设置在第一绝缘夹层202a上,第二绝缘夹层202b可以设置在第一牺牲层204a上,等等。Referring to FIG. 6, insulating interlayers 202 (eg, 202a-202g) and sacrificial layers 204 (eg, 204a-204f) may be alternately and repeatedly disposed on the base layer 201 in a first direction D1 (eg, Z-axis direction) to form a mold. system structure. For example, the first insulating interlayer 202a can be disposed on the base layer 201, the first sacrificial layer 204a can be disposed on the first insulating interlayer 202a, the second insulating interlayer 202b can be disposed on the first sacrificial layer 204a, and so on.

在本发明构思的示范性实施方式中,绝缘夹层202可以包括基于硅氧化物的材料,例如二氧化硅、硅碳氧化物和/或硅氟氧化物。牺牲层204可以包括相对于绝缘夹层202可具有蚀刻选择性并可通过湿蚀刻工艺容易地去除的材料。例如,牺牲层204可以包括硅氮化物(SiN)和/或硅硼氮化物(SiBN)。In an exemplary embodiment of the present inventive concept, the insulating interlayer 202 may include a silicon oxide-based material, such as silicon dioxide, silicon oxycarbide, and/or silicon oxyfluoride. The sacrificial layer 204 may include a material that may have etch selectivity with respect to the insulating interlayer 202 and may be easily removed through a wet etching process. For example, the sacrificial layer 204 may include silicon nitride (SiN) and/or silicon boron nitride (SiBN).

绝缘夹层202和牺牲层204可以通过CVD工艺、PECVD工艺、旋涂工艺、ALD工艺等形成。The insulating interlayer 202 and the sacrificial layer 204 can be formed by CVD process, PECVD process, spin coating process, ALD process and so on.

牺牲层204可以在随后的工艺中被去除以向GSL、字线和SSL提供空间。例如,GSL和SSL的每条可以形成在单个层级中,字线可以形成在4个层级中。在此示例中,如图6所示,牺牲层204可以形成在6个层级中,绝缘夹层202可以形成在7个层级中。然而,GSL、SSL和字线的堆叠数目可以不限于这里提供的示例。The sacrificial layer 204 may be removed in a subsequent process to provide space for the GSL, word lines and SSL. For example, each of GSL and SSL may be formed in a single level, and word lines may be formed in 4 levels. In this example, as shown in FIG. 6, the sacrificial layer 204 may be formed in 6 levels, and the insulating interlayer 202 may be formed in 7 levels. However, the stacked numbers of GSLs, SSLs, and word lines may not be limited to the examples provided here.

参照图7,模制结构的侧向部分可以被去除,并且覆盖模制结构的绝缘层可以设置在基底层201上。此外,为了形成模制保护层212,绝缘层的上部可以被平坦化直到最上面的绝缘夹层202g被暴露。Referring to FIG. 7 , lateral portions of the molded structure may be removed, and an insulating layer covering the molded structure may be disposed on the base layer 201 . In addition, to form the mold protection layer 212, the upper portion of the insulating layer may be planarized until the uppermost insulating interlayer 202g is exposed.

参照图8,沟道孔可以穿过模制结构设置,并且电介质层结构220、沟道225和填充层图案230可以设置在每个沟道孔中。覆盖沟道孔的焊盘240可以设置在电介质层结构220、沟道225和填充层图案230上。Referring to FIG. 8, channel holes may be disposed through the mold structure, and a dielectric layer structure 220, a channel 225, and a filling layer pattern 230 may be disposed in each of the channel holes. A pad 240 covering the channel hole may be disposed on the dielectric layer structure 220 , the channel 225 and the filling layer pattern 230 .

可以形成第一上接触248a。例如,模制保护层212、基底层201以及第二下绝缘层160的一部分可以被蚀刻以形成第一下布线150的顶表面通过其暴露的第一接触孔。第一绝缘层图案241a可以设置在第一接触孔的侧壁上。然后,可以形成第一上接触248a以填充第一接触孔的剩余部分。A first upper contact 248a may be formed. For example, a portion of the mold protection layer 212, the base layer 201, and the second lower insulating layer 160 may be etched to form a first contact hole through which the top surface of the first lower wiring 150 is exposed. The first insulating layer pattern 241a may be disposed on a sidewall of the first contact hole. Then, a first upper contact 248a may be formed to fill the remaining portion of the first contact hole.

可以形成上栅线切割区域(例如图15中的元件250)和栅线切割区域(例如图15中的元件256)。由栅线切割区域暴露的牺牲层204可以被去除,并且栅线260a-260f可以设置在牺牲层204从其去除的空间处。Upper gridline cutting regions (eg, element 250 in FIG. 15 ) and gridline cutting regions (eg, element 256 in FIG. 15 ) may be formed. The sacrificial layer 204 exposed by the gate line cut region may be removed, and the gate lines 260 a - 260 f may be disposed at spaces from which the sacrificial layer 204 is removed.

参照图9,第一上绝缘层275可以设置在最上面的绝缘夹层202g、焊盘240和第一上接触248a上。第一上绝缘层275可以通过CVD工艺由例如硅氧化物形成。Referring to FIG. 9, a first upper insulating layer 275 may be disposed on the uppermost insulating interlayer 202g, the pad 240, and the first upper contact 248a. The first upper insulating layer 275 may be formed of, for example, silicon oxide through a CVD process.

第一插塞291和位线接触280可以穿过第一上绝缘层275设置并可以分别与第一上接触248a和焊盘240接触。The first plug 291 and the bit line contact 280 may be disposed through the first upper insulating layer 275 and may make contact with the first upper contact 248 a and the pad 240 , respectively.

位线285可以设置在第一上绝缘层275上并可以电连接到位线接触280。位线285可以在第三方向D3(例如Y轴方向)上延伸并可以电连接到多个位线接触280。A bit line 285 may be disposed on the first upper insulating layer 275 and may be electrically connected to the bit line contact 280 . The bit line 285 may extend in a third direction D3 (eg, the Y-axis direction) and may be electrically connected to the plurality of bit line contacts 280 .

第一上布线330可以电连接到第一插塞291。此外,第一上布线330可以设置在第一上绝缘层275上。第一电源布线310、第二电源布线320和第一连接布线332也可以设置在第一上绝缘层275上。第一上布线330可以是可电连接到第一电源布线310和第二电源布线320中的一个。包括栅结构130和源极/漏极区103的第一晶体管可以通过第一上布线330(其与第一电源布线310和第二电源布线320中的一个电连接)接收第一电压和第二电压中的一个(例如电源电压和接地电压中的一个)。The first upper wiring 330 may be electrically connected to the first plug 291 . In addition, the first upper wiring 330 may be disposed on the first upper insulating layer 275 . The first power wiring 310 , the second power wiring 320 and the first connection wiring 332 may also be disposed on the first upper insulating layer 275 . The first upper wiring 330 may be electrically connectable to one of the first power wiring 310 and the second power wiring 320 . The first transistor including the gate structure 130 and the source/drain region 103 may receive the first voltage and the second voltage through the first upper wiring 330 (which is electrically connected to one of the first power wiring 310 and the second power wiring 320). One of the voltages (such as one of the supply voltage and the ground voltage).

例如,上导电层可以使用金属或金属氮化物设置在第一上绝缘层275上,然后可以被图案化以形成位线285和布线310、320、330和332。位线285和布线310、320、330和332可以通过基本上相同的蚀刻工艺来设置。For example, an upper conductive layer may be disposed on the first upper insulating layer 275 using metal or metal nitride, and then may be patterned to form bit lines 285 and wirings 310 , 320 , 330 and 332 . The bit line 285 and the wirings 310, 320, 330, and 332 may be provided through substantially the same etching process.

覆盖位线285和布线310、320、330和332的第二上绝缘层290可以设置在第一上绝缘层275上。A second upper insulating layer 290 covering the bit line 285 and the wirings 310 , 320 , 330 and 332 may be disposed on the first upper insulating layer 275 .

图5、图6、图7、图8和图9示出其中在形成存储单元阵列之后形成布线310、320、330和332的工艺;然而,工艺顺序在此不被具体地限制。例如,可以执行用于外围电路区域PCR的工艺,可以形成布线310、320、330和332,然后可以执行用于存储单元区域MCR的工艺。5 , 6 , 7 , 8 , and 9 illustrate processes in which the wirings 310 , 320 , 330 , and 332 are formed after forming the memory cell array; however, the process order is not particularly limited here. For example, a process for a peripheral circuit region PCR may be performed, wirings 310, 320, 330, and 332 may be formed, and then a process for a memory cell region MCR may be performed.

图10是根据本发明构思的示范性实施方式的存储器件的俯视图。图11是根据本发明构思的示范性实施方式的沿图10的线I-I'截取的剖面图。FIG. 10 is a top view of a memory device according to an exemplary embodiment of the inventive concept. FIG. 11 is a cross-sectional view taken along line II' of FIG. 10 according to an exemplary embodiment of the present inventive concept.

参照图10和图11,存储器件可以包括外围电路区域PCR和存储单元区域MCR,外围电路区域PCR包括设置在衬底100上的外围电路结构,存储单元区域MCR包括设置在外围电路结构上的存储单元结构。Referring to FIG. 10 and FIG. 11 , the memory device may include a peripheral circuit region PCR and a memory cell region MCR, the peripheral circuit region PCR includes a peripheral circuit structure disposed on the substrate 100, and the memory cell region MCR includes memory cells disposed on the peripheral circuit structure. cell structure.

图10和图11的存储器件可以与图2和图3的存储器件基本上相同,除了图10和图11的存储器件还包括第二晶体管、第二布线340、第二连接布线342和用于将第二晶体管与第二布线340连接的元件并且图10和图11的存储器件中的下布线层(例如图1中的第一布线层30)用多个层实现之外。10 and FIG. 11 may be substantially the same as the memory device in FIG. 2 and FIG. 3, except that the memory device in FIG. 10 and FIG. The element connecting the second transistor to the second wiring 340 and the lower wiring layer (for example, the first wiring layer 30 in FIG. 1 ) in the memory device of FIGS. 10 and 11 are implemented with a plurality of layers.

外围电路结构可以例如包括设置在衬底100上的栅结构130和132、源极/漏极区103和104、绝缘层140、160、162和164、接触145、147a、147b和147c、布线150、152a、152b和152c等。The peripheral circuit structure may, for example, include gate structures 130 and 132, source/drain regions 103 and 104, insulating layers 140, 160, 162 and 164, contacts 145, 147a, 147b and 147c, wiring 150 disposed on the substrate 100. , 152a, 152b and 152c etc.

晶体管(例如第二晶体管)的栅结构132可以包括堆叠在衬底100上的栅绝缘层图案112和栅电极122。源极/漏极区104可以包括n型或p型杂质。包括栅结构132和源极/漏极区104的晶体管(例如第二晶体管)可以被设置并限定在衬底100上。A gate structure 132 of a transistor (eg, a second transistor) may include a gate insulating layer pattern 112 and a gate electrode 122 stacked on the substrate 100 . The source/drain regions 104 may include n-type or p-type impurities. A transistor (eg, a second transistor) including a gate structure 132 and a source/drain region 104 may be provided and defined on the substrate 100 .

第一下绝缘层140可以设置在衬底100上以覆盖诸如晶体管(例如第一晶体管和第二晶体管)的结构。第一下接触145可以延伸穿过第一下绝缘层140的一部分,并可以电连接到栅结构130的栅电极120。A first lower insulating layer 140 may be disposed on the substrate 100 to cover structures such as transistors (eg, first and second transistors). The first lower contact 145 may extend through a portion of the first lower insulating layer 140 and may be electrically connected to the gate electrode 120 of the gate structure 130 .

第一下布线150可以设置在第一下绝缘层140上,并可以电连接到第一下接触145。The first lower wiring 150 may be disposed on the first lower insulating layer 140 and may be electrically connected to the first lower contact 145 .

第二下绝缘层160可以设置在第一下绝缘层140上以覆盖下布线150和152a。第三下绝缘层162可以设置在第二下绝缘层160上以覆盖下布线152b。第四下绝缘层164可以设置在第三下绝缘图案162上以覆盖下布线152c。栅电极122可以通过下接触147a、147b和147c分别电连接到下布线152a、152b和152c。下布线与下接触之间的连接可以根据信号线的布线(routing)而变化。The second lower insulating layer 160 may be disposed on the first lower insulating layer 140 to cover the lower wirings 150 and 152a. A third lower insulating layer 162 may be disposed on the second lower insulating layer 160 to cover the lower wiring 152b. A fourth lower insulating layer 164 may be disposed on the third lower insulating pattern 162 to cover the lower wiring 152c. The gate electrode 122 may be electrically connected to lower wirings 152a, 152b, and 152c through lower contacts 147a, 147b, and 147c, respectively. The connection between the lower wiring and the lower contact may vary according to the routing of the signal line.

存储单元结构可以包括可设置在下布线层上(例如设置在第四下绝缘层164上)的基底层201、沟道225、栅线260a-260f、位线285、绝缘层275和290、接触248a和248b以及布线310、320、330、332、340和342等。The memory cell structure may include a base layer 201, a channel 225, gate lines 260a-260f, a bit line 285, insulating layers 275 and 290, a contact 248a, which may be disposed on a lower wiring layer (for example, disposed on a fourth lower insulating layer 164). and 248b and wires 310, 320, 330, 332, 340, and 342, etc.

与第一上接触248a类似,第二上接触248b可以延伸穿过模制保护层212、基底层201以及第四下绝缘层164的一部分。然而,接触248a与248b之间的差异是第二上接触248b可以与下布线152c接触。与第一绝缘层图案241a可以相对于第一上接触248a如何设置相似,第二绝缘层图案241b可以设置在第二上接触248b的侧壁上。Similar to the first upper contact 248 a , the second upper contact 248 b may extend through the mold protection layer 212 , the base layer 201 , and a portion of the fourth lower insulating layer 164 . However, the difference between the contacts 248a and 248b is that the second upper contact 248b may be in contact with the lower wiring 152c. Similar to how the first insulating layer pattern 241a may be disposed with respect to the first upper contact 248a, the second insulating layer pattern 241b may be disposed on a sidewall of the second upper contact 248b.

与第一插塞291类似,第二插塞293可以延伸穿过第一上绝缘层275并可以与第二上接触248b接触。第二上布线340可以设置在第一上绝缘层275上以分别电连接第二插塞293和第二上接触248b。Similar to the first plug 291, the second plug 293 may extend through the first upper insulating layer 275 and may make contact with the second upper contact 248b. The second upper wiring 340 may be disposed on the first upper insulating layer 275 to electrically connect the second plug 293 and the second upper contact 248b, respectively.

第二晶体管可以通过接触147a、147b、147c和248b、下布线152a、152b和152c以及第二插塞293电连接到第二上布线340。The second transistor may be electrically connected to the second upper wiring 340 through the contacts 147 a , 147 b , 147 c and 248 b , the lower wirings 152 a , 152 b and 152 c , and the second plug 293 .

在本发明构思的示范性实施方式中,布线310、320、330、332、340和342可以设置在第一上绝缘层275上的相同的层上(例如设置在俯视图中的相同的平面上)。例如,第一电源布线310和第二电源布线320的每个可以在第二方向D2(例如X轴方向)上延伸,并且第一电源布线310和第二电源布线320可以彼此间隔开。第一上布线330和第二上布线340可以布置在第一电源布线310和第二电源布线320之间。第一连接布线332可以将第一电源布线310与第一上布线330电连接。第二连接布线342可以将第二电源布线320与第二上布线340电连接。如同第一上布线330一样,第二上布线340可以是可电连接到电源布线310和320中的一个。于是,对于第二晶体管的电源选项可以通过改变将第二上布线340与电源布线310和320中的一个连接的连接布线的布置而基于第二上布线340被有效地且容易地选择。In an exemplary embodiment of the present inventive concept, the wirings 310, 320, 330, 332, 340, and 342 may be disposed on the same layer on the first upper insulating layer 275 (for example, disposed on the same plane in plan view) . For example, each of the first power wiring 310 and the second power wiring 320 may extend in the second direction D2 (eg, the X-axis direction), and the first power wiring 310 and the second power wiring 320 may be spaced apart from each other. The first upper wiring 330 and the second upper wiring 340 may be arranged between the first power wiring 310 and the second power wiring 320 . The first connection wiring 332 may electrically connect the first power wiring 310 and the first upper wiring 330 . The second connection wiring 342 may electrically connect the second power wiring 320 and the second upper wiring 340 . Like the first upper wiring 330 , the second upper wiring 340 may be one of the power wirings 310 and 320 electrically connectable. Then, a power supply option for the second transistor can be efficiently and easily selected based on the second upper wiring 340 by changing the arrangement of the connection wiring connecting the second upper wiring 340 with one of the power supply wirings 310 and 320 .

图12是根据本发明构思的示范性实施方式的存储器件的俯视图。图13是根据本发明构思的示范性实施方式的沿图12的线II-II'截取的剖面图。FIG. 12 is a top view of a memory device according to an exemplary embodiment of the inventive concept. FIG. 13 is a cross-sectional view taken along line II-II' of FIG. 12 according to an exemplary embodiment of the present inventive concept.

参照图12和图13,存储器件可以包括外围电路区域PCR和存储单元区域MCR,外围电路区域PCR包括设置在衬底100上的外围电路结构,存储单元区域MCR包括设置在外围电路结构上的存储器单元结构。Referring to FIG. 12 and FIG. 13 , the memory device may include a peripheral circuit region PCR and a memory cell region MCR, the peripheral circuit region PCR includes a peripheral circuit structure disposed on the substrate 100, and the memory cell region MCR includes a memory cell disposed on the peripheral circuit structure. cell structure.

图12和图13的存储器件可以与图2和图3的存储器件基本上相同,除了图12和图13的存储器件还包括第三晶体管、第三电源布线350、第三布线360、第三连接布线362和用于将第三晶体管与第三布线360连接的元件并且图12和图13的存储器件中的下布线层(例如第一布线层)用多个层来实现之外。The memory device of FIG. 12 and FIG. 13 may be substantially the same as the memory device of FIG. 2 and FIG. 3, except that the memory device of FIG. 12 and FIG. The connection wiring 362 and the elements for connecting the third transistor to the third wiring 360 and the lower wiring layer (for example, the first wiring layer) in the memory device of FIGS. 12 and 13 are realized with a plurality of layers.

与第一电源布线310相似,第三电源布线350可以供应可是电源电压的第一电压。Similar to the first power supply wiring 310, the third power supply wiring 350 may supply a first voltage which may be a power supply voltage.

外围电路结构可以包括例如可设置在衬底100上的栅结构130和134、源极/漏极区103和105、绝缘层140、160、162和164、接触145、149a、149b和149c、布线150、154a、154b和154c等。The peripheral circuit structure may include, for example, gate structures 130 and 134, source/drain regions 103 and 105, insulating layers 140, 160, 162 and 164, contacts 145, 149a, 149b and 149c, wiring 150, 154a, 154b and 154c, etc.

晶体管(例如第三晶体管)的栅结构134可以包括堆叠在衬底100上的栅绝缘层图案114和栅电极124。源极/漏极区105可以包括n型或p型杂质。包括栅结构134和源极/漏极区105的晶体管(例如第三晶体管)可以被设置并限定在衬底100上。A gate structure 134 of a transistor (eg, a third transistor) may include a gate insulating layer pattern 114 and a gate electrode 124 stacked on the substrate 100 . The source/drain regions 105 may include n-type or p-type impurities. A transistor (eg, a third transistor) including a gate structure 134 and a source/drain region 105 may be provided and defined on the substrate 100 .

第一下绝缘层140可以设置在衬底100上以覆盖诸如晶体管(例如第三晶体管)的结构。第一下接触145可以延伸穿过第一下绝缘层140的一部分,并可以电连接到栅结构130的栅电极120。A first lower insulating layer 140 may be disposed on the substrate 100 to cover structures such as transistors (eg, third transistors). The first lower contact 145 may extend through a portion of the first lower insulating layer 140 and may be electrically connected to the gate electrode 120 of the gate structure 130 .

第一下布线150可以设置在第一下绝缘层140上,并可以电连接到第一下接触145。The first lower wiring 150 may be disposed on the first lower insulating layer 140 and may be electrically connected to the first lower contact 145 .

第二下绝缘层160可以设置在第一下绝缘层140上以覆盖下布线150和154a。第三下绝缘层162可以设置在第二下绝缘层160上以覆盖下布线154b。第四下绝缘层164可以设置在第三下绝缘图案162上以覆盖下布线154c。栅电极124可以通过下接触149a、149b和149c分别电连接到下布线154a、154b和154c。下布线与下接触之间的连接可以根据信号线的布线而变化。The second lower insulating layer 160 may be disposed on the first lower insulating layer 140 to cover the lower wirings 150 and 154a. A third lower insulating layer 162 may be disposed on the second lower insulating layer 160 to cover the lower wiring 154b. A fourth lower insulating layer 164 may be disposed on the third lower insulating pattern 162 to cover the lower wiring 154c. The gate electrode 124 may be electrically connected to lower wirings 154a, 154b, and 154c through lower contacts 149a, 149b, and 149c, respectively. The connection between the lower wiring and the lower contact may vary according to the wiring of the signal line.

存储单元结构可以包括可设置在下布线层上(例如设置在第四下绝缘层164上)的基底层201、沟道225、栅线260a-260f、位线285、绝缘层275和290、接触248a和248c、以及布线310、320、330、332、350、360和362等。The memory cell structure may include a base layer 201, a channel 225, gate lines 260a-260f, a bit line 285, insulating layers 275 and 290, a contact 248a, which may be disposed on a lower wiring layer (for example, disposed on a fourth lower insulating layer 164). and 248c, and wires 310, 320, 330, 332, 350, 360, and 362, and the like.

与第一上接触248a类似,第三上接触248c可以延伸穿过模制保护层212、基底层201以及第四下绝缘层164的一部分。然而,接触248a与248c之间的差异在于第二上接触248c可以与下布线154c接触。与第一绝缘层图案241a可以相对于第一上接触248a如何设置类似,第三绝缘层图案241c可以设置在第三上接触248c的侧壁上。Similar to the first upper contact 248 a , the third upper contact 248 c may extend through the mold protection layer 212 , the base layer 201 , and a portion of the fourth lower insulating layer 164 . However, the difference between the contacts 248a and 248c is that the second upper contact 248c may be in contact with the lower wiring 154c. Similar to how the first insulating layer pattern 241a may be disposed with respect to the first upper contact 248a, the third insulating layer pattern 241c may be disposed on a sidewall of the third upper contact 248c.

与第一插塞291类似,第三插塞295可以延伸穿过第一上绝缘层275并可以与第三上接触248c接触。第三上布线360可以设置在第一上绝缘层275上以分别电连接第三插塞295和第三上接触248c。Similar to the first plug 291, the third plug 295 may extend through the first upper insulating layer 275 and may make contact with the third upper contact 248c. The third upper wiring 360 may be disposed on the first upper insulating layer 275 to electrically connect the third plug 295 and the third upper contact 248c, respectively.

第三晶体管可以通过接触149a、149b、149c和248c、下布线154a、154b和154c以及第三插塞295电连接到第三上布线360。The third transistor may be electrically connected to the third upper wiring 360 through the contacts 149 a , 149 b , 149 c and 248 c , the lower wirings 154 a , 154 b and 154 c , and the third plug 295 .

在本发明构思的示范性实施方式中,布线310、320、330、332、350、360和362可以设置在第一上绝缘层275上的相同的层上(例如设置在俯视图中的相同的平面上)。例如,第一电源布线310、第二电源布线320和第三电源布线350中的每个可以在第二方向D2(例如X轴方向)上延伸,并且第一电源布线310、第二电源布线320和第三电源布线350可以彼此间隔开。第一上布线330可以布置在第一电源布线310和第二电源布线320之间。第三上布线360可以布置在第二电源布线320和第三电源布线350之间。第一连接布线332可以将第一电源布线310与第一上布线330电连接。第三连接布线362可以将第三电源布线350与第三上布线360电连接。如同第一上布线330一样,第三上布线360可以是可电连接到电源布线320和350中的一个。于是,对于第三晶体管的电源选项可以通过改变将第三上布线360与电源布线320和350之一连接的连接布线的布置而基于第三上布线360被有效地且容易地选择。In an exemplary embodiment of the present inventive concept, the wirings 310, 320, 330, 332, 350, 360, and 362 may be disposed on the same layer on the first upper insulating layer 275 (for example, disposed on the same plane in plan view). superior). For example, each of the first power supply wiring 310, the second power supply wiring 320, and the third power supply wiring 350 may extend in the second direction D2 (for example, the X-axis direction), and the first power supply wiring 310, the second power supply wiring 320 and the third power wiring 350 may be spaced apart from each other. The first upper wiring 330 may be disposed between the first power wiring 310 and the second power wiring 320 . The third upper wiring 360 may be disposed between the second power wiring 320 and the third power wiring 350 . The first connection wiring 332 may electrically connect the first power wiring 310 and the first upper wiring 330 . The third connection wiring 362 may electrically connect the third power wiring 350 and the third upper wiring 360 . Like the first upper wiring 330 , the third upper wiring 360 may be electrically connectable to one of the power wirings 320 and 350 . Then, a power supply option for the third transistor can be efficiently and easily selected based on the third upper wiring 360 by changing the arrangement of the connection wiring connecting the third upper wiring 360 with one of the power supply wirings 320 and 350 .

尽管图2、图10和图12示出上布线和电源布线的示例,但是上布线和电源布线的数量、布置和配置不限于此。此外,示出的上布线和电源布线被包括在存储单元阵列上的上布线层(例如第二布线层)中并电连接到外围电路中的晶体管。例如,存储器件的上布线层可以包括在任何方向上延伸并彼此间隔开的任何数目的电源布线、以及电连接到外围电路中的元件(例如晶体管)并可配置为可电连接到电源布线之一的任何数目的上布线。Although FIGS. 2 , 10 , and 12 show examples of upper wiring and power wiring, the number, arrangement, and configuration of the upper wiring and power wiring are not limited thereto. In addition, the upper wiring and the power supply wiring shown are included in an upper wiring layer (for example, a second wiring layer) on the memory cell array and are electrically connected to transistors in the peripheral circuit. For example, the upper wiring layer of the memory device may include any number of power supply wirings extending in any direction and spaced apart from each other, and elements (such as transistors) electrically connected to peripheral circuits and configured to be electrically connectable between the power supply wirings. Any number of upper wires for one.

图14是根据本发明构思的示范性实施方式的存储器件的俯视图。图15是根据本发明构思的示范性实施方式的沿图14的线III-III'截取的剖面图。FIG. 14 is a top view of a memory device according to an exemplary embodiment of the inventive concepts. FIG. 15 is a cross-sectional view taken along line III-III' of FIG. 14 according to an exemplary embodiment of the present inventive concept.

参照图14和图15,存储器件可以包括外围电路区域PCR和存储单元区域MCR,外围电路区域PCR包括设置在衬底100上的外围电路结构,存储单元区域MCR包括设置在外围电路结构上的存储器单元结构。14 and 15, the memory device may include a peripheral circuit region PCR and a memory cell region MCR, the peripheral circuit region PCR includes a peripheral circuit structure disposed on the substrate 100, and the memory cell region MCR includes a memory cell disposed on the peripheral circuit structure cell structure.

图14和图15的存储器件可以与图2和图3的存储器件基本上相同,除了图14和图15的存储器件中的基底层被物理地划分成多个基底层图案并且沟道225和焊盘240的布置在图14和图15的存储器件中改变之外。The memory devices of FIGS. 14 and 15 may be substantially the same as the memory devices of FIGS. 2 and 3, except that the base layer in the memory devices of FIGS. 14 and 15 is physically divided into a plurality of base layer patterns and the channels 225 and The arrangement of the pads 240 is changed in the memory devices of FIGS. 14 and 15 .

为了清楚和简明的描述,存储器件的一些元件没有在图14中示出。例如,图14示出基底层图案201a、201b和201c、分隔层图案206、杂质区域266、焊盘240、模制保护层212、第一电源布线310、第二电源布线320、第一布线330和第一连接布线332,除了上述之外的其它元件被省略。Some elements of the memory device are not shown in FIG. 14 for clarity and conciseness of description. For example, FIG. 14 shows base layer patterns 201a, 201b, and 201c, separation layer patterns 206, impurity regions 266, pads 240, mold protection layer 212, first power supply wiring 310, second power supply wiring 320, first wiring 330 and the first connection wiring 332, other elements than the above are omitted.

存储单元结构可以包括可设置在下布线层上(例如设置在第二下绝缘层160上)的第一基底层图案201a、第二基底层图案201b和第三基底层图案201c、沟道225、栅线260a、260b、260c、260d、260e和260f、位线285、绝缘层275和290以及布线310、320、330和332等。The memory cell structure may include a first base layer pattern 201a, a second base layer pattern 201b, and a third base layer pattern 201c, a channel 225, a gate, and The lines 260a, 260b, 260c, 260d, 260e and 260f, the bit line 285, the insulating layers 275 and 290, the wirings 310, 320, 330 and 332, and the like.

分隔层图案206可以在第二方向D2(例如X轴方向)上延伸,并且多个分隔层图案206可以沿第三方向D3(例如Y轴方向)布置。因此,基底层可以被物理地划分成第一至第三基底层图案201a-201c。图14和图15示出三个基底层图案201a-201c;然而,基底层图案的数目不限于此。分隔层图案206可以包括绝缘层图案,例如硅氧化物。The separation layer pattern 206 may extend in the second direction D2 (eg, the X-axis direction), and the plurality of separation layer patterns 206 may be arranged along the third direction D3 (eg, the Y-axis direction). Accordingly, the base layer may be physically divided into first to third base layer patterns 201a-201c. 14 and 15 illustrate three base layer patterns 201a-201c; however, the number of base layer patterns is not limited thereto. The separation layer pattern 206 may include an insulating layer pattern, such as silicon oxide.

在本发明构思的示范性实施方式中,最下面的绝缘夹层202a可以与分隔层图案206基本上成整体或一体。在本发明构思的示范性实施方式中,分隔层的形成可以被省略,并且最下面的绝缘夹层202a可以填充对应于分隔层图案206的开口并覆盖基底层图案201a-201c。In an exemplary embodiment of the present inventive concept, the lowermost insulating interlayer 202 a may be substantially integrated or integrated with the separation layer pattern 206 . In an exemplary embodiment of the present inventive concept, the formation of the spacer layer may be omitted, and the lowermost insulating interlayer 202a may fill the opening corresponding to the spacer layer pattern 206 and cover the base layer patterns 201a-201c.

基底层图案201a-201c可以包括例如多晶硅或由单晶形成的晶体硅。在本发明构思的示范性实施方式中,基底层图案201a-201c可以进一步包括p型杂质诸如硼(B)。在此示范性实施方式中,基底层图案201a-201c可以用作p型阱。The base layer patterns 201a-201c may include, for example, polysilicon or crystalline silicon formed of a single crystal. In an exemplary embodiment of the inventive concept, the base layer patterns 201a-201c may further include p-type impurities such as boron (B). In this exemplary embodiment, the base layer patterns 201a-201c may serve as p-type wells.

沟道225可以设置在基底层图案201a-201c上,并可以在第一方向D1(例如Z轴方向)上从基底层图案201a-201c的顶表面延伸。在本发明构思的示范性实施方式中,多个沟道225可以布置在第二方向D2(例如X轴方向)上以形成沟道行,并且包括在相邻的沟道行中的沟道225可以以Z字形方式布置而彼此面对。因此,基底层图案201a-201c的单位面积中的沟道225的密度可以增大。The channel 225 may be disposed on the base layer patterns 201a-201c, and may extend from the top surfaces of the base layer patterns 201a-201c in the first direction D1 (eg, the Z-axis direction). In an exemplary embodiment of the present inventive concept, a plurality of channels 225 may be arranged in the second direction D2 (for example, the X-axis direction) to form a channel row, and the channels 225 included in adjacent channel rows may be formed in Arranged in a zigzag manner facing each other. Accordingly, the density of the channels 225 in a unit area of the base layer patterns 201a-201c may be increased.

栅线切割区域256可以沿第一方向D1(例如Z轴方向)穿过栅线260a-260f和绝缘夹层202a-202g设置。栅线切割区域256可以具有在第二方向D2(例如X轴方向)上延伸的沟槽形状或沟渠形状。The gate line cutting region 256 may be disposed along the first direction D1 (eg, the Z-axis direction) through the gate lines 260 a - 260 f and the insulating interlayers 202 a - 202 g. The gate line cutting area 256 may have a groove shape or a ditch shape extending in the second direction D2 (eg, the X-axis direction).

在第二方向D2(例如X轴方向)上延伸的栅线切割图案270可以设置在杂质区域266上。多个杂质区域266和多个栅线切割图案270可以沿第三方向D3(例如Y轴方向)布置。在本发明构思的示范性实施方式中,杂质区域266可以包括n型杂质,例如磷(P)或砷(As)。栅线切割图案270可以包括绝缘层图案,例如硅氧化物。金属硅化物图案诸如钴硅化物图案和/或镍硅化物图案可以进一步设置在杂质区域266上。A gate line cutting pattern 270 extending in the second direction D2 (eg, the X-axis direction) may be disposed on the impurity region 266 . A plurality of impurity regions 266 and a plurality of gate line cutting patterns 270 may be arranged along a third direction D3 (eg, a Y-axis direction). In an exemplary embodiment of the inventive concept, the impurity region 266 may include n-type impurities such as phosphorus (P) or arsenic (As). The gate line cutting pattern 270 may include an insulating layer pattern, such as silicon oxide. A metal silicide pattern such as a cobalt silicide pattern and/or a nickel silicide pattern may be further disposed on the impurity region 266 .

在本发明构思的示范性实施方式中,对于基底层图案201a-201c的每一个可以提供杂质区域266中的一个和栅线切割图案270中的一个。如图15所示,例如,栅线切割区域256可以设置在第二基底层图案201b的中央区域。杂质区域266可以设置在第二基底层图案201b的由栅线切割区域256暴露的上部中,并且填充栅线切割区域256的栅线切割图案270可以在第一方向D1(例如Z轴方向)上设置在杂质区域266上。In an exemplary embodiment of the inventive concept, one of the impurity regions 266 and one of the gate line cutting patterns 270 may be provided for each of the base layer patterns 201a-201c. As shown in FIG. 15, for example, the gate line cutting area 256 may be disposed in the central area of the second base layer pattern 201b. The impurity region 266 may be disposed in an upper portion of the second base layer pattern 201b exposed by the gate line cut region 256, and the gate line cut pattern 270 filling the gate line cut region 256 may be in the first direction D1 (eg, the Z-axis direction). on the impurity region 266 .

在本发明构思的示范性实施方式中,共用栅线260a-260f的单元块可以由栅线切割图案270限定。单元块可以通过分隔层图案206划分成子单元块。因此,单个块的尺寸或大小可以被减小,从而可以实现分段操作控制(segmented operational control)。例如,单元块可以通过分隔层图案206被进一步分割或划分,因此可以防止当单元块的尺寸或大小变得增大时出现的信号干扰或扰动。因此,可以提高存储器件的操作可靠性。In an exemplary embodiment of the inventive concept, the cell blocks sharing the gate lines 260 a - 260 f may be defined by the gate line cutting pattern 270 . The unit block may be divided into sub-unit blocks by the separation layer pattern 206 . Therefore, the size or size of a single block can be reduced, so that segmented operational control can be realized. For example, the unit block may be further divided or divided by the separation layer pattern 206, and thus signal interference or disturbance occurring when the size or size of the unit block becomes increased may be prevented. Therefore, the operational reliability of the memory device can be improved.

上栅线切割图案252可以设置在上栅线切割区域250中。上栅线切割图案252可以包括绝缘材料,例如硅氧化物。An upper gate line cutting pattern 252 may be disposed in the upper gate line cutting region 250 . The upper gate line cutting pattern 252 may include an insulating material such as silicon oxide.

在本发明构思的示范性实施方式中,上栅线切割区域250或上栅线切割图案252可以被提供用于每个单元块中的SSL的分隔。在本发明构思的此示范性实施方式中,上栅线切割区域250或上栅线切割图案252可以延伸穿过最上面的绝缘夹层202g和SSL 260f,并可以部分地延伸穿过直接在SSL 260f下面的绝缘夹层202f。In an exemplary embodiment of the present inventive concept, an upper gate line cut region 250 or an upper gate line cut pattern 252 may be provided for separation of SSLs in each cell block. In this exemplary embodiment of the present inventive concept, the upper gate line cutting region 250 or the upper gate line cutting pattern 252 may extend through the uppermost insulating interlayer 202g and the SSL 260f, and may partially extend through the uppermost insulating interlayer 202g and the SSL 260f. The lower insulating interlayer 202f.

在本发明构思的示范性实施方式中,上布线310、320、330和332可以对应于基底层图案201a-201c的每个布置。In an exemplary embodiment of the inventive concept, the upper wires 310, 320, 330, and 332 may correspond to each arrangement of the base layer patterns 201a-201c.

在本发明构思的示范性实施方式中,包括在图14和图15的存储器件的上布线层(例如图1的第二布线层50)中的上布线和电源布线的数目、布置和配置可以改变。在本发明构思的示范性实施方式中,图14和图15的存储器件的下布线层(例如图1中的第一布线层30)可以用多个层来实现。In an exemplary embodiment of the inventive concept, the number, arrangement, and configuration of upper wirings and power wirings included in an upper wiring layer (for example, the second wiring layer 50 of FIG. 1 ) of the memory device of FIGS. 14 and 15 may be Change. In an exemplary embodiment of the inventive concept, the lower wiring layer (eg, the first wiring layer 30 in FIG. 1 ) of the memory device of FIGS. 14 and 15 may be implemented with a plurality of layers.

图16是示出根据本发明构思的示范性实施方式的存储器件的方框图。FIG. 16 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept.

参照图16,存储器件500可以包括存储单元阵列510、地址解码器520、读写单元530、数据输入/输出(I/O)单元540、电压产生单元550和控制逻辑560。Referring to FIG. 16 , the memory device 500 may include a memory cell array 510 , an address decoder 520 , a read/write unit 530 , a data input/output (I/O) unit 540 , a voltage generation unit 550 and control logic 560 .

在根据本发明构思的示范性实施方式的存储器件500中,存储单元阵列510可以设置在图1中的存储单元区域MCR中,其它元件例如地址解码器520、读写单元530、数据输入/输出(I/O)单元540、电压产生单元550和控制逻辑560可以设置在图1中的外围电路区域PCR中。In the memory device 500 according to the exemplary embodiment of the inventive concept, the memory cell array 510 may be disposed in the memory cell region MCR in FIG. The (I/O) unit 540 , the voltage generating unit 550 and the control logic 560 may be disposed in the peripheral circuit region PCR in FIG. 1 .

存储单元阵列510可以通过字线WL和选择线连接到地址解码器520。例如,选择线可以包括串选择线SSL和接地选择线GSL。存储单元阵列510可以通过位线BL连接到读写单元530。The memory cell array 510 may be connected to an address decoder 520 through a word line WL and a selection line. For example, the selection lines may include a string selection line SSL and a ground selection line GSL. The memory cell array 510 may be connected to a read/write unit 530 through a bit line BL.

存储单元阵列510可以包括多个存储单元。例如,存储单元阵列510可以包括沿行方向和列方向设置的存储单元。例如,存储单元阵列510可以包括多个存储单元,每个单元存储一个或多个数据位。例如,存储单元阵列510可以具有如图4所示的垂直NAND闪存结构。The memory cell array 510 may include a plurality of memory cells. For example, the memory cell array 510 may include memory cells arranged in a row direction and a column direction. For example, memory cell array 510 may include a plurality of memory cells, each storing one or more bits of data. For example, the memory cell array 510 may have a vertical NAND flash memory structure as shown in FIG. 4 .

地址解码器520可以通过字线WL、串选择线SSL和接地选择线GSL连接到存储单元阵列510。地址解码器520可以响应于控制逻辑560的控制而操作。地址解码器520可以从外部装置诸如存储控制器接收地址ADDR。The address decoder 520 may be connected to the memory cell array 510 through a word line WL, a string selection line SSL, and a ground selection line GSL. Address decoder 520 may operate in response to control of control logic 560 . The address decoder 520 may receive an address ADDR from an external device such as a memory controller.

地址解码器520可以解码所接收的地址ADDR中的行地址。地址解码器520可以选择字线WL当中的对应于被解码的行地址的至少一条字线。地址解码器520可以选择包括串选择线SSL和接地选择线GSL的选择线当中的对应于被解码的行地址的至少一条选择线。The address decoder 520 may decode a row address in the received address ADDR. The address decoder 520 may select at least one word line corresponding to the decoded row address among the word lines WL. The address decoder 520 may select at least one selection line corresponding to the decoded row address among selection lines including a string selection line SSL and a ground selection line GSL.

地址解码器520可以将从电压产生单元550接收的各种电压传送到所选择的字线、未选择的字线、所选择的选择线和未选择的选择线。The address decoder 520 may transmit various voltages received from the voltage generating unit 550 to selected word lines, unselected word lines, selected selection lines, and unselected selection lines.

地址解码器520可以解码所接收的地址ADDR中的列地址。此外,地址解码器520可以将解码的列地址DCA传送到读写单元530。The address decoder 520 may decode a column address in the received address ADDR. In addition, the address decoder 520 may transmit the decoded column address DCA to the read and write unit 530 .

在本发明构思的示范性实施方式中,地址解码器520可以包括解码行地址的行解码器、解码列地址的列解码器以及存储所接收的地址ADDR的地址缓冲器。In an exemplary embodiment of the inventive concept, the address decoder 520 may include a row decoder decoding a row address, a column decoder decoding a column address, and an address buffer storing a received address ADDR.

读写单元530可以通过位线BL连接到存储单元阵列510,并可以通过数据线DL连接到数据I/O单元540。读写单元530可以响应于控制逻辑560的控制而操作。读写单元530可以从地址解码器520接收被解码的列地址DCA。基于被解码的列地址DCA,读写单元530可以选择位线BL当中的至少一条位线。The read/write unit 530 may be connected to the memory cell array 510 through the bit line BL, and may be connected to the data I/O unit 540 through the data line DL. The read-write unit 530 may operate in response to the control of the control logic 560 . The read-write unit 530 may receive the decoded column address DCA from the address decoder 520 . Based on the decoded column address DCA, the read/write unit 530 may select at least one bit line among the bit lines BL.

在本发明构思的示范性实施方式中,读写单元530可以从数据I/O单元540接收数据,并可以将所接收的数据写入到存储单元阵列510中。读写单元530可以从存储单元阵列510读取数据,并可以将读取的数据传送到数据I/O单元540。读写单元530可以从存储单元阵列510的第一存储区域读取数据,并可以将读取的数据写入在存储单元阵列510的第二存储区域中。例如,读写单元530可以执行回拷(copy-back)操作。In an exemplary embodiment of the present inventive concept, the read-write unit 530 may receive data from the data I/O unit 540 and may write the received data into the memory cell array 510 . The read-write unit 530 can read data from the memory cell array 510 and transmit the read data to the data I/O unit 540 . The read-write unit 530 can read data from the first storage area of the memory cell array 510 , and can write the read data into the second storage area of the memory cell array 510 . For example, the read-write unit 530 may perform a copy-back operation.

在本发明构思的示范性实施方式中,读写单元530可以包括诸如页缓冲器(或页寄存器)和列选择电路的部件。在本发明构思的示范性实施方式中,读写单元530可以包括诸如感测放大器、写驱动器和列选择电路的部件。In an exemplary embodiment of the inventive concept, the read and write unit 530 may include components such as a page buffer (or page register) and a column selection circuit. In an exemplary embodiment of the inventive concept, the read and write unit 530 may include components such as a sense amplifier, a write driver, and a column selection circuit.

数据I/O单元540可以通过数据线DL连接到读写单元530。数据I/O单元540可以响应于控制逻辑560的控制而操作。数据I/O单元540可以与外部设备交换数据DATA。数据I/O单元540可以通过数据线DL将数据DATA从外部设备传送到读写单元530。数据I/O单元540可以将通过数据线DL从读写单元530传送的数据DATA输出到外部设备。在本发明构思的示范性实施方式中,数据I/O单元540可以包括诸如数据缓冲器的部件。The data I/O unit 540 may be connected to the read/write unit 530 through a data line DL. The data I/O unit 540 may operate in response to the control of the control logic 560 . The data I/O unit 540 may exchange data DATA with external devices. The data I/O unit 540 can transmit data DATA from an external device to the read/write unit 530 through the data line DL. The data I/O unit 540 may output data DATA transferred from the read/write unit 530 through the data line DL to an external device. In an exemplary embodiment of the inventive concept, the data I/O unit 540 may include components such as a data buffer.

电压产生单元550连接到存储单元阵列510、地址解码器520和控制逻辑560。电压产生单元550可以从外部设备接收电力。在本发明构思的示范性实施方式中,电压产生单元550可以从外部设备接收电源电压Vcc和接地电压Vss。基于控制逻辑560的控制,电压产生单元550可以从电源电压Vcc和接地电压Vss产生具有各种电平的电压。在本发明构思的示范性实施方式中,电压产生单元550可以产生各种电压,诸如高电压Vpp、编程电压Vpgm、通过电压Vpass、读取电压Vread和擦除电压Vers。The voltage generating unit 550 is connected to the memory cell array 510 , the address decoder 520 and the control logic 560 . The voltage generation unit 550 may receive power from an external device. In an exemplary embodiment of the inventive concept, the voltage generating unit 550 may receive a power voltage Vcc and a ground voltage Vss from an external device. Based on the control of the control logic 560, the voltage generation unit 550 may generate voltages having various levels from the power supply voltage Vcc and the ground voltage Vss. In an exemplary embodiment of the inventive concept, the voltage generating unit 550 may generate various voltages, such as a high voltage Vpp, a program voltage Vpgm, a pass voltage Vpass, a read voltage Vread, and an erase voltage Vers.

由电压产生单元550产生的电压可以基于控制逻辑560的控制而被供应到地址解码器520和存储单元阵列510。例如,编程电压Vpgm和通过电压Vpass可以在编程操作期间被供应到地址解码器520。读取电压Vread可以在读取操作期间被供应到地址解码器520。擦除电压Vers可以在擦除操作期间被供应到存储单元阵列510。The voltage generated by the voltage generating unit 550 may be supplied to the address decoder 520 and the memory cell array 510 based on the control of the control logic 560 . For example, a program voltage Vpgm and a pass voltage Vpass may be supplied to the address decoder 520 during a program operation. The read voltage Vread may be supplied to the address decoder 520 during a read operation. An erase voltage Vers may be supplied to the memory cell array 510 during an erase operation.

由电压产生单元550产生的电压不限于上述电压。The voltage generated by the voltage generating unit 550 is not limited to the above-mentioned voltage.

控制逻辑560可以连接到地址解码器520、读写单元530和数据I/O单元540。控制逻辑560可以控制存储器件500的一般操作。控制逻辑560可以响应于从外部设备传送的控制信号CTRL而操作。The control logic 560 may be connected to the address decoder 520 , the read/write unit 530 and the data I/O unit 540 . The control logic 560 may control general operations of the memory device 500 . The control logic 560 may operate in response to a control signal CTRL transmitted from an external device.

图17和图18是示出根据本发明构思的示范性实施方式的存储器封装的图。17 and 18 are diagrams illustrating a memory package according to an exemplary embodiment of the inventive concept.

参照图17,存储器封装700包括基底基板710和堆叠在基底基板710上的多个存储芯片CHP1、CHP2和CHP3。Referring to FIG. 17 , the memory package 700 includes a base substrate 710 and a plurality of memory chips CHP1 , CHP2 and CHP3 stacked on the base substrate 710 .

存储芯片CHP1-CHP3的每个可以包括外围电路区域PCR和存储单元区域MCR,并且还可以包括多个I/O焊盘IOPAD。外围电路区域PCR可以包括半导体衬底、设置在半导体衬底的第一表面(例如顶表面)上的外围电路、以及设置在外围电路上的第一布线层。此外,外围电路可以包括至少一个晶体管。存储单元区域MCR可以包括设置在第一布线层上的基底层、设置在基底层上的存储单元阵列、以及在存储单元阵列上的第二布线层。所述多个I/O焊盘IOPAD可以设置在第二布线层上。Each of the memory chips CHP1-CHP3 may include a peripheral circuit region PCR and a memory cell region MCR, and may further include a plurality of I/O pads IOPAD. The peripheral circuit region PCR may include a semiconductor substrate, a peripheral circuit disposed on a first surface (eg, a top surface) of the semiconductor substrate, and a first wiring layer disposed on the peripheral circuit. Furthermore, the peripheral circuit may include at least one transistor. The memory cell region MCR may include a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer on the memory cell array. The plurality of I/O pads IOPAD may be disposed on the second wiring layer.

存储芯片CHP1-CHP3的每个可以用根据本发明构思的示范性实施方式的存储器件来实现。例如,存储芯片CHP1-CHP3的每个中的第二布线层(例如上布线层)可以包括电连接到外围电路中的至少一个晶体管的至少一个上布线。所述至少一个上布线可以是可电连接到电源布线中的一个,因此对于所述至少一个晶体管的电源选项可以通过改变电源布线之一和上布线的连接而基于所述至少一个上布线被有效地且容易地选择。Each of the memory chips CHP1-CHP3 may be implemented with a memory device according to an exemplary embodiment of the inventive concept. For example, a second wiring layer (for example, an upper wiring layer) in each of the memory chips CHP1-CHP3 may include at least one upper wiring electrically connected to at least one transistor in the peripheral circuit. The at least one upper wiring may be electrically connectable to one of the power supply wirings, whereby a power supply option for the at least one transistor may be enabled based on the at least one upper wiring by changing a connection between one of the power supply wirings and the upper wiring. Choose easily and easily.

在本发明构思的示范性实施方式中,存储芯片CHP1-CHP3可以堆叠在基底基板710上使得其上可设置所述多个I/O焊盘IOPAD的表面面朝上。例如,存储芯片CHP1-CHP3可以以下侧向下的状态堆叠使得每个存储芯片的半导体衬底730的第二表面(例如底表面)面朝下。换言之,相对于存储芯片CHP1-CHP3的每个,存储单元区域MCR可以位于外围电路区域PCR上。In an exemplary embodiment of the inventive concept, the memory chips CHP1 - CHP3 may be stacked on the base substrate 710 such that a surface on which the plurality of I/O pads IOPAD may be disposed faces upward. For example, the memory chips CHP1-CHP3 may be stacked in a downside-down state such that the second surface (eg, bottom surface) of the semiconductor substrate 730 of each memory chip faces down. In other words, the memory cell region MCR may be located on the peripheral circuit region PCR with respect to each of the memory chips CHP1-CHP3.

在本发明构思的示范性实施方式中,相对于存储芯片CHP1-CHP3的每个,所述多个I/O焊盘IOPAD可以靠近半导体衬底的一侧布置。因而,存储芯片CHP1-CHP3可以阶梯状地堆叠,即以台阶形状堆叠,使得每个存储芯片的所述多个I/O焊盘IOPAD可以被暴露(例如所述多个I/O焊盘IOPAD可以在每个台阶的边缘上被暴露)。在这样的堆叠状态中,存储芯片CHP1-CHP3可以通过多个接合线BW电连接到基底基板710。In an exemplary embodiment of the inventive concept, the plurality of I/O pads IOPAD may be arranged near one side of the semiconductor substrate with respect to each of the memory chips CHP1-CHP3. Thus, the memory chips CHP1-CHP3 can be stacked in steps, that is, stacked in a step shape, so that the plurality of I/O pads IOPAD of each memory chip can be exposed (for example, the plurality of I/O pads IOPAD may be exposed on the edge of each step). In such a stacked state, the memory chips CHP1-CHP3 may be electrically connected to the base substrate 710 through a plurality of bonding wires BW.

堆叠的存储芯片CHP1-CHP3和接合线BW可以通过密封构件740固定,并且粘合构件730可以介于基底基板710与存储芯片CHP1-CHP3之间。导电凸块720可以设置在基底基板710的底表面上用于电连接到外部设备。The stacked memory chips CHP1-CHP3 and the bonding wires BW may be fixed by a sealing member 740, and an adhesive member 730 may be interposed between the base substrate 710 and the memory chips CHP1-CHP3. Conductive bumps 720 may be disposed on the bottom surface of the base substrate 710 for electrical connection to external devices.

参照图18,存储器封装700a包括基底基板710和堆叠在基底基板710上的多个存储芯片CHP1'、CHP2'和CHP3'。Referring to FIG. 18 , a memory package 700 a includes a base substrate 710 and a plurality of memory chips CHP1 ′, CHP2 ′, and CHP3 ′ stacked on the base substrate 710 .

图18的存储器封装700a可以与图17的存储器封装700基本上相同,除了多个I/O焊盘IOPAD'的布置和存储芯片CHP1'-CHP3'的堆叠结构在图18的存储器封装700a中改变之外。The memory package 700a of FIG. 18 may be substantially the same as the memory package 700 of FIG. 17, except that the arrangement of the plurality of I/O pads IOPAD' and the stacked structure of the memory chips CHP1'-CHP3' are changed in the memory package 700a of FIG. outside.

存储芯片CHP1'-CHP3'的每个可以包括外围电路区域PCR和存储单元区域MCR,并且还可以包括所述多个I/O焊盘IOPAD'。外围电路区域PCR可以包括半导体衬底、设置在半导体衬底的第一表面(例如顶表面或上表面)上的外围电路、以及设置在外围电路上的第一布线层。外围电路可以包括至少一个晶体管。存储单元区域MCR可以包括设置在第一布线层上的基底层、设置在基底层上的存储单元阵列、以及在存储单元阵列上的第二布线层。Each of the memory chips CHP1'-CHP3' may include a peripheral circuit region PCR and a memory cell region MCR, and may further include the plurality of I/O pads IOPAD'. The peripheral circuit region PCR may include a semiconductor substrate, a peripheral circuit disposed on a first surface (eg, a top surface or an upper surface) of the semiconductor substrate, and a first wiring layer disposed on the peripheral circuit. The peripheral circuit may include at least one transistor. The memory cell region MCR may include a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer on the memory cell array.

所述多个I/O焊盘IOPAD'可以设置在半导体衬底的与半导体衬底的第一表面相反的第二表面(例如底表面)上。I/O焊盘IOPAD'可以覆盖设置在外围电路区域PCR中的贯穿衬底通路(through-substrate via)TSV。然后,I/O焊盘IOPAD'可以电连接到包括在外围电路区域PCR的第一布线层(例如下布线层)中的至少一个下布线。The plurality of I/O pads IOPAD' may be disposed on a second surface (eg, a bottom surface) of the semiconductor substrate opposite to the first surface of the semiconductor substrate. The I/O pad IOPAD′ may cover a through-substrate via TSV disposed in the peripheral circuit region PCR. Then, the I/O pad IOPAD' may be electrically connected to at least one lower wiring included in the first wiring layer (eg, lower wiring layer) of the peripheral circuit region PCR.

相对于存储芯片CHP1'-CHP3'的每个,所述多个I/O焊盘IOPAD'可以在垂直方向上与存储单元区域MCR的其中设置存储单元阵列的部分重叠。The plurality of I/O pads IOPAD' may vertically overlap a portion of the memory cell region MCR in which the memory cell array is disposed, with respect to each of the memory chips CHP1'-CHP3'.

在本发明构思的一些示范性实施方式中,存储芯片CHP1'-CHP3'可以堆叠在基底基板710上使得其上可设置所述多个I/O焊盘IOPAD'的表面面朝上。例如,存储芯片CHP1'-CHP3'可以以倒置的状态被堆叠使得每个存储芯片的半导体衬底的第二表面(例如底表面)面朝上。换言之,相对于存储芯片CHP1'-CHP3'的每个,存储单元区域MCR可以位于外围电路区域PCR下面。In some exemplary embodiments of the inventive concepts, the memory chips CHP1 ′-CHP3 ′ may be stacked on the base substrate 710 such that a surface on which the plurality of I/O pads IOPAD′ may be disposed faces upward. For example, the memory chips CHP1'-CHP3' may be stacked in an inverted state such that the second surface (eg, bottom surface) of the semiconductor substrate of each memory chip faces upward. In other words, the memory cell region MCR may be located under the peripheral circuit region PCR with respect to each of the memory chips CHP1'-CHP3'.

图19是示出根据本发明构思的示范性实施方式的固态盘或固态硬盘(SSD)的方框图。FIG. 19 is a block diagram illustrating a solid state disk or a solid state drive (SSD) according to an exemplary embodiment of the inventive concept.

参照图19,SSD 1000可以包括多个非易失性存储器件1100和SSD控制器1200。Referring to FIG. 19 , an SSD 1000 may include a plurality of nonvolatile memory devices 1100 and an SSD controller 1200 .

可选地,非易失性存储器件1100可以被供应有外部高电压VPP。非易失性存储器件1100的每个可以包括上述垂直NAND闪存器件。非易失性存储器件1100可以具有根据本发明构思的示范性实施方式的COP结构和包括上布线的上布线层,如参照图1至18所述。Alternatively, the nonvolatile memory device 1100 may be supplied with an external high voltage VPP. Each of the nonvolatile memory devices 1100 may include the above-mentioned vertical NAND flash memory device. The nonvolatile memory device 1100 may have a COP structure according to an exemplary embodiment of the inventive concept and an upper wiring layer including an upper wiring, as described with reference to FIGS. 1 to 18 .

SSD控制器1200可以通过多个通道CH1、CH2、CH3……CHi连接到非易失性存储器件1100。SSD控制器1200可以包括一个或多个处理器1210、缓冲存储器1220、错误校正码(ECC)块1230、主机接口1250和非易失性存储器接口1260。The SSD controller 1200 may be connected to the nonvolatile memory device 1100 through a plurality of channels CH1, CH2, CH3 . . . CHi. SSD controller 1200 may include one or more processors 1210 , buffer memory 1220 , error correction code (ECC) block 1230 , host interface 1250 and nonvolatile memory interface 1260 .

缓冲存储器1220可以存储用于驱动SSD控制器1200的数据。缓冲存储器1220可以包括每条存储数据或指令的多条存储线。尽管图19示出本发明构思的示范性实施方式(其中缓冲存储器1220被包括在SSD控制器1200中),但是本发明构思不限于此。例如,缓冲存储器1220可以位于SSD控制器1200外面。The buffer memory 1220 may store data for driving the SSD controller 1200 . Cache memory 1220 may include multiple memory lines each storing data or instructions. Although FIG. 19 illustrates an exemplary embodiment of the inventive concept in which the cache memory 1220 is included in the SSD controller 1200, the inventive concept is not limited thereto. For example, the cache memory 1220 may be located outside the SSD controller 1200 .

ECC块1230可以计算数据的错误校正码值并可以在编程操作期间被编程,并且可以在读取操作期间使用错误校正码值来校正读取的数据的错误。在数据恢复操作中,ECC块1230可以校正从非易失性存储器件1100恢复的数据的错误。此外,代码存储器还可以被包括以存储驱动SSD控制器1200所需要的代码数据。代码存储器可以由非易失性存储器件来实现。The ECC block 1230 may calculate an error correction code value of data and may be programmed during a program operation, and may correct errors of read data using the error correction code value during a read operation. In a data recovery operation, the ECC block 1230 may correct errors of data recovered from the nonvolatile memory device 1100 . In addition, a code memory may also be included to store code data required to drive the SSD controller 1200 . Code memory can be implemented by non-volatile memory devices.

主机接口1250可以提供与外部设备的接口。非易失性存储器(NVM)接口1260可以提供与非易失性存储器件1100的接口。The host interface 1250 may provide an interface with external devices. A non-volatile memory (NVM) interface 1260 may provide an interface with the non-volatile memory device 1100 .

图20是示出根据本发明构思的示范性实施方式的嵌入式多媒体卡(eMMC)的方框图。FIG. 20 is a block diagram illustrating an embedded multimedia card (eMMC) according to an exemplary embodiment of the inventive concept.

参照图20,eMMC 2000可以包括一个或多个NAND闪存器件2100和控制器2200。Referring to FIG. 20 , an eMMC 2000 may include one or more NAND flash memory devices 2100 and a controller 2200 .

如参照图1至图18所述,根据本发明构思的示范性实施方式,NAND闪存器件2100可以具有COP结构和包括上布线的上布线层。As described with reference to FIGS. 1 to 18 , according to an exemplary embodiment of the inventive concept, the NAND flash memory device 2100 may have a COP structure and an upper wiring layer including an upper wiring.

控制器2200可以经由多个通道与NAND闪存器件2100连接。控制器2200可以包括一个或多个控制器核心2210、主机接口2250和NAND接口2260。控制器核心2210可以控制eMMC2000的整个操作。主机接口2250可以提供控制器2200与主机2010之间的接口。NAND接口2260可以提供NAND闪存器件2100与控制器2200之间的接口。The controller 2200 may be connected with the NAND flash memory device 2100 via a plurality of channels. The controller 2200 may include one or more controller cores 2210 , a host interface 2250 and a NAND interface 2260 . The controller core 2210 can control the entire operation of the eMMC2000. The host interface 2250 may provide an interface between the controller 2200 and the host 2010 . The NAND interface 2260 may provide an interface between the NAND flash memory device 2100 and the controller 2200 .

在本发明构思的示范性实施方式中,主机接口2250可以是并行接口(例如MMC接口)。在本发明构思的另一些示范性实施方式中,主机接口2250可以是串行接口(例如UHS-II、UFS等)。In an exemplary embodiment of the inventive concept, the host interface 2250 may be a parallel interface (eg, an MMC interface). In other exemplary embodiments of the present inventive concepts, the host interface 2250 may be a serial interface (eg, UHS-II, UFS, etc.).

eMMC 2000可以从主机2010接收电源电压VCC和VCCq。例如,电源电压VCC(例如约3.3V)可以被供应到NAND闪存器件2100和NAND接口2260,电源电压VCCq(例如约1.8V/3.3V)可以被供应到控制器2200。在本发明构思的示范性实施方式中,可选地,eMMC 2000可以被供应有外部高电压VPP。此外,可选地,外部高电压VPP可以被供应到NAND闪存器件2100。The eMMC 2000 may receive power supply voltages VCC and VCCq from the host 2010 . For example, a power supply voltage VCC (eg, about 3.3V) may be supplied to the NAND flash memory device 2100 and the NAND interface 2260 , and a power supply voltage VCCq (eg, about 1.8V/3.3V) may be supplied to the controller 2200 . In an exemplary embodiment of the inventive concept, optionally, the eMMC 2000 may be supplied with an external high voltage VPP. Also, optionally, an external high voltage VPP may be supplied to the NAND flash memory device 2100 .

图21是示出根据本发明构思的示范性实施例方式的通用闪速存储器(UFS)的方框图。FIG. 21 is a block diagram illustrating a universal flash memory (UFS) according to an exemplary embodiment mode of the inventive concept.

参照图21,UFS系统3000可以包括UFS主机3100、UFS器件3200和3300、嵌入式UFS器件3400以及可移除UFS卡3500。Referring to FIG. 21 , a UFS system 3000 may include a UFS host 3100 , UFS devices 3200 and 3300 , an embedded UFS device 3400 , and a removable UFS card 3500 .

UFS主机3100可以是移动设备的应用处理器。UFS主机3100、UFS器件3200和3300、嵌入式UFS器件3400以及可移除UFS卡3500的每个可以通过UFS协议与外部设备通信。UFS器件3200和3300、嵌入式UFS器件3400以及可移除UFS卡3500中的至少一个可以由非易失性存储器件来实现。如参照图1至图18所述,根据本发明构思的示范性实施方式,非易失性存储器件可以具有COP结构和包括上布线的上布线层。UFS host 3100 may be an application processor of a mobile device. Each of the UFS host 3100, the UFS devices 3200 and 3300, the embedded UFS device 3400, and the removable UFS card 3500 may communicate with external devices through the UFS protocol. At least one of the UFS devices 3200 and 3300, the embedded UFS device 3400, and the removable UFS card 3500 may be implemented by a nonvolatile memory device. As described with reference to FIGS. 1 to 18 , according to an exemplary embodiment of the inventive concept, a nonvolatile memory device may have a COP structure and an upper wiring layer including an upper wiring.

嵌入式UFS器件3400和可移除UFS卡3500可以使用不同于UFS协议的协议来进行通信。UFS主机3100和可移除UFS卡3500可以通过各种卡协议(例如UFD、MMC、安全数字(SD)、迷你SD、微型SD等)通信。Embedded UFS device 3400 and removable UFS card 3500 may communicate using a protocol other than the UFS protocol. The UFS host 3100 and the removable UFS card 3500 can communicate through various card protocols (eg, UFD, MMC, Secure Digital (SD), mini SD, micro SD, etc.).

图22是示出根据本发明构思的示范性实施方式的移动设备的方框图。FIG. 22 is a block diagram illustrating a mobile device according to an exemplary embodiment of the inventive concept.

参照图22,移动设备4000可以包括应用处理器4100、通信模块4200、显示/触摸模块4300、存储器件4400和移动随机存取存储器(RAM)(例如缓冲RAM)4500。Referring to FIG. 22 , a mobile device 4000 may include an application processor 4100 , a communication module 4200 , a display/touch module 4300 , a storage device 4400 , and a mobile random access memory (RAM) (eg, buffer RAM) 4500 .

应用处理器4100可以控制移动设备4000的操作。通信模块4200可以被实现为执行与外部设备的无线或有线通信。显示/触摸模块4300可以被实现为显示由应用处理器4100处理的数据或者被实现为通过触摸面板接收数据。存储器件4400可以被实现为存储用户数据。移动RAM(例如缓冲RAM)4500可以临时存储用于移动设备4000的处理操作的数据。The application processor 4100 may control operations of the mobile device 4000 . The communication module 4200 may be implemented to perform wireless or wired communication with external devices. The display/touch module 4300 may be implemented to display data processed by the application processor 4100 or to receive data through a touch panel. The storage device 4400 may be implemented to store user data. The mobile RAM (eg buffer RAM) 4500 may temporarily store data for processing operations of the mobile device 4000 .

在本发明构思的示范性实施方式中,存储器件4400可以是例如eMMC、SSD、UFS器件等。存储器件4400可以包括非易失性存储器件。如参照图1至18所述,根据本发明构思的示范性实施方式,非易失性存储器件可以具有COP结构和包括上布线的上布线层。In an exemplary embodiment of the inventive concept, the storage device 4400 may be, for example, eMMC, SSD, UFS device, or the like. The memory device 4400 may include a nonvolatile memory device. As described with reference to FIGS. 1 to 18 , according to an exemplary embodiment of the inventive concept, a nonvolatile memory device may have a COP structure and an upper wiring layer including an upper wiring.

根据本发明构思的示范性实施方式的存储器件或存储装置可以使用各种封装类型或封装构造来封装,诸如层叠封装(PoP)、球栅阵列(BGA)、芯片级封装(CSP)、带引线的塑料芯片载体(PLCC)、塑料双列直插式封装(PDIP)、华夫管芯封装(Die in Waffle Pack)、晶圆式管芯(Die in Wafer form)、板上芯片(COB)、陶瓷双列直插封装(CERDIP)、塑料公制四方扁平封装(MQFP)、薄四方扁平封装(TQFP)、小外形集成电路(SOIC)、窄间距小外形封装(SSOP)、薄小外形封装(TSOP)、系统级封装(SIP)、多芯片封装(MCP)、晶圆级制造封装(WFP)、晶圆级处理堆叠封装(WSP)等。A memory device or a memory device according to an exemplary embodiment of the present inventive concept may be packaged using various package types or package configurations, such as package on package (PoP), ball grid array (BGA), chip scale package (CSP), leaded Plastic chip carrier (PLCC), plastic dual in-line package (PDIP), waffle die package (Die in Waffle Pack), wafer die (Die in Wafer form), chip on board (COB), Ceramic Dual Inline Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Narrow Pitch Small Outline Package (SSOP), Thin Small Outline Package (TSOP) ), System-in-Package (SIP), Multi-Chip Package (MCP), Wafer-Level Manufacturing Package (WFP), Wafer-Level Processing Stacked Package (WSP), etc.

本公开可以应用于各种设备和系统。例如,本公开可以应用于系统诸如移动电话、智能手机、个人数字助理(PDA)、便携式多媒体播放器(PMP)、数字照相机、摄像机、个人计算机(PC)、服务器计算机、工作站、膝上型计算机、数字TV、机顶盒、便携式游戏控制台、导航系统等。The present disclosure can be applied to various devices and systems. For example, the present disclosure can be applied to systems such as mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video cameras, personal computers (PCs), server computers, workstations, laptop computers , digital TV, set-top boxes, portable game consoles, navigation systems, etc.

以上内容是对本发明构思的示范性实施方式的说明,而不应被解释为对其进行限制。尽管已经描述了一些示范性实施方式,但是本领域技术人员将容易地理解,在示范性实施方式中可以有许多修改,而在实质上没有背离本公开的新颖教导。因此,所有这样的修改旨在被包括在本公开的如权利要求书中限定的范围内。因此,将理解,以上内容是对各种示范性实施方式的说明,而不应被解释为限于所公开的特定示范性实施方式,并且对所公开的示范性实施方式的修改以及另外的示范性实施方式旨在被包括在权利要求书的范围内。The foregoing is a description of exemplary embodiments of the present inventive concept and should not be construed as limiting the same. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. Accordingly, it is to be understood that the foregoing is a description of various exemplary embodiments, and that it is not to be construed as limited to the particular exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as additional exemplary Embodiments are intended to be included within the scope of the claims.

Claims (19)

1.一种存储器件,包括:1. A storage device, comprising: 衬底;Substrate; 外围电路,设置在所述衬底的第一表面上,其中所述外围电路包括第一晶体管;peripheral circuitry disposed on the first surface of the substrate, wherein the peripheral circuitry includes a first transistor; 第一布线层,设置在所述外围电路上;a first wiring layer disposed on the peripheral circuit; 基底层,设置在所述第一布线层上;a base layer disposed on the first wiring layer; 存储单元阵列,设置在所述基底层上;以及an array of memory cells disposed on the base layer; and 第二布线层,设置在所述存储单元阵列上,其中所述第二布线层包括:A second wiring layer disposed on the memory cell array, wherein the second wiring layer includes: 第一电源布线,配置为供应第一电压;a first power wiring configured to supply a first voltage; 第二电源布线,配置为供应第二电压;a second power supply wiring configured to supply a second voltage; 第一布线,电连接到所述第一晶体管,其中所述第一布线配置为可电连接到所述第一电源布线或所述第二电源布线;以及a first wiring electrically connected to the first transistor, wherein the first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring; and 第一连接布线,将所述第一布线电连接到所述第一电源布线或所述第二电源布线,a first connection wiring electrically connecting the first wiring to the first power supply wiring or the second power supply wiring, 其中所述第一电源布线和所述第二电源布线的每个在第一方向上延伸,并且所述第一电源布线和所述第二电源布线彼此间隔开,wherein each of the first power supply wiring and the second power supply wiring extends in a first direction, and the first power supply wiring and the second power supply wiring are spaced apart from each other, 其中所述第一布线设置在所述第一电源布线和所述第二电源布线之间,在所述第一布线通过所述第一连接布线电连接到所述第一电源布线的情况下,所述第一电压通过所述第一布线供应到所述第一晶体管,以及wherein the first wiring is provided between the first power supply wiring and the second power supply wiring, and in a case where the first wiring is electrically connected to the first power supply wiring through the first connection wiring, the first voltage is supplied to the first transistor through the first wiring, and 在所述第一布线通过所述第一连接布线电连接到所述第二电源布线的情况下,所述第二电压通过所述第一布线供应到所述第一晶体管。In a case where the first wiring is electrically connected to the second power supply wiring through the first connection wiring, the second voltage is supplied to the first transistor through the first wiring. 2.如权利要求1所述的存储器件,其中所述第一电源布线和所述第二电源布线、所述第一布线和第一连接布线设置在相同的平面上。2. The memory device according to claim 1, wherein the first power supply wiring and the second power supply wiring, the first wiring and the first connection wiring are arranged on the same plane. 3.如权利要求1所述的存储器件,其中所述第一布线电连接到所述第一晶体管的栅电极。3. The memory device according to claim 1, wherein the first wiring is electrically connected to a gate electrode of the first transistor. 4.如权利要求3所述的存储器件,还包括:4. The memory device of claim 3, further comprising: 第一接触和第二接触,穿过包括在所述第一布线层中的绝缘层的一部分设置。The first contact and the second contact are provided through a part of the insulating layer included in the first wiring layer. 5.如权利要求4所述的存储器件,其中所述第一接触将所述第一晶体管的所述栅电极与包括在所述第一布线层中的第二布线电连接,5. The memory device according to claim 4, wherein the first contact electrically connects the gate electrode of the first transistor with a second wiring included in the first wiring layer, 其中所述第二接触将所述第一布线与所述第二布线电连接。Wherein the second contact electrically connects the first wiring and the second wiring. 6.如权利要求1所述的存储器件,其中所述外围电路还包括第二晶体管,6. The memory device of claim 1, wherein the peripheral circuit further comprises a second transistor, 其中所述第二布线层还包括电连接到所述第二晶体管的第二布线,其中所述第二布线配置为可电连接到所述第一电源布线或所述第二电源布线。The second wiring layer further includes a second wiring electrically connected to the second transistor, wherein the second wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring. 7.如权利要求1所述的存储器件,其中所述外围电路还包括第二晶体管,7. The memory device of claim 1, wherein the peripheral circuit further comprises a second transistor, 其中所述第二布线层还包括:Wherein the second wiring layer also includes: 第三电源布线,配置为供应所述第一电压;a third power wiring configured to supply the first voltage; 第二布线,电连接到所述第二晶体管,所述第二布线配置为可电连接到所述第二电源布线或所述第三电源布线;以及a second wiring electrically connected to the second transistor, the second wiring being configured to be electrically connectable to the second power supply wiring or the third power supply wiring; and 第二连接布线,将所述第二布线电连接到所述第二电源布线或所述第三电源布线。A second connection wiring electrically connects the second wiring to the second power supply wiring or the third power supply wiring. 8.如权利要求7所述的存储器件,其中所述第一电源布线、所述第二电源布线和所述第三电源布线的每个在第一方向上延伸,并且所述第一电源布线、所述第二电源布线和所述第三电源布线彼此间隔开,8. The memory device according to claim 7, wherein each of the first power supply wiring, the second power supply wiring, and the third power supply wiring extends in a first direction, and the first power supply wiring , the second power supply wiring and the third power supply wiring are spaced apart from each other, 所述第二布线布置在所述第二电源布线和所述第三电源布线之间。The second wiring is arranged between the second power supply wiring and the third power supply wiring. 9.如权利要求1所述的存储器件,其中所述第一电压是电源电压,所述第二电压是接地电压。9. The memory device of claim 1, wherein the first voltage is a power supply voltage, and the second voltage is a ground voltage. 10.如权利要求1所述的存储器件,其中所述基底层包括多晶硅或单晶硅。10. The memory device of claim 1, wherein the base layer comprises polysilicon or single crystal silicon. 11.如权利要求10所述的存储器件,其中所述基底层被划分成多个基底层图案,并且所述多个基底层图案的每个用作p型阱。11. The memory device of claim 10, wherein the base layer is divided into a plurality of base layer patterns, and each of the plurality of base layer patterns functions as a p-type well. 12.如权利要求1所述的存储器件,其中所述存储单元阵列包括多个垂直NAND闪存单元。12. The memory device of claim 1, wherein the array of memory cells comprises a plurality of vertical NAND flash memory cells. 13.如权利要求1所述的存储器件,其中所述存储单元阵列包括:13. The memory device of claim 1, wherein the memory cell array comprises: 多个沟道,在垂直于所述第一表面的第一方向上延伸;和a plurality of channels extending in a first direction perpendicular to the first surface; and 多条栅线,围绕所述沟道的外侧壁,所述多条栅线堆叠在所述第一方向上并彼此间隔开。A plurality of gate lines surrounds the outer sidewall of the trench, the plurality of gate lines are stacked in the first direction and spaced apart from each other. 14.一种存储器封装,包括:14. A memory package comprising: 基底基板;以及base substrate; and 多个存储芯片,堆叠在所述基底基板上,所述多个存储芯片的每个包括:a plurality of memory chips stacked on the base substrate, each of the plurality of memory chips comprising: 衬底;Substrate; 外围电路,设置在所述衬底的第一表面上,其中所述外围电路包括第一晶体管;peripheral circuitry disposed on the first surface of the substrate, wherein the peripheral circuitry includes a first transistor; 第一布线层,设置在所述外围电路上;a first wiring layer disposed on the peripheral circuit; 基底层,设置在所述第一布线层上;a base layer disposed on the first wiring layer; 存储单元阵列,设置在所述基底层上;以及an array of memory cells disposed on the base layer; and 第二布线层,设置在所述存储单元阵列上,其中所述第二布线层包括:A second wiring layer disposed on the memory cell array, wherein the second wiring layer includes: 第一电源布线,配置为供应第一电压;a first power wiring configured to supply a first voltage; 第二电源布线,配置为供应第二电压;a second power supply wiring configured to supply a second voltage; 第一布线,电连接到所述第一晶体管,其中所述第一布线配置为可电连接到所述第一电源布线或所述第二电源布线;以及a first wiring electrically connected to the first transistor, wherein the first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring; and 第一连接布线,将所述第一布线电连接到所述第一电源布线或所述第二电源布线,a first connection wiring electrically connecting the first wiring to the first power supply wiring or the second power supply wiring, 其中所述第一电源布线和所述第二电源布线的每个在第一方向上延伸,并且所述第一电源布线和所述第二电源布线彼此间隔开,wherein each of the first power supply wiring and the second power supply wiring extends in a first direction, and the first power supply wiring and the second power supply wiring are spaced apart from each other, 其中所述第一布线设置在所述第一电源布线和所述第二电源布线之间,在所述第一布线通过所述第一连接布线电连接到所述第一电源布线的情况下,所述第一电压通过所述第一布线供应到所述第一晶体管,以及wherein the first wiring is provided between the first power supply wiring and the second power supply wiring, and in a case where the first wiring is electrically connected to the first power supply wiring through the first connection wiring, the first voltage is supplied to the first transistor through the first wiring, and 在所述第一布线通过所述第一连接布线电连接到所述第二电源布线的情况下,所述第二电压通过所述第一布线供应到所述第一晶体管。In a case where the first wiring is electrically connected to the second power supply wiring through the first connection wiring, the second voltage is supplied to the first transistor through the first wiring. 15.一种存储器件,包括:15. A memory device comprising: 衬底;Substrate; 外围电路,设置在所述衬底的第一表面上,所述外围电路包括第一晶体管和第二晶体管;a peripheral circuit disposed on the first surface of the substrate, the peripheral circuit including a first transistor and a second transistor; 下布线层,设置在所述外围电路上;a lower wiring layer disposed on the peripheral circuit; 基底层,设置在所述下布线层上;a base layer disposed on the lower wiring layer; 存储单元阵列,设置在所述基底层上,其中所述存储单元阵列包括多个沟道;以及a memory cell array disposed on the base layer, wherein the memory cell array includes a plurality of channels; and 上布线层,设置在所述存储单元阵列上,其中所述上布线层包括:The upper wiring layer is arranged on the memory cell array, wherein the upper wiring layer includes: 至少两个电源布线,其中所述至少两个电源布线中的第一电源布线配置为供应第一电压并且所述至少两个电源布线中的第二电源布线配置为供应第二电压;at least two power supply wirings, wherein a first of the at least two power supply wirings is configured to supply a first voltage and a second of the at least two power supply wirings is configured to supply a second voltage; 第一布线,电连接到所述第一晶体管,其中所述第一布线配置为可电连接到所述第一电源布线或所述第二电源布线;a first wiring electrically connected to the first transistor, wherein the first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring; 第二布线,电连接到所述第二晶体管,其中所述第二布线配置为可电连接到所述第一电源布线或所述第二电源布线;a second wiring electrically connected to the second transistor, wherein the second wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring; 第一连接布线,将所述第一布线电连接到所述第一电源布线或所述第二电源布线;以及a first connection wiring electrically connecting the first wiring to the first power supply wiring or the second power supply wiring; and 第二连接布线,将所述第二布线电连接到所述第一电源布线或所述第二电源布线,second connection wiring electrically connecting the second wiring to the first power supply wiring or the second power supply wiring, 其中所述第一电源布线和所述第二电源布线的每个在第一方向上延伸,并且所述第一电源布线和所述第二电源布线彼此间隔开,wherein each of the first power supply wiring and the second power supply wiring extends in a first direction, and the first power supply wiring and the second power supply wiring are spaced apart from each other, 其中所述第一布线和所述第二布线设置在所述第一电源布线和所述第二电源布线之间,wherein the first wiring and the second wiring are provided between the first power wiring and the second power wiring, 在所述第一布线通过所述第一连接布线电连接到所述第一电源布线的情况下,所述第一电压通过所述第一布线供应到所述第一晶体管,以及In a case where the first wiring is electrically connected to the first power supply wiring through the first connection wiring, the first voltage is supplied to the first transistor through the first wiring, and 在所述第一布线通过所述第一连接布线电连接到所述第二电源布线的情况下,所述第二电压通过所述第一布线供应到所述第一晶体管。In a case where the first wiring is electrically connected to the second power supply wiring through the first connection wiring, the second voltage is supplied to the first transistor through the first wiring. 16.如权利要求15所述的存储器件,其中所述多个沟道布置在第二方向上以形成至少一个沟道行,并且所述多个沟道中的设置在相邻的沟道行中的沟道以Z字形方式布置。16. The memory device according to claim 15 , wherein the plurality of channels are arranged in the second direction to form at least one channel row, and among the plurality of channels disposed in adjacent channel rows The roads are arranged in a zigzag manner. 17.如权利要求15所述的存储器件,其中所述基底层通过多个分隔层图案被划分成多个基底层图案。17. The memory device of claim 15, wherein the base layer is divided into a plurality of base layer patterns by a plurality of separation layer patterns. 18.如权利要求15所述的存储器件,其中所述多个沟道在垂直于所述衬底的所述第一表面的第一方向上延伸。18. The memory device of claim 15, wherein the plurality of channels extend in a first direction perpendicular to the first surface of the substrate. 19.如权利要求18所述的存储器件,其中所述存储单元阵列包括围绕所述沟道的外侧壁的多条栅线,其中所述多条栅线堆叠在所述第一方向上、彼此间隔开并被所述多个沟道共用。19. The memory device according to claim 18, wherein the memory cell array comprises a plurality of gate lines surrounding outer sidewalls of the trenches, wherein the plurality of gate lines are stacked in the first direction, mutually spaced apart and shared by the plurality of channels.
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