CN108346664B

CN108346664B - Memory device having peripheral upper cell structure and memory package including the same

Info

Publication number: CN108346664B
Application number: CN201710060999.2A
Authority: CN
Inventors: 金昶汎; 金成勋
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2017-01-25
Filing date: 2017-01-25
Publication date: 2023-08-22
Anticipated expiration: 2037-01-25
Also published as: CN108346664A

Abstract

The present disclosure provides a memory device having a peripheral on cell structure and a memory package including the same. A memory device includes a substrate and peripheral circuitry disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. The memory device further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power supply wiring configured to supply a first voltage, a second power supply wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to either the first power wiring or the second power wiring.

Description

Memory device having peripheral upper cell structure and memory package including the same

Technical Field

Example embodiments of the inventive concepts relate generally to memory devices, and more particularly, to memory devices having a peripheral on cell (cell over periphery, COP) structure and memory packages including the same.

Background

A vertical memory device, so-called a three-dimensional (3D) memory device, is a memory device that includes a plurality of memory cells repeatedly stacked on a surface of a substrate. These memory devices can have very high memory capacity within very small structures. For example, in a vertical memory device, a channel may protrude from a surface of a substrate or may extend vertically from the surface of the substrate, and a gate line and an insulating layer surrounding the vertical channel may be repeatedly stacked.

However, the reduction in size of the vertical memory device is limited because the memory device must still include an interface to electrically connect the memory device to peripheral circuitry for communication with and driving by external devices.

Disclosure of Invention

According to an exemplary embodiment of the inventive concept, a memory device includes a substrate and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. The memory device further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power supply wiring configured to supply a first voltage, a second power supply wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to either the first power wiring or the second power wiring.

According to an exemplary embodiment of the inventive concept, a memory package includes a base substrate and a plurality of memory chips stacked on the base substrate. Each of the plurality of memory chips includes a substrate and peripheral circuitry disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. Each memory chip further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power supply wiring configured to supply a first voltage, a second power supply wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to either the first power wiring or the second power wiring.

According to an exemplary embodiment of the inventive concept, a memory device includes a substrate and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor and a second transistor, a lower wiring layer disposed on the peripheral circuit, a base layer disposed on the lower wiring layer, and a memory cell array disposed on the base layer. The memory cell array includes a plurality of channels. The memory device further includes an upper wiring layer disposed on the memory cell array. The upper wiring layer includes at least two power supply wirings. A first power supply wiring of the at least two power supply wirings is configured to supply a first voltage, and a second power supply wiring of the at least two power supply wirings is configured to supply a second voltage. The upper wiring layer further includes a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to either the first power wiring or the second power wiring. The upper wiring layer further includes a second wiring electrically connected to the second transistor. The second wiring is configured to be electrically connectable to the first power wiring or the second power wiring.

Drawings

The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

fig. 1 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept;

fig. 2 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

fig. 3 is a cross-sectional view taken along line I-I' of fig. 2 according to an exemplary embodiment of the inventive concept;

fig. 4 is a circuit diagram illustrating an example of a memory cell array that may be disposed in the memory cell region of fig. 3 according to an exemplary embodiment of the inventive concept;

fig. 5, 6, 7, 8, and 9 are cross-sectional views for describing a process of manufacturing a memory device according to an exemplary embodiment of the inventive concept;

fig. 10 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

FIG. 11 is a cross-sectional view taken along line I-I' of FIG. 10, according to an exemplary embodiment of the present inventive concept;

fig. 12 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

fig. 13 is a cross-sectional view taken along line II-II' of fig. 12 according to an exemplary embodiment of the inventive concept;

Fig. 14 is a top view of a memory device according to an exemplary embodiment of the inventive concept;

fig. 15 is a cross-sectional view taken along line III-III' of fig. 14 according to an exemplary embodiment of the inventive concept;

fig. 16 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept;

fig. 17 and 18 are diagrams illustrating a memory package according to an exemplary embodiment of the inventive concept;

fig. 19 is a block diagram illustrating a solid state disk or Solid State Disk (SSD) according to an exemplary embodiment of the inventive concept;

fig. 20 is a block diagram illustrating an embedded multimedia card (eMMC) according to an exemplary embodiment of the inventive concept;

fig. 21 is a block diagram illustrating a universal flash memory (UFS) according to an exemplary embodiment of the inventive concept; and

fig. 22 is a block diagram illustrating a mobile device according to an exemplary embodiment of the inventive concept.

Detailed Description

Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Fig. 1 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept.

In fig. 1, a direction substantially perpendicular to a first surface (e.g., top surface) of the substrate is referred to as a first direction D1 (e.g., Z-axis direction). Further, two directions that are substantially parallel to the first surface of the substrate and cross each other are referred to as a second direction D2 (e.g., X-axis direction) and a third direction D3 (e.g., Y-axis direction). For example, the second direction D2 and the third direction D3 may be substantially perpendicular to each other. Further, the first direction D1 (e.g., Z-axis direction) is substantially perpendicular to both the second direction D2 (e.g., X-axis direction) and the third direction D3 (e.g., Y-axis direction).

Referring to fig. 1, a memory device 10 includes a peripheral circuit region PCR in which peripheral circuits are disposed. The memory device 10 further includes a memory cell region MCR in which the memory cell array MCA is disposed. The memory device 10 may further include a plurality of input/output (I/O) pads IOPAD disposed on a top surface thereof.

The peripheral circuit region PCR includes the semiconductor substrate 20, the peripheral circuit may be on a first surface (e.g., a top surface) of the semiconductor substrate 20, and the first wiring layer 30 may be disposed on the peripheral circuit. Further, the peripheral circuit may include a first transistor TR disposed on the first surface of the semiconductor substrate 20. The memory cell region MCR includes a base layer 40 that may be disposed on the first wiring layer 30, a memory cell array MCA that may be disposed on the base layer 40, and a second wiring layer 50 that may be disposed on the memory cell array MCA. The plurality of I/O pads IOPAD may be disposed on the second wiring layer 50.

The second wiring layer 50 may include a first power wiring 52, a second power wiring 54, and a first wiring 56. The second wiring layer 50 may further include a first connection wiring 58.

The first power supply wiring 52 may be configured to supply a first voltage to the memory device 10, and the second power supply wiring 54 may be configured to supply a second voltage to the memory device 10. Further, the second voltage may be different from the first voltage. For example, the first voltage may be a power supply voltage (e.g., vcc) and the second voltage may be a ground voltage (e.g., vss).

The first wiring 56 may be electrically connected to the first transistor TR. For example, as will be described with reference to fig. 3, the first wiring 56 may be electrically connected to the gate electrode of the first transistor TR by at least one contact provided through the first wiring layer 30 and the second wiring layer 50.

The first wiring 56 may be configured to be electrically connectable to one of the first power wiring 52 and the second power wiring 54. For example, as shown in fig. 1, the first wiring 56 may be electrically connected to the first power supply wiring 52 through a first connection wiring 58. The first transistor TR may receive a first voltage. In another example, the first wiring 56 may be electrically connected to the second power wiring 54 through a second connection wiring. Furthermore, the first transistor TR may then receive the second voltage.

The memory device 10 according to an exemplary embodiment of the inventive concept may have a relatively small size by adopting a on-peripheral unit (COP) structure. By adopting this structure, the peripheral circuit is provided on the semiconductor substrate 20 and the memory cell array MCA is stacked on the peripheral circuit. Further, in the memory device 10 according to the exemplary embodiment of the inventive concept, the first wiring 56 electrically connected to the first transistor TR in the peripheral circuit may be disposed in the second wiring layer 50, and the second wiring layer 50 is disposed on the memory cell array MCA. Further, the first wiring 56 may be electrically connectable to the first power wiring 52 or the second power wiring 54. Accordingly, the design of the memory device 10 can be easily modified, and thus the time for manufacturing the memory device 10 can be reduced even if the design of the memory device 10 is modified.

Fig. 2 is a top view of a memory device according to an exemplary embodiment of the inventive concept. Fig. 3 is a cross-sectional view taken along line I-I' of fig. 2 according to an exemplary embodiment of the inventive concept.

Referring to fig. 2 and 3, the memory device may include a peripheral circuit region PCR including a peripheral circuit structure disposed on the substrate 100 and a memory cell region MCR including a memory cell structure disposed on the peripheral circuit structure.

In some exemplary embodiments of the inventive concept, the memory device may be a nonvolatile memory device. For example, the nonvolatile memory device may have a COP structure in which a memory cell structure is stacked on a peripheral circuit structure. The memory cell structure may have a vertical NAND flash structure in which a plurality of NAND flash memory cells are vertically arranged. For example, NAND flash memory cells may be stacked in a first direction D1 with respect to a first surface (e.g., a top surface) of the substrate 100.

Further, fig. 2 shows the base layer 201, the pad 240, the mold protective layer 212, the first power supply wiring 310, the second power supply wiring 320, the first wiring 330, and the first connection wiring 332.

The peripheral circuit structures may include, for example, a gate structure 130, source/drain regions 103, insulating layers 140 and 160, contacts 145, wiring 150, and the like, which may be disposed on the substrate 100. The insulating layers 140 and 160, the contacts 145, and the wires 150 may form a first wiring layer (e.g., the first wiring layer 30 in fig. 1). Further, the first wiring layer may be referred to as a lower wiring layer. The insulating layers 140 and 160 may be referred to as lower insulating layers. The contact 145 may be referred to as a lower contact or a first contact, and the wiring 150 may be referred to as a lower wiring or a second wiring.

The substrate 100 may comprise a semiconductor material, such as crystalline silicon formed from a single crystal or crystalline germanium formed from a single crystal. The gate structure 130 may include a gate insulating layer pattern 110 and a gate electrode 120 stacked on the substrate 100. Further, a gate electrode 120 is disposed on the gate insulating layer pattern 110.

The gate insulating layer pattern 110 may include, for example, silicon oxide or metal oxide. The gate electrode 120 may include, for example, metal nitride, or doped polysilicon. The source/drain regions 103 may include n-type or p-type impurities. A transistor (e.g., the first transistor TR in fig. 1) including a gate structure 130 and source/drain regions 103 may be disposed on the substrate 100.

A first lower insulating layer 140 may be disposed on the substrate 100 to cover structures, such as the transistors, that may be disposed on the substrate 100. The first lower contact 145 may extend through a portion of the first lower insulating layer 140 and may be electrically connected to the gate electrode 120.

The first lower wiring 150 may be disposed on an upper surface of the first lower insulating layer 140, and may be electrically connected to the first lower contact 145. The second lower insulating layer 160 may be disposed on the first lower insulating layer 140 to cover the first lower wiring 150. Although fig. 3 illustrates an exemplary embodiment of the inventive concept in which the lower wiring layer includes a single lower wiring 150, the lower wiring layer may include a plurality of lower wirings distributed in different layers as will be described with reference to fig. 11 and 13.

The first and second lower insulating layers 140 and 160 may include an insulating material, such as silicon oxide. The first lower contact 145 and the first lower wiring 150 may include, for example, metal nitride, or doped polysilicon.

The memory cell structure may include a base layer 201, a channel 225, gate lines 260a, 260b, 260c, 260d, 260e, and 260f, bit lines 285, insulating layers 275 and 290, contacts 248a, and wirings 310, 320, 330, and 332, etc., which may be disposed on a lower wiring layer (e.g., disposed on the second lower insulating layer 160). The insulating layers 275 and 290, the contacts 248a, and the wirings 310, 320, 330, and 332 may form a second wiring layer (e.g., the second wiring layer 50 in fig. 1). The second wiring layer may be referred to as an upper wiring layer, and the insulating layers 275 and 290 may be referred to as upper insulating layers, wherein, for example, the second upper insulating layer 290 may be disposed on the first upper insulating layer 275. Further, the contact 248a may be referred to as an upper contact, and the wirings 310, 320, 330, and 332 may be referred to as upper wirings.

The base layer 201 may include, for example, polysilicon or crystalline silicon formed of single crystals. In some exemplary embodiments of the inventive concept, the base layer 201 may further include a p-type impurity such as boron (B), and in this case, the base layer 201 may function as a p-type well.

The channel 225 may be disposed on the substrate layer 201 and may extend from a first surface (e.g., a top surface) of the substrate layer 201 in a first direction D1 (e.g., a Z-axis direction). The channel 225 may have a hollow cylindrical shape or a cup shape. Channel 225 may comprise polysilicon or crystalline silicon formed from a single crystal and may comprise an impurity region doped with, for example, a p-type impurity such as boron.

The plurality of channels 225 may be arranged in the second direction D2 (e.g., the X-axis direction) to form channel rows, and the plurality of channel rows may be arranged in the third direction D3 (e.g., the Y-axis direction). Further, the plurality of channels 225 extend in a first direction (e.g., a Z-axis direction) that is substantially perpendicular to the first surface.

The filling layer pattern 230 may be disposed in an inner space of the trench 225. The filling layer pattern 230 may have a pillar shape or a solid cylindrical shape. The filling layer pattern 230 may include an insulating layer pattern such as silicon oxide.

In some exemplary embodiments of the inventive concept, the channel 225 may have a pillar shape or a solid cylindrical shape, and in such a case, the filling layer pattern 230 may be omitted.

Dielectric layer structure 220 may be disposed on the outer sidewalls of channel 225. The dielectric layer structure 220 may have a cup shape with an open center bottom, a straw shape, or a shape substantially similar to a hollow cylindrical shape.

The dielectric layer structure 220 may include, for example, a tunnel insulating layer, a charge storage layer, and a blocking layer, which may be sequentially stacked from an outer sidewall of the channel 225. The barrier layer may comprise, for example, silicon oxide or a metal oxide such as hafnium oxide or aluminum oxide. The charge storage layer may comprise, for example, a nitride (such as silicon nitride) or a metal oxide, and the tunnel insulating layer may comprise, for example, an oxide such as silicon oxide. For example, the dielectric layer structure 220 may have an oxide-nitride-oxide (ONO) layer stacked to form the dielectric layer structure 220.

The pad 240 may be disposed on the filling layer pattern 230, the channel 225, and the dielectric layer structure 220. For example, the filling layer pattern 230, the channel 225, and the dielectric layer structure 220 may be covered or enclosed by the pad 240. The pad 240 may include, for example, polysilicon or crystalline silicon formed of single crystal. The pad 240 may further include, for example, n-type impurities, such As phosphorus (P) or arsenic (As).

As shown in fig. 2, the plurality of pads 240 may be arranged in a second direction D2 (e.g., an X-axis direction) to form a pad row that is substantially comparable to the channel row. The plurality of pad rows may be arranged in a third direction D3 (e.g., Y-axis direction).

The gate lines 260a-260f may be disposed on an outer sidewall of the dielectric layer structure 220 and may be spaced apart from each other in a first direction D1 (e.g., a Z-axis direction). In some exemplary embodiments of the inventive concept, each of the gate lines 260a-260f may surround the channel 225 of at least one channel row and may extend in a second direction D2 (e.g., an X-axis direction). For example, as shown in fig. 2 and 3, each of the gate lines 260a-260f may surround four channel rows; however, the number of channel rows surrounded by each of the gate lines 260a to 260f is not limited thereto.

The gate lines 260a-260f may include, for example, a metal having a low resistance and/or a nitride thereof. For example, the gate lines 260a-260f may include tungsten (W), tungsten nitride, titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, platinum (Pt), and the like. In some exemplary embodiments of the inventive concept, the gate lines 260a to 260f may have a multi-layered structure including a barrier layer including a metal nitride and a metal layer.

In some exemplary embodiments of the inventive concept, the lowermost gate line 260a (e.g., the first from the base layer 201) may be used as a Ground Selection Line (GSL), and the uppermost gate line 260f (e.g., closest to the first upper insulating layer 275) may be used as a String Selection Line (SSL). Other gate lines 260b, 260c, 260d, and 260e between GSL and SSL may be used as word lines.

According to exemplary embodiments of the inventive concept, GSLs, word lines, and SSL may be formed in a single hierarchy, four levels, and a single hierarchy, respectively. However, the respective numbers of the levels of GSL, word line, and SSL are not limited thereto. In some exemplary embodiments of the inventive conceptGSL and SSL may be formed in two levels, respectively, and word lines may be formed at 2 ⁿ Where n is a positive integer, for example, a word line may have 4, 8, or 16 levels. The number of stacks of gate lines 260a-260f may be determined in consideration of the integration level and circuit design of the memory device.

The insulating interlayers 202a, 202b, 202c, 202D, 202e, 202f, and 202g may be alternately stacked with the gate lines 260a to 260f in the first direction D1 (e.g., the Z-axis direction). The insulating interlayers 202a-202g may comprise a silicon oxide-based material, such as silicon dioxide (SiO ₂ ) Silicon oxycarbide (SiOC) or silicon oxyfluoride (SiOF). The gate lines 260a-260f may be insulated from each other along a first direction D1 (e.g., Z-axis direction) by insulating interlayers 202a-202 g.

A first upper insulating layer 275 may be disposed on the uppermost insulating interlayer 202g, the pads 240, and the first upper contacts 248 a.

A bit line contact 280 may be disposed through the first upper insulating layer 275 to contact the pad 240. The plurality of bit line contacts 280 may be formed to define an array similar to the arrangement of the channels 225 or pads 240.

Bit line 285 may be disposed on first upper insulating layer 275 and may be electrically connected to bit line contact 280. For example, the bit line 285 may extend in a third direction D3 (e.g., Y-axis direction) and may be electrically connected to the plurality of bit line contacts 280.

In some exemplary embodiments of the inventive concept, the mold protective layer 212 may be disposed on a lateral portion (lateral portion) of the base layer 201. The first upper contact 248a may extend through the mold protection layer 212, the base layer 201, and a portion of the second lower insulating layer 160, and may contact the first lower wiring 150. The first insulating layer pattern 241a may be disposed on sidewalls of the first upper contact 248 a.

The first plug 291 may extend through the first upper insulating layer 275 and may contact the first upper contact 248a. The first upper wiring 330 may be disposed on the first upper insulating layer 275 (e.g., an upper surface of the first upper insulating layer 275) and may electrically connect the first plug 291 and the first upper contact 248a, respectively. The second upper insulating layer 290 may be disposed on the first upper insulating layer 275 and may cover the first upper wiring 330.

In the memory device according to the exemplary embodiment of the inventive concept, the first transistor included in the peripheral circuit region PCR may be used to implement a logic circuit. For example, the peripheral circuit region PCR may include various elements for driving the memory device. Further, each element may include various logic circuits such as an OR gate (OR gate), an AND gate (AND gate), a NOR gate (NOR gate), a NAND gate (NAND gate), AND the like, AND each logic circuit may include at least one transistor. For example, the first transistor may be included in the first logic circuit and may be connected to a first input terminal of the first logic circuit. The first transistor may be electrically connected to the first upper wiring 330 through contacts 145 and 248a, the first lower wiring 150, and the first plug 291.

In some exemplary embodiments of the inventive concept, the first power wiring 310, the second power wiring 320, the first upper wiring 330, and the first connection wiring 332 may be disposed on the same layer (e.g., on the same plane in a top view) on the first upper insulating layer 275. For example, the first power wiring 310 and the second power wiring 320 may be disposed on the same layer on the memory cell array. For example, each of the first and second power supply wirings 310 and 320 may extend in the second direction D2 (e.g., the X-axis direction). Further, the first power wiring 310 and the second power wiring 320 may be spaced apart from each other. The first upper wiring 330 may be disposed between the first power wiring 310 and the second power wiring 320. The first connection wiring 332 may electrically connect the first power wiring 310 with the first upper wiring 330. Further, the first connection wiring 332 may be replaced with a second connection wiring that connects the second power supply wiring 320 with the first upper wiring 330.

Thus, in the memory device according to the exemplary embodiment of the inventive concept, the first upper wiring 330 electrically connected to the first transistor in the peripheral circuit may be disposed in an upper wiring layer (e.g., the second wiring layer 50 in fig. 1). Then, a power option (power option) for the first transistor can be efficiently and easily selected based on the first upper wiring 330 by changing the arrangement of connection wirings that connect the first upper wiring 330 with one of the power wirings 310 and 320. For example, the first upper wiring 330 may be electrically connectable to one of the power supply wirings 310 and 320, and one of the first voltage (e.g., a power supply voltage) and the second voltage (e.g., a ground voltage) may be selected to be provided to the first transistor without excessive design change. Accordingly, the design of the memory device can be easily modified, and thus the time for manufacturing the memory device can be reduced even if the design of the memory device is modified.

Fig. 4 is a circuit diagram illustrating an example of a memory cell array that may be disposed in the memory cell region in fig. 3 according to an exemplary embodiment of the inventive concept.

Referring to fig. 4, the memory cell array 400 may include a plurality of strings 410, each string 410 having a vertical structure. The plurality of strings 410 may be arranged in a second direction D2 (e.g., an X-axis direction) to define a string. Further, a plurality of strings may be arranged in a third direction D3 (e.g., Y-axis direction) to define a string array. Each string may include a string selection transistor SSTV, a ground selection transistor GSTV, and a plurality of memory cells MC arranged in a first direction D1 (e.g., a Z-axis direction) and connected in series between the string selection transistor SSTV and the ground selection transistor GSTV.

The string selection transistor SSTV may be connected to the bit line BL (1),..and BL (m), and the ground selection transistor GSTV may be connected to the common source line CSL. The string selection transistor SSTV may be connected to string selection lines SSL11, SSL12,..the SSLi1, SSLi2, and the ground selection transistor GSTV may be connected to ground selection lines GSL11, GSL12,..the GSLi1, GSLi2. Memory cells in the same layer may be connected to the same one of the word lines WL (1), WL (2),. WL (n-1), WL (n). Each string selection line and each ground selection line may extend in a second direction D2 (e.g., an X-axis direction), and the string selection lines SSL11-SSLi2 and the ground selection lines GSL11-GSLi2 may be arranged along a third direction D3 (e.g., a Y-axis direction). Each word line may extend in a second direction D2 (e.g., an X-axis direction), and the word lines WL (1) -WL (n) may be arranged along a first direction D1 (e.g., a Z-axis direction) and a third direction D3 (e.g., a Y-axis direction). Each bit line (e.g., BL (1)) may extend in a third direction D3 (e.g., Y-axis direction), and bit lines BL (1) -BL (m) may be arranged along a second direction D2 (e.g., X-axis direction). The memory cell MC may be controlled by voltages on the word lines WL (1) -WL (n).

As with the two-dimensional (2D) flash memory device, the vertical or three-dimensional (3D) flash memory device including the memory cell array 400 may perform a program operation and a read operation in units of pages and perform an erase operation in units of blocks.

Further, according to an exemplary embodiment of the inventive concept, two string selection transistors included in a single string may be connected to a single string selection line, and two ground selection transistors included in a single string may be connected to a single ground selection line. According to an exemplary embodiment of the inventive concept, a single string may include one string selection transistor and one ground selection transistor.

Fig. 5, 6, 7, 8, and 9 are cross-sectional views for describing a process of manufacturing a memory device according to an exemplary embodiment of the inventive concept.

Referring to fig. 5, a gate structure 130 and source/drain regions 103 may be disposed on a substrate 100.

A semiconductor substrate including crystalline silicon formed of a single crystal and/or crystalline germanium formed of a single crystal may be used as the substrate 100. For example, the substrate 100 may be obtained from a silicon wafer.

The gate insulating layer and the gate electrode layer may be disposed on the substrate 100 and then may be etched to form the gate insulating layer pattern 110 and the gate electrode 120. Accordingly, the gate structure 130 may be formed, the gate structure 130 including the gate insulating layer pattern 110 and the gate electrode 120 sequentially stacked on the substrate 100.

An ion implantation process may be performed using the gate structure 130 as an implantation mask to form source/drain regions 103 at an upper portion of the substrate 100 adjacent to the gate structure 130 (e.g., an upper surface of the substrate 100). Thus, the source/drain regions 103 may be disposed at an upper portion of the substrate 100 adjacent to the gate structure 130. Thus, a first transistor may be defined and disposed on the substrate 100.

The gate insulating layer may be formed of silicon oxide or metal oxide by, for example, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, a spin-on process, an Atomic Layer Deposition (ALD) process, or the like. In addition, the gate insulating layer may be formed through a thermal oxidation process to the top surface of the substrate 100. The gate electrode layer may include metal, metal nitride, or doped polysilicon by, for example, an ALD process or a sputtering process.

A first lower insulating layer 140 covering the gate structure 130 may be disposed on the substrate 100. The first lower contact 145 may be disposed through the first lower insulating layer 140 and may contact the first transistor by contacting the gate electrode 120 included in the gate structure 130. Further, the first lower contact 145 may contact the source/drain region 103.

A first lower wiring 150 electrically connected to the lower contact 145 may be disposed on the first lower insulating layer 140. A second lower insulating layer 160 covering the first lower wiring 150 may be disposed on the first lower insulating layer 140.

The first and second lower insulating layers 140 and 160 may include an insulating material such as silicon oxide by, for example, a CVD process or a spin-on process. The first lower contact 145 and the first lower wiring 150 may include a metal or a metal nitride by, for example, an ALD process or a sputtering process.

A single level lower wiring is shown in fig. 5; however, as will be described with reference to fig. 11 and 13, additional lower insulating layers and lower wirings may be stacked.

The base layer 201 may be disposed on the second lower insulating layer 160.

In an exemplary embodiment of the inventive concept, the base layer 201 may include a polysilicon material and may be manufactured by a sputtering process, a CVD process, an ALD process, a Physical Vapor Deposition (PVD) process, or the like. The base layer 201 may include polysilicon doped with, for example, a p-type impurity such as boron (B). Here, the base layer 201 may serve as a p-type well.

In an exemplary embodiment of the inventive concept, an amorphous silicon layer may be disposed on an upper surface of the second lower insulating layer 160 (e.g., disposed on the second lower insulating layer 160 in the first direction D1), and then a heat treatment or laser irradiation may be performed to convert the amorphous silicon layer into the base layer 201 including single crystal crystalline silicon. Here, the defects in the base layer 201 may be substantially repaired so that the functional characteristics of the base layer 201 as a p-type well may be improved.

In an exemplary embodiment of the inventive concept, the base layer 201 may be formed through a wafer bonding process. Here, a wafer (e.g., crystalline silicon formed of a single crystal wafer) may be attached on the second lower insulating layer 160. The upper portion of the wafer may be removed or planarized to form a base layer 201.

Referring to fig. 6, insulating interlayers 202 (e.g., 202a-202 g) and sacrificial layers 204 (e.g., 204a-204 f) may be alternately and repeatedly disposed on a base layer 201 in a first direction D1 (e.g., Z-axis direction) to form a molded structure. For example, a first insulating interlayer 202a may be disposed on the base layer 201, a first sacrificial layer 204a may be disposed on the first insulating interlayer 202a, a second insulating interlayer 202b may be disposed on the first sacrificial layer 204a, and so on.

In exemplary embodiments of the inventive concept, the insulating interlayer 202 may include a silicon oxide-based material, such as silicon dioxide, silicon oxycarbide, and/or silicon oxyfluoride. The sacrificial layer 204 may include a material that may have an etch selectivity with respect to the insulating interlayer 202 and may be easily removed by a wet etching process. For example, the sacrificial layer 204 may include silicon nitride (SiN) and/or silicon boron nitride (SiBN).

The insulating interlayer 202 and the sacrificial layer 204 may be formed by a CVD process, a PECVD process, a spin-on process, an ALD process, or the like.

The sacrificial layer 204 may be removed in a subsequent process to provide space for GSLs, word lines, and SSL. For example, each of GSL and SSL may be formed in a single level, and word lines may be formed in 4 levels. In this example, as shown in fig. 6, the sacrificial layer 204 may be formed in 6 levels, and the insulating interlayer 202 may be formed in 7 levels. However, the number of stacks of GSLs, SSL, and word lines may not be limited to the examples provided herein.

Referring to fig. 7, lateral portions of the molded structure may be removed, and an insulating layer covering the molded structure may be disposed on the base layer 201. Further, in order to form the mold protective layer 212, an upper portion of the insulating layer may be planarized until the uppermost insulating interlayer 202g is exposed.

Referring to fig. 8, channel holes may be disposed through the mold structure, and a dielectric layer structure 220, a channel 225, and a filling layer pattern 230 may be disposed in each channel hole. A pad 240 covering the channel hole may be disposed on the dielectric layer structure 220, the channel 225, and the filling layer pattern 230.

A first upper contact 248a may be formed. For example, the mold protection layer 212, the base layer 201, and a portion of the second lower insulating layer 160 may be etched to form a first contact hole through which the top surface of the first lower wiring 150 is exposed. The first insulating layer pattern 241a may be disposed on a sidewall of the first contact hole. Then, a first upper contact 248a may be formed to fill the remaining portion of the first contact hole.

Upper gate line cut regions (e.g., element 250 in fig. 15) and gate line cut regions (e.g., element 256 in fig. 15) may be formed. The sacrificial layer 204 exposed by the gate line cut region may be removed, and the gate lines 260a to 260f may be disposed at spaces from which the sacrificial layer 204 is removed.

Referring to fig. 9, a first upper insulating layer 275 may be disposed on the uppermost insulating interlayer 202g, the pad 240, and the first upper contact 248 a. The first upper insulating layer 275 may be formed of, for example, silicon oxide by a CVD process.

The first plug 291 and the bit line contact 280 may be disposed through the first upper insulating layer 275 and may be in contact with the first upper contact 248a and the pad 240, respectively.

Bit line 285 may be disposed on first upper insulating layer 275 and may be electrically connected to bit line contact 280. The bit line 285 may extend in a third direction D3 (e.g., Y-axis direction) and may be electrically connected to the plurality of bit line contacts 280.

The first upper wiring 330 may be electrically connected to the first plug 291. Further, the first upper wiring 330 may be disposed on the first upper insulating layer 275. The first power supply wiring 310, the second power supply wiring 320, and the first connection wiring 332 may also be disposed on the first upper insulating layer 275. The first upper wiring 330 may be one electrically connectable to the first power wiring 310 and the second power wiring 320. The first transistor including the gate structure 130 and the source/drain region 103 may receive one of a first voltage and a second voltage (e.g., one of a power supply voltage and a ground voltage) through the first upper wiring 330 (which is electrically connected to one of the first power supply wiring 310 and the second power supply wiring 320).

For example, an upper conductive layer may be disposed on the first upper insulating layer 275 using metal or metal nitride, and then may be patterned to form the bit line 285 and the wirings 310, 320, 330, and 332. Bit line 285 and wirings 310, 320, 330, and 332 may be provided by substantially the same etching process.

A second upper insulating layer 290 covering the bit line 285 and the wirings 310, 320, 330, and 332 may be disposed on the first upper insulating layer 275.

Fig. 5, 6, 7, 8, and 9 illustrate a process in which the wirings 310, 320, 330, and 332 are formed after the memory cell array is formed; however, the process sequence is not particularly limited herein. For example, a process for the peripheral circuit region PCR may be performed, the wirings 310, 320, 330, and 332 may be formed, and then a process for the memory cell region MCR may be performed.

Fig. 10 is a top view of a memory device according to an exemplary embodiment of the inventive concept. Fig. 11 is a cross-sectional view taken along line I-I' of fig. 10 according to an exemplary embodiment of the inventive concept.

Referring to fig. 10 and 11, the memory device may include a peripheral circuit region PCR including a peripheral circuit structure disposed on the substrate 100 and a memory cell region MCR including a memory cell structure disposed on the peripheral circuit structure.

The memory device of fig. 10 and 11 may be substantially the same as the memory device of fig. 2 and 3 except that the memory device of fig. 10 and 11 further includes a second transistor, a second wiring 340, a second connection wiring 342, and an element for connecting the second transistor to the second wiring 340 and that a lower wiring layer (e.g., the first wiring layer 30 in fig. 1) in the memory device of fig. 10 and 11 is implemented with a plurality of layers.

The peripheral circuit structures may include, for example, gate structures 130 and 132, source/drain regions 103 and 104, insulating layers 140, 160, 162, and 164, contacts 145, 147a, 147b, and 147c, wirings 150, 152a, 152b, and 152c, and the like disposed on the substrate 100.

The gate structure 132 of a transistor (e.g., a second transistor) may include a gate insulating layer pattern 112 and a gate electrode 122 stacked on the substrate 100. The source/drain regions 104 may include n-type or p-type impurities. A transistor (e.g., a second transistor) including a gate structure 132 and source/drain regions 104 may be disposed and defined on the substrate 100.

A first lower insulating layer 140 may be disposed on the substrate 100 to cover structures such as transistors (e.g., first and second transistors). The first lower contact 145 may extend through a portion of the first lower insulating layer 140 and may be electrically connected to the gate electrode 120 of the gate structure 130.

The first lower wiring 150 may be disposed on the first lower insulating layer 140 and may be electrically connected to the first lower contact 145.

The second lower insulating layer 160 may be disposed on the first lower insulating layer 140 to cover the lower wirings 150 and 152a. A third lower insulating layer 162 may be disposed on the second lower insulating layer 160 to cover the lower wiring 152b. A fourth lower insulating layer 164 may be disposed on the third lower insulating pattern 162 to cover the lower wiring 152c. The gate electrode 122 may be electrically connected to the lower wirings 152a, 152b, and 152c through the lower contacts 147a, 147b, and 147c, respectively. The connection between the lower wiring and the lower contact may vary according to the wiring (routing) of the signal line.

The memory cell structure may include a base layer 201, a channel 225, gate lines 260a-260f, a bit line 285, insulating layers 275 and 290, contacts 248a and 248b, and wirings 310, 320, 330, 332, 340 and 342, etc., which may be disposed on a lower wiring layer (e.g., disposed on a fourth lower insulating layer 164).

Similar to the first upper contact 248a, the second upper contact 248b may extend through the mold cap layer 212, the base layer 201, and a portion of the fourth lower insulating layer 164. However, the difference between the contacts 248a and 248b is that the second upper contact 248b may be in contact with the lower wiring 152c. Similar to how the first insulating layer pattern 241a may be disposed with respect to the first upper contact 248a, the second insulating layer pattern 241b may be disposed on a sidewall of the second upper contact 248 b.

Similar to the first plug 291, the second plug 293 may extend through the first upper insulating layer 275 and may contact the second upper contact 248b. The second upper wiring 340 may be disposed on the first upper insulating layer 275 to electrically connect the second plug 293 and the second upper contact 248b, respectively.

The second transistor may be electrically connected to the second upper wiring 340 through contacts 147a, 147b, 147c and 248b, lower wirings 152a, 152b and 152c, and a second plug 293.

In an exemplary embodiment of the inventive concept, the wirings 310, 320, 330, 332, 340, and 342 may be disposed on the same layer (e.g., on the same plane in a top view) on the first upper insulating layer 275. For example, each of the first and second power supply wirings 310 and 320 may extend in the second direction D2 (e.g., the X-axis direction), and the first and second power supply wirings 310 and 320 may be spaced apart from each other. The first upper wiring 330 and the second upper wiring 340 may be disposed between the first power wiring 310 and the second power wiring 320. The first connection wiring 332 may electrically connect the first power wiring 310 with the first upper wiring 330. The second connection wiring 342 may electrically connect the second power wiring 320 with the second upper wiring 340. As with the first upper wiring 330, the second upper wiring 340 may be electrically connectable to one of the power supply wirings 310 and 320. Then, the power supply option for the second transistor can be efficiently and easily selected based on the second upper wiring 340 by changing the arrangement of the connection wiring that connects the second upper wiring 340 with one of the power supply wirings 310 and 320.

Fig. 12 is a top view of a memory device according to an exemplary embodiment of the inventive concept. Fig. 13 is a cross-sectional view taken along line II-II' of fig. 12 according to an exemplary embodiment of the inventive concept.

Referring to fig. 12 and 13, the memory device may include a peripheral circuit region PCR including a peripheral circuit structure disposed on the substrate 100 and a memory cell region MCR including a memory cell structure disposed on the peripheral circuit structure.

The memory device of fig. 12 and 13 may be substantially the same as the memory device of fig. 2 and 3 except that the memory device of fig. 12 and 13 further includes a third transistor, a third power supply wiring 350, a third wiring 360, a third connection wiring 362, and an element for connecting the third transistor to the third wiring 360, and a lower wiring layer (e.g., a first wiring layer) in the memory device of fig. 12 and 13 is implemented with a plurality of layers.

Similar to the first power wiring 310, the third power wiring 350 may supply a first voltage, which may be a power supply voltage.

The peripheral circuit structures may include, for example, gate structures 130 and 134, source/drain regions 103 and 105, insulating layers 140, 160, 162, and 164, contacts 145, 149a, 149b, and 149c, wirings 150, 154a, 154b, and 154c, and the like, which may be disposed on the substrate 100.

The gate structure 134 of the transistor (e.g., the third transistor) may include the gate insulating layer pattern 114 and the gate electrode 124 stacked on the substrate 100. The source/drain regions 105 may include n-type or p-type impurities. A transistor (e.g., a third transistor) including a gate structure 134 and source/drain regions 105 may be disposed and defined on the substrate 100.

A first lower insulating layer 140 may be disposed on the substrate 100 to cover structures such as transistors (e.g., third transistors). The first lower contact 145 may extend through a portion of the first lower insulating layer 140 and may be electrically connected to the gate electrode 120 of the gate structure 130.

The second lower insulating layer 160 may be disposed on the first lower insulating layer 140 to cover the lower wirings 150 and 154a. A third lower insulating layer 162 may be disposed on the second lower insulating layer 160 to cover the lower wiring 154b. A fourth lower insulating layer 164 may be disposed on the third lower insulating pattern 162 to cover the lower wiring 154c. The gate electrode 124 may be electrically connected to the lower wirings 154a, 154b, and 154c through the lower contacts 149a, 149b, and 149c, respectively. The connection between the lower wiring and the lower contact may vary according to the wiring of the signal line.

The memory cell structure may include a base layer 201, a channel 225, gate lines 260a-260f, a bit line 285, insulating layers 275 and 290, contacts 248a and 248c, and wirings 310, 320, 330, 332, 350, 360, and 362, etc., which may be disposed on a lower wiring layer (e.g., disposed on a fourth lower insulating layer 164).

Similar to the first upper contact 248a, the third upper contact 248c may extend through the mold cap layer 212, the base layer 201, and a portion of the fourth lower insulating layer 164. However, the difference between the contacts 248a and 248c is that the second upper contact 248c may be in contact with the lower wiring 154 c. Similar to how the first insulating layer pattern 241a may be disposed with respect to the first upper contact 248a, the third insulating layer pattern 241c may be disposed on a sidewall of the third upper contact 248c.

Similar to the first plug 291, the third plug 295 may extend through the first upper insulating layer 275 and may contact the third upper contact 248c. The third upper wiring 360 may be disposed on the first upper insulating layer 275 to electrically connect the third plug 295 and the third upper contact 248c, respectively.

The third transistor may be electrically connected to the third upper wiring 360 through contacts 149a, 149b, 149c, and 248c, the lower wirings 154a, 154b, and 154c, and a third plug 295.

In an exemplary embodiment of the inventive concept, the wirings 310, 320, 330, 332, 350, 360, and 362 may be disposed on the same layer (e.g., on the same plane in a top view) on the first upper insulating layer 275. For example, each of the first, second, and third power supply wirings 310, 320, and 350 may extend in the second direction D2 (e.g., the X-axis direction), and the first, second, and third power supply wirings 310, 320, and 350 may be spaced apart from each other. The first upper wiring 330 may be disposed between the first power wiring 310 and the second power wiring 320. The third upper wiring 360 may be disposed between the second power wiring 320 and the third power wiring 350. The first connection wiring 332 may electrically connect the first power wiring 310 with the first upper wiring 330. The third connection wiring 362 may electrically connect the third power wiring 350 with the third upper wiring 360. As with the first upper wiring 330, the third upper wiring 360 may be electrically connectable to one of the power supply wirings 320 and 350. Accordingly, the power supply option for the third transistor can be efficiently and easily selected based on the third upper wiring 360 by changing the arrangement of the connection wiring that connects the third upper wiring 360 with one of the power supply wirings 320 and 350.

Although fig. 2, 10, and 12 show examples of the upper wiring and the power supply wiring, the number, arrangement, and configuration of the upper wiring and the power supply wiring are not limited thereto. Further, the illustrated upper wiring and power supply wiring are included in an upper wiring layer (e.g., a second wiring layer) on the memory cell array and electrically connected to transistors in the peripheral circuit. For example, the upper wiring layer of the memory device may include any number of power supply wirings extending in any direction and spaced apart from each other, and any number of upper wirings electrically connected to elements (e.g., transistors) in the peripheral circuit and configurable to be electrically connectable to one of the power supply wirings.

Fig. 14 is a top view of a memory device according to an exemplary embodiment of the inventive concept. Fig. 15 is a cross-sectional view taken along line III-III' of fig. 14 according to an exemplary embodiment of the inventive concept.

Referring to fig. 14 and 15, the memory device may include a peripheral circuit region PCR including a peripheral circuit structure disposed on the substrate 100 and a memory cell region MCR including a memory cell structure disposed on the peripheral circuit structure.

The memory device of fig. 14 and 15 may be substantially the same as the memory device of fig. 2 and 3, except that the base layer in the memory device of fig. 14 and 15 is physically divided into a plurality of base layer patterns and the arrangement of the channels 225 and the pads 240 is changed in the memory device of fig. 14 and 15.

For clarity and conciseness of description, some elements of the memory device are not shown in fig. 14. For example, fig. 14 shows base layer patterns 201a, 201b, and 201c, separation layer pattern 206, impurity region 266, pad 240, mold protective layer 212, first power wiring 310, second power wiring 320, first wiring 330, and first connection wiring 332, and other elements except the above are omitted.

The memory cell structure may include first, second, and third base layer patterns 201a, 201b, and 201c, a channel 225, gate lines 260a, 260b, 260c, 260d, 260e, and 260f, a bit line 285, insulating layers 275 and 290, and wirings 310, 320, 330, and 332, etc., which may be disposed on a lower wiring layer (e.g., on the second lower insulating layer 160).

The separation layer pattern 206 may extend in a second direction D2 (e.g., an X-axis direction), and the plurality of separation layer patterns 206 may be arranged along a third direction D3 (e.g., a Y-axis direction). Thus, the base layer may be physically divided into first to third base layer patterns 201a to 201c. Fig. 14 and 15 show three base layer patterns 201a-201c; however, the number of base layer patterns is not limited thereto. The spacer layer pattern 206 may include an insulating layer pattern, such as silicon oxide.

In exemplary embodiments of the inventive concept, the lowermost insulating interlayer 202a may be substantially integral or unitary with the separation layer pattern 206. In exemplary embodiments of the inventive concept, the formation of the separation layer may be omitted, and the lowermost insulating interlayer 202a may fill the openings corresponding to the separation layer pattern 206 and cover the base layer patterns 201a-201c.

The base layer patterns 201a-201c may include, for example, polysilicon or crystalline silicon formed of single crystals. In exemplary embodiments of the inventive concept, the base layer patterns 201a-201c may further include a p-type impurity such as boron (B). In this exemplary embodiment, the base layer patterns 201a-201c may be used as p-type wells.

The channels 225 may be disposed on the base layer patterns 201a-201c and may extend from the top surfaces of the base layer patterns 201a-201c in a first direction D1 (e.g., a Z-axis direction). In an exemplary embodiment of the inventive concept, a plurality of channels 225 may be arranged in the second direction D2 (e.g., the X-axis direction) to form a channel row, and the channels 225 included in adjacent channel rows may be arranged to face each other in a zigzag manner. Accordingly, the density of the channels 225 in the unit area of the base layer patterns 201a-201c may be increased.

The gate line cut region 256 may be disposed through the gate lines 260a-260f and the insulating interlayers 202a-202g in a first direction D1 (e.g., a Z-axis direction). The gate line cutting region 256 may have a trench shape or a trench shape extending in the second direction D2 (e.g., the X-axis direction).

A gate line cutting pattern 270 extending in a second direction D2 (e.g., an X-axis direction) may be disposed on the impurity region 266. The plurality of impurity regions 266 and the plurality of gate line cutting patterns 270 may be arranged along a third direction D3 (e.g., Y-axis direction). In an exemplary embodiment of the inventive concept, the impurity region 266 may include an n-type impurity, such As phosphorus (P) or arsenic (As). The gate line cutting pattern 270 may include an insulating layer pattern, for example, silicon oxide. A metal silicide pattern such as a cobalt silicide pattern and/or a nickel silicide pattern may be further disposed on the impurity region 266.

In an exemplary embodiment of the inventive concept, one of the impurity regions 266 and one of the gate line cutting patterns 270 may be provided for each of the base layer patterns 201a to 201 c. As shown in fig. 15, for example, a gate line cutting region 256 may be disposed at a central region of the second base layer pattern 201 b. The impurity region 266 may be disposed in an upper portion of the second base layer pattern 201b exposed by the gate line cutting region 256, and the gate line cutting pattern 270 filling the gate line cutting region 256 may be disposed on the impurity region 266 in the first direction D1 (e.g., the Z-axis direction).

In an exemplary embodiment of the inventive concept, the cell blocks of the common gate lines 260a to 260f may be defined by a gate line cutting pattern 270. The cell blocks may be divided into sub-cell blocks by the separation layer pattern 206. Thus, the size or dimension of the individual blocks can be reduced, so that the segment operation control (segmented operational control) can be realized. For example, the cell block may be further divided or divided by the separation layer pattern 206, and thus signal interference or disturbance occurring when the size or the size of the cell block becomes increased may be prevented. Therefore, the operation reliability of the memory device can be improved.

The upper gate line cutting pattern 252 may be disposed in the upper gate line cutting region 250. The upper gate line cutting pattern 252 may include an insulating material, such as silicon oxide.

In an exemplary embodiment of the inventive concept, the upper gate line cutting region 250 or the upper gate line cutting pattern 252 may be provided for separation of SSL in each unit block. In this exemplary embodiment of the inventive concept, the upper gate line cutting region 250 or the upper gate line cutting pattern 252 may extend through the uppermost insulating interlayer 202g and the SSL 260f, and may extend partially through the insulating interlayer 202f directly under the SSL 260 f.

In an exemplary embodiment of the inventive concept, the upper wirings 310, 320, 330, and 332 may be disposed corresponding to each of the base layer patterns 201a to 201 c.

In exemplary embodiments of the inventive concept, the number, arrangement, and configuration of upper wirings and power supply wirings included in the upper wiring layer (e.g., the second wiring layer 50 of fig. 1) of the memory device of fig. 14 and 15 may vary. In exemplary embodiments of the inventive concept, the lower wiring layer (e.g., the first wiring layer 30 in fig. 1) of the memory device of fig. 14 and 15 may be implemented with a plurality of layers.

Fig. 16 is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept.

Referring to fig. 16, the memory device 500 may include a memory cell array 510, an address decoder 520, a read/write unit 530, a data input/output (I/O) unit 540, a voltage generation unit 550, and control logic 560.

In the memory device 500 according to an exemplary embodiment of the inventive concept, the memory cell array 510 may be disposed in the memory cell region MCR in fig. 1, and other elements such as the address decoder 520, the read/write unit 530, the data input/output (I/O) unit 540, the voltage generating unit 550, and the control logic 560 may be disposed in the peripheral circuit region PCR in fig. 1.

The memory cell array 510 may be connected to an address decoder 520 through word lines WL and select lines. For example, the selection lines may include a string selection line SSL and a ground selection line GSL. The memory cell array 510 may be connected to the read-write unit 530 through a bit line BL.

The memory cell array 510 may include a plurality of memory cells. For example, the memory cell array 510 may include memory cells arranged in a row direction and a column direction. For example, memory cell array 510 may include a plurality of memory cells, each cell storing one or more bits of data. For example, the memory cell array 510 may have a vertical NAND flash memory structure as shown in fig. 4.

The address decoder 520 may be connected to the memory cell array 510 through a word line WL, a string selection line SSL, and a ground selection line GSL. Address decoder 520 may operate in response to control by control logic 560. The address decoder 520 may receive the address ADDR from an external device such as a memory controller.

Address decoder 520 may decode a row address in the received address ADDR. The address decoder 520 may select at least one word line corresponding to the decoded row address among the word lines WL. The address decoder 520 may select at least one selection line corresponding to the decoded row address among the selection lines including the string selection line SSL and the ground selection line GSL.

The address decoder 520 may transfer various voltages received from the voltage generating unit 550 to the selected word line, the unselected word line, the selected select line, and the unselected select line.

Address decoder 520 may decode column addresses in received address ADDR. In addition, the address decoder 520 may transfer the decoded column address DCA to the read-write unit 530.

In an exemplary embodiment of the inventive concept, the address decoder 520 may include a row decoder decoding a row address, a column decoder decoding a column address, and an address buffer storing the received address ADDR.

The read/write unit 530 may be connected to the memory cell array 510 through a bit line BL and may be connected to the data I/O unit 540 through a data line DL. The read-write unit 530 may operate in response to control of the control logic 560. The read-write unit 530 may receive the decoded column address DCA from the address decoder 520. Based on the decoded column address DCA, the read-write unit 530 may select at least one bit line among the bit lines BL.

In an exemplary embodiment of the inventive concept, the read-write unit 530 may receive data from the data I/O unit 540 and may write the received data into the memory cell array 510. The read-write unit 530 may read data from the memory cell array 510 and may transfer the read data to the data I/O unit 540. The read-write unit 530 may read data from the first storage area of the memory cell array 510 and may write the read data in the second storage area of the memory cell array 510. For example, the read-write unit 530 may perform copy-back (copy-back) operation.

In an exemplary embodiment of the inventive concept, the read-write unit 530 may include components such as a page buffer (or page register) and a column selection circuit. In an exemplary embodiment of the inventive concept, the read-write unit 530 may include components such as a sense amplifier, a write driver, and a column selection circuit.

The data I/O unit 540 may be connected to the read/write unit 530 through a data line DL. The data I/O unit 540 may operate in response to control of the control logic 560. The DATA I/O unit 540 may exchange DATA with an external device. The DATA I/O unit 540 may transfer the DATA from the external device to the read/write unit 530 through the DATA line DL. The DATA I/O unit 540 may output the DATA transferred from the read/write unit 530 through the DATA line DL to an external device. In an exemplary embodiment of the inventive concept, the data I/O unit 540 may include a component such as a data buffer.

The voltage generating unit 550 is connected to the memory cell array 510, the address decoder 520, and the control logic 560. The voltage generating unit 550 may receive power from an external device. In an exemplary embodiment of the inventive concept, the voltage generating unit 550 may receive the power supply voltage Vcc and the ground voltage Vss from an external device. The voltage generating unit 550 may generate voltages having various levels from the power supply voltage Vcc and the ground voltage Vss based on the control of the control logic 560. In an exemplary embodiment of the inventive concept, the voltage generating unit 550 may generate various voltages, such as a high voltage Vpp, a program voltage Vpgm, a pass voltage Vpass, a read voltage Vread, and an erase voltage Vers.

The voltage generated by the voltage generating unit 550 may be supplied to the address decoder 520 and the memory cell array 510 based on the control of the control logic 560. For example, the program voltage Vpgm and the pass voltage Vpass may be supplied to the address decoder 520 during a program operation. The read voltage Vread may be supplied to the address decoder 520 during a read operation. The erase voltage Vers may be supplied to the memory cell array 510 during an erase operation.

The voltage generated by the voltage generating unit 550 is not limited to the above voltage.

The control logic 560 may be connected to the address decoder 520, the read-write unit 530, and the data I/O unit 540. The control logic 560 may control the general operation of the memory device 500. The control logic 560 may operate in response to a control signal CTRL transmitted from an external device.

Fig. 17 and 18 are diagrams illustrating a memory package according to an exemplary embodiment of the inventive concept.

Referring to fig. 17, the memory package 700 includes a base substrate 710 and a plurality of memory chips CHP1, CHP2, and CHP3 stacked on the base substrate 710.

Each of the memory chips CHP1 to CHP3 may include a peripheral circuit region PCR and a memory cell region MCR, and may further include a plurality of I/O pads IOPAD. The peripheral circuit region PCR may include a semiconductor substrate, a peripheral circuit disposed on a first surface (e.g., a top surface) of the semiconductor substrate, and a first wiring layer disposed on the peripheral circuit. Further, the peripheral circuit may include at least one transistor. The memory cell region MCR may include a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer on the memory cell array. The plurality of I/O pads IOPAD may be disposed on the second wiring layer.

Each of the memory chips CHP1 to CHP3 may be implemented with a memory device according to an exemplary embodiment of the inventive concept. For example, a second wiring layer (e.g., an upper wiring layer) in each of the memory chips CHP1 to CHP3 may include at least one upper wiring electrically connected to at least one transistor in the peripheral circuit. The at least one upper wiring may be one electrically connectable to the power supply wiring, and thus a power supply option for the at least one transistor may be efficiently and easily selected based on the at least one upper wiring by changing a connection of one of the power supply wirings and the upper wiring.

In an exemplary embodiment of the inventive concept, the memory chips CHP1 to CHP3 may be stacked on the base substrate 710 such that a surface on which the plurality of I/O pads IOPAD may be disposed faces upward. For example, the memory chips CHP1 to CHP3 may be stacked in a state that the lower side is downward such that the second surface (e.g., bottom surface) of the semiconductor substrate 730 of each memory chip faces downward. In other words, the memory cell region MCR may be located on the peripheral circuit region PCR with respect to each of the memory chips CHP1 to CHP 3.

In exemplary embodiments of the inventive concept, the plurality of I/O pads IOPAD may be disposed near one side of the semiconductor substrate with respect to each of the memory chips CHP1 to CHP 3. Thus, the memory chips CHP1 to CHP3 may be stacked stepwise, i.e., stacked in a step shape, such that the plurality of I/O pads IOPAD of each memory chip may be exposed (e.g., the plurality of I/O pads IOPAD may be exposed on an edge of each step). In such a stacked state, the memory chips CHP1 to CHP3 may be electrically connected to the base substrate 710 through a plurality of bonding wires BW.

The stacked memory chips CHP1 to CHP3 and the bonding wire BW may be fixed by a sealing member 740, and an adhesive member 730 may be interposed between the base substrate 710 and the memory chips CHP1 to CHP 3. Conductive bumps 720 may be disposed on the bottom surface of the base substrate 710 for electrical connection to external devices.

Referring to fig. 18, the memory package 700a includes a base substrate 710 and a plurality of memory chips CHP1', CHP2', and CHP3' stacked on the base substrate 710.

The memory package 700a of fig. 18 may be substantially the same as the memory package 700 of fig. 17, except that the arrangement of the plurality of I/O pads IOPAD ' and the stacked structure of the memory chips CHP1' -CHP3' are changed in the memory package 700a of fig. 18.

Each of the memory chips CHP1' -CHP3' may include a peripheral circuit region PCR and a memory cell region MCR, and may further include the plurality of I/O pads IOPAD '. The peripheral circuit region PCR may include a semiconductor substrate, a peripheral circuit disposed on a first surface (e.g., a top surface or an upper surface) of the semiconductor substrate, and a first wiring layer disposed on the peripheral circuit. The peripheral circuitry may include at least one transistor. The memory cell region MCR may include a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer on the memory cell array.

The plurality of I/O pads IOPAD' may be disposed on a second surface (e.g., a bottom surface) of the semiconductor substrate opposite the first surface of the semiconductor substrate. The I/O pad IOPAD' may cover a through-substrate via (TSV) TSV provided in the peripheral circuit region PCR. The I/O pad IOPAD' may then be electrically connected to at least one lower wiring included in a first wiring layer (e.g., a lower wiring layer) of the peripheral circuit region PCR.

The plurality of I/O pads IOPAD ' may vertically overlap with a portion of the memory cell region MCR in which the memory cell array is disposed, with respect to each of the memory chips CHP1' -CHP3 '.

In some exemplary embodiments of the inventive concept, the memory chips CHP1' -CHP3' may be stacked on the base substrate 710 such that a surface on which the plurality of I/O pads IOPAD ' may be disposed faces upward. For example, the memory chips CHP1'-CHP3' may be stacked in an inverted state such that the second surface (e.g., bottom surface) of the semiconductor substrate of each memory chip faces upward. In other words, the memory cell region MCR may be located under the peripheral circuit region PCR with respect to each of the memory chips CHP1'-CHP 3'.

Fig. 19 is a block diagram illustrating a solid state disk or Solid State Disk (SSD) according to an exemplary embodiment of the inventive concept.

Referring to fig. 19, the SSD 1000 may include a plurality of nonvolatile memory devices 1100 and an SSD controller 1200.

Alternatively, the nonvolatile memory device 1100 may be supplied with the external high voltage VPP. Each of the nonvolatile memory devices 1100 may include the vertical NAND flash memory device described above. The nonvolatile memory device 1100 may have a COP structure and an upper wiring layer including an upper wiring according to an exemplary embodiment of the inventive concept, as described with reference to fig. 1 to 18.

SSD controller 1200 can be connected to nonvolatile memory device 1100 through multiple channels CH1, CH2, CH3 … … CHi. SSD controller 1200 may include one or more processors 1210, buffer memory 1220, error Correction Code (ECC) block 1230, host interface 1250, and non-volatile memory interface 1260.

The buffer memory 1220 may store data for driving the SSD controller 1200. The buffer memory 1220 may include a plurality of memory lines each storing data or instructions. Although fig. 19 illustrates an exemplary embodiment of the inventive concept in which the buffer memory 1220 is included in the SSD controller 1200, the inventive concept is not limited thereto. For example, the buffer memory 1220 may be located outside the SSD controller 1200.

The ECC block 1230 may calculate an error correction code value of data and may be programmed during a program operation, and may correct errors of the read data using the error correction code value during a read operation. In the data recovery operation, the ECC block 1230 may correct errors of the data recovered from the nonvolatile memory device 1100. In addition, a code memory may be included to store code data required to drive the SSD controller 1200. The code memory may be implemented by a nonvolatile memory device.

Host interface 1250 may provide an interface to external devices. A non-volatile memory (NVM) interface 1260 may provide an interface to the non-volatile memory device 1100.

Fig. 20 is a block diagram illustrating an embedded multimedia card (eMMC) according to an exemplary embodiment of the inventive concept.

Referring to fig. 20, the emmc 2000 may include one or more NAND flash memory devices 2100 and a controller 2200.

As described with reference to fig. 1 to 18, according to an exemplary embodiment of the inventive concept, the NAND flash memory device 2100 may have a COP structure and an upper wiring layer including an upper wiring.

The controller 2200 may be connected with the NAND flash memory device 2100 via a plurality of channels. The controller 2200 may include one or more controller cores 2210, a host interface 2250, and a NAND interface 2260. The controller core 2210 may control the entire operation of the eMMC 2000. Host interface 2250 may provide an interface between controller 2200 and host 2010. The NAND interface 2260 may provide an interface between the NAND flash memory device 2100 and the controller 2200.

In an exemplary implementation of the inventive concept, the host interface 2250 may be a parallel interface (e.g., an MMC interface). In other exemplary embodiments of the inventive concept, the host interface 2250 may be a serial interface (e.g., UHS-II, UFS, etc.).

eMMC 2000 may receive supply voltages VCC and VCCq from host 2010. For example, a power supply voltage VCC (e.g., about 3.3V) may be supplied to the NAND flash memory device 2100 and the NAND interface 2260, and a power supply voltage VCCq (e.g., about 1.8V/3.3V) may be supplied to the controller 2200. In an exemplary embodiment of the inventive concept, the eMMC 2000 may be optionally supplied with an external high voltage VPP. Further, alternatively, the external high voltage VPP may be supplied to the NAND flash memory device 2100.

Fig. 21 is a block diagram illustrating a universal flash memory (UFS) according to an exemplary embodiment of the inventive concept.

Referring to fig. 21, UFS system 3000 may include UFS host 3100, UFS devices 3200 and 3300, embedded UFS device 3400, and removable UFS card 3500.

UFS host 3100 can be an application processor of a mobile device. Each of UFS host 3100, UFS devices 3200 and 3300, embedded UFS device 3400, and removable UFS card 3500 may communicate with an external device via a UFS protocol. At least one of UFS devices 3200 and 3300, embedded UFS device 3400, and removable UFS card 3500 may be implemented by a non-volatile memory device. As described with reference to fig. 1 to 18, according to an exemplary embodiment of the inventive concept, the nonvolatile memory device may have a COP structure and an upper wiring layer including an upper wiring.

The embedded UFS device 3400 and the removable UFS card 3500 may communicate using a protocol other than the UFS protocol. UFS host 3100 and removable UFS card 3500 can communicate through various card protocols (e.g., UFD, MMC, secure Digital (SD), mini SD, micro SD, etc.).

Referring to fig. 22, the mobile device 4000 may include an application processor 4100, a communication module 4200, a display/touch module 4300, a storage 4400, and a mobile Random Access Memory (RAM) (e.g., buffer RAM) 4500.

The application processor 4100 may control the operation of the mobile device 4000. The communication module 4200 may be implemented to perform wireless or wired communication with external devices. The display/touch module 4300 may be implemented to display data processed by the application processor 4100 or to receive data through a touch panel. The storage 4400 may be implemented to store user data. The mobile RAM (e.g., buffer RAM) 4500 may temporarily store data for processing operations of the mobile device 4000.

In an exemplary embodiment of the inventive concept, the memory device 4400 may be, for example, a eMMC, SSD, UFS device or the like. The memory device 4400 may include a nonvolatile memory device. As described with reference to fig. 1 to 18, according to an exemplary embodiment of the inventive concept, the nonvolatile memory device may have a COP structure and an upper wiring layer including an upper wiring.

A memory device or a memory apparatus according to an exemplary embodiment of the inventive concept may be packaged using various package types or package configurations, such as a package on package (PoP), a Ball Grid Array (BGA), a Chip Scale Package (CSP), a leaded plastic chip carrier (PLCC), a plastic dual in-line package (PDIP), a waffle die package (Die in Waffle Pack), a wafer die (Die in Wafer form), a Chip On Board (COB), a ceramic dual in-line package (CERDIP), a plastic Metric Quad Flat Package (MQFP), a Thin Quad Flat Package (TQFP), a Small Outline Integrated Circuit (SOIC), a narrow pitch small outline package (SSOP), a Thin Small Outline Package (TSOP), a System In Package (SIP), a multi-chip package (MCP), a wafer level manufacturing package (WFP), a wafer level processing stack package (WSP), and the like.

The present disclosure may be applied to a variety of devices and systems. For example, the present disclosure may be applied to systems such as mobile phones, smart phones, personal Digital Assistants (PDAs), portable Multimedia Players (PMPs), digital cameras, video cameras, personal Computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, and the like.

The above is illustrative of exemplary embodiments of the inventive concept and should not be construed as limiting the same. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limited to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as additional exemplary embodiments, are intended to be included within the scope of the appended claims.

Claims

1. A memory device, comprising:

a substrate;

peripheral circuitry disposed on the first surface of the substrate, wherein the peripheral circuitry includes a first transistor;

a first wiring layer disposed on the peripheral circuit;

a base layer provided on the first wiring layer;

a memory cell array disposed on the base layer; and

and a second wiring layer disposed on the memory cell array, wherein the second wiring layer includes:

A first power supply wiring configured to supply a first voltage;

a second power supply wiring configured to supply a second voltage;

a first wiring electrically connected to the first transistor, wherein the first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring; and

a first connection wiring electrically connecting the first wiring to the first power supply wiring or the second power supply wiring,

wherein each of the first power supply wiring and the second power supply wiring extends in a first direction, and the first power supply wiring and the second power supply wiring are spaced apart from each other,

wherein the first wiring is provided between the first power supply wiring and the second power supply wiring, the first voltage is supplied to the first transistor through the first wiring in a case where the first wiring is electrically connected to the first power supply wiring through the first connection wiring, and

in the case where the first wiring is electrically connected to the second power supply wiring through the first connection wiring, the second voltage is supplied to the first transistor through the first wiring.

2. The memory device according to claim 1, wherein the first power supply wiring and the second power supply wiring, the first wiring, and the first connection wiring are provided on the same plane.

3. The memory device according to claim 1, wherein the first wiring is electrically connected to a gate electrode of the first transistor.

4. The memory device of claim 3, further comprising:

a first contact and a second contact are provided through a portion of an insulating layer included in the first wiring layer.

5. The memory device of claim 4, wherein the first contact electrically connects the gate electrode of the first transistor with a second wiring included in the first wiring layer,

wherein the second contact electrically connects the first wiring with the second wiring.

6. The memory device of claim 1 wherein the peripheral circuit further comprises a second transistor,

wherein the second wiring layer further includes a second wiring electrically connected to the second transistor, wherein the second wiring is configured to be electrically connectable to the first power wiring or the second power wiring.

7. The memory device of claim 1 wherein the peripheral circuit further comprises a second transistor,

wherein the second wiring layer further includes:

a third power supply wiring configured to supply the first voltage;

a second wiring electrically connected to the second transistor, the second wiring being configured to be electrically connectable to the second power supply wiring or the third power supply wiring; and

And a second connection wiring electrically connecting the second wiring to the second power supply wiring or the third power supply wiring.

8. The memory device of claim 7, wherein each of the first power supply wiring, the second power supply wiring, and the third power supply wiring extends in a first direction, and the first power supply wiring, the second power supply wiring, and the third power supply wiring are spaced apart from each other,

the second wiring is arranged between the second power wiring and the third power wiring.

9. The memory device of claim 1, wherein the first voltage is a supply voltage and the second voltage is a ground voltage.

10. The memory device of claim 1, wherein the base layer comprises polysilicon or monocrystalline silicon.

11. The memory device of claim 10, wherein the base layer is divided into a plurality of base layer patterns, and each of the plurality of base layer patterns functions as a p-type well.

12. The memory device of claim 1, wherein the array of memory cells comprises a plurality of vertical NAND flash memory cells.

13. The memory device of claim 1, wherein the memory cell array comprises:

A plurality of channels extending in a first direction perpendicular to the first surface; and

and a plurality of gate lines surrounding an outer sidewall of the channel, the plurality of gate lines being stacked in the first direction and spaced apart from each other.

14. A memory package, comprising:

a base substrate; and

a plurality of memory chips stacked on the base substrate, each of the plurality of memory chips including:

a substrate;

a first wiring layer disposed on the peripheral circuit;

a base layer provided on the first wiring layer;

a memory cell array disposed on the base layer; and

a first power supply wiring configured to supply a first voltage;

a second power supply wiring configured to supply a second voltage;

15. A memory device, comprising:

a substrate;

a peripheral circuit disposed on the first surface of the substrate, the peripheral circuit including a first transistor and a second transistor;

a lower wiring layer disposed on the peripheral circuit;

a base layer disposed on the lower wiring layer;

a memory cell array disposed on the base layer, wherein the memory cell array includes a plurality of channels; and

an upper wiring layer disposed on the memory cell array, wherein the upper wiring layer includes:

At least two power supply wirings, wherein a first power supply wiring of the at least two power supply wirings is configured to supply a first voltage and a second power supply wiring of the at least two power supply wirings is configured to supply a second voltage;

a first wiring electrically connected to the first transistor, wherein the first wiring is configured to be electrically connectable to the first power supply wiring or the second power supply wiring;

a second wiring electrically connected to the second transistor, wherein the second wiring is configured to be electrically connectable to the first power wiring or the second power wiring;

a first connection wiring electrically connecting the first wiring to the first power supply wiring or the second power supply wiring; and

a second connection wiring electrically connecting the second wiring to the first power wiring or the second power wiring,

wherein the first wiring and the second wiring are provided between the first power supply wiring and the second power supply wiring,

in the case where the first wiring is electrically connected to the first power supply wiring through the first connection wiring, the first voltage is supplied to the first transistor through the first wiring, and

16. The memory device of claim 15, wherein the plurality of channels are arranged in a second direction to form at least one channel row, and channels of the plurality of channels disposed in adjacent channel rows are arranged in a zigzag manner.

17. The memory device of claim 15, wherein the base layer is divided into a plurality of base layer patterns by a plurality of separation layer patterns.

18. The memory device of claim 15, wherein the plurality of channels extend in a first direction perpendicular to the first surface of the substrate.

19. The memory device of claim 18, wherein the memory cell array comprises a plurality of gate lines surrounding an outer sidewall of the channel, wherein the plurality of gate lines are stacked in the first direction, spaced apart from each other, and shared by the plurality of channels.