CN108346594A - Semiconductor packages limited part - Google Patents
Semiconductor packages limited part Download PDFInfo
- Publication number
- CN108346594A CN108346594A CN201710056146.1A CN201710056146A CN108346594A CN 108346594 A CN108346594 A CN 108346594A CN 201710056146 A CN201710056146 A CN 201710056146A CN 108346594 A CN108346594 A CN 108346594A
- Authority
- CN
- China
- Prior art keywords
- support plate
- limited part
- semiconductor packages
- chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
Abstract
This exposure provides a kind of semiconductor packages limited part, the first support plate and chip to be fixed on the second support plate.Semiconductor packages limited part includes the first bottom surface and the second bottom surface.First bottom surface contacts the first surface of the second support plate.Second bottom surface contacts the first surface of chip.
Description
Technical field
This exposure is related to a kind of semiconductor packages limited part, is particularly related in reflow process for limiting semiconductor
The semiconductor packages limited part of encapsulation.
Background technology
Integrated circuit is formed on the semiconductor wafer, then engages semiconductor wafer onto package substrates.It was engaging
The journey phase asks, directly chip is positioned on reflow machine hot plate and carries out reflow, does not apply additional auxiliary and sets tool, this is easy in crystalline substance
Apparent warpage is caused in piece.Because chip warpage causes temperature uniformity when reflow process to be unevenly distributed, generated in Waffer edge
Reflow is incomplete, and the yield loss of most serious is up to 50%.
Invention content
The embodiment of this exposure provides a kind of semiconductor packages limited part, the first support plate and chip are fixed to the
On two support plates.The semiconductor packages limited part includes the first bottom surface, contacts the first surface of the second support plate；And second bottom
Face contacts the first surface of chip.In one or more embodiments, the semiconductor packages limited part includes third bottom surface,
It contacts the first surface of first support plate.In one or more embodiments, first bottom surface is less than second bottom surface,
The third bottom surface is less than second bottom surface, and first bottom surface is less than the third bottom surface.In one or more embodiments,
First bottom surface, second bottom surface and the third bottom surface are arranged in step shape.In one or more embodiments, described half
It is the cyclic structure around the chip that conductor, which encapsulates limited part,.In one or more embodiments, the semiconductor packages limitation
Part further includes third support plate, wherein first support plate is above the third support plate.
Another embodiment of this exposure provides a kind of separable semiconductor packages limited part, to by the first support plate and
Chip is fixed on the second support plate.The semiconductor packages limited part includes：First bottom surface, separably in the second support plate
On；And second bottom surface, separably on chip.In one or more embodiments, the semiconductor packages limited part includes
Third bottom surface contacts the first surface of first support plate.In one or more embodiments, first bottom surface is less than described
Second bottom surface, the third bottom surface are less than second bottom surface, and first bottom surface is less than the third bottom surface.At one or more
In embodiment, first bottom surface, second bottom surface and the third bottom surface are arranged in step shape.In one or more embodiments
In, the semiconductor packages limited part is the cyclic structure around the chip.In one or more embodiments, the semiconductor
Encapsulation limited part further includes third support plate, wherein first support plate is above the third support plate.
Description of the drawings
By the various aspects described further below for being able to most preferably understanding present application disclosure with subsidiary schema.Note that root
According to the Standard implementation of industry, various features are not painted to scale.In fact, for clear discussion, can arbitrarily increase or
Reduce the size of various features.
1st figure is painted the top view of the chip and semiconductor packages limited part of the embodiment of this exposure.
2nd figure is painted the sectional view of the chip and semiconductor packages limited part of the present embodiment.
3rd figure is painted the sectional view of the chip and semiconductor packages limited part of another embodiment of this exposure.
Specific implementation mode
This exposure provides several different implementations or embodiment, can be used for realizing the different characteristic of the present invention.For
For the sake of simplifying explanation, this exposure also describes specific spare part and the example of arrangement simultaneously.It please notes that and these particular examples is provided
Purpose be only that demonstration, rather than give any restrictions.For example, illustrate fisrt feature how in second feature following
May include some embodiments or in the narration of top, wherein fisrt feature is in direct contact with second feature, and in describing
It may also include other different embodiments, wherein separately have other feature among fisrt feature and second feature, so that first is special
Sign with second feature and be not directly contacted with.In addition, the various examples in this exposure may use the reference number and/or text repeated
Word annotation so that file simplerization and clear, these reference numbers repeated do not represented from annotation different embodiments and
Relevance between configuration.
In addition, this is disclosed in the narration vocabulary used with space correlation, as " ... under ", " low ", "lower", " top ", "
When upper ", " ... on " and similar vocabulary, for ease of narration, usage be in description diagram an elements or features with
The relativeness of another (or multiple) elements or features.Other than angle direction shown in diagram, these spaces are opposite
Vocabulary is also used for describing possibility angle and direction when described device in use and operation.The angle direction of described device can
Can different (are rotated by 90 ° or other orientation), and these space correlations used in this exposures describe and can be subject in the same fashion
It explains.
Herein used in " first ", " second ", " third " and " the 4th " word describe various elements, component,
Region, layer and/or section, these elements, component, region, layer and/or section should be not only restricted to these words.These
Word can be only used for element, component, region, layer or section and another element, component, region, layer or section.Unless in interior text
It clearly indicates, otherwise when using such as " first ", " second ", " third " and " the 4th " word in this article, is not meant as
Sequence or sequence.
Chip and substrate can be fixed in heating plate by semiconductor packages limited part described in this exposure, accelerate heating
The speed that plate heats chip, and then promote the efficiency of reflow process.
Refering to the 1st figure.1st figure is painted the top view of the chip and semiconductor packages limited part of the embodiment of this exposure.Such as
Shown in 1st figure, the semiconductor packages limited part 101 of the present embodiment is around chip 100.Fig. 2 be Fig. 1 in along A-A' section
Figure.
Refering to the 2nd figure.In fig. 2, semiconductor packages limited part 201 is stairstepping.Semiconductor packages limited part 201 has
There are bottom surface 202, bottom surface 203 and bottom surface 204.Bottom surface 202 is less than bottom surface 203.204 are less than bottom surface 203.Bottom surface 202 is less than bottom surface
204.Bottom surface 202, bottom surface 203 and bottom surface 204 are arranged in step shape.Bottom surface 202 contacts the surface 207 of support plate 206.Bottom surface 203
Contact the surface 208 of chip 200.Bottom surface 204 contacts the surface 209 of support plate 205.Chip 200 passes through sticker 210 and support plate
205 engagements.Chip 200 is fixed on support plate 205 by a part 211 for semiconductor packages limited part 201.Semiconductor packages limits
Support plate 205 is fixed on support plate 206 by another part 212 of part 201.
(in encapsulation process, such as in reflow process) support plate 205, sticker can be transferred heat to via support plate 206
210 and chip 200 bare die 213 (as shown in arrow 214).It can pass through the part 211 and part of semiconductor packages limited part 201
212 transfer heat to chip 200 (as shown in arrow 215).This may make chip 200 to be more rapidly heated and reaches thermal balance.Half
Conductor encapsulates the material that limited part 201 can be thermal conduction characteristic good (such as thermal coefficient is big).Semiconductor packages limited part 201 can be
Metal.Semiconductor packages limited part 201 can limit the warpage degree of chip 200.The width of part 212 can be about 0.35 millimeter.
The radius of support plate 205 can be 200 millimeters or 300 millimeters.
Reflow process can carry out in about 200 DEG C to about 300 DEG C of environment.Reflow process can be in about 260 DEG C of environment
It carries out.The melting temperature of sticker 210 is up to about 300 DEG C at about 200 DEG C.In one or more embodiments, support plate 205 may include selecting
From the one of which of silicon, stainless steel, glass and mold compound.Useful binders (not shown) between bottom surface 202 and surface 207
Bonding.In one or more embodiments, since chip 200 is the two-sided process with carrier, semiconductor limited part 201 can design
To be ladder-like to meet two-sided process.Semiconductor packages limited part 201 can chip 200 be arranged on support plate 206 after again with
Support plate 206 contacts.
Semiconductor packages limited part 201 may include having magnetic material.Semiconductor packages limited part 201 may include not having
Magnetic material.Semiconductor packages limited part 201 can be engaged by magnetic force with support plate 206.206 bearing semiconductor of support plate encapsulates
The weight of limited part 201.Semiconductor packages limited part 201 can be engaged by adhesive (not shown) with support plate 206.It had been heated
Journey can limit chip when chip 200 generates warpage or deformation because heated by the weight of semiconductor packages limited part 201
200 warpage degree.In thermal histories, when chip 200 generates warpage or deformation because heated, if semiconductor packages limits
When part 201 and the adhesive (not shown) of support plate 206 reach fusing point or can not provide bonding effect, it can be limited by semiconductor packages
The warpage degree of the weight limitation chip 200 of product 201.In thermal histories, when chip 200 generates warpage or deformation because heated
When, the warpage degree of chip 200 can be limited by the magnetic force between semiconductor packages limited part 201 and support plate 206.It had been heated
Journey, when chip 200 generates warpage or deformation because heated, if the adhesive of semiconductor packages limited part 201 and support plate 206
When (not shown) reaches fusing point or can not provide bonding effect, the magnetic between semiconductor packages limited part 201 and support plate 206 can be passed through
The warpage degree of power limit chip 200.It is stuck up in thermal histories when chip 200 generates larger warpage or deformation because heated
Bent or deformation strength is likely larger than the weight of semiconductor limited part 201 and semiconductor limited part 201 is caused to be detached from support plate 206,
Chip 200 is avoided to rupture.In thermal histories, when chip 200 generates larger warpage or deformation because heated, warpage or deformation
Strength be likely larger than the weight of semiconductor limited part 201 plus the magnetic force between semiconductor packages limited part 201 and support plate 206 and
Cause semiconductor limited part 201 to be detached from support plate 206, chip 200 is avoided to rupture.In addition, can more simplify crystalline substance using magnetic connection
Step and time on support plate 206 is arranged in piece 200.
Referring now to Fig. 3.In another embodiment, semiconductor packages limited part 301 is stairstepping.Semiconductor packages limits
Part 301 has bottom surface 302, bottom surface 303 and bottom surface 304.Bottom surface 302 is less than bottom surface 303.Bottom surface 304 is less than bottom surface 303.Bottom surface
302 are less than bottom surface 304.Bottom surface 302, bottom surface 303 and bottom surface 304 are arranged in step shape.Bottom surface 302 contacts the surface of support plate 306
307.Bottom surface 303 contacts the surface 308 of chip 300.Bottom surface 304 contacts the surface 309 of support plate 305.Chip 300 passes through sticker
310 engage with the first support plate 305.Chip 300 is fixed on support plate 305 by a part 311 for semiconductor packages limited part 301.
Support plate 305 is fixed on support plate 306 by a part 312 for semiconductor packages limited part 301.Support plate 306 contacted with support plate 313 and
It is fixed on support plate 313.Support plate 305 is above support plate 313.Support plate 306 is above support plate 313.
(in encapsulation process, such as in reflow process) support plate can be transferred heat to via support plate 310, support plate 306
305, the bare die 314 of sticker 310 and chip 300 (as shown in arrow 315).It can pass through the portion of semiconductor packages limited part 301
Points 311 and part 312 transfer heat to chip 300 (as shown in arrow 316).This may make chip 300 to be more rapidly heated and reaches
To thermal balance.Semiconductor packages limited part 301 can be the material of thermal conduction characteristic good (such as thermal coefficient is big).Semiconductor packages limits
Product 301 can be metal.Semiconductor packages limited part 301 can limit the warpage degree of chip 300.The width of part 312 can be
About 0.35 millimeter.In one or more embodiments, the radius of support plate 305 can be 200 millimeters or 300 millimeters.
Reflow process can carry out in about 200 DEG C to about 300 DEG C of environment.Reflow process can be in about 260 DEG C of environment
It carries out.The melting temperature of sticker 610 is up to about 300 DEG C at about 200 DEG C.Support plate 305 may include selected from silicon, stainless steel, glass and
The one of which of mold compound.Useful binders bonding (not shown) between bottom surface 302 and surface 307.Since chip 300 is
The two-sided process with carrier, semiconductor limited part 301 may be designed as ladder-like to meet two-sided process.In one or more implementations
In example, semiconductor packages limited part 301 can be contacted with support plate 306 again after chip 300 is arranged on support plate 306.
In one or more embodiments, semiconductor packages limited part 301 can be to have magnetic material.Semiconductor packages limits
Product 301 can be engaged by magnetic force with support plate 306.In reflow process, when chip 300 bestows semiconductor limited part because of warpage
When 301 active force is less than magnetic force, semiconductor limited part 301 can limit the warpage degree of chip 300.Once aforementioned active force
When more than magnetic force, semiconductor limited part 301 can be detached from support plate 306, and semiconductor limited part 301 is avoided to generate excessive reaction force
And chip 300 is caused to rupture.Such design can be considered as a kind of security mechanism, and chip 300 is avoided to be ruptured in reflow process.
Semiconductor packages limited part 301 may include having magnetic material.Semiconductor packages limited part 301 may include without magnetism
Material.Semiconductor packages limited part 301 can be engaged by magnetic force with support plate 306.306 bearing semiconductor of support plate encapsulates limited part
301 weight.Semiconductor packages limited part 301 can be engaged by adhesive (not shown) with support plate 306.In thermal histories, when
When chip 300 generates warpage or deformation because heated, chip 300 can be limited by the weight of semiconductor packages limited part 301
Warpage degree.In thermal histories, when chip 200 generates warpage or deformation because heated, if semiconductor packages limited part 301
When reaching fusing point with the adhesive (not shown) of support plate 306 or bonding effect can not be provided, semiconductor packages limited part can be passed through
The warpage degree of 301 weight limitation chip 300.In thermal histories, when chip 300 generates warpage or deformation because heated,
The warpage degree of chip 300 can be limited by the magnetic force between semiconductor packages limited part 301 and support plate 306.In thermal histories, when
When chip 300 generates warpage or deformation because heated, if semiconductor packages limited part 301 and the adhesive of support plate 306 (are not schemed
Show) when reaching fusing point or bonding effect can not be provided, it can be limited by the magnetic force between semiconductor packages limited part 301 and support plate 306
The warpage degree of combinations piece 200.In thermal histories, when chip 300 generates larger warpage or deformation because heated, warpage or
The strength of deformation is likely larger than the weight of semiconductor limited part 301 and semiconductor limited part 301 is caused to be detached from support plate 306, avoids
Chip 300 ruptures.In thermal histories, when chip 300 generates larger warpage or deformation because heated, the power of warpage or deformation
The weight that amount is likely larger than semiconductor limited part 301 causes plus the magnetic force between semiconductor packages limited part 301 and support plate 306
Semiconductor limited part 301 is detached from support plate 306, and chip 300 is avoided to rupture.In addition, can more simplify chip 300 using magnetic connection
Step on support plate 306 and time are set.
It is worth noting that visual other consider of the parameters such as size and type of above-mentioned semiconductor packages limited part and be subject to
Adjustment, without being limited with the revealed numerical value of above-described embodiment.
As used herein, word " approximatively ", " substantial ", " substantive " and " about " is describing and illustrate small change
Change.When being used in combination with event or situation, the word can refer to event or situation clearly there is a situation where and event or situation
Pole be similar to there is a situation where.For example, when in conjunction with numerical value in use, what the word can refer to less than or equal to the numerical value
± 10% variation range, e.g., less than or equal to ± 5%, be less than or equal to ± 4%, be less than or equal to ± 3%, be less than or wait
In ± 2%, be less than or equal to ± 1%, be less than or equal to ± 0.5%, be less than or equal to ± 0.1% or less than or equal to ±
0.05%.For by way of further example, " essence is orthogonal " can refer to ± 10% of variation range less than or equal to 90 ° (for example, being less than or waiting
In ± 5%, it is less than or equal to ± 4%, is less than or equal to ± 3%, is less than or equal to ± 2%, is less than or equal to ± 1%, is less than
Or be equal to ± 0.5%, be less than or equal to ± 0.1% or less than or equal to ± 0.05%).
In addition, pressing range format presentation amount, ratio and other numerical value herein sometimes.It should be understood that such range format
It uses for facility and for purpose of brevity, and should be interpreted flexibly to include not only to be expressly specified as the numerical value of range limit, and go back
Including all individual numbers or the subrange in the range are covered by, just as clearly specified each numerical value and subrange one
As.
Although having referred to the particular embodiment of the present invention describes and illustrate the present invention, these descriptions and explanation are not intended to limit
The present invention.Those skilled in the art will appreciate that not departing from the true of the present invention as defined by the appended claims
In the case of spirit and scope, it can be variously modified and available equivalents replace.Illustrate to be not drawn necessarily to scale.Attribution
Difference may be present between art recurring and actual device in process and tolerance, the present invention.Not certain illustrated may be present
Other embodiments of the invention.This specification and schema should be considered as illustrative and not restrictive.It can modify, so that special
Shape, material, material composition, method or the process of pledging love are adapted to the target of the present invention, spirit and scope.All modifications are anticipated
It is intended in the range of appended claims herein.Although being described herein referring to the specific operation being performed in a specific order
Disclosed in method, it should be appreciated that in the case where not departing from teachings of the present invention, can combine, divide again or re-sequence this
A little operations are to form equivalent method.Therefore, unless specific instruction herein, the order otherwise operated and grouping are not to the present invention
Limitation.
Symbol description
100 chips
101 semiconductor limited parts
200 chips
201 semiconductor limited parts
202 bottom surfaces
203 bottom surfaces
204 bottom surfaces
205 support plates
206 support plates
207 surfaces
208 surfaces
209 surfaces
210 stickers
211 parts
212 parts
213 bare dies
214 arrows
215 arrows
300 chips
301 semiconductor limited parts
302 bottom surfaces
303 bottom surfaces
304 bottom surfaces
305 support plates
306 support plates
307 surfaces
308 surfaces
309 surfaces
310 stickers
311 parts
312 parts
313 support plates
314 bare dies
315 arrows
316 arrows
Claims (12)
1. a kind of semiconductor packages limited part, the first support plate and chip to be fixed on the second support plate, the semiconductor package
Filling limited part includes：
First bottom surface contacts the first surface of the second support plate；
Second bottom surface contacts the first surface of chip.
2. semiconductor packages limited part according to claim 1, further includes：
Third bottom surface contacts the first surface of first support plate.
3. semiconductor packages limited part according to claim 2, wherein first bottom surface is less than second bottom surface, institute
It states third bottom surface and is less than second bottom surface, first bottom surface is less than the third bottom surface.
4. semiconductor packages limited part according to claim 3, wherein first bottom surface, second bottom surface and described
Third bottom surface is arranged in step shape.
5. semiconductor packages limited part according to claim 3, wherein the semiconductor packages limited part is around described
The cyclic structure of chip.
6. semiconductor packages limited part according to claim 1, further includes third support plate, wherein described first carries
Plate is above the third support plate.
7. a kind of separable semiconductor packages limited part, described the first support plate and chip to be fixed on the second support plate
Semiconductor packages limited part includes：
First bottom surface, separably on the second support plate；
Second bottom surface, separably on chip.
8. semiconductor packages limited part according to claim 7, further includes：
Third bottom surface contacts the first surface of the first support plate.
9. semiconductor packages limited part according to claim 7, wherein first bottom surface is less than second bottom surface, institute
It states third bottom surface and is less than second bottom surface, first bottom surface is less than the third bottom surface.
10. semiconductor packages limited part according to claim 9, wherein first bottom surface, second bottom surface and institute
It is arranged in step shape to state third bottom surface.
11. semiconductor packages limited part according to claim 9, wherein the semiconductor packages limited part is around described
The cyclic structure of chip.
12. semiconductor packages limited part according to claim 7, further includes third support plate, wherein described first
Support plate is above the third support plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710056146.1A CN108346594B (en) | 2017-01-25 | 2017-01-25 | Semiconductor package limiting part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710056146.1A CN108346594B (en) | 2017-01-25 | 2017-01-25 | Semiconductor package limiting part |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108346594A true CN108346594A (en) | 2018-07-31 |
| CN108346594B CN108346594B (en) | 2022-08-09 |
Family
ID=62961971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710056146.1A Active CN108346594B (en) | 2017-01-25 | 2017-01-25 | Semiconductor package limiting part |
Country Status (1)
| Country | Link |
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| CN (1) | CN108346594B (en) |
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| US20140359996A1 (en) * | 2013-06-05 | 2014-12-11 | International Business Machines Corporation | Laminate peripheral clamping to control microelectronic module bsm warpage |
| US20150235892A1 (en) * | 2014-02-18 | 2015-08-20 | HGST Netherlands B.V. | Wafer clamp for controlling wafer bowing and film stress |
| US20160351467A1 (en) * | 2015-05-28 | 2016-12-01 | International Business Machines Corporation | Limiting electronic package warpage |
| CN206639781U (en) * | 2017-01-25 | 2017-11-14 | 日月光半导体制造股份有限公司 | Semiconductor packages limited part |
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|---|---|---|---|---|
| US20020104622A1 (en) * | 2001-02-06 | 2002-08-08 | Bhola De | Wafer demount gas distribution tool |
| US20030019585A1 (en) * | 2001-07-19 | 2003-01-30 | Hitachi Kokusai Electric Inc. | Substrate processing apparatus and method for fabricating semiconductor device |
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| US20130113147A1 (en) * | 2011-11-08 | 2013-05-09 | Tokyo Ohka Kogyo Co., Ltd. | Substrate processing apparatus and substrate processing method |
| US20140359996A1 (en) * | 2013-06-05 | 2014-12-11 | International Business Machines Corporation | Laminate peripheral clamping to control microelectronic module bsm warpage |
| US20150235892A1 (en) * | 2014-02-18 | 2015-08-20 | HGST Netherlands B.V. | Wafer clamp for controlling wafer bowing and film stress |
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| CN206639781U (en) * | 2017-01-25 | 2017-11-14 | 日月光半导体制造股份有限公司 | Semiconductor packages limited part |
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| Publication number | Publication date |
|---|---|
| CN108346594B (en) | 2022-08-09 |
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