CN108346573B - Preparation method of semiconductor device - Google Patents
Preparation method of semiconductor device Download PDFInfo
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- CN108346573B CN108346573B CN201710058601.1A CN201710058601A CN108346573B CN 108346573 B CN108346573 B CN 108346573B CN 201710058601 A CN201710058601 A CN 201710058601A CN 108346573 B CN108346573 B CN 108346573B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
Abstract
The invention relates to a preparation method of a semiconductor device. The method comprises the following steps: providing a substrate; forming a plurality of first patterns and second patterns which are alternately arranged on the substrate by a directional self-assembly method; hardening the first pattern; and removing the second pattern. The method improves the low-frequency line width roughness of the device and the line edge roughness of the pattern, and further improves the performance and yield of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device.
Background
As semiconductor device sizes continue to shrink, it has been difficult to obtain finer pitch patterns using conventional Lithography (lithrography).
As a solution to the problem of making smaller size patterns, Directed self-assembly (DSA) technology has attracted attention. DSA techniques deposit a Block Copolymer (BCP) or polymer blend on a substrate, through a specific process to "direct" it into an ordered structure. DSA enables formation of small pitch patterns.
Under appropriate conditions, such copolymer blocks separate into micro-domains (also known as "domains") and, in the process, form nanoscale features of different chemical compositions. The ability of block copolymers to form such features makes them useful in nanopatterning to form features with smaller Critical Dimensions (CD), enabling the construction of features that are difficult to achieve using conventional lithography.
The DSA process is a preferred method for obtaining a finer pitch pattern due to a lower production cost and a smaller low frequency Line Width Roughness (LWR), and the DSA process is a process in which the block copolymer has a smaller hardness and thus is inclined or deformed during patterning, so that the low frequency Line Width Roughness (LWR) of the device and the Line Edge Roughness (LER) of the pattern are deteriorated, thereby causing adverse effects.
There is therefore a need for further improvements in the methods described herein to eliminate the above problems and further improve device yield and performance.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps:
providing a substrate;
forming a plurality of first patterns and second patterns which are alternately arranged on the substrate by a directional self-assembly method;
hardening the first pattern;
and removing the second pattern.
Optionally, the first pattern is hardened using a continuous infiltration synthesis process.
Optionally, in the continuous infiltration synthesis method, the hardening treatment is performed on the first pattern using a material containing aluminum to form the first pattern containing aluminum.
Optionally, the aluminum-containing material comprises trimethylaluminum.
Optionally, the step of hardening the first pattern and removing the second pattern includes:
removing the top layer of the second pattern to expose the top layer part of the first pattern;
hardening the exposed first pattern;
and repeating the steps of removing the top layer of the second pattern and hardening the exposed first pattern until the second pattern is removed and the first pattern is completely hardened.
Optionally, the substrate comprises a semiconductor substrate, a spin-coated carbon material, and a spin-coated glass, stacked in sequence.
Optionally, the method further comprises performing post-hardening treatment on the first pattern after removing the second pattern and the hardening treatment.
Optionally, the post-hardening treatment is performed on the first pattern using HBr-based plasma.
Optionally, the second pattern is removed using a gas cluster ion beam etching method or a ribbon plasma ion beam etching method.
Optionally, the directed self-assembly method comprises:
coating a polymer film comprising a block copolymer over the substrate;
and performing directed self-assembly on the block copolymer in the polymer film to form first domains and second domains which are alternately arranged as the first pattern and the second pattern respectively.
According to the invention, after a plurality of first patterns and second patterns which are mutually spaced and prepared by a directional self-assembly method, the first patterns are hardened to improve the hardness of the first patterns so as to ensure that the first patterns are not deformed or inclined in subsequent pattern transfer, the second patterns are removed so as to form gaps between the first patterns, and therefore the mutually spaced first patterns are formed, and the first patterns have higher hardness, so that the low-frequency Line Width Roughness (LWR) and the Line Edge Roughness (LER) of the patterns of the device are improved, and the performance and the yield of the semiconductor device are further improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 shows a flow chart of a process for fabricating a semiconductor device according to the present invention;
FIGS. 2A to 2D are schematic cross-sectional views showing structures obtained by implementing the method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIGS. 3A to 3D are schematic cross-sectional views showing structures obtained by implementing a method for manufacturing a semiconductor device according to another embodiment of the present invention;
fig. 4 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
A method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings, and fig. 1 shows a flow chart of a manufacturing process of the semiconductor device according to the present invention; fig. 2A to 2D are schematic cross-sectional views showing structures obtained by implementing the method for manufacturing a semiconductor device according to an embodiment of the present invention.
The invention provides a preparation method of a semiconductor device, as shown in figure 1, the main steps of the preparation method comprise:
step S1: providing a substrate;
step S2: forming a plurality of first patterns and second patterns which are alternately arranged on the substrate by a directional self-assembly method;
step S3: hardening the first pattern;
step S4: and removing the second pattern.
Next, a detailed description will be given of a specific embodiment of the method for manufacturing a semiconductor device of the present invention.
Firstly, a first step is executed, a substrate is provided, and a plurality of first patterns and second patterns which are alternately arranged are formed on the substrate through a directional self-assembly method.
Specifically, as shown in fig. 2A, the substrate at least includes a semiconductor substrate 201, and the semiconductor substrate 201 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and the like.
In this embodiment, the semiconductor substrate 201 is a silicon substrate, and various active or integrated devices may be further formed in the base, which is not described herein again.
In order to further improve the performance of the device, for example, the low frequency Line Width Roughness (LWR) and the Line Edge Roughness (LER) of the pattern, the Spin-coated carbon material 202 and Spin-on-Glass (SoG) 203 are further formed on the semiconductor substrate.
Dislocation of a pattern existing in the DSA can also be well solved by forming the spin-coated carbon material and SoG on the semiconductor substrate.
The Spin-on-Glass (SoG) 203 belongs to the Methyl Silsesquioxane (MSQ) family. The hydrogen silsesquioxane alkane (HSQ) film may also be used for spin coating. The Spin-on-Glass (SoG) is a low-K dielectric material with a dielectric constant of 2.7 to 3.1.
The method for preparing the plurality of first patterns 206 and the second patterns 205 which are spaced apart from each other by the directional self-assembly method comprises the following steps:
first, an Anti-reflection Coating (Anti-reflection Coating)/Polystyrene (PS) Brush layer (Brush layer), a positive photoresist layer 204, and a patterned mask plate (not shown) over the positive photoresist layer are sequentially formed on the substrate.
Specifically, the middle of the mask plate has a large opening to expose the photoresist 204, so that the mask plate is used as a template to expose the positive photoresist.
And exposing the photoresist, removing the exposed photoresist area in a developing solution, and exposing the brush layer below the photoresist layer.
A polymer film comprising a block copolymer is coated over the exposed brush layer.
Specifically, the block copolymer in the polymer film (BCP) is a diblock copolymer. In the following examples, the diblock copolymer is poly (styrene-block-methyl methacrylate) (PS-b-PMMA) as an example.
However, it should be noted that the block copolymer is not limited to the above examples, and poly (styrene-b-vinylpyridine), poly (styrene-b-butadiene), poly (styrene-b-isoprene), poly (styrene-b-methyl methacrylate), poly (styrene-b-alkenyl aromatic), poly (isoprene-b-ethylene oxide), poly (styrene-b- (ethylene-propylene)), poly (ethylene oxide-b-caprolactone), poly (butadiene-b-ethylene oxide), poly (styrene-b- (t-butyl) acrylate), poly (methyl methacrylate-b-t-butyl methacrylate), poly (ethylene oxide-b-propylene oxide), poly (styrene-b-vinyl acetate), poly (styrene-b-propylene oxide), poly (styrene-b-vinyl acetate), poly (styrene-, Poly (styrene-b-tetrahydrofuran) and poly (styrene-block-methyl methacrylate) (PS-b-PMMA).
The block copolymers in the polymer film undergo directed self-assembly to form domains of different composition, such as a first pattern 206 and a second pattern 205.
Wherein, the first pattern 206 is a first domain (domain) or a first micro domain (domain) formed after the copolymer block is separated, and the second pattern 205 is a second domain (domain) or a second micro domain formed after the copolymer block is separated.
Specifically, an annealing step is performed to anneal the BCP coating. For example, annealing may be performed using solvent annealing at room temperature (about 21 ℃). Alternatively, the temperature may be between about 25 c and about 300 c,
the annealing is performed for an annealing duration of between about 0.5 minutes and about 2 hours. As a result of the annealing step, phase separation occurs in the BCP layer, and the PS and PMMA are separated into parallel lengthwise multiple stripes.
In the embodiment shown, PS is labeled as the second pattern 205 and PMMA is labeled as the first pattern 206. The first patterns 206 and the second patterns 205 are positioned in an alternating arrangement, each first pattern 206 being located between two second patterns 205 and next to two second patterns 205, or vice versa, as shown in fig. 2A.
The alternating arrangement refers to an arrangement manner in which the first patterns 206 and the second patterns 205 are alternately arranged, as shown in fig. 2A.
And executing a second step of hardening the first pattern.
In order to solve the problem that the first pattern may be deformed or changed in profile in the process of forming the linear pattern by removing the second pattern by etching, the low frequency Line Width Roughness (LWR) and the Line Edge Roughness (LER) of the pattern are improved, and the first pattern is hardened before removing the second pattern, so that the hardness of the first pattern is improved.
Specifically, in the present invention, a Sequential Infiltration Synthesis (SIS) method is selected to harden the first pattern, by which a film composed of block copolymer macromolecules is used as a template to manufacture materials having various shapes and patterns.
Continuous Infiltration Synthesis (SIS) can produce materials that cannot be produced by ALD techniques alone or block copolymers, and can also better control the geometry and chemical composition of the produced materials. Using this block copolymer as the original substrate, materials with different shapes (from spherical to cylindrical to curved) can be formed by SIS techniques.
In the invention, the first pattern is subjected to continuous infiltration synthesis by using a material containing aluminum to form the first pattern containing aluminum.
More specifically, trimethyl aluminum is selected for continuous infiltration synthesis of the first pattern to form a first pattern 206 comprising aluminum, as shown in fig. 2B.
In this process, trimethyl aluminum is oxidized by water under the atmosphere of pure nitrogen and penetrates into the first pattern 207, and through the continuous circulation of penetration, a material layer containing aluminum is formed in the first pattern, the hardness of which is greatly improved and which becomes denser.
And step three, removing the second pattern 205.
Specifically, as shown in fig. 2C, the second pattern 205 is removed using a Gas Cluster Ion Beam (GCIB) etching method or a ribbon plasma etching method in this step.
Wherein the GCIB system may include a GCIB generating system and a molecular beam generating system, which may be used in combination to process a substrate within a vacuum chamber.
The GCIB and molecular beam may interact with each other or directly with the substrate within the vacuum chamber. For example, the interaction may occur at an offset distance from or at the exposed surface of the substrate. The angle of incidence between the GCIB and the molecular beam may vary from 0 to 90 degrees. In particular embodiments, the angle of incidence may vary from 5 degrees to 45 degrees. In these embodiments, the GCIB may have an angle of incidence with respect to the substrate from 0 degrees to 90 degrees. The GCIB may include a high pressure nozzle, a nozzle diverter positioned distal to an outlet of the high pressure nozzle, an ionizer positioned distal to an outlet of the nozzle diverter, and one or more accelerating electrodes.
The Gas Cluster Ion Beam (GCIB) is formed from a pressurized gas mixture containing at least one etching gas. The at least one etching gas may include a halogen element. The at least one etching gas may include a halogen element and one or more elements selected from C, H, N and S.
The second pattern may also be etched with a selection of beam energy, beam energy distribution, beam angular distribution, beam divergence angle, stagnation pressure, stagnation temperature, mass flow rate (mass flow rate), cluster size distribution, beam size, beam composition, beam electrode potential, or gas nozzle design (e.g., nozzle throat diameter, nozzle length, and/or nozzle branch half angle).
Any one or more of the foregoing GCIB properties may be selected to achieve control of a target etch process index (e.g., those noted above). Further, any one or more of the foregoing GCIB properties can be modified to achieve control of a target etch process index (e.g., those noted above).
For example, the beam acceleration potential of the GCIB can vary from about 1kV to about 70kV (i.e., the beam energy can vary from about 1keV to about 70keV, assuming uniform average cluster charge states). Additionally, for example, the beam dose of the GCIB canTo from about 1 × 10 per square centimeter12Clustering to about 1 × 10 per square centimeter14The clusters change.
GCIB can be established with energy per atom ratios varying from about 0.25eV per atom to about 100eV per atom. Alternatively, GCIB can be established with energy per atom ratios varying from about 0.25eV per atom to about 10eV per atom. Alternatively, GCIB can be established with energy per atom ratios varying from about 1eV per atom to about 10eV per atom.
In addition, the second pattern may be removed using a plasma ribbon beam (plasma ribbon beam).
In the invention, the Gas Cluster Ion Beam (GCIB) etching method or the ribbon plasma beam etching method has larger etching selection ratio to the first pattern and the second pattern, and can also improve the performance of low frequency Line Width Roughness (LWR) and Line Edge Roughness (LER) of the pattern.
Optionally, a step of removing the positive photoresist layer 204 is further included simultaneously with or after the second pattern 205 is removed.
After removing the second pattern, line patterns spaced apart from each other by gaps are obtained, as shown in fig. 2C.
And step four, carrying out post-hardening treatment on the first pattern.
Specifically, as shown in fig. 2D, the first pattern 207 is subjected to a post-hardening process to further increase the hardness of the first pattern.
Optionally, the post-hardening treatment is performed on the first pattern using HBR-based plasma to form a dense layer 207 on the surface of the first pattern.
After the post-hardening treatment of the first pattern, the method further includes a step of transferring the line pattern of the first pattern into the substrate. The transfer method may be a conventional etching method, and will not be described herein.
Thus, the description of the steps related to the fabrication of the semiconductor device of the embodiment of the present invention is completed. After the above steps, other related steps may also be included, which are not described herein again. Besides the above steps, the preparation method of this embodiment may further include other steps among the above steps or between different steps, and these steps may be implemented by various processes in the prior art, and are not described herein again.
According to the invention, after a plurality of first patterns and second patterns which are mutually spaced and prepared by a directional self-assembly method, the first patterns are subjected to hardening treatment to improve the hardness of the first patterns so as to ensure that the first patterns are not deformed or inclined in subsequent pattern transfer, and then the second patterns are removed so as to form gaps between the first patterns, thereby forming the mutually spaced first patterns.
Example two
Firstly, a first step is executed, a substrate is provided, and a plurality of first patterns and second patterns which are alternately arranged are formed on the substrate through a directional self-assembly method.
Specifically, as shown in fig. 3A, the substrate at least includes a semiconductor substrate 301, and the semiconductor substrate 301 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and the like.
In this embodiment, the semiconductor substrate 301 is a silicon substrate, and various active or integrated devices may be further formed in the base, which is not described herein again.
In order to further improve the performance of the device, for example, the low frequency Line Width Roughness (LWR) and the Line Edge Roughness (LER) of the pattern, the Spin-coated carbon material 302 and Spin-on-Glass (SoG) 303 over the Spin-coated carbon material are further formed on the semiconductor substrate.
Dislocation of a pattern existing in the DSA can also be well solved by forming the spin-coated carbon material and SoG on the semiconductor substrate.
The Spin-on-Glass (SoG) 303 belongs to the Methyl Silsesquioxane (MSQ) family. The hydrogen silsesquioxane alkane (HSQ) film may also be used for spin coating. The Spin-on-Glass (SoG) is a low-K dielectric material with a dielectric constant of 2.7 to 3.1.
The method for preparing a plurality of first patterns 306 and second patterns 305 spaced from each other by the directional self-assembly method comprises the following steps:
first, an Anti-reflection Coating (Anti-reflection Coating)/Polystyrene (PS) Brush layer (Brush layer), a positive photoresist layer 304, and a patterned mask plate (not shown) are sequentially stacked on the substrate.
Specifically, the middle of the mask plate has a large opening to expose the photoresist 304, so that the positive photoresist is exposed by using the mask plate as a template.
And exposing the photoresist, removing the exposed photoresist area in a developing solution, and exposing the brush layer below the photoresist layer.
A polymer film comprising a block copolymer is coated over the exposed brush layer.
Specifically, the block copolymer in the polymer film (BCP) is a diblock copolymer. In the following examples, the diblock copolymer is poly (styrene-block-methyl methacrylate) (PS-b-PMMA) as an example.
However, it should be noted that the block copolymer is not limited to the above examples, and poly (styrene-b-vinylpyridine), poly (styrene-b-butadiene), poly (styrene-b-isoprene), poly (styrene-b-methyl methacrylate), poly (styrene-b-alkenyl aromatic), poly (isoprene-b-ethylene oxide), poly (styrene-b- (ethylene-propylene)), poly (ethylene oxide-b-caprolactone), poly (butadiene-b-ethylene oxide), poly (styrene-b- (t-butyl) acrylate), poly (methyl methacrylate-b-t-butyl methacrylate), poly (ethylene oxide-b-propylene oxide), poly (styrene-b-vinyl acetate), poly (styrene-b-propylene oxide), poly (styrene-b-vinyl acetate), poly (styrene-, Poly (styrene-b-tetrahydrofuran) and poly (styrene-block-methyl methacrylate) (PS-b-PMMA).
The block copolymers in the polymer film undergo directed self-assembly to form domains of different composition, such as a first pattern 306 and a second pattern 305.
Wherein the first pattern 306 is a first domain (domain) or a first micro domain (domain) formed after the copolymer block is separated, and the second pattern 305 is a second domain (domain) or a second micro domain formed after the copolymer block is separated.
Specifically, an annealing step is performed to anneal the BCP coating. For example, annealing may be performed using solvent annealing at room temperature (about 21 ℃). Alternatively, the temperature may be between about 25 c and about 300 c,
the annealing is performed for an annealing duration of between about 0.5 minutes and about 2 hours. As a result of the annealing step, phase separation occurs in the BCP layer, and the PS and PMMA are separated into parallel lengthwise multiple stripes.
In the embodiment shown, PS is labeled as the second pattern 305 and PMMA is labeled as the first pattern 306. The first patterns 306 and the second patterns 305 are positioned in an alternating layout, with each first pattern 306 being located between two second patterns 305 and immediately adjacent to two second patterns 305, or vice versa, as shown in fig. 3A.
The alternating arrangement refers to an arrangement manner in which the first patterns 206 and the second patterns 205 are alternately arranged, as shown in fig. 3A.
And step two, removing part of the second pattern to expose the top of the first pattern and carrying out hardening treatment on the exposed first pattern.
In order to solve the problem that the first pattern may be deformed or changed in profile in the process of forming the linear pattern by removing the second pattern by etching, the low frequency Line Width Roughness (LWR) and the Line Edge Roughness (LER) of the pattern are improved, and the first pattern is hardened before removing the second pattern, so that the hardness of the first pattern is improved.
Specifically, as shown in fig. 3B, in this embodiment, in order to better harden the first pattern, first, a portion of the second pattern is etched away to expose a top layer portion and a side surface of the first pattern, and then, the exposed portion is hardened, and the sidewall may be hardened compared to the first embodiment, so that the hardening effect of the first pattern is better.
Specifically, in the present invention, a Sequential Infiltration Synthesis (SIS) method is selected to harden the first pattern, by which a film composed of block copolymer macromolecules is used as a template to manufacture materials having various shapes and patterns.
Continuous Infiltration Synthesis (SIS) can produce materials that cannot be produced by ALD techniques alone or block copolymers, and can also better control the geometry and chemical composition of the produced materials. Using this block copolymer as the original substrate, materials with different shapes (from spherical to cylindrical to curved) can be formed by SIS techniques.
In the invention, the first pattern is subjected to continuous infiltration synthesis by using a material containing aluminum to form the first pattern containing aluminum.
More specifically, trimethyl aluminum is selected for continuous infiltration synthesis of the first pattern to form a first pattern 306 containing aluminum, as shown in fig. 3B.
In this process trimethyl aluminium is oxidized by the action of water and penetrates into the first pattern 306 under the atmosphere of pure nitrogen, and by means of continuously circulating penetration a layer of material comprising aluminium is formed in the first pattern, the hardness of which is greatly increased and which becomes more dense.
And then repeating the steps of removing the top layer of the second pattern and hardening the exposed first pattern until the second pattern is removed and the first pattern is completely hardened, for example, removing one fifth of the height of the second pattern each time, then hardening the exposed first pattern each time, removing one fifth of the second pattern again for the second time to expose two fifths of the first pattern, and then hardening the exposed part, wherein in the hardening step, the first pattern which is hardened before is repeatedly hardened, so that the hardening effect is better. This is repeated until all of the second pattern is removed and all of the first pattern is hardened, as shown in fig. 3C.
Step three is executed to remove the second pattern 305.
Specifically, as shown in fig. 3D, the second pattern 305 is removed using a Gas Cluster Ion Beam (GCIB) etching method or a ribbon plasma etching method in this step.
Wherein the GCIB system may include a GCIB generating system and a molecular beam generating system, which may be used in combination to process a substrate within a vacuum chamber. The GCIB and molecular beam may interact with each other or directly with the substrate within the vacuum chamber. For example, the interaction may occur at an offset distance from or at the exposed surface of the substrate. The angle of incidence between the GCIB and the molecular beam may vary from 0 to 90 degrees. In particular embodiments, the angle of incidence may vary from 5 degrees to 45 degrees. In these embodiments, the GCIB may have an angle of incidence with respect to the substrate from 0 degrees to 90 degrees. The GCIB may include a high pressure nozzle, a nozzle diverter positioned distal to an outlet of the high pressure nozzle, an ionizer positioned distal to an outlet of the nozzle diverter, and one or more accelerating electrodes.
The Gas Cluster Ion Beam (GCIB) is formed from a pressurized gas mixture containing at least one etching gas. The at least one etching gas may include a halogen element. The at least one etching gas may include a halogen element and one or more elements selected from C, H, N and S.
The second pattern may also be etched with a selection of beam energy, beam energy distribution, beam angular distribution, beam divergence angle, stagnation pressure, stagnation temperature, mass flow rate (mass flow rate), cluster size distribution, beam size, beam composition, beam electrode potential, or gas nozzle design (e.g., nozzle throat diameter, nozzle length, and/or nozzle branch half angle).
Any one or more of the foregoing GCIB properties may be selected to achieve control of a target etch process index (e.g., those noted above). Further, any one or more of the foregoing GCIB properties can be modified to achieve control of a target etch process index (e.g., those noted above).
For example, the beam acceleration potential of the GCIB can vary from about 1kV to about 70kV (i.e., the beam energy can vary from about 1keV to about 70keV, assuming uniform average cluster charge states)12Clustering to about 1 × 10 per square centimeter14The clusters change.
GCIB can be established with energy per atom ratios varying from about 0.25eV per atom to about 100eV per atom. Alternatively, GCIB can be established with energy per atom ratios varying from about 0.25eV per atom to about 10eV per atom. Alternatively, GCIB can be established with energy per atom ratios varying from about 1eV per atom to about 10eV per atom.
In addition, the second pattern may be removed using a plasma ribbon beam (plasma ribbon beam).
In the invention, the Gas Cluster Ion Beam (GCIB) etching method or the ribbon plasma beam etching method has larger etching selection ratio to the first pattern and the second pattern, and can also improve the performance of low frequency Line Width Roughness (LWR) and Line Edge Roughness (LER) of the pattern.
After removing the second pattern, line patterns spaced apart from each other by gaps are obtained, as shown in fig. 3D.
And step four, carrying out post-hardening treatment on the first pattern.
Specifically, the first pattern is subjected to post-hardening treatment to further increase the hardness of the first pattern.
Optionally, the post-hardening treatment is performed on the first pattern using HBR-based plasma to form a dense layer on a surface of the first pattern.
After the post-hardening treatment of the first pattern, the method further includes a step of transferring the line pattern of the first pattern into the substrate. The transfer method may be a conventional etching method, and will not be described herein.
Thus, the description of the steps related to the fabrication of the semiconductor device of the embodiment of the present invention is completed. After the above steps, other related steps may also be included, which are not described herein again. Besides the above steps, the preparation method of this embodiment may further include other steps among the above steps or between different steps, and these steps may be implemented by various processes in the prior art, and are not described herein again.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. A method of fabricating a semiconductor device, the method comprising:
providing a substrate;
forming a plurality of first patterns and second patterns which are alternately arranged on the substrate by a directional self-assembly method;
hardening the first pattern to increase the hardness of the first pattern;
removing the second pattern;
the hardening process of the first pattern and the removing of the second pattern include:
removing the top layer of the second pattern to expose the top layer part of the first pattern;
hardening the exposed first pattern;
and repeating the steps of removing the top layer of the second pattern and hardening the exposed first pattern until the second pattern is removed and the first pattern is completely hardened.
2. The method of claim 1, wherein the first pattern is hardened using a continuous infiltration synthesis process.
3. The method of claim 2, wherein the hardening process is performed on the first pattern using a material containing aluminum in the continuous infiltration synthesis method to form the first pattern containing aluminum.
4. The method of claim 3, wherein the aluminum-containing material comprises trimethylaluminum.
5. The method of claim 1, wherein the substrate comprises a semiconductor substrate, a spin-coated carbon material, and a spin-coated glass stacked in sequence.
6. The method of claim 1, further comprising post-hardening the first pattern after removing the second pattern and the hardening.
7. The method of claim 6, wherein the post-hardening treatment is performed on the first pattern using an HBr-based plasma.
8. The method of claim 1, wherein the second pattern is removed using a gas cluster ion beam etching method or a ribbon plasma beam etching method.
9. The method of claim 1, wherein the directed self-assembly method comprises:
coating a polymer film comprising a block copolymer over the substrate;
and performing directed self-assembly on the block copolymer in the polymer film to form first domains and second domains which are alternately arranged as the first pattern and the second pattern respectively.
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| CN103681249A (en) * | 2012-09-05 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method for fine pattern on semiconductor device |
| CN104364713A (en) * | 2012-05-15 | 2015-02-18 | 东京毅力科创株式会社 | Forming patterns using block copolymers and articles |
| US9416447B2 (en) * | 2014-02-07 | 2016-08-16 | HGST Netherlands B.V. | Method for line density multiplication using block copolymers and sequential infiltration synthesis |
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| CN104364713A (en) * | 2012-05-15 | 2015-02-18 | 东京毅力科创株式会社 | Forming patterns using block copolymers and articles |
| CN103681249A (en) * | 2012-09-05 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method for fine pattern on semiconductor device |
| US9416447B2 (en) * | 2014-02-07 | 2016-08-16 | HGST Netherlands B.V. | Method for line density multiplication using block copolymers and sequential infiltration synthesis |
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