CN108346573A - A kind of preparation method of semiconductor devices - Google Patents
A kind of preparation method of semiconductor devices Download PDFInfo
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- CN108346573A CN108346573A CN201710058601.1A CN201710058601A CN108346573A CN 108346573 A CN108346573 A CN 108346573A CN 201710058601 A CN201710058601 A CN 201710058601A CN 108346573 A CN108346573 A CN 108346573A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
Abstract
The present invention relates to a kind of preparation methods of semiconductor devices.The method includes：Substrate is provided；By orienting self-assembling method, several first pattern and the second patterns being arranged alternately are formed over the substrate；Cure process is carried out to first pattern；Remove second pattern.The method makes the low frequency line width roughness of device and the line edge roughness performance of pattern improve, and further improves the performance and yield of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of preparation method of semiconductor devices.
Background technology
As dimensions of semiconductor devices constantly reduces, it has been difficult using traditional lithography technique (Lithography)
Obtain finer pitch pattern.
As make smaller szie design problems solution, orientation self assembly (Directed self-assembly,
DSA) technology has caused the concern of people.DSA technologies are by block copolymer (Block Copolymer, BCP) or polymerization
Object mixture is deposited on substrate, and via special process, with " commander ", it forms orderly structure.DSA can form fine pith figure
Case.
Under proper condition, such copolymer block is separated into micro- domain (also referred to as " domain ", (domain)), and in this process
In, form the nanoscale features of different Chemical composition thats.The ability that block copolymer forms this category feature makes them that can be used in
During nano-pattern is formed, to form the feature with smaller critical size (Critical Dimension, CD), enabling structure
Build the feature being difficult to realize using conventional lithographic.
The DSA techniques are due to lower production cost and smaller low frequency line width roughness (line width
Roughness, LWR), become a kind of preferred method for obtaining finer pitch pattern, due to the block in DSA techniques
The hardness of copolymer is smaller, therefore meeting run-off the straight or deformation during patterned, keeps the low frequency wire of device broad and rough rough
The line edge roughness (line edge roughness, LER) for spending (line width roughness, LWR) and pattern becomes
Difference brings adverse effect.
Therefore it needs to be improved further the method, to eliminate the above problem, further increases the good of device
Rate and performance.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are the present invention provides a kind of preparation method of semiconductor devices, the methods
Including：
Substrate is provided；
By orienting self-assembling method, several first pattern and the second patterns being arranged alternately are formed over the substrate；
Cure process is carried out to first pattern；
Remove second pattern.
Optionally, cure process is carried out to first pattern using continuous infiltration synthetic method.
Optionally, in the continuous infiltration synthetic method, first pattern is carried out using the material containing aluminium described hard
Change is handled, to form first pattern containing aluminium.
Optionally, the material containing aluminium includes trimethyl aluminium.
Optionally, cure process is carried out to first pattern and includes the step of removing second pattern：
The top layer for first removing second pattern, to expose the top layer portion of first pattern；
Cure process is carried out to first pattern of exposing；
The top layer of above-mentioned removal second pattern is repeated, and first pattern of exposing is carried out at hardening
The step of reason, until second pattern is removed, the first pattern through-hardening.
Optionally, the substrate includes the semiconductor substrate stacked gradually, the carbon material of spin coating and spin cloth of coating-type glass
Glass.
Optionally, the method is still further comprised to institute after removing second pattern and the cure process
It states the first pattern and carries out after-hardening processing.
Optionally, the after-hardening processing is carried out to first pattern using HBr bases plasma.
Optionally, using gas cluster ion beam engraving method or band-like beam-plasma engraving method removal described second
Pattern.
Optionally, the orientation self-assembling method includes：
Coating includes the thin polymer film of block copolymer on the substrate；
Block copolymer in thin polymer film is oriented self assembly, to form the first domain and second being arranged alternately
Domain, respectively as first pattern and second pattern.
After several spaced first pattern and the second patterns in the present invention by orienting self-assembling method preparation,
Cure process is carried out to first pattern therein, to improve the hardness of first pattern, to ensure first pattern
It will not deform or tilt in the transfer of subsequent pattern, second pattern be removed, to be formed between the first pattern
Gap, to form the first spaced pattern, first pattern is due to greater hardness, making the low frequency wire of device
Broad and rough rugosity (line width roughness, LWR) and pattern line edge roughness (line edge roughness,
LER) performance improves, and further improves the performance and yield of semiconductor devices.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows the preparation technology flow chart of semiconductor devices of the present invention；
Fig. 2A -2D show that the preparation method of semiconductor devices described in one embodiment of the invention implements cuing open for obtained structure
Face schematic diagram；
Fig. 3 A-3D show that the preparation method of semiconductor devices described in another embodiment of the present invention implements obtained structure
Diagrammatic cross-section；
Fig. 4 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further include using and
The different orientation of device in operation.For example, if the device in attached drawing is overturn, then, it is described as " below other elements "
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair
It is bright to have other embodiment.
Embodiment one
Below with reference to the accompanying drawings the preparation method of the semiconductor devices of the present invention is described in detail, Fig. 1 shows the present invention
The preparation technology flow chart of the semiconductor devices；Fig. 2A -2D show the system of semiconductor devices described in one embodiment of the invention
Preparation Method implements the diagrammatic cross-section of obtained structure.
The present invention provides a kind of preparation method of semiconductor devices, as shown in Figure 1, the key step packet of the preparation method
It includes：
Step S1：Substrate is provided；
Step S2：By orienting self-assembling method, several the first patterns being arranged alternately and the are formed over the substrate
Two patterns；
Step S3：Cure process is carried out to first pattern；
Step S4：Remove second pattern.
In the following, being described in detail to the specific implementation mode of the preparation method of the semiconductor devices of the present invention.
First, step 1 is executed, substrate is provided, by orienting self-assembling method, forms several alternatings over the substrate
The first pattern and the second pattern of arrangement.
Specifically, as shown in Figure 2 A, the substrate includes at least semiconductor substrate 201, and the semiconductor substrate 201 can be with
Select following at least one of the material being previously mentioned：Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI), insulation on insulator
SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. are laminated on body.
The semiconductor substrate 201 selects silicon substrate in this embodiment, can also be further formed in the substrate each
The active or integrated device of kind, details are not described herein.
In order to further increase the performance of the device, such as further increase low frequency line width roughness (line width
Roughness, LWR) and pattern line edge roughness (line edge roughness, LER) performance, partly led described
The carbon material 202 of the spin coating and the spin cloth of coating-type glass above the carbon material of the spin coating are also formed in body substrate
Glass (Spin-on-Glass, SoG) 203.
It can also be solved in DSA well by the carbon material and SoG that form the spin coating on the semiconductor substrate
The dislocation of existing pattern.
The spin cloth of coating-type glass (Spin-on-Glass, SoG) 203 belongs to methyl sesquichloride alkane film
(Methyl silsesquioxane, MSQ) race.Hydrogen silicon half as much again oxide alkane (HSQ) film can also be used for spin coating.Institute
State spin cloth of coating-type glass (Spin-on-Glass, SoG) and belong to low-K dielectric material, dielectric constant between 2.7 to 3.1 it
Between.
Wherein, several spaced the first patterns 206 and the second pattern 205 prepared by orientation self-assembling method
Method includes：
Formed over the substrate first the ARC (Anti-reflection Coating, anti-reflecting layer) that stacks gradually/
PS (polystyrene, polystyrene) brush layer (Brush layer), positive photoresist layer 204, and it is located at the positivity light
Patterned mask plate (not shown) above photoresist layer.
Specifically, there is larger opening among the mask plate, exposes the photoresist 204, for mask plate
Positive photoresist is exposed for template.
Photoresist is exposed, the photoresist region of exposure is removed in developer solution, and exposure is located under photoresist layer
The brush layer of side.
Coating includes the thin polymer film of block copolymer above exposed brush layer.
Specifically, block copolymer described in the thin polymer film (BCP) is diblock copolymer.The following examples
In by diblock copolymer be poly- (styrene-b-methyl methacrylate) (PS-b-PMMA) for illustrate.
It should be understood that the block copolymer is not limited to the example, poly- (styrene-can also be selected
B- vinylpyridines), poly- (styrene-b-butadiene), poly- (styrene-block-isoprene), poly- (styrene-b- methyl propylenes
Sour methyl esters), poly- (styrene-b- alkenyl aromatic compounds), poly- (isoprene-b- ethylene oxide), poly- (styrene-b- (second
Alkene-propylene)), poly- (ethylene oxide-b- caprolactones), poly- (butadiene-b- ethylene oxide), poly- (styrene-b- (methyl) propylene
Tert-butyl acrylate), poly- (methyl methacrylate-b- methacrylates tert-butyl ester), poly- (ethylene oxide-b- propylene oxide), poly- (benzene
Ethylene-b- tetrahydrofurans) and poly- (styrene-b-methyl methacrylate) (PS-b-PMMA) combination.
Block copolymer in thin polymer film is oriented self assembly, forms the domain that different groups is grouped as, such as
One pattern 206 and the second pattern 205.
Wherein, first pattern 206 is the first domain (domain) or first micro- domain formed after copolymer block detaches
(domain), second pattern 205 is the second domain (domain) or second micro- domain formed after copolymer block detaches
(domain)。
Specifically, annealing steps are carried out to anneal to BCP coatings.For example, under room temperature (about 21 DEG C), can make
Implement to anneal with solvent anneal.It is alternatively possible between such as about 25 DEG C and about 300 DEG C,
Implement the anneal duration between annealing about 0.5 minute and about 2 hours.As annealing steps as a result,
PHASE SEPARATION occurs in BCP layers, and PS is divided into the multi-ribbon of parallel length direction with PMMA.
In an illustrated embodiment, PS is marked as the second pattern 205, and PMMA is marked as the first pattern 206.With
It is arranged alternately the first pattern 206 of positioning and the second pattern 205, every first pattern 206 is located between two second patterns 205 simultaneously
And close to two second patterns 205, vice versa, as shown in Figure 2 A.
Wherein, described be arranged alternately refers to arrangement side that first pattern, 206 and second pattern 205 alternates setting
Formula, as shown in Figure 2 A.
Step 2 is executed, cure process is carried out to first pattern.
Wherein, the hardness of the thin polymer film (BCP) is smaller, and etching removes second pattern and forms linearity pattern
In the process, first pattern may deform upon or it is broad and rough to improve low frequency wire in order to solve this problem for the variation of profile
The line edge roughness (line edge roughness, LER) of rugosity (line width roughness, LWR) and pattern
Performance carries out cure process, to improve the hard of first pattern before removing second pattern to first pattern
Degree.
Specifically, continuous infiltration synthetic method (Sequential Infiltration are selected in the present invention
Synthesis, SIS) cure process is carried out to first pattern, by this method with one piece by block copolymer macromolecular group
At film as template, produce with variously-shaped and pattern material.
Continuous infiltration synthetic method (Sequential Infiltration Synthesis, SIS) can produce only by
The material that ALD technique or block copolymer can not produce also can preferably control the geometry and chemistry of manufactured material
Ingredient.Using this block copolymer as initial substrates, by SIS technologies, can be formed with material of different shapes (from
Spherical shape arrives curved again to cylinder).
The material containing aluminium is selected to carry out continuous infiltration synthesis to first pattern in the present invention, to form the containing aluminium
One pattern.
More specifically, selecting trimethyl aluminium to carry out continuous infiltration synthesis to first pattern, to form first containing aluminium
Pattern 206, as shown in Figure 2 B.
In this process under the atmosphere of pure nitrogen gas, aluminium is aoxidized and permeated under the action of water by trimethyl aluminium
Into in first pattern 207, by the infiltration continuously recycled, the material comprising aluminium is formd in first pattern
Layer, hardness are greatly improved, and become finer and close.
Step 3 is executed, second pattern 205 is removed.
Specifically, as shown in Figure 2 C, in this step use gas cluster ion beam (gas cluster ion beam,
GCIB) engraving method or band-like beam-plasma engraving method remove second pattern 205.
Wherein, the GCIB systems may include that GCIB generates system and molecular beam and generates system, GCIB generate system and
Molecular beam generates system and can be used in combination to handle the indoor substrate of vacuum.
GCIB and molecular beam can be interacted with each other in vacuum chamber or directly be interacted with substrate.For example, phase
Interaction can occur with the exposing surface of substrate at offset distance or at the exposing surface of substrate.GCIB with point
Incidence angle between beamlet can degree variation from 0 degree to 90.In specific embodiment, incidence angle can be from 5 degree to 45 degree
Variation.In these embodiments, the incidence angle that GCIB can have relative to substrate from 0 degree to 90 degree.GCIB can be wrapped
High pressure nozzle is included, is positioned to be distal to the nozzle manifold of the outlet of the high pressure nozzle, is positioned to be distal to the nozzle manifold
Outlet electro-dissociator and one or more acceleration electrodes.
Gas cluster ion beam (GCIB) is formed by the pressurised gas mixture containing at least one etching gas.It is described extremely
A kind of few etching gas can include halogen.It is described at least one etching gas can include halogen and selected from C,
H, one or more of elements in N and S.
In addition it is also an option that it is beam energy, beam energy distribution, beam angle distribution, beam-divergence angle, stagnation pressure, stagnant
Only temperature, mass flowrate (mass flow rate), cluster size, cluster size distribution, beam size, beam ingredient, beam
Electrode potential or gas nozzle design (for example, nozzle throat diameter, nozzle length, and/or nozzle difference unit half-angle) are to described the
Two patterns are etched.
Can select any one of aforementioned GCIB properties or more with realize target etch processing index (for example,
It is above-indicated these) control.Furthermore, it is possible to change any one in aforementioned GCIB properties or more to realize target
The control of etching process index (for example, above-indicated these).
For example, the beam acceleration potential of GCIB can change from about 1kV to about 70kV (that is, beam energy can be from about 1keV
Change to about 70keV, it is assumed that average agglomerate state of charge is consistent).In addition, for example, the beam dosage of GCIB can be from every square
Centimetre about 1 × 1012Cluster is to every square centimeter about 1 × 1014Cluster changes.
GCIB, which can be created as energy, to be changed to about 100eV per atom per atomic ratio from about 0.25eV per atom.It is alternative
Ground, GCIB, which can be created as energy, to be changed to about 10eV per atom per atomic ratio from about 0.25eV per atom.Alternatively, GCIB
Energy can be created as per atomic ratio to change per atom to about 10eV from about 1eV per atom.
Further, it is also possible to remove second pattern using band shaped plasma beam (plasma ribbon beam).
Gas cluster ion beam (gas cluster ion beam, GCIB) engraving method or band-like etc. in the present invention
Ion beam etching method has larger etching selectivity to first pattern and second pattern, can also improve low frequency
Line width roughness (line width roughness, LWR) and pattern line edge roughness (line edge roughness,
LER performance).
Optionally, removal positive photoresist layer is still further comprised while removing the second pattern 205 or later
204 the step of.
It is obtained by the spaced linear pattern in gap, as shown in Figure 2 C after removing second pattern.
Step 4 is executed, after-hardening processing is carried out to first pattern.
Specifically, as shown in Figure 2 D, after-hardening processing is carried out to first pattern 207, to further increase described the
The hardness of one pattern.
Optionally, the after-hardening processing is carried out to first pattern using HBR bases plasma, with described first
The surface of pattern forms compacted zone 207.
After carrying out the after-hardening processing to first pattern, the method is still further comprised described first
The linear pattern of pattern is transferred to the step in the substrate.Specifically transfer method can select conventional engraving method,
This is repeated no more.
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Above-mentioned steps it
Afterwards, can also include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the preparation side of the present embodiment
Method can also include other steps among above-mentioned each step or between different steps, these steps can be by existing
Various techniques in technology realize that details are not described herein again.
After several spaced first pattern and the second patterns in the present invention by orienting self-assembling method preparation,
Cure process is carried out to first pattern therein, to improve the hardness of first pattern, to ensure first pattern
Subsequent pattern transfer in will not deform or tilt, then remove second pattern again, with the first pattern it
Between form gap, to form the first spaced pattern, first pattern is due to greater hardness, making device
Line edge roughness (the line edge of low frequency line width roughness (line width roughness, LWR) and pattern
Roughness, LER) performance improve, further improve the performance and yield of semiconductor devices.
Embodiment two
First, step 1 is executed, substrate is provided, by orienting self-assembling method, forms several alternatings over the substrate
The first pattern and the second pattern of arrangement.
Specifically, as shown in Figure 3A, the substrate includes at least semiconductor substrate 301, and the semiconductor substrate 301 can be with
Select following at least one of the material being previously mentioned：Silicon, silicon-on-insulator (SOI), stacking silicon (SSOI), insulation on insulator
SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. are laminated on body.
The semiconductor substrate 301 selects silicon substrate in this embodiment, can also be further formed in the substrate each
The active or integrated device of kind, details are not described herein.
In order to further increase the performance of the device, such as further increase low frequency line width roughness (line width
Roughness, LWR) and pattern line edge roughness (line edge roughness, LER) performance, partly led described
The carbon material 302 of the spin coating and the spin cloth of coating-type glass above the carbon material of the spin coating are also formed in body substrate
Glass (Spin-on-Glass, SoG) 303.
It can also be solved in DSA well by the carbon material and SoG that form the spin coating on the semiconductor substrate
The dislocation of existing pattern.
The spin cloth of coating-type glass (Spin-on-Glass, SoG) 303 belongs to methyl sesquichloride alkane film
(Methyl silsesquioxane, MSQ) race.Hydrogen silicon half as much again oxide alkane (HSQ) film can also be used for spin coating.Institute
State spin cloth of coating-type glass (Spin-on-Glass, SoG) and belong to low-K dielectric material, dielectric constant between 2.7 to 3.1 it
Between.
Wherein, several spaced the first patterns 306 and the second pattern 305 prepared by orientation self-assembling method
Method includes：
Formed over the substrate first the ARC (Anti-reflection Coating, anti-reflecting layer) that stacks gradually/
PS (polystyrene, polystyrene) brush layer (Brush layer), positive photoresist layer 304, and it is located at the positivity light
Patterned mask plate (not shown) above photoresist layer.
Specifically, there is larger opening among the mask plate, exposes the photoresist 304, for mask plate
Positive photoresist is exposed for template.
Photoresist is exposed, the photoresist region of exposure is removed in developer solution, and exposure is located under photoresist layer
The brush layer of side.
Coating includes the thin polymer film of block copolymer above exposed brush layer.
Specifically, block copolymer described in the thin polymer film (BCP) is diblock copolymer.The following examples
In by diblock copolymer be poly- (styrene-b-methyl methacrylate) (PS-b-PMMA) for illustrate.
It should be understood that the block copolymer is not limited to the example, poly- (styrene-can also be selected
B- vinylpyridines), poly- (styrene-b-butadiene), poly- (styrene-block-isoprene), poly- (styrene-b- methyl propylenes
Sour methyl esters), poly- (styrene-b- alkenyl aromatic compounds), poly- (isoprene-b- ethylene oxide), poly- (styrene-b- (second
Alkene-propylene)), poly- (ethylene oxide-b- caprolactones), poly- (butadiene-b- ethylene oxide), poly- (styrene-b- (methyl) propylene
Tert-butyl acrylate), poly- (methyl methacrylate-b- methacrylates tert-butyl ester), poly- (ethylene oxide-b- propylene oxide), poly- (benzene
Ethylene-b- tetrahydrofurans) and poly- (styrene-b-methyl methacrylate) (PS-b-PMMA) combination.
Block copolymer in thin polymer film is oriented self assembly, forms the domain that different groups is grouped as, such as
One pattern 306 and the second pattern 305.
Wherein, first pattern 306 is the first domain (domain) or first micro- domain formed after copolymer block detaches
(domain), second pattern 305 is the second domain (domain) or second micro- domain formed after copolymer block detaches
(domain)。
Specifically, annealing steps are carried out to anneal to BCP coatings.For example, under room temperature (about 21 DEG C), can make
Implement to anneal with solvent anneal.It is alternatively possible between such as about 25 DEG C and about 300 DEG C,
Implement the anneal duration between annealing about 0.5 minute and about 2 hours.As annealing steps as a result,
PHASE SEPARATION occurs in BCP layers, and PS is divided into the multi-ribbon of parallel length direction with PMMA.
In an illustrated embodiment, PS is marked as the second pattern 305, and PMMA is marked as the first pattern 306.With
Alternate layout positions the first pattern 306 and the second pattern 305, and every first pattern 306 is located between two second patterns 305 simultaneously
And close to two second patterns 305, vice versa, as shown in Figure 3A.
Wherein, described be arranged alternately refers to arrangement side that first pattern, 206 and second pattern 205 alternates setting
Formula, as shown in Figure 3A.
Step 2 is executed, part second pattern is removed, to expose the top of first pattern and to the institute of exposing
It states the first pattern and carries out cure process.
Wherein, the hardness of the thin polymer film (BCP) is smaller, and etching removes second pattern and forms linearity pattern
In the process, first pattern may deform upon or it is broad and rough to improve low frequency wire in order to solve this problem for the variation of profile
The line edge roughness (line edge roughness, LER) of rugosity (line width roughness, LWR) and pattern
Performance carries out cure process, to improve the hard of first pattern before removing second pattern to first pattern
Degree.
Specifically, as shown in Figure 3B, in this embodiment, in order to preferably be hardened to first pattern, first
Etching removal part second pattern, exposes top layer portion and the side of first pattern, then to the part of exposing into
Row hardening, can also harden the side wall relative to being improved described in embodiment one so that the hardening of first pattern
Effect is more preferable.
Specifically, continuous infiltration synthetic method (Sequential Infiltration are selected in the present invention
Synthesis, SIS) cure process is carried out to first pattern, by this method with one piece by block copolymer macromolecular group
At film as template, produce with variously-shaped and pattern material.
Continuous infiltration synthetic method (Sequential Infiltration Synthesis, SIS) can produce only by
The material that ALD technique or block copolymer can not produce also can preferably control the geometry and chemistry of manufactured material
Ingredient.Using this block copolymer as initial substrates, by SIS technologies, can be formed with material of different shapes (from
Spherical shape arrives curved again to cylinder).
The material containing aluminium is selected to carry out continuous infiltration synthesis to first pattern in the present invention, to form the containing aluminium
One pattern.
More specifically, selecting trimethyl aluminium to carry out continuous infiltration synthesis to first pattern, to form first containing aluminium
Pattern 306, as shown in Figure 3B.
In this process under the atmosphere of pure nitrogen gas, aluminium is aoxidized and permeated under the action of water by trimethyl aluminium
Into in first pattern 306, by the infiltration continuously recycled, the material comprising aluminium is formd in first pattern
Layer, hardness are greatly improved, and become finer and close.
Then the top layer of above-mentioned removal second pattern is repeated, and first pattern of exposing is carried out hard
The step of changing processing, until second pattern is removed, the first pattern through-hardening, such as removal 1/5th every time
Then second pattern of height hardens first pattern exposed every time, removes 1/5th again for the second time
Second pattern, so that 2/5ths first pattern is exposed, then the part of exposing hardened, at this
In cure step, what the first pattern for being hardened before repeated is hardened, therefore its hardening effect is more preferable.So repeat to
Second pattern all removes, the first pattern through-hardening, as shown in Figure 3 C.
Step 3 is executed, second pattern 305 is removed.
Specifically, as shown in Figure 3D, in this step use gas cluster ion beam (gas cluster ion beam,
GCIB) engraving method or band-like beam-plasma engraving method remove second pattern 305.
Wherein, the GCIB systems may include that GCIB generates system and molecular beam and generates system, GCIB generate system and
Molecular beam generates system and can be used in combination to handle the indoor substrate of vacuum.GCIB and molecular beam can be in vacuum chambers each other
Interaction directly interacts with substrate.For example, interaction can with the exposing surface of substrate at a distance of offset distance
Occur from place or at the exposing surface of substrate.Incidence angle between GCIB and molecular beam can degree variation from 0 degree to 90.
In specific embodiment, incidence angle can degree variation from 5 degree to 45.In these embodiments, GCIB can have opposite
In incidence angle of the substrate from 0 degree to 90 degree.GCIB may include high pressure nozzle, be positioned to be distal to the outlet of the high pressure nozzle
Nozzle manifold, be positioned to be distal to the electro-dissociator of the outlet of the nozzle manifold and one or more acceleration electrodes.
Gas cluster ion beam (GCIB) is formed by the pressurised gas mixture containing at least one etching gas.It is described extremely
A kind of few etching gas can include halogen.It is described at least one etching gas can include halogen and selected from C,
H, one or more of elements in N and S.
In addition it is also an option that it is beam energy, beam energy distribution, beam angle distribution, beam-divergence angle, stagnation pressure, stagnant
Only temperature, mass flowrate (mass flow rate), cluster size, cluster size distribution, beam size, beam ingredient, beam
Electrode potential or gas nozzle design (for example, nozzle throat diameter, nozzle length, and/or nozzle difference unit half-angle) are to described the
Two patterns are etched.
Can select any one of aforementioned GCIB properties or more with realize target etch processing index (for example,
It is above-indicated these) control.Furthermore, it is possible to change any one in aforementioned GCIB properties or more to realize target
The control of etching process index (for example, above-indicated these).
For example, the beam acceleration potential of GCIB can change from about 1kV to about 70kV (that is, beam energy can be from about 1keV
Change to about 70keV, it is assumed that average agglomerate state of charge is consistent).In addition, for example, the beam dosage of GCIB can be from every square
Centimetre about 1 × 1012Cluster is to every square centimeter about 1 × 1014Cluster changes.
GCIB, which can be created as energy, to be changed to about 100eV per atom per atomic ratio from about 0.25eV per atom.It is alternative
Ground, GCIB, which can be created as energy, to be changed to about 10eV per atom per atomic ratio from about 0.25eV per atom.Alternatively, GCIB
Energy can be created as per atomic ratio to change per atom to about 10eV from about 1eV per atom.
Further, it is also possible to remove second pattern using band shaped plasma beam (plasma ribbon beam).
Gas cluster ion beam (gas cluster ion beam, GCIB) engraving method or band-like etc. in the present invention
Ion beam etching method has larger etching selectivity to first pattern and second pattern, can also improve low frequency
Line width roughness (line width roughness, LWR) and pattern line edge roughness (line edge roughness,
LER performance).
It is obtained by the spaced linear pattern in gap, as shown in Figure 3D after removing second pattern.
Step 4 is executed, after-hardening processing is carried out to first pattern.
Specifically, after-hardening processing is carried out to first pattern, to further increase the hardness of first pattern.
Optionally, the after-hardening processing is carried out to first pattern using HBR bases plasma, with described first
The surface of pattern forms compacted zone.
After carrying out the after-hardening processing to first pattern, the method is still further comprised described first
The linear pattern of pattern is transferred to the step in the substrate.Specifically transfer method can select conventional engraving method,
This is repeated no more.
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Above-mentioned steps it
Afterwards, can also include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the preparation side of the present embodiment
Method can also include other steps among above-mentioned each step or between different steps, these steps can be by existing
Various techniques in technology realize that details are not described herein again.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of preparation method of semiconductor devices, which is characterized in that the method includes：
Substrate is provided；
By orienting self-assembling method, several first pattern and the second patterns being arranged alternately are formed over the substrate；
Cure process is carried out to first pattern；
Remove second pattern.
2. according to the method described in claim 1, it is characterized in that, using continuous infiltration synthetic method to first pattern into
Row cure process.
3. according to the method described in claim 2, it is characterized in that, in the continuous infiltration synthetic method, the material containing aluminium is used
Material carries out the cure process to first pattern, to form first pattern containing aluminium.
4. according to the method described in claim 3, it is characterized in that, the material containing aluminium includes trimethyl aluminium.
5. method according to claim 1 or 2, which is characterized in that carry out cure process and removal to first pattern
The step of second pattern includes：
The top layer for first removing second pattern, to expose the top layer portion of first pattern；
Cure process is carried out to first pattern of exposing；
The top layer of above-mentioned removal second pattern is repeated, and cure process is carried out to first pattern of exposing
Step, until second pattern is removed, the first pattern through-hardening.
6. according to the method described in claim 1, it is characterized in that, the substrate includes the semiconductor substrate stacked gradually, rotation
The carbon material and spin cloth of coating-type glass of painting.
7. according to the method described in claim 1, it is characterized in that, remove second pattern and the cure process it
The method is still further comprised afterwards carries out after-hardening processing to first pattern.
8. the method according to the description of claim 7 is characterized in that being carried out to first pattern using HBr bases plasma
The after-hardening processing.
9. according to the method described in claim 1, it is characterized in that, using gas cluster ion beam engraving method or band-like etc.
Ion beam etching method removes second pattern.
10. according to the method described in claim 1, it is characterized in that, the orientation self-assembling method includes：
Coating includes the thin polymer film of block copolymer on the substrate；
Block copolymer in thin polymer film is oriented self assembly, to form the first domain and the second domain that are arranged alternately,
Respectively as first pattern and second pattern.
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| JP2020149037A (en) * | 2019-03-11 | 2020-09-17 | キオクシア株式会社 | Pattern forming material, composition for pattern formation, pattern forming method and method for producing semiconductor device |
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| US20120046421A1 (en) * | 2010-08-17 | 2012-02-23 | Uchicago Argonne, Llc | Ordered Nanoscale Domains by Infiltration of Block Copolymers |
| CN103681249A (en) * | 2012-09-05 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method for fine pattern on semiconductor device |
| CN104364713A (en) * | 2012-05-15 | 2015-02-18 | 东京毅力科创株式会社 | Forming patterns using block copolymers and articles |
| US9416447B2 (en) * | 2014-02-07 | 2016-08-16 | HGST Netherlands B.V. | Method for line density multiplication using block copolymers and sequential infiltration synthesis |
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| US20120046421A1 (en) * | 2010-08-17 | 2012-02-23 | Uchicago Argonne, Llc | Ordered Nanoscale Domains by Infiltration of Block Copolymers |
| CN104364713A (en) * | 2012-05-15 | 2015-02-18 | 东京毅力科创株式会社 | Forming patterns using block copolymers and articles |
| CN103681249A (en) * | 2012-09-05 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method for fine pattern on semiconductor device |
| US9416447B2 (en) * | 2014-02-07 | 2016-08-16 | HGST Netherlands B.V. | Method for line density multiplication using block copolymers and sequential infiltration synthesis |
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