CN108344959B

CN108344959B - Adapter and coil recognition system of magnetic resonance imaging system

Info

Publication number: CN108344959B
Application number: CN201710062727.6A
Authority: CN
Inventors: 杜述; 李文明
Original assignee: Siemens Shenzhen Magnetic Resonance Ltd
Current assignee: Siemens Shenzhen Magnetic Resonance Ltd
Priority date: 2017-01-25
Filing date: 2017-01-25
Publication date: 2020-06-26
Anticipated expiration: 2037-01-25
Also published as: CN108344959A

Abstract

The embodiment of the invention discloses an adapter of a magnetic resonance imaging system and a coil identification system. The adapter includes: a plug that, when connected to a system socket, triggers a first type of interrupt signal for powering up the adapter; the system comprises a plurality of sockets, a plurality of control units and a plurality of control units, wherein the sockets are respectively and correspondingly connected with a plurality of coils, and when the sockets are connected with at least one coil in the coils, a second type interrupt signal used for sending identification information of the at least one coil is triggered; an interrupt retainer, connected to each of the plurality of receptacles, for retaining the second type of interrupt signal in an enabled state. In the embodiment of the invention, the coil can be identified without specifying a socket. Also, the identification information of the adapter can be read.

Description

Adapter and coil recognition system of magnetic resonance imaging system

Technical Field

The invention relates to the technical field of magnetic resonance imaging, in particular to an adapter of a magnetic resonance imaging system and a coil identification system.

Background

Magnetic Resonance (MR) imaging is a kind of biomagnetic nuclear spin imaging technology that has been rapidly developed with the development of computer technology, electronic circuit technology, and superconductor technology. The hydrogen nuclei (H +) precessing in human tissue are vibrated by magnetic field and RF pulse to generate RF signal, which is processed by computer to form image. When an object is placed in a magnetic field, it is irradiated with an appropriate electromagnetic wave to resonate it, and then the electromagnetic wave released from it is analyzed, the position and kind of nuclei constituting the object can be known, and an accurate stereoscopic image of the inside of the object can be drawn therefrom.

In a magnetic resonance imaging system, when a radio frequency receiving coil is connected to the system, the radio frequency receiving coil needs to be identified by the system to work. Typically, the system socket allows access to only one coil. When the number of system sockets is limited, a plurality of coils may be commonly connected to one system socket through an adapter.

In the prior art, the coil inserted into the adapter for the first time needs to be connected into a specific adapter socket, otherwise, the coil inserted into the adapter for the subsequent time cannot be normally identified, which brings inconvenience to users.

Disclosure of Invention

The embodiment of the invention provides an adapter of a magnetic resonance imaging system and a coil identification system.

The technical scheme of the embodiment of the invention is as follows:

an adapter for a magnetic resonance imaging system, comprising:

a plug that, when connected to a system socket, triggers a first type of interrupt signal for powering up the adapter;

the system comprises a plurality of sockets, a plurality of control units and a plurality of control units, wherein the sockets are respectively and correspondingly connected with a plurality of coils, and when the sockets are connected with at least one coil in the coils, a second type interrupt signal used for sending identification information of the at least one coil is triggered;

an interrupt retainer, coupled to each of the plurality of receptacles, for retaining the second type of interrupt signal in an enabled state.

In one embodiment, further comprising:

a register for storing an identification information of the adapter;

wherein the plug is further configured to read the identification information of the adapter from the register via a data transfer bus.

In one embodiment, the plurality of receptacles includes a first receptacle and a second receptacle;

the interrupt holder includes a first NPN transistor, a second NPN transistor, and an interrupt enable line;

a base of the first NPN transistor is connected to a power line through a first bias resistor, the base of the first NPN transistor is further connected to an emitter of the second NPN transistor, and an emitter of the first NPN transistor is connected to the first socket; a base electrode of the second NPN transistor is connected with the power line through a second bias resistor, and the base electrode of the second NPN transistor is also connected with an emitter electrode of the first NPN transistor; the emitter of the second NPN transistor is connected with the second socket; a collector of the first NPN transistor is connected to a collector of the second NPN transistor; the collector of the first NPN transistor and the collector of the second NPN transistor are connected with the power line through a third bias resistor; the interrupt enable line is connected to a collector of the first NPN transistor and a collector of the second NPN transistor.

the interrupt holder includes a first PNP type transistor, a second PNP type transistor, and an interrupt enable line;

wherein a base of the first PNP transistor is connected to the first socket, an emitter of the first PNP transistor is connected to a power line through a first bias resistor, and an emitter of the first PNP transistor is further connected to a base of the second PNP transistor; the base electrode of the second PNP type transistor is connected with the second socket, an emitter electrode of the second PNP type transistor is connected with the power line through a second bias resistor, and the emitter electrode of the second PNP type transistor is also connected with the base electrode of the first PNP type transistor; a collector of the first PNP transistor is connected to a collector of the second PNP transistor; the collector electrode of the first PNP transistor and the collector electrode of the second PNP transistor are connected with the power line through a third bias resistor; the interrupt enable line is connected to the collector of the first PNP transistor and the collector of the second PNP transistor.

the interrupt retainer comprises a first MOS type transistor, a second MOS type transistor and an interrupt enable line;

a source of the first MOS transistor is connected to the first socket, a gate of the first MOS transistor is connected to a power line through a first bias resistor, and the gate of the first MOS transistor is further connected to a source of the second MOS transistor; the source electrode of the second MOS type transistor is connected with the second socket, a grid electrode of the second MOS type transistor is connected with the power line through a second bias resistor, and the grid electrode of the second MOS type transistor is also connected with the source electrode of the first MOS type transistor; a drain electrode of the first MOS type transistor is connected with a drain electrode of the second MOS type transistor; the drain electrode of the first MOS type transistor and the drain electrode of the second MOS type transistor are connected with the power line through a third bias resistor; the interrupt enable line is connected to the drain of the first MOS type transistor and the drain of the second MOS type transistor.

In one embodiment, the data transmission bus is an inter-integrated circuit bus or a serial peripheral interface bus.

A coil identification system for a magnetic resonance imaging system, comprising:

an adapter, comprising:

an interrupt retainer, connected to each of said plurality of receptacles, for retaining said second type of interrupt signal in an enabled state;

the system socket is used for powering on the adapter and acquiring the identification information of the at least one coil.

In one embodiment, the adapter further comprises a register for storing an identification information of the adapter;

the interrupt retainer comprises a first NPN transistor, a second NPN transistor and an interrupt enable line; a base of the first NPN transistor is connected to a power line through a first bias resistor, the base of the first NPN transistor is further connected to an emitter of the second NPN transistor, and an emitter of the first NPN transistor is connected to the first socket; a base electrode of the second NPN transistor is connected with the power line through a second bias resistor, and the base electrode of the second NPN transistor is also connected with an emitter electrode of the first NPN transistor; the emitter of the second NPN transistor is connected with the second socket; a collector of the first NPN transistor is connected to a collector of the second NPN transistor; the collector of the first NPN transistor and the collector of the second NPN transistor are connected with the power line through a third bias resistor; the interruption enabling line is connected with a collector of the first NPN transistor and a collector of the second NPN transistor; or

The interrupt retainer comprises a first PNP type transistor, a second PNP type transistor and an interrupt enable line; wherein a base of the first PNP transistor is connected to the first socket, an emitter of the first PNP transistor is connected to a power line through a first bias resistor, and an emitter of the first PNP transistor is further connected to a base of the second PNP transistor; the base electrode of the second PNP type transistor is connected with the second socket, an emitter electrode of the second PNP type transistor is connected with the power line through a second bias resistor, and the emitter electrode of the second PNP type transistor is also connected with the base electrode of the first PNP type transistor; a collector of the first PNP transistor is connected to a collector of the second PNP transistor; the collector electrode of the first PNP transistor and the collector electrode of the second PNP transistor are connected with the power line through a third bias resistor; the interrupt enable line is connected to the collector of the first PNP transistor and the collector of the second PNP transistor.

As can be seen from the above technical solutions, in the embodiment of the present invention, the adaptor includes a plug, a plurality of sockets, and an interruption holder. The interrupt retainer may maintain the second class of interrupt signals in an enabled state after the adapter has been powered on, so that each socket may transmit identification information of each respective access coil using the second class of interrupt regardless of the order in which each respective access adapter is sequenced. Therefore, the coil can be identified without a specified socket in the embodiment of the invention, thereby being convenient for users to use.

In addition, the embodiment of the invention can further read the identification information of the adapter after the adapter is powered on.

Drawings

Fig. 1 is a schematic diagram of an operation structure of two coils connected to a system socket through an adapter in the prior art.

FIG. 2 is a functional block diagram of an adapter according to an embodiment of the present invention.

Fig. 3 is a first exemplary block diagram of an adapter according to an embodiment of the present invention.

Fig. 4 is a second exemplary block diagram of an adapter according to an embodiment of the present invention.

Fig. 5 is a third exemplary block diagram of an adapter according to an embodiment of the present invention.

Fig. 6 is a fourth exemplary block diagram of an adapter according to an embodiment of the present invention.

Fig. 7 is a fifth exemplary block diagram of an adapter according to an embodiment of the present invention.

Fig. 8 is an exemplary block diagram of an application of multiple coils to the same system jack, according to an embodiment of the present invention.

Detailed Description

In order to make the technical scheme and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the detailed description and specific examples, while indicating the scope of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

For simplicity and clarity of description, the invention will be described below by describing several representative embodiments. Numerous details of the embodiments are set forth to provide an understanding of the principles of the invention. It will be apparent, however, that the invention may be practiced without these specific details. Some embodiments are not described in detail, but rather are merely provided as frameworks, in order to avoid unnecessarily obscuring aspects of the invention. Hereinafter, "including" means "including but not limited to", "according to … …" means "at least according to … …, but not limited to … … only". In view of the language convention of chinese, the following description, when it does not specifically state the number of a component, means that the component may be one or more, or may be understood as at least one.

Typically, each System Socket (System Socket) of the magnetic resonance System is configured with a set of data transfer buses (e.g., I2C buses). The data transfer bus allows access to a plurality of registers, each of which may be distinguished by an address. Thus, from a data transfer bus perspective, one system socket can access multiple coils. When multiple coils are connected to a system socket via an adapter, communication between the coils and the system socket is typically triggered by an interrupt. Typically, two types of interrupts are included, referred to as a first type of interrupt and a second type of interrupt. The first type of interrupt is used primarily to power up the coil and adapter through the system socket; the second category is primarily for the coil to send identification information stored in the coil to the system socket.

In the prior art, when a first coil is connected to an adapter, the magnetic resonance system needs to power up the first coil and the adapter and read the identification information of the first coil, which belongs to the first type of interrupt. Specifically, the method comprises the following steps: when the first coil is connected into the adapter, the level of the enabling end of the voltage stabilizing module which is responsible for supplying power to the coil is pulled up from the default low level to the high level, and the output end of the voltage stabilizing module generates output voltage so as to supply power to the coil. Furthermore, when the magnetic resonance system detects an enable level jump, the identification information of the first coil is read using the communication bus. When the second coil is connected to the adapter, if the first type of interruption is triggered continuously, the level of the enabling end of the voltage stabilizing module needs to be reduced from a high level to a low level, so that the output end of the voltage stabilizing module does not generate output voltage any more, and the coil information can not be read by using the communication bus. Thus, when the second coil is connected to the adapter, the first type of interrupt can no longer be triggered, but rather the second type of interrupt needs to be triggered in order to continue reading the identification information stored in the second coil. When the second coil is connected with the adapter, the signal wire of the second type interruption is pulled down from the default high level to the low level, and the magnetic resonance system reads the identification information of the second coil by using the communication bus after detecting the level jump of the signal wire of the second type interruption.

As shown in fig. 1, the adapter 1 has one end connected to the system socket 2 and the other end including a first socket 4 and a second socket 5. The first socket 4 contains a first type interrupt (/ int1) line and no second type interrupt (/ int2) line, and the second socket contains a first type interrupt (/ int1) line and a second type interrupt (/ int 2).

In order to use the adapter 1 correctly, the coil that is first coupled into the adapter 1 needs to be plugged into the first socket 4, but not into the second socket 5. For example, after the first coil 6 is inserted into the first socket 4 of the adapter 1, the first type of interrupt triggers, the control system 3 (e.g., a hospital bed) powers on the adapter 1 and the first coil 6 through the system socket 2, and the adapter 1 reads the identification information in the first coil 6 through the I2C bus (as shown in fig. 1, the I2C bus includes an SDA line and an SCL line). When the first coil 6 is inserted into the first socket 4 of the adapter 1, the first coil 6 cannot trigger the second type interrupt, otherwise, when the second coil 7 is inserted into the second socket 5, the second type interrupt does not have high-low level jump, so that the identification information of the second coil 7 cannot be read.

If the second coil 7 is inserted into the second socket 5 of the adapter 1 after the first coil 6 is inserted into the first socket 4 of the adapter 1, which may be triggered by a second type of interrupt, the adapter 1 reads the identification information in the second coil 7 via the I2C bus.

Therefore, in the prior art, when two coils are connected into the system through the adapter, the coils need to be inserted into the socket according to a predetermined sequence, otherwise, the coils inserted later cannot be identified. That is, the coil that is first connected to the adapter must trigger the first type of interrupt, and the coil that is subsequently connected to the adapter must trigger the second type of interrupt, in order to enable coil identification.

In addition, when the adapter incorporates a register containing its own identification information, the configuration of the related art cannot read the identification information of the adapter.

In the embodiment of the invention, when a plurality of coils are simultaneously connected into one system socket through the adapter, the coils can be connected into any socket in the adapter to realize identification, and the adapter can be further identified.

In an embodiment of the present invention, an adapter includes: a plug that triggers a first type of interrupt signal for powering up the adapter when connected to the system socket; the multiple sockets are respectively and correspondingly connected with the multiple coils, and when the multiple sockets are connected with at least one coil in the multiple coils, a second type interrupt signal for sending the identification information of the at least one coil is triggered; and the interrupt retainer is respectively connected with each socket in the plurality of sockets and is used for keeping the second type of interrupt signals in an enabling state.

In one embodiment, the adapter further comprises a register for holding identification information of the adapter; wherein the plug is further configured to read the identification information of the adapter from the register via the data transfer bus.

The following describes an adapter according to an embodiment of the present invention, taking an example in which the adapter includes at least two sockets.

As shown in fig. 2, the adapter 20 includes:

a first socket 11 for triggering a first interrupt signal for transmitting identification information of the first coil 21 when the adapter 20 has been powered on and connected to the first coil 21;

a second socket 12 for triggering a second interrupt signal for transmitting identification information of the second coil 22 when the adapter 20 has been powered on and connected to the second coil 22;

and an interrupt holder 13 connected to the first socket 11 and the second socket 12, respectively, for holding the first interrupt signal and the second interrupt signal in an enabled state when the adapter 20 has been powered on.

The first interrupt signal and the second interrupt signal are of the same type and belong to the second type of interrupt, i.e. are each used for transmitting the identification information stored in the coil. It can be seen that, since the present invention employs the interrupt holder 13 for keeping the first interrupt signal and the second interrupt signal continuously enabled, the first socket 11 and the second socket 12 can transmit the identification information of the respective access coils using the second class interrupt, respectively, regardless of the order in which the coils are accessed to the adapters.

In one embodiment, the adapter further comprises:

a plug 14 for triggering a third interrupt signal when connected to the system socket 23 to draw power from the system socket 23 and power up the adapter 20.

Here, the third interrupt signal does not belong to the same type of interrupt as the first and second interrupt signals, but rather to the aforementioned first type of interrupt, i.e. for powering up the adapter 20. When the adapter 20 is powered up, the coils connected to the adapter (including the first coil 21 and the second coil 22) may also be powered up accordingly.

In one embodiment, the adapter further comprises: the register 15 is used for storing the identification information of the adapter 20, for example, the register 15 may be implemented as an Erasable Programmable Read Only Memory (EPROM) or a charged Erasable Programmable Read Only Memory (EPROM)Programmable read-Only Memory (Electrically Erasable programmable read-Only Memory, E)²PROM), and the like.

The plug 14 is also used to read the identification information of the adapter from the register 15 via the data transfer bus. In particular, the data transmission bus may be implemented as an I2C bus or a Serial Peripheral Interface (SPI) bus, or the like.

After the plug 14 reads the identification information of the adapter, the identification information of the adapter may be transmitted to the system socket 23 via the data transmission bus, and the system socket 23 may transmit the identification information of the adapter to a magnetic resonance system control unit or the like.

Thus, in an embodiment of the present invention, the plug 14 may also read the identification information of the adapter 20 from the register 15 via the data transfer bus.

The above exemplary description is of the kind of register and data transfer bus, and those skilled in the art will appreciate that this description is merely exemplary and is not intended to limit the scope of embodiments of the present invention.

In fig. 2, a specific structure of the adapter according to the embodiment of the present invention is described by taking an example in which the adapter includes two sockets. Indeed, the adapter of embodiments of the present invention may also be adapted for use with more than two receptacles.

In one embodiment, the adapter comprises at least one socket in addition to the first socket 11 and the second socket 12. Each of the at least one receptacle is configured to trigger a respective interrupt to transmit identification information of a respective corresponding coil when the adapter 20 is powered on and connected to the respective corresponding coil. Accordingly, an interrupt retainer 13, also connected to each of the at least one receptacle, is also used to keep the respective interrupt in an enabled state when the adapter has been powered up.

Therefore, the interruption holder 13 can transmit the identification information of the respective incoming coils independently with the respective interruptions regardless of the number of sockets included in the adapter by holding all the interruptions of all the sockets for transmitting the identification information of the respective incoming coils in the enabled state, regardless of the order in which the coils are accessed into the adapter.

In an embodiment of the present invention, the interrupt holder 13 in fig. 2 may be implemented by various components.

In one embodiment, the interruption holder 13 in fig. 2 may be implemented with two NPN transistors. Specifically, the interrupt holder 13 includes a first NPN-type transistor Q1, a second NPN-type transistor Q2, and an interrupt enable line (/ int 2); the base of the first NPN transistor is connected with a power line through a first bias resistor, the base of the first NPN transistor is also connected with the emitter of the second NPN transistor, and the emitter of the first NPN transistor is connected with a first socket; the base electrode of the second NPN transistor is connected with a power line through a second bias resistor, and the base electrode of the second NPN transistor is also connected with the emitter electrode of the first NPN transistor; the emitter of the second NPN transistor is connected with the second socket; the collector of the first NPN transistor is connected with the collector of the second NPN transistor; an interrupt enable line connected to a collector of the first NPN transistor and a collector of the second NPN transistor; the collector of the first NPN transistor and the collector of the second NPN transistor are connected with a power line through a third bias resistor. And an interrupt enable line connected to the collector of the first NPN transistor and the collector of the second NPN transistor.

Fig. 3 is a first exemplary block diagram of an adapter according to an embodiment of the present invention. In fig. 3, the interruption holder 13 in fig. 2 is implemented with two NPN transistors.

As shown in fig. 3, the adaptor 30 includes a first NPN transistor Q1, a second NPN transistor Q2, an interrupt enable line (/ int2), a plug 311, a first socket 111, and a second socket 112.

The base of the first NPN transistor Q1 is connected to a power supply line (Vcc) through a first bias resistor Rb1, the base of the first NPN transistor Q1 is further connected to the emitter of the second NPN transistor Q2, and the emitter of the first NPN transistor Q1 is connected to the first socket 111; the base of the second NPN transistor Q2 is connected to a power supply line (Vcc) through a second bias resistor Rb2, and the base of the second NPN transistor Q2 is further connected to the emitter of the first NPN transistor Q1; the emitter of the second NPN transistor Q2 is connected to the second socket 112; the collector of the first NPN transistor Q1 is connected to the collector of the second NPN transistor Q2; the collector of the first NPN transistor Q1 and the collector of the second NPN transistor Q2 are connected to a power supply line (Vcc) through a third bias resistor Rc. The interrupt enable line (/ int2) is connected to the collector of the first NPN transistor Q1 and the collector of the second NPN transistor Q2, respectively.

Specifically, in fig. 3, the adapter 30 includes three interfaces, one interface being a plug 311 that is accessed to a System Socket (SS), and the other two interfaces being a first socket 111 and a second socket 112 for coil access.

The plug 311 includes a signal line SCL, a signal line SDA, an interruption line of the first kind/int 1, an interruption line of the second kind/int 2, and a power supply line Vcc, wherein the signal line SCL and the signal line SDA belong to the I2C bus. The first and

second sockets

111 and 112 include a signal line SCL, a signal line SDA, an enable line EN, and a power supply line Vcc, respectively. Both the first type interrupt line/int 1 and the second type interrupt line/int 2 can trigger I2C communications, with the power supply line Vcc being used for the various E²And the PROM supplies power. The signal line SCL and the signal line SDA are communicated in the plug 311, the first receptacle 111, and the second receptacle 112. The power supply line Vcc is connected among the plug 311, the first socket 111, and the second socket 112.

The collectors of the first NPN transistor Q1 and the second NPN transistor Q2 are connected, and the second class interrupt/int 2 is connected to the collectors of the first NPN transistor Q1 and the second NPN transistor Q2, respectively. The collectors and bases of the first NPN transistor Q1 and the second NPN transistor Q2 are connected to the power supply line Vcc through respective bias resistors, respectively. The values of the resistors Rc, Rb1, and Rb2 are suitably selected to enable the first NPN transistor Q1 and the second NPN transistor Q2 to turn on. The bases of the first NPN transistor Q1 and the second NPN transistor Q2 are connected to the emitters of the respective other. The method specifically comprises the following steps: the base of the first NPN transistor Q1 is connected to the emitter of the second NPN transistor Q2, and the base of the second NPN transistor Q2 is connected to the emitter of the first NPN transistor Q1. The emitters of the first and second NPN transistors Q1 and Q2 are connected to the EN lines of the first and

second sockets

111 and 112, respectively.

At the first coil 211 and the second coil 212, the signal line EN is connected to a low level. The adapter 30 also includes therein E storing adapter identification information²PROM3, E²PROM3 is connected to the I2C bus.

When the adapter 30 is plugged into the System Socket (SS) of the magnetic resonance system, the first type interrupt/int 1 becomes active, triggering the system to communicate I2C, reading E in the adapter 30²PROM3, the adapter is recognized by the system.

The triggering of the second type of interrupt/int 2 is achieved indirectly via the coil connection, and it can be assumed that the second type of interrupt/int 2 is a high signal.

In the case where the adapter 30 has been connected to the system, when neither the first socket 111 nor the second socket 112 of the adapter 30 is connected to the coil,/int 2 is at the default high level and has no transition, which will not trigger the system to perform I2C communication.

When the first receptacle 111 or the second receptacle 112 of the adapter 30 is brought into coil access, the I2C communication buses SCL and SDA and the power line Vcc on the access coil communicate with the corresponding signal lines and power lines on the receptacle of the adapter 30. Assuming that the first coil 211 is connected to the first socket 111, since the emitter of the transistor Q1 is pulled to a low level by the EN signal line, the transistor Q1 is saturated and turned on, the transistor Q2 is turned off, the level on the interrupt line/int 2 in the second class changes from high to low, and the system is triggered to perform I2C communication, and read E in the first coil 211²The identification data of the PROM1, the first coil 211 is identified.

Then, when the second coil 212 is connected to the second socket 112, since the emitter of the transistor Q2 is pulled to low level by the EN signal line, the base and the emitter of the transistor Q1 and the transistor Q2 are both low level, the transistor Q1 and the transistor Q2 are both off, the level of the interrupt line/int 2 in the second type jumps from low to high, the trigger system performs l2C communication again, and reads the E signal in the second coil 212²The second coil 212 is identified as identification data of the PROM 2.

Therefore, for the first coil 211 and the second coil 212, normal identification of all coils can be realized no matter which coil is firstly connected to the system.

Without access to the system at adapter 30In this case, when the coil is connected to each of the two sockets of the adapter 30, and then the adapter 30 is connected to the system, the number of the coils is three²PROM (namely E)²PROM1、E²PRO2 and E²PROM3) is hung on the I2C bus, so that the three E can be read at one time²The PROM data, coil and adapter can be identified. At this time, E in the coil²PROM and E in adapter²PROM requires different addresses to be set to be distinguished and recognized by the system.

In one embodiment, the interrupt holder 13 in fig. 2 may be implemented with a PNP type transistor. Specifically, the interrupt holder 13 includes a first PNP type transistor, a second PNP type transistor, and an interrupt enable line; the base electrode of the first PNP transistor is connected with the first socket, the emitter electrode of the first PNP transistor is connected with the power line through the first bias resistor, and the emitter electrode of the first PNP transistor is also connected with the base electrode of the second PNP transistor; the base electrode of the second PNP transistor is connected with the second socket, the emitter electrode of the second PNP transistor is connected with the power line through the second bias resistor, and the emitter electrode of the second PNP transistor is also connected with the base electrode of the first PNP transistor; the collector of the first PNP transistor is connected with the collector of the second PNP transistor; the collector electrode of the first PNP transistor and the collector electrode of the second PNP transistor are connected with a power line through a third bias resistor; the interrupt enable line is connected to the collector of the first PNP type transistor and the collector of the second PNP type transistor.

Fig. 4 is a second exemplary block diagram of an adapter according to an embodiment of the present invention. In fig. 4, the interruption holder 13 in fig. 2 is implemented with two PNP type transistors.

As shown in fig. 4, the adapter 40 includes three interfaces, one being a plug 312 that is plugged into a System Socket (SS), and the other two being a first socket 113 and a second socket 114 for coil access, respectively.

The plug 312 includes a signal line SCL, a signal line SDA, an interruption line of the first kind/int 1, an interruption line of the second kind/int 2, and a power line Vcc, wherein the signal line SCL and the signal line SDA belong to the I2C bus. The first and

second sockets

113 and 114 include signal lines SCL, and,A signal line SDA, an enable line EN, and a power supply line Vcc. I2C communication can be triggered by a first type interrupt line/int 1 and a second type interrupt line/int 2, with power supply lines Vcc for various E²And the PROM supplies power. The signal line SCL and the signal line SDA are communicated at the plug 312, the first receptacle 113, and the second receptacle 114. The power supply line Vcc is connected among the plug 312, the first socket 113, and the second socket 114.

The collectors of the first PNP transistor Q1 and the second PNP transistor Q2 are connected, and the second class of interrupt/int 2 is also connected to the collectors of the first PNP transistor Q1 and the second PNP transistor Q2, respectively. The collectors and emitters of the first PNP type transistor Q1 and the second PNP type transistor Q2 are connected to the power supply line Vcc through respective bias resistors. The values of the resistors Rc, Rb1, and Rb2 are suitably selected to enable the first PNP transistor Q1 and the second PNP transistor Q2 to turn on. The bases of the first PNP transistor Q1 and the second PNP transistor Q2 are connected to the emitters of the respective other. The method specifically comprises the following steps: the base of the first PNP transistor Q1 is connected to the emitter of the second PNP transistor Q2, and the base of the second PNP transistor Q2 is connected to the emitter of the first PNP transistor Q1. The bases of the first PNP transistor Q1 and the second PNP transistor Q2 are connected to the EN lines of the first and

second sockets

113 and 114, respectively.

At the first winding 213 and the second winding 214, the signal line EN is connected low. The adapter 40 also contains an E storing adapter identification information²PROM3, E²PROM3 is connected to the I2C bus.

When the adapter 40 is plugged into the System Socket (SS) of the magnetic resonance system, the first type interrupt/int 1 becomes active, triggering the system to communicate I2C, reading E in the adapter 40²PROM3, the adapter is recognized by the system.

The triggering of the second type of interrupt/int 2 takes place indirectly via the coil connection. The default second type interrupt/int 2 is a high signal.

In the case where the adapter 40 has been plugged into the system, when neither the first socket 113 nor the second socket 114 of the adapter 40 has been plugged into the coil,/int 2 is the default high level and does not trip, triggering the system to communicate I2C.

When the first receptacle 113 or the second receptacle 114 of the adaptor 40 starts coil access, the I2C communication buses SCL and SDA and the power line Vcc on the access coil communicate with the corresponding signal lines and power lines on the receptacle of the adaptor 40. Assuming that the first coil 213 is connected to the first socket 113 of the adaptor, since the base of the transistor Q1 is pulled to low level by the EN signal line, the transistor Q1 is saturated and turned on, the transistor Q2 is turned off, and the level on the/int 2 line changes from high to low, triggering the system to perform I2C communication, reading E in the first coil 213²The identification data of the PROM1, the first coil 211 is identified.

Then, when the second coil 214 is connected to the second socket 114, since the base of the transistor Q2 is pulled to low level by the EN signal line, the base and the emitter of the transistors Q1 and Q2 are both low level, the transistor Q1 and the transistor Q2 are both turned off, the level on the/int 2 line is changed from low to high, the trigger system performs l2C communication again, and reads the E in the second coil 214²The identification data of the PROM 2, the second coil 214 is recognized.

Therefore, for the first coil 213 and the second coil 214, the normal identification of all coils can be realized no matter which coil is first connected to the system.

In the case where the adapter 40 is not connected to the system, when both receptacles of the adapter 40 are connected to the coil and then the adapter 40 is connected to the system, since there are three E' s²PROM (namely E)²PROM1、E²PRO2 and E²PROM3) are hung on the I2C bus, and three E can be read at one time²The PROM data, and therefore the coil and adapter, are also identified. At this time, E in the coil²PROM and E in adapter²PROM requires different addresses to be set to be distinguished and recognized by the system.

In one embodiment, the interruption holder 13 in fig. 2 may be implemented using a MOS transistor. Specifically, the interrupt holder 13 includes a first MOS-type transistor, a second MOS-type transistor, and an interrupt enable line; the source electrode of the first MOS type transistor is connected with the first socket, the grid electrode of the first MOS type transistor is connected with the power line through the first bias resistor, and the grid electrode of the first MOS type transistor is also connected with the source electrode of the second MOS type transistor; the source electrode of the second MOS type transistor is connected with the second socket, the grid electrode of the second MOS type transistor is connected with the power line through a second bias resistor, and the grid electrode of the second MOS type transistor is also connected with the source electrode of the first MOS type transistor; the drain electrode of the first MOS type transistor is connected with the drain electrode of the second MOS type transistor; an interrupt enable line connected to a drain of the first MOS type transistor and a drain of the second MOS type transistor; the drain electrode of the first MOS type transistor and the drain electrode of the second MOS type transistor are connected with a power line through a third bias resistor.

Fig. 5 is a third exemplary block diagram of an adapter according to an embodiment of the present invention. In fig. 5, the interrupt holder 13 in fig. 2 is implemented with two MOS tube bodies.

As shown in fig. 5, the adapter 50 includes three interfaces, one being a plug 313 that is plugged into a System Socket (SS), and the other two being a first socket 115 and a second socket 116, respectively, for coil access.

The plug 313 includes a signal line SCL, a signal line SDA, an interruption line of the first kind/int 1, an interruption line of the second kind/int 2, and a power supply line Vcc, wherein the signal line SCL and the signal line SDA belong to the I2C bus. The first and

second sockets

115 and 116 include a signal line SCL, a signal line SDA, an enable line EN, and a power supply line Vcc, respectively. I2C communication can be triggered by a first type interrupt line/int 1 and a second type interrupt line/int 2, with power supply lines Vcc for various E²And the PROM supplies power. The signal line SCL and the signal line SDA are communicated at both the plug 313, the first receptacle 115, and the second receptacle 116. The power supply line Vcc is connected among the plug 313, the first socket 115, and the second socket 116.

The drain of the MOS transistor Q1 and the drain of the MOS transistor Q2 are connected, while the second type interrupt/int 2 is connected to the drains of these two MOS transistors. The gates and drains of MOS transistor Q1 and Q2 are electrically connected to a power supply Vcc by respective biases. The values of the resistors Rg1, Rg2 and Rc are properly selected to enable the MOS transistor Q1 and the MOS transistor Q2 to be conducted. The source electrodes of the MOS transistor Q1 and the MOS transistor Q2 are respectively connected to the gate electrode of the other, specifically: the gate of the MOS transistor Q1 is connected to the source of the MOS transistor Q2, and the gate of the MOS transistor Q2 is connected to the source of the MOS transistor Q1. The sources of the two MOS transistors are connected to the EN signal lines of the first socket 115 and the second socket 116, respectively.

At the first coil 215 and the second coil 216, the signal line EN is low-level. The adapter 50 also includes therein E storing adapter identification information²PROM3, E²PROM3 is connected to the I2C bus.

When the adapter 50 is plugged into the System Socket (SS) of the magnetic resonance system, the first type interrupt/int 1 becomes active, triggering the system to communicate I2C, reading E in the adapter 50²PROM3, the adapter 50 is recognized by the system.

In the case where the adapter 50 has been plugged into the system, when neither the first socket 115 nor the second socket 116 of the adapter 50 has been plugged into the coil,/int 2 is the default high level and does not jump, triggering the system to communicate I2C.

When the first receptacle 115 or the second receptacle 116 of the adaptor 50 begins coil access, the I2C communication buses SCL and SDA and the power line Vcc on the access coil communicate with the corresponding signal lines and power lines on the receptacle of the adaptor 50. Assuming that the first coil 215 is connected to the first socket 115 of the adaptor, since the source of the MOS transistor Q1 is pulled to low level by the EN signal line, the MOS transistor Q1 is saturated and turned on, the MOS transistor Q2 is turned off, and the level on the/int 2 signal line changes from high to low, triggering the system to perform I2C communication, and reading E in the first coil 215²The identification data of the PROM1, the first coil 215 is recognized.

Then, when the second socket 116 is connected to the second coil 216, since the source of the transistor Q2 is pulled to low level by the EN signal line, the gates and sources of the transistors Q1 and Q2 are both at low level, the transistors Q1 and Q2 are both turned off, the level on the/int 2 signal line jumps from low to high, the trigger system performs l2C communication again, and reads the E signal in the second coil 216²The identification data of the PROM 2, the second coil 216, is recognized.

Thus, for the first coil 215 and the second coil 216, normal identification of all coils can be achieved no matter who first accesses the system at which socket.

In the case where the adapter 50 has no access to the systemIn this case, when the coil is connected to both sockets of the adapter 50 and then the adapter 50 is connected to the system, the result is three E²PROM (namely E)²PROM1、E²PRO2 and E²PROM3) are hung on the I2C bus, and the three E can be read at one time²The PROM data, and therefore the coil and adapter, are also identified. At this time, E in the coil²PROM and E in adapter²PROM requires different addresses to be set to be distinguished and recognized by the system.

The above example describes an adapter that supports two coil identifications. In fact, the adapter can also recognize a greater number of coils.

Fig. 6 is a fourth exemplary block diagram of an adapter according to an embodiment of the present invention. In fig. 6, a specific circuit implementation of an adapter supporting three coil identifications is illustrated.

As shown in fig. 6, the external features of the adapter 60 include four interfaces, one being a plug 314 that is plugged into a System Socket (SS), and the other three being a first socket 117, a second socket 118, and a third socket 119 for coil access.

The plug 314 includes signal lines SCL, SDA,/int 1 and/int 2 and a power line Vcc. The first, second and

third sockets

117, 118 and 119 include a signal line SCL, a signal line SDA, an enable line EN and a power supply line Vcc, respectively. The I2C communication buses SCL and SDA are all connected at the plug 314 and the three sockets, respectively. The power supply line Vcc is connected among the plug 314, the first socket 117, the second socket 118, and the third socket 11.

The collectors of transistors Q1 and Q2 are connected to each other, the collectors of transistors Q3 and Q4 are connected to each other, while the collectors of transistors Q1 and Q2 are connected to the emitter of transistor Q3, and the second class of interrupt/int 2 is connected to the collectors of transistor Q3 and transistor Q4.

The collectors and bases of transistors Q1-Q4 are connected to a power supply Vcc through bias resistors, respectively. The values of the resistors Rc, Rb1, Rb2, Rb3 and Rb4 are suitably chosen so that the transistors Q1-Q4 can all be turned on. The bases of the transistors Q1 and Q2 are connected to the emitters of the other, specifically: the base of the transistor Q1 is connected to the emitter of the transistor Q2, and the base of the transistor Q2 is connected to the emitter of the transistor Q1. The bases of the transistor Q3 and the transistor Q4 are respectively connected with the emitter of the other, specifically: the base of the transistor Q3 is connected to the emitter of the transistor Q4, and the base of the transistor Q4 is connected to the emitter of the transistor Q3. An emitter of the transistor Q1 is connected to the EN signal line of the first socket 117, an emitter of the transistor Q2 is connected to the EN signal line of the second socket 118, and an emitter of the transistor Q4 is connected to the EN signal line of the third socket 119.

At the coil 217, the coil 218, and the coil 219, the signal line EN is low.

The adapter 60 also includes E for storing adapter identification information²PROM3，E²The PROM3 hangs directly from the 12C bus. The transistors Q1 to Q4 in this embodiment mode may be PNP transistors or N-channel MOS transistors.

The specific structure of the adapter that supports 2 and 3 insert coils is described in detail above. In fact, the adapter of embodiments of the present invention may be adapted for any number of insertion coils.

As shown in fig. 7, the external features of the adapter 70 include N +1 interfaces, one interface being the plug 315 of the access system (SS), and the other N interfaces being N sockets (511, 512 …..51N) for coil access. Wherein n is any positive integer.

The plug 315 includes signal lines SCL, SDA, first class interrupt line/int 1, second class interrupt line/int 2, and power supply line Vcc. The n sockets (511, 512 …..51n) respectively include signal lines SCL, SDA, EN and power supply line Vcc. The I2C communication buses (SCL and SDA) are all connected in the plug 315 and the n receptacles (511, 512 …..51n), respectively. The power supply line Vcc is connected between the plug 315 and each of the n sockets (511, 512 …..51 n).

The total number of transistors is (2 n-2). The collectors of transistors Q1 and Q2 are connected to each other, the collectors of transistors Q3 and Q4 are connected to each other …, and so on, and the collectors of transistors Q (2n-3) and Q (2n-2) are connected to each other. Meanwhile, the collectors of the transistors Ql and Q2 are connected to the emitter of the transistor Q3, the collectors of the transistors Q3 and Q4 are connected to the emitter of the transistor Q5 …, and so on, and the collectors of the transistors Q (2N-5) and Q (2N-4) are connected to the emitter of the transistor Q (2N-3).

The second type of interrupt line/int 2 is connected to the collectors of transistors Q (2N-3) and Q (2N-2). The collector and base of each of the transistors Q1 through Q (2N-1) are connected to the power supply Vcc through a bias resistor, respectively. The appropriate resistance values are selected to render each of the transistors Q1 through Q (2N-1) conductive.

The bases of the transistors Q1 and Q2 are connected to the emitter of the other, specifically: the base of the transistor Q1 is connected to the emitter of the transistor Q2, and the base of the transistor Q2 is connected to the emitter of the transistor Q1.

The bases of the transistor Q3 and the transistor Q4 are respectively connected with the emitter of the other, specifically: the base of the transistor Q3 is connected to the emitter of the transistor Q4, and the base of the transistor Q4 is connected to the emitter of the transistor Q3.

By analogy, the bases of the transistor Q (2N-3) and the transistor Q (2N-2) are respectively connected with the emitter of the other side, and the specific steps are as follows: the base of the transistor Q (2N-3) is connected with the emitter of the transistor Q (2N-2), and the base of the transistor Q (2N-2) is connected with the emitter of the transistor Q (2N-3).

The emitter of the transistor Q1 is connected to the EN signal line of the first socket 311, the emitter of the transistor Q2 is connected to the EN signal line … of the adaptor second socket 312, and so on, and the emitter of the transistor Q (2N-2) is connected to the EN signal line of the nth socket 51N.

At the n coils (81, 82 … 8n), the signal line EN is low. The adapter 70 further comprises E for storing adapter identification information²And the PROM is directly hung on the I2C bus. The transistor Q1-Q (2N-2) in the method of this embodiment may be a PNP type or an N-channel MOS transistor type.

The invention also provides a coil identification system of the magnetic resonance imaging system. The identification system includes an adapter and a system socket. Wherein: an adapter, comprising: a plug for powering up the adapter; at least two sockets, wherein each socket is used for triggering respective interrupt to respectively send identification information of respective coil to the plug when the adapter is powered on and is connected with the respective coil; interrupt retainers, connected to the at least two sockets respectively, for retaining the respective interrupts in an enabled state when the adapter has been powered up; and the system socket is used for providing power for the plug and acquiring the identification information of the respective coil from the plug.

In one embodiment, the adapter further comprises a register for holding identification information of the adapter; a plug further configured to trigger an interrupt when connected to a system outlet to draw power from the system outlet and to read identification information of the adapter from a register via a data transfer bus.

In summary, the embodiment of the present invention provides a coil identification method and a corresponding implementation circuit from the coil identification perspective, which can realize the normal identification of multiple coils when a group of data transmission buses is accessed, and have no requirement on the coil access sequence, and have the characteristics of flexibility and freedom. An adapter designed according to the present invention facilitates such applications: when a plurality of low-channel coils need to be connected to the system for scanning at the same time, the plurality of coils can be connected to one system socket through the adapter without occupying other system sockets, so that the aims of reducing cost and optimizing resources are fulfilled.

For example, a typical example would be to connect two carotid coils to one coil socket via an adapter, leaving an additional system socket connected to the abdominal coil array.

FIG. 8 is an exemplary block diagram of a multi-coil application in accordance with an embodiment of the present invention.

As shown in fig. 8, the hospital bed has a first system socket 90 and a second system socket 91. The first system socket 90 is connected to an adapter 92, and the first carotid coil 93 and the second carotid coil 94 are connected to the first system socket 90 through the adapter 92, respectively; the abdominal coil array 95 is connected to the second system socket 91. Wherein the adapter 92 may have the specific structure of any of the adapters of fig. 2-7.

It should be noted that not all the modules in the above structure diagrams are necessary, and some modules may be omitted according to actual needs. The division of each module is only for convenience of describing adopted functional division, and in actual implementation, one module may be divided into multiple modules, and the functions of multiple modules may also be implemented by the same module, and these modules may be located in the same device or in different devices.

The hardware modules in the various embodiments may be implemented mechanically or electronically. For example, a hardware module may include a specially designed permanent circuit or logic device (e.g., a special purpose processor such as an FPGA or ASIC) for performing specific operations. A hardware module may also include programmable logic devices or circuits (e.g., including a general-purpose processor or other programmable processor) that are temporarily configured by software to perform certain operations. The implementation of the hardware module in a mechanical manner, or in a dedicated permanent circuit, or in a temporarily configured circuit (e.g., configured by software), may be determined based on cost and time considerations.

In summary, in the embodiments of the present invention, the adapter includes the interruption retainers connected to the first receptacle and the second receptacle, respectively. The interrupt retainer may maintain the first interrupt and the second interrupt in an enabled state continuously after the adapter has been powered on, so that the first receptacle may transmit the identification information of the access coil using the first interrupt, and the second receptacle may transmit the identification information of the access coil using the second interrupt, regardless of the order in which the respective access adapters are sequenced. Therefore, the coil can be identified without a specified socket in the embodiment of the invention, thereby being convenient for users to use.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An adapter for a magnetic resonance imaging system, comprising:

2. The adapter of a magnetic resonance imaging system according to claim 1, further comprising:

a register for storing an identification information of the adapter;

3. An adapter for a magnetic resonance imaging system according to claim 1,

the plurality of sockets comprises a first socket and a second socket;

the interrupt retainer comprises a first NPN transistor, a second NPN transistor and an interrupt enable line;

4. An adapter for a magnetic resonance imaging system according to claim 1,

the plurality of sockets comprises a first socket and a second socket;

the interrupt retainer comprises a first PNP type transistor, a second PNP type transistor and an interrupt enable line;

5. An adapter for a magnetic resonance imaging system according to claim 1,

the plurality of sockets comprises a first socket and a second socket;

6. An adapter for a magnetic resonance imaging system according to claim 2,

the data transmission bus is a built-in integrated circuit bus or a serial peripheral interface bus.

7. A coil identification system for a magnetic resonance imaging system, comprising:

an adapter, comprising:

8. A coil identification system for a magnetic resonance imaging system according to claim 7,

the adapter also comprises a register used for storing identification information of the adapter;

9. A coil identification system for a magnetic resonance imaging system according to claim 7,

the plurality of sockets comprises a first socket and a second socket;

10. A coil identification system for a magnetic resonance imaging system according to claim 7,

the plurality of sockets comprises a first socket and a second socket;