CN108335708A

CN108335708A - A kind of programmable double data rate register circuit and control method of single-particle reinforcing

Info

Publication number: CN108335708A
Application number: CN201810139176.3A
Authority: CN
Inventors: 陈雷; 倪劼; 李琦; 孙华波; 王文锋; 郭琨; 孙健爽; 刘亚泽; 钱涛涛
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2018-02-11
Filing date: 2018-02-11
Publication date: 2018-07-27
Anticipated expiration: 2038-02-11
Also published as: CN108335708B

Abstract

A kind of programmable double data rate register circuit and control method of single-particle reinforcing, by the single-particle Design of Reinforcement that convention latches are realized with register memory cell using the circuit of dual redundant interlocking structure, on this basis by the way that clock generation circuit, data multiplexer and data holding circuit is added, the double data rate register functions of various modes can be realized to control multiple dual redundant interlocking structure register sequential.Single-particle of the present invention reinforces index and improves three orders of magnitude than legacy register, and level latch, haploidy number may be implemented according to rate edge triggered flip flop, instead along pattern double data rate edge triggered flip flop and with along programmable functions such as pattern double data rate edge triggered flip flops, user is made to reinforce index with higher flexibility, better timing performance and high anti-single particle when using programmable user register.

Description

A kind of programmable double data rate register circuit and control method of single-particle reinforcing

Technical field

The programmable double data rate register circuit and control method reinforced the present invention relates to a kind of single-particle, especially A kind of programmable single-particle of optimization design reinforcing register circuit and control for programmable logic device application demand Method belongs to integrated circuit fields.

Background technology

Programmable logic device has many advantages, such as that flexibility is high, at low cost, the period is short, can substantially reduce grinding for product Period processed and maximization reduce risk, have become the core component in IC industry.Programmable user therein Register is the core circuit that user's sequential logic function is realized in programmable logic device, can be programmed according to the demand of user Realize a variety of sequential functions.

On the other hand, due to the influence of space single particle effect, the data in programmable user register can be made to occur single Particle is overturn, and causes the mistake of user storage data, and key is used as in case of the programmable user register of single-particle inversion When state machine, this user function can be made to interrupt.

Traditional single-particle reinforcement means is by using the methods of duplication redundancy, triplication redundancy into line storage, trigger Design of Reinforcement, and it is limited for the reinforcement ability of programmable logic device.Meanwhile these programmable user registers need energy It is enough operated under very high message transmission rate, can be brought greatly using traditional reinforcement means in double data rate register Area requirements, and be difficult to meet the requirement of high-speed transfer.Therefore, it is necessary to for the space application ring of programmable logic device The border design double data rate register that targetedly single-particle is reinforced.Both ensure that the anti-single particle for storing data overturns ability, There are flexible programmable features again, while meeting the speed of user and the design requirement of sequential.

Invention content

The technology of the present invention solves the problems, such as：In place of overcome the deficiencies in the prior art, for the sky of programmable logic device Between application environment, provide the programmable double data rate register circuit and control method that a kind of single-particle is reinforced, both solved The anti-single particle of storage data overturns ability, and has flexible programmable features, while meeting the speed and sequential of user Design requirement.

The technical solution that the present invention solves is：A kind of programmable double data rate register circuit packet that single-particle is reinforced It includes：Pulse-generating circuit, clock switch, data control switch, the reinforcing register of dual redundant interlocking structure and dual redundant The data holding circuit of interlocking structure；

Clock pulse generating circuit can generate clock pulses, and clock switch can control clock pulse generating circuit Clock pulses is sent to data control switch, or the reinforcing of control dual redundant interlocking structure and is posted by the phase for sending out clock pulses Data input of the storage outside being stored according to clock；Data control switch can select dual redundant interlocking knot according to clock pulses The data output of the reinforcing register of structure, send to the data holding circuit of dual redundant interlocking structure, the number of dual redundant interlocking structure Output valve is kept according to holding circuit (111).

The reinforcing register of dual redundant interlocking structure, including：The reinforcing register of first dual redundant interlocking structure (104), the reinforcing register of the reinforcing register (105) of second dual redundant interlocking structure, third dual redundant interlocking structure (106)；

Clock switch, including：First clock switch (101), second clock switch (102), Three clock switches (103)；

Clock pulse generating circuit, including：First clock pulse generating circuit (108), second clock pulses generate Circuit (109), third clock pulse generating circuit (110)；

When realizing that haploidy number is transmitted according to rate, third clock switch (103) controls clock pulse generating circuit (110) Clock pulses is given to a data control switch (107) in the rising edge of clock, while third dual redundant interlocking structure It is logical to reinforce register (106) first data input D1 (100), data control switch (107) outside rising edge clock capture D3 is crossed to be output to the data (Q i.e. first data input 100) of the reinforcing register (106) of third dual redundant interlocking structure The data holding circuit (111) of one dual redundant interlocking structure is kept by the data holding circuit (111) of dual redundant interlocking structure Output valve.

When realizing double data rate instead along transmission, third clock switch (103) controls the production of third clock pulses Raw circuit (110) send clock pulses to a data control switch (107) in the rising edge of clock；Third dual redundant simultaneously The reinforcing register (106) of interlocking structure first data input D1 (100) outside rising edge clock capture；Data control is opened Close the number that the data of the reinforcing register (106) of third dual redundant interlocking structure are output to dual redundant interlocking structure by (107) According to holding circuit (111)；First clock switch (101) controls first clock pulse generating circuit (108) in clock Clock pulses is given to a data control switch (107), the reinforcing register of first dual redundant interlocking structure by failing edge (104) second data input D2 (112) outside clock falling edge capture, data control switch (107) is by D1 by first The data of the reinforcing register (104) of a dual redundant interlocking structure are output to the data holding circuit of dual redundant interlocking structure (111), output valve is kept by the data holding circuit (111) of dual redundant interlocking structure.

When realizing double data rate with along transmission, third clock switch (103) controls the production of third clock pulses Clock pulses is given to data control switch (107) by raw circuit (110) in the rising edge of clock；Third dual redundant interlocking structure Reinforcing register (106) outside rising edge clock capture first data input D1 (100), data control switch (107) The data that the data of the reinforcing register (106) of third dual redundant interlocking structure are output to a dual redundant interlocking structure are protected Hold circuit (111)；

First clock switch (101) control the reinforcing register (104) of first dual redundant interlocking structure when Second data input D2 (112) outside the storage of clock rising edge；Second clock switch (102) controls second clock Pulse-generating circuit (109) generates a clock pulses in clock falling edge and send to data control switch (107), and second double superfluous The reinforcing register (105) of remaining interlocking structure captures the reinforcing register (104) of first dual redundant interlocking structure by reversed Output afterwards, data control switch (107) by the data transmission of the reinforcing register (105) of second dual redundant interlocking structure extremely The data holding circuit (111) of one dual redundant interlocking structure is kept by the data holding circuit (111) of dual redundant interlocking structure Output valve.

The reinforcing register of dual redundant interlocking structure, including：The reinforcing register of first dual redundant interlocking structure (104), the reinforcing register of the reinforcing register (105) of second dual redundant interlocking structure, third dual redundant interlocking structure (106),

The reinforcing register (104) of first dual redundant interlocking structure includes a data input pin, a positive clock Input terminal, a reversed input end of clock and a data output end, the rising edge in positive input end of clock and reversed clock When the failing edge of input terminal, the data output end fan-out at end is entered data into；First dual redundant interlocking structure plus Gu second data of the programmable double data rate register circuit that the data input pin of register (104) is reinforced with single-particle Input terminal D2 (112) connections；The positive input end of clock and first of the reinforcing register (104) of first dual redundant interlocking structure The positive output terminal of clock of a clock switch (101) connects；The reinforcing register (104) of first dual redundant interlocking structure Reversed input end of clock connect with the reversed output terminal of clock of first clock switch (101)；First dual redundant is mutual First number of the data output end and phase inverter (118) and data control switch (107) of the reinforcing register (104) of lock construction It is connected according to input terminal；

The reinforcing register (105) of second dual redundant interlocking structure includes a data input pin, a positive clock Input terminal, a reversed input end of clock and a data output end, the rising edge in positive input end of clock and reversed clock When the failing edge of input terminal, the data output end fan-out at end is entered data into；First dual redundant interlocking structure plus Gu the data input pin of register (105) is connect with the output of phase inverter (118)；The reinforcing of second dual redundant interlocking structure is posted The positive input end of clock of storage (105) is connect with the positive output terminal of clock of second clock switch (102)；Second The reversed input end of clock of the reinforcing register (105) of dual redundant interlocking structure is anti-with second clock switch (105) It is connected to output terminal of clock；The data output end of the reinforcing register (105) of second dual redundant interlocking structure is controlled with data Switch second data input pin connection of (107)；

The reinforcing register (106) of third dual redundant interlocking structure includes a data input pin, a positive clock Input terminal, a reversed input end of clock and a data output end, the rising edge in positive input end of clock and reversed clock When the failing edge of input terminal, the data output end fan-out at end is entered data into；Third dual redundant interlocking structure adds Gu first data of the programmable double data rate register circuit that the data input pin of register (106) is reinforced with single-particle Input terminal D1 (100) connections；The positive input end of clock and third of the reinforcing register (106) of third dual redundant interlocking structure The positive output terminal of clock of a clock switch (103) connects；The reinforcing register (106) of third dual redundant interlocking structure Reversed input end of clock connect with the reversed output terminal of clock of third clock switch (106)；Third dual redundant is mutual The data output end of the reinforcing register (106) of lock construction is connect with the third data input pin of data control switch (107).

The composition and connection relation of first clock switch (101)

First clock switch (101) includes an input end of clock, a control terminal, a positive clock output End and a reversed output terminal of clock, when control terminal is high level, positive output terminal of clock is identical as input end of clock phase, Reversed output terminal of clock and input end of clock opposite in phase, when control terminal is low level, positive output terminal of clock and clock are defeated Enter and hold opposite in phase, reversed output terminal of clock is identical as input end of clock phase；The clock of first clock switch (101) Input terminal is connect with the input end of clock CPP (113) for the programmable double data rate register circuit that single-particle is reinforced；First First configuration of the programmable double data rate register circuit that the control terminal of clock switch (101) is reinforced with single-particle Port S1 (114) connections；The positive output terminal of clock and first dual redundant interlocking structure of first clock switch (101) Reinforcing register (104) positive input end of clock and first clock pulse generating circuit (108) the input of positive clock End connection；The reinforcing of the reversed output terminal of clock and first dual redundant interlocking structure of first clock switch (101) is posted The reversed input end of clock of storage (104) connects；

Second clock switch (102) includes an input end of clock, a control terminal, a positive clock output End and a reversed output terminal of clock, when control terminal is high level, positive output terminal of clock is identical as input end of clock phase, Reversed output terminal of clock and input end of clock opposite in phase, when control terminal is low level, positive output terminal of clock and clock are defeated Enter and hold opposite in phase, reversed output terminal of clock is identical as input end of clock phase；The clock of second clock switch (102) Input terminal is connect with the input end of clock CPP (113) for the programmable double data rate register circuit that single-particle is reinforced；Second Second configuration of the programmable double data rate register circuit that the control terminal of clock switch (102) is reinforced with single-particle Port S2 (115) connections；The positive output terminal of clock and second dual redundant interlocking structure of second clock switch (102) Reinforcing register (105) positive input end of clock and second clock pulse generating circuit (109) the input of positive clock End connection；The reinforcing of the reversed output terminal of clock and second dual redundant interlocking structure of second clock switch (102) is posted The reversed input end of clock of storage (105) connects；

Third clock switch (103) includes an input end of clock, a control terminal, a positive clock output End and a reversed output terminal of clock, when control terminal is high level, positive output terminal of clock is identical as input end of clock phase, Reversed output terminal of clock and input end of clock opposite in phase, when control terminal is low level, positive output terminal of clock and clock are defeated Enter and hold opposite in phase, reversed output terminal of clock is identical as input end of clock phase；The clock of third clock switch (103) Input terminal is connect with the input end of clock CPP (113) for the programmable double data rate register circuit that single-particle is reinforced；Third The third for the programmable double data rate register circuit that the control terminal of clock switch (103) is reinforced with single-particle configures Port S3 (116) connections；The positive output terminal of clock of third clock switch (103) and third dual redundant interlocking structure Reinforcing register (106) positive input end of clock and third clock pulse generating circuit (110) positive clock input End connection；The reversed output terminal of clock of third clock switch (103) and the reinforcing of third dual redundant interlocking structure are posted The reversed input end of clock of storage (106) connects.

When first clock pulse generating circuit (108) is including a positive input end of clock, two control terminals and one Clock output end, two control terminals can control output terminal of clock pulse and export clock in the rising edge of positive input end of clock Pulse, permanent High level or lasting low level；The positive input end of clock and first of first clock pulse generating circuit (108) The positive output terminal of clock of a clock switch (101) connects；First control of first clock pulse generating circuit (108) 4th configuration port EN11 (118) of the programmable double data rate register circuit that end processed is reinforced with single-particle connect；The The programmable double data rate register electricity that second control terminal of one clock pulse generating circuit (108) is reinforced with single-particle The 5th configuration port EN21 (119) on road connects；The output terminal of clock pulse of first clock pulse generating circuit (108) with First clock pulse input terminal of data control switch (107) connects；

When second clock pulse generating circuit (109) is including a positive input end of clock, two control terminals and one Clock output end, two control terminals can control output terminal of clock pulse and export clock in the rising edge of positive input end of clock Pulse, permanent High level or lasting low level；The positive input end of clock and second of second clock pulse generating circuit (109) The positive output terminal of clock of a clock switch (102) connects；First control of second clock pulse generating circuit (109) 6th configuration port EN12 (120) of the programmable double data rate register circuit that end processed is reinforced with single-particle connect；The The programmable double data rate register electricity that second control terminal of two clock pulse generating circuits (109) is reinforced with single-particle The 7th configuration port EN22 (121) on road connects；The output terminal of clock pulse of second clock pulse generating circuit (109) with Second clock pulse input terminal of data control switch (107) connects；

When third clock pulse generating circuit (110) is including a positive input end of clock, two control terminals and one Clock output end, two control terminals can control output terminal of clock pulse and export clock in the rising edge of positive input end of clock Pulse, permanent High level or lasting low level；The positive input end of clock and third of third clock pulse generating circuit (110) The positive output terminal of clock of a clock switch (103) connects；First control of third clock pulse generating circuit (110) 8th configuration port EN13 (122) of the programmable double data rate register circuit that end processed is reinforced with single-particle connect；The The programmable double data rate register electricity that second control terminal of three clock pulse generating circuits (110) is reinforced with single-particle The 9th configuration port EN23 (123) on road connects；The output terminal of clock pulse of third clock pulse generating circuit (110) with The third clock pulse input terminal of data control switch (107) connects.

Data control switch (107), including three data input pins, three clock pulse input terminals and two data outputs The data of first data input pin are respectively outputted to the by end when clock pulses occurs in first clock pulse input terminal One data output end and second data output end, when clock pulses occurs in second clock pulse input terminal, by second The data of a data input pin are respectively outputted to first data output end and second data output end, when third clock arteries and veins When rushing input terminal and clock pulses occur, the data of third data input pin are respectively outputted to first data output end and Two data output ends；The reinforcing of first data input pin and first dual redundant interlocking structure of data control switch (107) The data output end of register (104) connects；Second data input pin and second dual redundant of data control switch (107) The data output end of the reinforcing register (105) of interlocking structure connects；The third data input pin of data control switch (107) It is connect with the data output end of the reinforcing register (106) of third dual redundant interlocking structure；The of data control switch (107) One clock pulse input terminal is connect with the output terminal of clock pulse of first clock pulse generating circuit (108)；Data control Switch the output terminal of clock pulse of second clock pulse input terminal and second clock pulse generating circuit (109) of (107) Connection；The third clock pulse input terminal of data control switch (107) and third clock pulse generating circuit (110) when Clock output end connects；First data output end of data control switch (107) is protected with the data of dual redundant interlocking structure Hold first data input pin connection of circuit (111)；Second data output end and dual redundant of data control switch (107) Second data input pin of the data holding circuit (111) of interlocking structure connects.

The data holding circuit (111) of dual redundant interlocking structure, including two data input pins and a data output end, When the data of two data input pins are identical, the data of data output end output data input terminal, when two data input pins Data Data difference when, data output end keeps the output data at a moment；The data of dual redundant interlocking structure are kept First data input pin of circuit (111) is connect with first data output end of data control switch (107)；Dual redundant is mutual Second data input pin of the data holding circuit (111) of lock construction and second data of data control switch (107) are defeated Outlet connects；The data output end of the data holding circuit (111) of dual redundant interlocking structure is reinforced programmable double with single-particle Output end Q (117) connections of haplotype data rate register circuit.

The data of the reinforcing register (104) of the input terminal of phase inverter (118) and first dual redundant interlocking structure export End connection；The data input pin of the reinforcing register (105) of the output end of phase inverter (118) and second dual redundant interlocking structure Connection.

The reinforcing register of three dual redundant interlocking structures, three clock switches, three clock pulse generating circuits, One data control switch (107), the data holding circuit (111) of dual redundant interlocking structure and a phase inverter (118)；

The reinforcing register of three dual redundant interlocking structures, respectively：The reinforcing deposit of first dual redundant interlocking structure The reinforcing deposit of device (104), the reinforcing register (105) of second dual redundant interlocking structure, third dual redundant interlocking structure Device (106)；

Three clock switches, respectively：First clock switch (101), second clock switch (102), third clock switch (103)；

Three clock pulse generating circuits, respectively：First clock pulse generating circuit (108), second clock arteries and veins Rush generation circuit (109), third clock pulse generating circuit (110)；

Clock switch (101,102,103), including buffer B1 (207), phase inverter I 1 (208), phase inverter I2 (209), buffer B2 (210), phase inverter I3 (211), alternative Port Multiplier M1 (205), alternative Port Multiplier M2 (206)；Often A alternative Port Multiplier includes two input terminals, an output end and a control terminal, and when control terminal is high level, alternative is more First input terminal of road device is connected with output end, when control terminal be low level, second input terminal of alternative Port Multiplier with Output end is connected；

The input terminal CP (201) of the input terminal connection clock switch of buffer B1 (207), buffer B1's (207) Output end connects first input terminal of alternative Port Multiplier M1 (205)；

The input terminal CP (201) of the input terminal connection clock switch of phase inverter I1 (208), phase inverter I1's (208) Output end connects second input terminal of alternative Port Multiplier M1 (205)；

The input terminal S (202) of the input terminal connection clock switch of phase inverter I2 (209), phase inverter I1's (208) is defeated Outlet connects the control terminal of alternative Port Multiplier M2 (206)；

The input terminal CP (201) of the input terminal connection clock switch of buffer B2 (210), buffer B2's (210) Output end connects first input terminal of alternative Port Multiplier M2 (206)；

The input terminal CP (201) of the input terminal connection clock switch of phase inverter I3 (211), phase inverter I3's (211) Output end connects second input terminal of alternative Port Multiplier M2 (206)；

The control terminal of alternative Port Multiplier M1 (205) is the input terminal S (202) of clock switch, alternative Port Multiplier The output end of M1 (205) is the output end CPP (203) of clock switch, when the output end of alternative Port Multiplier M2 (206) is The output end CPN (204) of clock system switch；

The reinforcing register (104,105,106) of dual redundant interlocking structure, including four memory nodes and four are programmable Switch；Four memory nodes are respectively memory node X1 (305), memory node X2 (307), memory node X3 (306), storage section Point X4 (308)；Each memory node includes a P-channel metal-oxide-semiconductor and a N-channel MOS pipe；Four programmable switch difference For programmable switch K1 (317), programmable switch K2 (318), programmable switch K3 (319), programmable switch K4 (320)；Often A programmable switch includes two fixing ends and a control terminal, and two fixing end connections can be turned on or off by control terminal, Programmable switch is set to be closed or disconnect；

The reinforcing deposit of the fixing end connection dual redundant interlocking structure of two fixing ends in programmable switch K1 (317) The input terminal D (301) of device；Another fixing end connection memory node X1 of two fixing ends in programmable switch K1 (317) (305) grid of the grid of N-channel MOS pipe N1 (310) and the P-channel metal-oxide-semiconductor P2 (313) of memory node X2 (307)；It can compile The control terminal of Cheng Kaiguan K1 (317) is the input terminal CPP (302) of the reinforcing register of dual redundant interlocking structure；

The reinforcing deposit of the fixing end connection dual redundant interlocking structure of two fixing ends in programmable switch K2 (318) The input terminal D (301) of device；Another fixing end connection memory node X1 of two fixing ends in programmable switch K2 (318) (305) grid of the grid of P-channel metal-oxide-semiconductor P1 (309) and the N-channel MOS pipe N2 (314) of memory node X2 (307)；It can compile The control terminal of Cheng Kaiguan K2 (318) is the input terminal CPP (302) of the reinforcing register of dual redundant interlocking structure；

The output end of the fixing end connection memory node X3 (306) of two fixing ends in programmable switch K3 (319) O3(323)；The P-channel of another fixing end connection memory node X1 (305) of two fixing ends in programmable switch K3 (319) The grid of the grid of metal-oxide-semiconductor P1 (309) and the N-channel MOS pipe N2 (314) of memory node X2 (307)；Programmable switch K3 (319) control terminal is the input terminal CPN (303) of the reinforcing register of dual redundant interlocking structure；

The output end of the fixing end connection memory node X4 (308) of two fixing ends in programmable switch K4 (320) O4(324)；The N of another fixing end connection connection memory node X1 (305) of two fixing ends in programmable switch K4 (320) The grid of the grid of channel MOS tube N1 (310) and the P-channel metal-oxide-semiconductor P2 (313) of memory node X2 (307)；Programmable switch K4 (320) control terminal is the input terminal CPN (303) of the reinforcing register of dual redundant interlocking structure；

The source electrode of the P-channel metal-oxide-semiconductor P1 (309) of memory node X1 (305) connects power supply；The N ditches of memory node X1 (305) The source electrode connection ground of road metal-oxide-semiconductor N1 (310)；The drain electrode connection storage section of the P-channel metal-oxide-semiconductor P1 (309) of memory node X1 (305) The drain electrode of the N-channel MOS pipe N1 (310) of point X1 (305), the output O1 (321) as memory node X1 (305)；Memory node The grid and memory node X4 of the P-channel metal-oxide-semiconductor P3 (311) of output O1 (321) the connection memory node X3 (306) of X1 (305) (308) grid of N-channel MOS pipe (316), the output end Q (304) of the reinforcing register as dual redundant interlocking structure；

The source electrode of the P-channel metal-oxide-semiconductor P2 (313) of memory node X2 (307) connects power supply；The N ditches of memory node X2 (307) The source electrode connection ground of road metal-oxide-semiconductor N2 (314)；The drain electrode connection storage section of the P-channel metal-oxide-semiconductor P2 (313) of memory node X2 (307) The drain electrode of the N-channel MOS pipe N2 (314) of point X2 (307), the output O2 (322) as memory node X2 (307)；Memory node The grid and memory node X4 of the N-channel MOS pipe N3 (312) of output O2 (322) the connection memory node X3 (306) of X2 (307) (308) grid of P-channel metal-oxide-semiconductor (315)；

The source electrode of the P-channel metal-oxide-semiconductor P3 (311) of memory node X3 (306) connects power supply；The N ditches of memory node X3 (306) The source electrode connection ground of road metal-oxide-semiconductor N3 (312)；The drain electrode connection storage section of the P-channel metal-oxide-semiconductor P3 (311) of memory node X3 (306) The drain electrode of the N-channel MOS pipe N3 (312) of point X3 (306), the output O3 (323) as memory node X3 (306)；

The source electrode of the P-channel metal-oxide-semiconductor P4 (315) of memory node X4 (308) connects power supply；The N ditches of memory node X4 (308) The source electrode connection ground of road metal-oxide-semiconductor N4 (316)；The drain electrode connection storage section of the P-channel metal-oxide-semiconductor P4 (315) of memory node X4 (308) The drain electrode of the N-channel MOS pipe N4 (316) of point X4 (308), the output O4 (324) as memory node X4 (308)；

Data control switch (107), including six programmable switches, respectively programmable switch K5 (409), programmable switch Close K6 (410), programmable switch K7 (411), programmable switch K8 (412), programmable switch K9 (413), programmable switch K10 (414)；

The input terminal D1 of the fixing end connection data control switch of two fixing ends in programmable switch K5 (409) (401)；The output end Q1 of another fixing end connection data control switch of two fixing ends in programmable switch K5 (409) (407)；The control terminal of programmable switch K5 (409) is the input terminal CP1 (404) of data control switch；

The input terminal D2 of the fixing end connection data control switch of two fixing ends in programmable switch K6 (410) (402)；The output end Q1 of another fixing end connection data control switch of two fixing ends in programmable switch K6 (410) (407)；The control terminal of programmable switch K6 (410) is the input terminal CP2 (405) of data control switch；

The input terminal D3 of the fixing end connection data control switch of two fixing ends in programmable switch K7 (411) (403)；The output end Q1 of another fixing end connection data control switch of two fixing ends in programmable switch K7 (411) (407)；The control terminal of programmable switch K7 (411) is the input terminal CP3 (406) of data control switch；

The input terminal D1 of the fixing end connection data control switch of two fixing ends in programmable switch K8 (412) (401)；The output end Q2 of another fixing end connection data control switch of two fixing ends in programmable switch K8 (412) (408)；The control terminal of programmable switch K8 (412) is the input terminal CP1 (404) of data control switch；

The input terminal D2 of the fixing end connection data control switch of two fixing ends in programmable switch K9 (413) (402)；The output end Q2 of another fixing end connection data control switch of two fixing ends in programmable switch K9 (413) (408)；The control terminal of programmable switch K9 (419) is the input terminal CP2 (405) of data control switch；

The input terminal D3 of the fixing end connection data control switch of two fixing ends in programmable switch K10 (414) (403)；The output end Q2 of another fixing end connection data control switch of two fixing ends in programmable switch K10 (414) (408)；The control terminal of programmable switch K10 (414) is the input terminal CP3 (406) of data control switch；

Clock pulse generating circuit (108,109,110), including phase inverter I4 (505), phase inverter I5 (506), nor gate R1 (507), NAND gate A1 (508), NAND gate A2 (509)；

The input terminal CPP (501), phase inverter I4 of the input terminal connection clock pulse generating circuit of phase inverter I4 (505) (505) input terminal of output end connection phase inverter I5 (506)；The output end connection nor gate R1 (507) of phase inverter I5 (506) An input terminal；The input terminal EN2 (503) of another input terminal connection clock pulse generating circuit of nor gate R1 (507), An input terminal of the output end connection NAND gate A1 (508) of nor gate R1 (507)；Another input of NAND gate A1 (508) The input terminal CPP (501) of end connection clock pulse generating circuit, the output end connection NAND gate A2 (509) of NAND gate A1 (508) An input terminal；The input terminal EN1 (502) of another input terminal connection clock pulse generating circuit of NAND gate A2 (509), Output end CPW (504) of the output end of NAND gate A2 (509) as clock pulse generating circuit；

The data holding circuit (111) of dual redundant interlocking structure, including four memory nodes, respectively memory node X5 (604), memory node X6 (606), memory node X7 (605), memory node X8 (607)；

The source electrode of the P-channel metal-oxide-semiconductor P5 (608) of memory node X5 (604) connects power supply；The N ditches of memory node X5 (604) The source electrode connection ground of road metal-oxide-semiconductor N5 (609)；The drain electrode connection storage section of the P-channel metal-oxide-semiconductor P5 (608) of memory node X5 (604) The drain electrode of the N-channel MOS pipe N5 (609) of point X5 (604), the output O5 (616) as memory node X5 (604)；Memory node The grid and memory node X8 of the P-channel metal-oxide-semiconductor P7 (610) of output O5 (616) the connection memory node X7 (605) of X5 (604) (607) grid of N-channel MOS pipe N8 (615), the output end Q of the data holding circuit as dual redundant interlocking structure (603)；

The source electrode of the P-channel metal-oxide-semiconductor P6 (612) of memory node X6 (606) connects power supply；The N ditches of memory node X6 (606) The source electrode connection ground of road metal-oxide-semiconductor N6 (613)；The drain electrode connection storage section of the P-channel metal-oxide-semiconductor P6 (612) of memory node X6 (606) The drain electrode of the N-channel MOS pipe N6 (612) of point X6 (606), the output O6 (618) as memory node X6 (606)；Memory node The grid and memory node X8 of the N-channel MOS pipe N7 (611) of output O6 (618) the connection memory node X7 (605) of X6 (606) (607) grid of P-channel metal-oxide-semiconductor P8 (614)；

The source electrode of the P-channel metal-oxide-semiconductor P7 (610) of memory node X7 (605) connects power supply；The N ditches of memory node X7 (605) The source electrode connection ground of road metal-oxide-semiconductor N7 (611)；The drain electrode connection storage section of the P-channel metal-oxide-semiconductor P7 (610) of memory node X7 (605) The drain electrode of the N-channel MOS pipe N7 (611) of point X7 (605), the output O7 (617) as memory node X7 (605)；Memory node Grid, the memory node X6 of the P-channel metal-oxide-semiconductor P5 (608) of output O7 (617) the connection memory node X5 (604) of X7 (605) (606) the input terminal D2 (602) of the grid of N-channel MOS pipe N6 (613) and the data holding circuit of dual redundant interlocking structure；

The source electrode of the P-channel metal-oxide-semiconductor P8 (614) of memory node X8 (607) connects power supply；The N ditches of memory node X8 (607) The source electrode connection ground of road metal-oxide-semiconductor N8 (615)；The drain electrode connection storage section of the P-channel metal-oxide-semiconductor P8 (614) of memory node X8 (607) The drain electrode of the N-channel MOS pipe N8 (615) of point X8 (607), the output O8 (619) as memory node X8 (607)；Memory node Grid, the memory node X6 of the N-channel MOS pipe N5 (609) of output O8 (619) the connection memory node X5 (604) of X8 (607) (606) the input terminal D1 (601) of the grid of P-channel metal-oxide-semiconductor P6 (612) and the data holding circuit of dual redundant interlocking structure.

Clock pulse generating circuit (108,109,110) can generate clock pulses, control in the rising edge and failing edge of clock Data control switch (107) processed clock rising edge and failing edge output data, by adjusting clock pulse generating circuit The delay of phase inverter I4 (505) and phase inverter I5 (506) can control the width of pulse in minimum clock in (108,109,110) Ten halfs in period are in the range of 1/6th.

The data holding circuit of dual redundant interlocking structure can keep output data within the time of not clock pulses Validity, the wherein driving capability of memory node X7 (605) and memory node X8 (607) be less than memory node X5 (604) and Metal-oxide-semiconductor grid width is storage section in the driving capability of memory node X6 (606), memory node X7 (605) and memory node X8 (607) The a quarter of metal-oxide-semiconductor grid width or memory node X7 (605) and memory node in point X5 (604) and memory node X6 (606) Metal-oxide-semiconductor grid length is four times of metal-oxide-semiconductor grid length in memory node X5 (604) and memory node X6 (606) in X8 (607).

The advantages of the present invention over the prior art are that：

(1) it by the present invention in that with the reinforcing register of third dual redundant interlocking structure, can be substantially improved programmable Double data rate register is programmed to the anti-single particle overturning ability of level latch state, with traditional level latch phase Than anti-single particle index at least improves 3 orders of magnitude.

(2) by the present invention in that reinforcing register and clock pulse generating circuit with third dual redundant interlocking structure Combination, can be substantially improved the anti-list that programmable double data rate register is programmed to haploidy number according to rate edge triggered flip flop state Particle overturns ability, and compared with traditional haploidy number is according to rate edge triggered flip flop, anti-single particle index at least improves 3 orders of magnitude.

(3) by the present invention in that the data of the reinforcing register and dual redundant interlocking structure with three dual redundant interlocking structures The combination of holding circuit can be substantially improved programmable double data rate register and organized double data rate edge triggered flip flop The anti-single particle of state overturns ability, compared with traditional double data rate edge triggered flip flop, anti-single particle index at least improves 3 A order of magnitude.

(4) by the present invention in that with three clock switches, three clock pulse generating circuits and data control switch, Flexible programmability can be provided to the user, the programmable double data rate register electricity for making the single-particle of the present invention reinforce Level latch, haploidy number may be implemented according to rate edge triggered flip flop, instead along pattern double data rate edge triggered flip flop and same edge in road The programmable functions such as pattern double data rate edge triggered flip flop.

(5) by the present invention in that rising edge and failing edge with clock pulse generating circuit in clock generate pulse respectively, The data transmission bauds being effectively lifted under double data rate, can be full by adjusting pulse width under different process node The requirement of the various clock frequencies of foot.

(6) by the present invention in that use the data holding circuit of dual redundant interlocking structure as under edge triggered flip flop pattern from Latch can effectively reduce design to chip using the reinforcing register of three dual redundant interlocking structures as main latch The demand of area, compared to the area that the design of traditional edge triggered flip flop can save about 40%.

Description of the drawings

Fig. 1 is the programmable double data rate register circuit schematic diagram that single-particle of the present invention is reinforced；

Fig. 2 is clock switch circuit diagram of the present invention；

Fig. 3 is the reinforcing register circuit schematic diagram of dual redundant interlocking structure of the present invention；

Fig. 4 is data control switch circuit diagram of the present invention；

Fig. 5 is clock pulse generating circuit circuit diagram of the present invention；

Fig. 6 is the data holding circuit circuit diagram of dual redundant interlocking structure of the present invention.

Specific implementation mode

The present invention is described in further detail in the following with reference to the drawings and specific embodiments.

The present invention basic ideas be：A kind of programmable double data rate register circuit that single-particle is reinforced, including three The reinforcing register of a dual redundant interlocking structure, three clock switches, three clock pulse generating circuits, a data control The data holding circuit of system switch, dual redundant interlocking structure.By using dual redundant interlocking structure to convention latches Circuit realizes the single-particle Design of Reinforcement of register memory cell, more by the way that clock generation circuit, data are added on this basis Road device and data holding circuit can realize the double number of various modes to control multiple dual redundant interlocking structure register sequential According to rate register functions.It can adapt in different process node and clock rates by adjusting the clock-pulse width of generation Requirement.It is dropped as the slave latch under edge triggered flip flop pattern by using the data holding circuit of dual redundant interlocking structure The low demand to chip area.Using this structure single-particle reinforce programmable double data rate register transmission delay, Identical as traditional flip-flop, latch structure in foundation/retention time parameter, single-particle reinforces index than traditional flip-flop, lock Storage improves 3 orders of magnitude, and level latch, haploidy number may be implemented according to rate edge triggered flip flop, instead along the double number of pattern According to rate edge triggered flip flop and with along programmable functions such as pattern double data rate edge triggered flip flops, user is made to be used using programmable When the register of family index is reinforced with higher flexibility, better timing performance and high anti-single particle.

The programmable double data rate register circuit that a kind of single-particle of the present invention is reinforced, as shown in Figure 1, its feature exists In including：The reinforcing register of three dual redundant interlocking structures, three clock switches, three clock pulse generating circuits, One data control switch (107), the data holding circuit (111) of dual redundant interlocking structure and a phase inverter (118)；

Clock switch (101,102,103), as shown in Fig. 2, including buffer B1 (207), phase inverter I1 (208), Phase inverter I2 (209), buffer B2 (210), phase inverter I3 (211), alternative Port Multiplier M1 (205), alternative Port Multiplier M2 (206)；Each alternative Port Multiplier includes two input terminals, an output end and a control terminal, when control terminal is high level, First input terminal of alternative Port Multiplier is connected with output end, when control terminal be low level, second of alternative Port Multiplier Input terminal is connected with output end；

The reinforcing register (104,105,106) of dual redundant interlocking structure, as shown in figure 3, including four memory nodes and Four programmable switches；Four memory nodes are respectively memory node X1 (305), memory node X2 (307), memory node X3 (306), (308) memory node X4；Each memory node includes a P-channel metal-oxide-semiconductor and a N-channel MOS pipe；Four can Program switch is respectively programmable switch K1 (317), programmable switch K2 (318), programmable switch K3 (319), programmable switch Close K4 (320)；Each programmable switch includes two fixing ends and a control terminal, and control terminal can connect two fixing ends It is turned on or off, programmable switch is made to be closed or disconnect；

Data control switch (107), as shown in figure 4, including six programmable switches, respectively programmable switch K5 (409), programmable switch K6 (410), programmable switch K7 (411), programmable switch K8 (412), programmable switch K9 (413), (414) programmable switch K10；

Clock pulse generating circuit (108,109,110), as shown in figure 5, including phase inverter I4 (505), phase inverter I5 (506), nor gate R1 (507), NAND gate A1 (508), NAND gate A2 (509)；

The data holding circuit (111) of dual redundant interlocking structure is respectively deposited as shown in fig. 6, including four memory nodes Store up nodes X 5 (604), memory node X6 (606), memory node X7 (605), memory node X8 (607)；

The working method of the reinforcing register of the dual redundant interlocking structure designed in the present invention is as follows：As programmable switch K3 (319), programmable switch K4 (320) is opened simultaneously, and programmable switch K1 (317), programmable switch K2 (318) are simultaneously switched off, Memory node X1 (305), memory node X2 (307), the memory node X3 of dual redundant interlocking structure reinforced in register (306), memory node X4 (308) forms single-particle and reinforces storage organization.Memory node X3 (306) and memory node X4 (308) Identical value is stored, memory node X1 (305) and memory node X2 (307) store identical value, memory node X3 (306), deposit It stores up nodes X 4 (308) and memory node X1 (305), memory node X2 (307) stores opposite value.When single event occurs When, as memory node X3 (306), memory node X4 (308) store 0 signal, memory node X1 (305), memory node X2 (307) 1 signal is stored, single-particle inversion storage value occurs for memory node X1 (305) becomes 0 signal from 1, at this time (306) memory node X3 In indefinite state, memory node X4 (308) keeps 0 signal of storage, memory node X2 (307) to keep 1 signal of storage.Work as single-particle After event, since memory node X4 (308) keeps 0 signal of storage, memory node X2 (307) to keep 1 signal of storage, storage Nodes X 4 (308) and the signal of memory node X2 (307) storages drive memory node X1's (305) and memory node X3 (306) Input, makes memory node X1 (305) reply 1 signal of storage, and memory node X3 (306) restores 0 signal of storage, it is single to form resistance The function of particle overturning.

The work side of the clock switch, clock pulse generating circuit and data control switching circuit that are designed in the present invention Method is as follows：When input port S3 (116) is high level, output CPP (707) and the input of third clock switch (103) CP (705) in the same direction, the output CPN (708) of third clock switch (103) and input CP (705) reversely, input port EN11 (118), EN21 (119), EN12 (120), EN22 (121) make first clock pulse generating circuit (108) and second In vain, input port EN13 (122), EN23 (123) make third clock pulse generating circuit to clock pulse generating circuit (109) (110) high level is exported always, to make entire circuit be operated in level latch pattern；When input port S3 (116) is height Level, in the same direction, third clock control is opened by the output CPP (707) and input CP (705) of third clock switch (103) Close (103) output CPN (708) with input CP (705) reversely, input port EN11 (118), EN21 (119), EN12 (120), EN22 (121) makes first clock pulse generating circuit (108) and second clock pulse generating circuit (109) in vain, input Port EN13 (122), EN23 (123) make third clock pulse generating circuit (110) export high impulse in rising edge clock, from And entire circuit is made to be operated in haploidy number according to rate edge triggered flip flop pattern；When input port S3 (116) is high level, when third Clock system switchs the output CPP (707) and input CP (705) of (103) in the same direction, the output of third clock switch (103) Reversely, input port S1 (114) is low level to CPN (708) and input CP (705), first clock switch (101) it is defeated Go out CPP (203) and input CP (201) reversely, the output CPN (204) and input CP of first clock switch (101) (201) in the same direction, the reinforcing register (106) of third dual redundant interlocking structure captures data, first dual redundant in rising edge The reinforcing register (104) of interlocking structure captures data in failing edge, and input port EN12 (120), EN22 (121) make second In vain, input port EN11 (118), EN21 (119) make first clock pulse generating circuit to clock pulse generating circuit (109) (108) high impulse is exported in clock falling edge, input port EN13 (122), EN23 (123) make third clock pulses generate electricity Road (110) exports high impulse in rising edge clock, to make entire circuit be operated in instead along double data rate edge triggered flip flop mould Formula；When input port S3 (116) is high level, the output CPP (707) and input CP of third clock switch (103) (705) in the same direction, the output CPN (708) of third clock switch (103) with input CP (705) reversely, input terminal S1 (114) be high level, the output CPP (203) of first clock switch (101) and input CP (201) in the same direction, at first Clock system switch (101) output CPN (204) with input CP (201) reversely, input port S2 (115) be low level, second The output CPP (703) of clock switch (102) and input CP (701) reversely, second clock switch (102) it is defeated Go out CPN (703) and input CP (701) in the same direction, the reinforcing register (106) of third dual redundant interlocking structure is captured in rising edge The reinforcing register (104) of data, first dual redundant interlocking structure captures data, second dual redundant interlocking knot in rising edge The reinforcing register (105) of structure captures the data of the reinforcing register (104) of first dual redundant interlocking structure in failing edge, defeated Inbound port EN11 (118), EN21 (119) make first clock pulse generating circuit (108) in vain, input port EN12 (120), EN22 (121) makes second clock pulse generating circuit (109) export high impulse, input port EN13 in clock falling edge (122), EN23 (123) makes third clock pulse generating circuit (110) export high impulse in rising edge clock, entire to make Circuit is operated in along double data rate edge triggered flip flop pattern.

The single particle experiment for programmable the double data rate register and legacy register that the single-particle of 1 present invention of table is reinforced The comparison of data

The programmable double data rate register and legacy register that the single-particle of the present invention is reinforced are shown by table 1 The comparison of single particle experiment data, under Si particles, the single-particle of the single event upset rate of circuit of the present invention than legacy register Overturning rate declines 3 orders of magnitude, when LET energy reaches 37MeV cm²/ mg also has extremely low overturning rate, shows the present invention's The programmable double data rate register that single-particle is reinforced achievees the effect that good single-particle is reinforced.

Claims

1. the programmable double data rate register circuit that a kind of single-particle is reinforced, it is characterised in that including：Pulse-generating circuit, The data guarantor for reinforcing register and dual redundant interlocking structure of clock switch, data control switch, dual redundant interlocking structure Hold circuit；

Clock pulse generating circuit can generate clock pulses, and clock switch can control clock pulse generating circuit submitting The phase of clock pulses send clock pulses to data control switch, or the reinforcing register of control dual redundant interlocking structure Data input outside being stored according to clock；Data control switch can select dual redundant interlocking structure according to clock pulses The data output for reinforcing register is sent to the data holding circuit of dual redundant interlocking structure, and the data of dual redundant interlocking structure are protected It holds circuit (111) and keeps output valve.

2. the programmable double data rate register circuit that a kind of single-particle according to claim 1 is reinforced, feature exist In：The reinforcing register of dual redundant interlocking structure, including：The reinforcing register (104) of first dual redundant interlocking structure, second The reinforcing register (105) of a dual redundant interlocking structure, the reinforcing register (106) of third dual redundant interlocking structure；

Clock switch, including：First clock switch (101), second clock switch (102), third Clock switch (103)；

Clock pulse generating circuit, including：First clock pulse generating circuit (108), second clock pulse generating circuit (109), third clock pulse generating circuit (110)；

Haploidy number is realized when being transmitted according to rate, third clock switch (103) control clock pulse generating circuit (110) when Clock pulses is given to a data control switch (107), while the reinforcing of third dual redundant interlocking structure by the rising edge of clock Register (106) first data input D1 (100), data control switch (107) outside rising edge clock capture pass through D3 The data (Q i.e. first data input 100) of the reinforcing register (106) of third dual redundant interlocking structure are output to one The data holding circuit (111) of dual redundant interlocking structure keeps output by the data holding circuit (111) of dual redundant interlocking structure Value；

When realizing double data rate instead along transmission, third clock switch (103) controls third clock pulses and generates electricity Clock pulses is sent to a data control switch (107) in the rising edge of clock on road (110)；Third dual redundant interlocking simultaneously The reinforcing register (106) of structure first data input D1 (100) outside rising edge clock capture；Data control switch (107) data of the reinforcing register (106) of third dual redundant interlocking structure are output to the data of dual redundant interlocking structure Holding circuit (111)；First clock switch (101) controls first clock pulse generating circuit (108) under clock Clock pulses is given to a data control switch (107), the reinforcing register (104) of first dual redundant interlocking structure by drop edge Second data input D2 (112) outside clock falling edge capture, data control switch (107) are double superfluous by first by D1 The data of the reinforcing register (104) of remaining interlocking structure are output to the data holding circuit (111) of dual redundant interlocking structure, by double The data holding circuit (111) of redundancy interlocking structure keeps output valve；

When realizing double data rate with along transmission, third clock switch (103) controls third clock pulses and generates electricity Clock pulses is given to data control switch (107) by road (110) in the rising edge of clock；Third dual redundant interlocking structure adds Gu register (106) first data input D1 (100) outside rising edge clock capture, data control switch (107) is by the The data that the data of the reinforcing register (106) of three dual redundant interlocking structures are output to a dual redundant interlocking structure keep electricity Road (111)；

First clock switch (101) controls the reinforcing register (104) of first dual redundant interlocking structure on clock Rise second data input D2 (112) outside storage；Second clock switch (102) controls second clock pulses Generation circuit (109) generates a clock pulses in clock falling edge and send to data control switch (107), and second dual redundant is mutual The reinforcing register (105) of lock construction captures the reinforcing register (104) of first dual redundant interlocking structure after reversed Output, data control switch (107) is by the data transmission of the reinforcing register (105) of second dual redundant interlocking structure to one The data holding circuit (111) of dual redundant interlocking structure keeps output by the data holding circuit (111) of dual redundant interlocking structure Value.

3. the programmable double data rate register circuit that a kind of single-particle according to claim 1 is reinforced, feature exist In：The reinforcing register of dual redundant interlocking structure, including：The reinforcing register (104) of first dual redundant interlocking structure, second The reinforcing register (105) of a dual redundant interlocking structure, the reinforcing register (106) of third dual redundant interlocking structure,

The reinforcing register (104) of first dual redundant interlocking structure includes a data input pin, a positive clock input End, a reversed input end of clock and a data output end are inputted in the rising edge of positive input end of clock and reversed clock When the failing edge at end, the data output end fan-out at end is entered data into；The reinforcing of first dual redundant interlocking structure is posted Second data of the programmable double data rate register circuit that the data input pin of storage (104) is reinforced with single-particle input D2 (112) is held to connect；The positive input end of clock of the reinforcing register (104) of first dual redundant interlocking structure and at first Clock system switchs the positive output terminal of clock connection of (101)；The reinforcing register (104) of first dual redundant interlocking structure it is anti- It is connect to input end of clock with the reversed output terminal of clock of first clock switch (101)；First dual redundant interlocking knot The data output end of the reinforcing register (104) of structure and first data of phase inverter (118) and data control switch (107) are defeated Enter end connection；

The reinforcing register (105) of second dual redundant interlocking structure includes a data input pin, a positive clock input End, a reversed input end of clock and a data output end are inputted in the rising edge of positive input end of clock and reversed clock When the failing edge at end, the data output end fan-out at end is entered data into；The reinforcing of first dual redundant interlocking structure is posted The data input pin of storage (105) is connect with the output of phase inverter (118)；The reinforcing register of second dual redundant interlocking structure (105) positive input end of clock is connect with the positive output terminal of clock of second clock switch (102)；Second double superfluous The reversed input end of clock of the reinforcing register (105) of remaining interlocking structure and second clock switch (105) it is reversed when Clock output end connects；The data output end and data control switch of the reinforcing register (105) of second dual redundant interlocking structure (107) second data input pin connection；

The reinforcing register (106) of third dual redundant interlocking structure includes a data input pin, a positive clock input End, a reversed input end of clock and a data output end are inputted in the rising edge of positive input end of clock and reversed clock When the failing edge at end, the data output end fan-out at end is entered data into；The reinforcing of third dual redundant interlocking structure is posted First data of the programmable double data rate register circuit that the data input pin of storage (106) is reinforced with single-particle input D1 (100) is held to connect；When the positive input end of clock of the reinforcing register (106) of third dual redundant interlocking structure is with third Clock system switchs the positive output terminal of clock connection of (103)；The reinforcing register (106) of third dual redundant interlocking structure it is anti- It is connect to input end of clock with the reversed output terminal of clock of third clock switch (106)；Third dual redundant interlocking knot The data output end of the reinforcing register (106) of structure is connect with the third data input pin of data control switch (107).

4. the programmable double data rate register circuit that a kind of single-particle according to claim 1 is reinforced, feature exist In：Clock switch, including：When first clock switch (101), second clock switch (102), third Clock system switchs (103)；

The composition and connection relation of first clock switch (101)

First clock switch (101) include an input end of clock, a control terminal, a positive output terminal of clock and One reversed output terminal of clock, when control terminal is high level, positive output terminal of clock is identical as input end of clock phase, reversely Output terminal of clock and input end of clock opposite in phase, when control terminal is low level, positive output terminal of clock and input end of clock Opposite in phase, reversed output terminal of clock are identical as input end of clock phase；The clock input of first clock switch (101) The input end of clock CPP (113) for the programmable double data rate register circuit reinforced with single-particle is held to connect；First clock First configuration port of the programmable double data rate register circuit that the control terminal of control switch (101) is reinforced with single-particle S1 (114) connections；The positive output terminal of clock of first clock switch (101) and first dual redundant interlocking structure plus Gu the positive input end of clock of register (104) and the positive input end of clock of first clock pulse generating circuit (108) connect It connects；The reinforcing register of the reversed output terminal of clock and first dual redundant interlocking structure of first clock switch (101) (104) reversed input end of clock connection；

Second clock switch (102) include an input end of clock, a control terminal, a positive output terminal of clock and One reversed output terminal of clock, when control terminal is high level, positive output terminal of clock is identical as input end of clock phase, reversely Output terminal of clock and input end of clock opposite in phase, when control terminal is low level, positive output terminal of clock and input end of clock Opposite in phase, reversed output terminal of clock are identical as input end of clock phase；The clock input of second clock switch (102) The input end of clock CPP (113) for the programmable double data rate register circuit reinforced with single-particle is held to connect；Second clock Second configuration port of the programmable double data rate register circuit that the control terminal of control switch (102) is reinforced with single-particle S2 (115) connections；The positive output terminal of clock of second clock switch (102) and second dual redundant interlocking structure plus Gu the positive input end of clock of register (105) and the positive input end of clock of second clock pulse generating circuit (109) connect It connects；The reinforcing register of the reversed output terminal of clock and second dual redundant interlocking structure of second clock switch (102) (105) reversed input end of clock connection；

Third clock switch (103) include an input end of clock, a control terminal, a positive output terminal of clock and One reversed output terminal of clock, when control terminal is high level, positive output terminal of clock is identical as input end of clock phase, reversely Output terminal of clock and input end of clock opposite in phase, when control terminal is low level, positive output terminal of clock and input end of clock Opposite in phase, reversed output terminal of clock are identical as input end of clock phase；The clock of third clock switch (103) inputs The input end of clock CPP (113) for the programmable double data rate register circuit reinforced with single-particle is held to connect；Third clock The third for the programmable double data rate register circuit that the control terminal of control switch (103) is reinforced with single-particle configures port S3 (116) connections；The positive output terminal of clock of third clock switch (103) adds with third dual redundant interlocking structure Gu the positive input end of clock of register (106) and the positive input end of clock of third clock pulse generating circuit (110) connect It connects；The reinforcing register of the reversed output terminal of clock and third dual redundant interlocking structure of third clock switch (103) (106) reversed input end of clock connection.

5. the programmable double data rate register circuit that a kind of single-particle according to claim 1 is reinforced, feature exist In：Clock pulse generating circuit, including：First clock pulse generating circuit (108), second clock pulse generating circuit (109), third clock pulse generating circuit (110)；

First clock pulse generating circuit (108) includes a positive input end of clock, two control terminals and a clock arteries and veins Output end is rushed, two control terminals can control output terminal of clock pulse and export clock arteries and veins in the rising edge of positive input end of clock Punching, permanent High level or lasting low level；The positive input end of clock of first clock pulse generating circuit (108) and first The positive output terminal of clock of clock switch (101) connects；First control of first clock pulse generating circuit (108) The 4th configuration port EN11 (118) of the programmable double data rate register circuit reinforced with single-particle is held to connect；First The programmable double data rate register circuit that second control terminal of a clock pulse generating circuit (108) is reinforced with single-particle The 5th configuration port EN21 (119) connect；The output terminal of clock pulse and number of first clock pulse generating circuit (108) According to first clock pulse input terminal connection of control switch (107)；

Second clock pulse generating circuit (109) includes a positive input end of clock, two control terminals and a clock arteries and veins Output end is rushed, two control terminals can control output terminal of clock pulse and export clock arteries and veins in the rising edge of positive input end of clock Punching, permanent High level or lasting low level；The positive input end of clock of second clock pulse generating circuit (109) and second The positive output terminal of clock of clock switch (102) connects；First control of second clock pulse generating circuit (109) The 6th configuration port EN12 (120) of the programmable double data rate register circuit reinforced with single-particle is held to connect；Second The programmable double data rate register circuit that second control terminal of a clock pulse generating circuit (109) is reinforced with single-particle The 7th configuration port EN22 (121) connect；The output terminal of clock pulse and number of second clock pulse generating circuit (109) According to second clock pulse input terminal connection of control switch (107)；

Third clock pulse generating circuit (110) includes a positive input end of clock, two control terminals and a clock arteries and veins Output end is rushed, two control terminals can control output terminal of clock pulse and export clock arteries and veins in the rising edge of positive input end of clock Punching, permanent High level or lasting low level；The positive input end of clock of third clock pulse generating circuit (110) and third The positive output terminal of clock of clock switch (103) connects；First control of third clock pulse generating circuit (110) The 8th configuration port EN13 (122) of the programmable double data rate register circuit reinforced with single-particle is held to connect；Third The programmable double data rate register circuit that second control terminal of a clock pulse generating circuit (110) is reinforced with single-particle The 9th configuration port EN23 (123) connect；The output terminal of clock pulse and number of third clock pulse generating circuit (110) According to the third clock pulse input terminal connection of control switch (107).

6. the programmable double data rate register circuit that a kind of single-particle according to claim 1 is reinforced, feature exist In：Data control switch (107), including three data input pins, three clock pulse input terminals and two data output ends, when When clock pulses occurs in first clock pulse input terminal, the data of first data input pin are respectively outputted to first number According to output end and second data output end, when clock pulses occurs in second clock pulse input terminal, by second data The data of input terminal are respectively outputted to first data output end and second data output end, when third clock pulses inputs When bringing out current clock, the data of third data input pin are respectively outputted to first data output end and the second data Output end；The reinforcing register of first data input pin and first dual redundant interlocking structure of data control switch (107) (104) data output end connection；Second data input pin of data control switch (107) and second dual redundant interlocking are tied The data output end of the reinforcing register (105) of structure connects；The third data input pin and third of data control switch (107) The data output end of the reinforcing register (106) of a dual redundant interlocking structure connects；At first of data control switch (107) Clock input terminal is connect with the output terminal of clock pulse of first clock pulse generating circuit (108)；Data control switch (107) second clock pulse input terminal is connect with the output terminal of clock pulse of second clock pulse generating circuit (109)； The clock arteries and veins of the third clock pulse input terminal and third clock pulse generating circuit (110) of data control switch (107) Rush output end connection；First data output end of data control switch (107) keeps electricity with the data of dual redundant interlocking structure First data input pin on road (111) connects；Second data output end of data control switch (107) is interlocked with dual redundant Second data input pin of the data holding circuit (111) of structure connects.

7. the programmable double data rate register circuit that a kind of single-particle according to claim 1 is reinforced, feature exist In：The data holding circuit (111) of dual redundant interlocking structure, including two data input pins and a data output end, when two When the data of a data input pin are identical, the data of data output end output data input terminal, when the number of two data input pins When according to data difference, data output end keeps the output data at a moment；The data holding circuit of dual redundant interlocking structure (111) first data input pin is connect with first data output end of data control switch (107)；Dual redundant interlocking knot Second data input pin of the data holding circuit (111) of structure and second data output end of data control switch (107) Connection；The data output end of the data holding circuit (111) of dual redundant interlocking structure may be programmed double number with what single-particle was reinforced According to output end Q (117) connections of rate register circuit.

8. the programmable double data rate register circuit that a kind of single-particle according to claim 1 is reinforced, feature exist In：The data output end of the reinforcing register (104) of the input terminal of phase inverter (118) and first dual redundant interlocking structure connects It connects；The data input pin of the reinforcing register (105) of the output end of phase inverter (118) and second dual redundant interlocking structure connects It connects.

9. the programmable double data rate register circuit that a kind of single-particle according to claim 1 is reinforced, feature exist In including：The reinforcing register of three dual redundant interlocking structures, three clock switches, three clock pulse generating circuits, One data control switch (107), the data holding circuit (111) of dual redundant interlocking structure and a phase inverter (118)；

The reinforcing register of three dual redundant interlocking structures, respectively：The reinforcing register of first dual redundant interlocking structure (104), the reinforcing register of the reinforcing register (105) of second dual redundant interlocking structure, third dual redundant interlocking structure (106)；

Three clock pulse generating circuits, respectively：First clock pulse generating circuit (108), second clock pulses production Raw circuit (109), third clock pulse generating circuit (110)；

Clock switch (101,102,103), including buffer B1 (207), phase inverter I1 (208), phase inverter I2 (209), Buffer B2 (210), phase inverter I3 (211), alternative Port Multiplier M1 (205), alternative Port Multiplier M2 (206)；Each two choosing One Port Multiplier include two input terminals, an output end and a control terminal, when control terminal be high level, alternative Port Multiplier First input terminal is connected with output end, when control terminal is low level, second input terminal and output end of alternative Port Multiplier Conducting；

The input terminal CP (201) of the input terminal connection clock switch of buffer B1 (207), the output of buffer B1 (207) First input terminal of end connection alternative Port Multiplier M1 (205)；

The input terminal CP (201) of the input terminal connection clock switch of phase inverter I1 (208), the output of phase inverter I1 (208) Second input terminal of end connection alternative Port Multiplier M1 (205)；

The input terminal S (202) of the input terminal connection clock switch of phase inverter I2 (209), the output end of phase inverter I1 (208) Connect the control terminal of alternative Port Multiplier M2 (206)；

The input terminal CP (201) of the input terminal connection clock switch of buffer B2 (210), the output of buffer B2 (210) First input terminal of end connection alternative Port Multiplier M2 (206)；

The input terminal CP (201) of the input terminal connection clock switch of phase inverter I3 (211), the output of phase inverter I3 (211) Second input terminal of end connection alternative Port Multiplier M2 (206)；

The control terminal of alternative Port Multiplier M1 (205) is the input terminal S (202), alternative Port Multiplier M1 of clock switch (205) output end is the output end CPP (203) of clock switch, and the output end of alternative Port Multiplier M2 (206) is clock Control the output end CPN (204) of switch；

The reinforcing register (104,105,106) of dual redundant interlocking structure, including four memory nodes and four programmable switches； Four memory nodes are respectively memory node X1 (305), memory node X2 (307), memory node X3 (306), memory node X4 (308)；Each memory node includes a P-channel metal-oxide-semiconductor and a N-channel MOS pipe；Four programmable switches are respectively can Program switch K1 (317), programmable switch K2 (318), programmable switch K3 (319), programmable switch K4 (320)；Each may be used Program switch includes two fixing ends and a control terminal, and two fixing end connections can be turned on or off by control terminal, and making can Program switch is closed or disconnects；

The reinforcing register of the fixing end connection dual redundant interlocking structure of two fixing ends in programmable switch K1 (317) Input terminal D (301)；Another fixing end connection memory node X1 (305) of two fixing ends in programmable switch K1 (317) The grid of the grid of N-channel MOS pipe N1 (310) and the P-channel metal-oxide-semiconductor P2 (313) of memory node X2 (307)；Programmable switch The control terminal of K1 (317) is the input terminal CPP (302) of the reinforcing register of dual redundant interlocking structure；

The reinforcing register of the fixing end connection dual redundant interlocking structure of two fixing ends in programmable switch K2 (318) Input terminal D (301)；Another fixing end connection memory node X1 (305) of two fixing ends in programmable switch K2 (318) The grid of the grid of P-channel metal-oxide-semiconductor P1 (309) and the N-channel MOS pipe N2 (314) of memory node X2 (307)；Programmable switch The control terminal of K2 (318) is the input terminal CPP (302) of the reinforcing register of dual redundant interlocking structure；

The output end O3 of the fixing end connection memory node X3 (306) of two fixing ends in programmable switch K3 (319) (323)；The P-channel of another fixing end connection memory node X1 (305) of two fixing ends in programmable switch K3 (319) The grid of the grid of metal-oxide-semiconductor P1 (309) and the N-channel MOS pipe N2 (314) of memory node X2 (307)；Programmable switch K3 (319) control terminal is the input terminal CPN (303) of the reinforcing register of dual redundant interlocking structure；

The output end O4 of the fixing end connection memory node X4 (308) of two fixing ends in programmable switch K4 (320) (324)；The N ditches of another fixing end connection connection memory node X1 (305) of two fixing ends in programmable switch K4 (320) The grid of the grid of road metal-oxide-semiconductor N1 (310) and the P-channel metal-oxide-semiconductor P2 (313) of memory node X2 (307)；Programmable switch K4 (320) control terminal is the input terminal CPN (303) of the reinforcing register of dual redundant interlocking structure；

The source electrode of the P-channel metal-oxide-semiconductor P1 (309) of memory node X1 (305) connects power supply；The N-channel of memory node X1 (305) The source electrode connection ground of metal-oxide-semiconductor N1 (310)；The drain electrode of the P-channel metal-oxide-semiconductor P1 (309) of memory node X1 (305) connects memory node The drain electrode of the N-channel MOS pipe N1 (310) of X1 (305), the output O1 (321) as memory node X1 (305)；Memory node X1 (305) grid and memory node X4 of the P-channel metal-oxide-semiconductor P3 (311) of output O1 (321) connection memory node X3 (306) (308) grid of N-channel MOS pipe (316), the output end Q (304) of the reinforcing register as dual redundant interlocking structure；

The source electrode of the P-channel metal-oxide-semiconductor P2 (313) of memory node X2 (307) connects power supply；The N-channel of memory node X2 (307) The source electrode connection ground of metal-oxide-semiconductor N2 (314)；The drain electrode of the P-channel metal-oxide-semiconductor P2 (313) of memory node X2 (307) connects memory node The drain electrode of the N-channel MOS pipe N2 (314) of X2 (307), the output O2 (322) as memory node X2 (307)；Memory node X2 (307) grid and memory node X4 of the N-channel MOS pipe N3 (312) of output O2 (322) connection memory node X3 (306) (308) grid of P-channel metal-oxide-semiconductor (315)；

The source electrode of the P-channel metal-oxide-semiconductor P3 (311) of memory node X3 (306) connects power supply；The N-channel of memory node X3 (306) The source electrode connection ground of metal-oxide-semiconductor N3 (312)；The drain electrode of the P-channel metal-oxide-semiconductor P3 (311) of memory node X3 (306) connects memory node The drain electrode of the N-channel MOS pipe N3 (312) of X3 (306), the output O3 (323) as memory node X3 (306)；

The source electrode of the P-channel metal-oxide-semiconductor P4 (315) of memory node X4 (308) connects power supply；The N-channel of memory node X4 (308) The source electrode connection ground of metal-oxide-semiconductor N4 (316)；The drain electrode of the P-channel metal-oxide-semiconductor P4 (315) of memory node X4 (308) connects memory node The drain electrode of the N-channel MOS pipe N4 (316) of X4 (308), the output O4 (324) as memory node X4 (308)；

Data control switch (107), including six programmable switches, respectively programmable switch K5 (409), programmable switch K6 (410), programmable switch K7 (411), programmable switch K8 (412), programmable switch K9 (413), programmable switch K10 (414)；

The input terminal D1 (401) of the fixing end connection data control switch of two fixing ends in programmable switch K5 (409)； The output end Q1 (407) of another fixing end connection data control switch of two fixing ends in programmable switch K5 (409)；It can The control terminal of program switch K5 (409) is the input terminal CP1 (404) of data control switch；

The input terminal D2 (402) of the fixing end connection data control switch of two fixing ends in programmable switch K6 (410)； The output end Q1 (407) of another fixing end connection data control switch of two fixing ends in programmable switch K6 (410)；It can The control terminal of program switch K6 (410) is the input terminal CP2 (405) of data control switch；

The input terminal D3 (403) of the fixing end connection data control switch of two fixing ends in programmable switch K7 (411)； The output end Q1 (407) of another fixing end connection data control switch of two fixing ends in programmable switch K7 (411)；It can The control terminal of program switch K7 (411) is the input terminal CP3 (406) of data control switch；

The input terminal D1 (401) of the fixing end connection data control switch of two fixing ends in programmable switch K8 (412)； The output end Q2 (408) of another fixing end connection data control switch of two fixing ends in programmable switch K8 (412)；It can The control terminal of program switch K8 (412) is the input terminal CP1 (404) of data control switch；

The input terminal D2 (402) of the fixing end connection data control switch of two fixing ends in programmable switch K9 (413)； The output end Q2 (408) of another fixing end connection data control switch of two fixing ends in programmable switch K9 (413)；It can The control terminal of program switch K9 (419) is the input terminal CP2 (405) of data control switch；

The input terminal CPP (501) of the input terminal connection clock pulse generating circuit of phase inverter I4 (505), phase inverter I4's (505) Output end connects the input terminal of phase inverter I5 (506)；One of the output end connection nor gate R1 (507) of phase inverter I5 (506) Input terminal；The input terminal EN2 (503) of another input terminal connection clock pulse generating circuit of nor gate R1 (507), nor gate An input terminal of the output end connection NAND gate A1 (508) of R1 (507)；Another input terminal of NAND gate A1 (508) connects One of the output end connection NAND gate A2 (509) of the input terminal CPP (501) of clock pulse generating circuit, NAND gate A1 (508) Input terminal；The input terminal EN1 (502) of another input terminal connection clock pulse generating circuit of NAND gate A2 (509), NAND gate Output end CPW (504) of the output end of A2 (509) as clock pulse generating circuit；

The source electrode of the P-channel metal-oxide-semiconductor P5 (608) of memory node X5 (604) connects power supply；The N-channel of memory node X5 (604) The source electrode connection ground of metal-oxide-semiconductor N5 (609)；The drain electrode of the P-channel metal-oxide-semiconductor P5 (608) of memory node X5 (604) connects memory node The drain electrode of the N-channel MOS pipe N5 (609) of X5 (604), the output O5 (616) as memory node X5 (604)；Memory node X5 (604) grid and memory node X8 of the P-channel metal-oxide-semiconductor P7 (610) of output O5 (616) connection memory node X7 (605) (607) grid of N-channel MOS pipe N8 (615), the output end Q of the data holding circuit as dual redundant interlocking structure (603)；

The source electrode of the P-channel metal-oxide-semiconductor P6 (612) of memory node X6 (606) connects power supply；The N-channel of memory node X6 (606) The source electrode connection ground of metal-oxide-semiconductor N6 (613)；The drain electrode of the P-channel metal-oxide-semiconductor P6 (612) of memory node X6 (606) connects memory node The drain electrode of the N-channel MOS pipe N6 (612) of X6 (606), the output O6 (618) as memory node X6 (606)；Memory node X6 (606) grid and memory node X8 of the N-channel MOS pipe N7 (611) of output O6 (618) connection memory node X7 (605) (607) grid of P-channel metal-oxide-semiconductor P8 (614)；

The source electrode of the P-channel metal-oxide-semiconductor P7 (610) of memory node X7 (605) connects power supply；The N-channel of memory node X7 (605) The source electrode connection ground of metal-oxide-semiconductor N7 (611)；The drain electrode of the P-channel metal-oxide-semiconductor P7 (610) of memory node X7 (605) connects memory node The drain electrode of the N-channel MOS pipe N7 (611) of X7 (605), the output O7 (617) as memory node X7 (605)；Memory node X7 (605) grid, the memory node X6 of the P-channel metal-oxide-semiconductor P5 (608) of output O7 (617) connection memory node X5 (604) (606) the input terminal D2 (602) of the grid of N-channel MOS pipe N6 (613) and the data holding circuit of dual redundant interlocking structure；

The source electrode of the P-channel metal-oxide-semiconductor P8 (614) of memory node X8 (607) connects power supply；The N-channel of memory node X8 (607) The source electrode connection ground of metal-oxide-semiconductor N8 (615)；The drain electrode of the P-channel metal-oxide-semiconductor P8 (614) of memory node X8 (607) connects memory node The drain electrode of the N-channel MOS pipe N8 (615) of X8 (607), the output O8 (619) as memory node X8 (607)；Memory node X8 (607) grid, the memory node X6 of the N-channel MOS pipe N5 (609) of output O8 (619) connection memory node X5 (604) (606) the input terminal D1 (601) of the grid of P-channel metal-oxide-semiconductor P6 (612) and the data holding circuit of dual redundant interlocking structure.

10. the programmable double data rate register circuit that a kind of single-particle according to one of claim 2~9 is reinforced Control method, it is characterised in that include the following steps：

(1) when input port S3 (116) is high level, output CPP (707) and the input of third clock switch (103) CP (705) in the same direction, the output CPN (708) of third clock switch (103) and input CP (705) reversely, input port EN11 (118), EN21 (119), EN12 (120), EN22 (121) make first clock pulse generating circuit (108) and second In vain, input port EN13 (122), EN23 (123) make third clock pulse generating circuit to clock pulse generating circuit (109) (110) high level is exported always, to make entire circuit be operated in level latch pattern；

(2) when input port S3 (116) is high level, output CPP (707) and the input of third clock switch (103) CP (705) in the same direction, the output CPN (708) of third clock switch (103) and input CP (705) reversely, input port EN11 (118), EN21 (119), EN12 (120), EN22 (121) make first clock pulse generating circuit (108) and second In vain, input port EN13 (122), EN23 (123) make third clock pulse generating circuit to clock pulse generating circuit (109) (110) high impulse is exported in rising edge clock, to make entire circuit be operated in haploidy number according to rate edge triggered flip flop pattern；

(3) when input port S3 (116) is high level, output CPP (707) and the input of third clock switch (103) CP (705) in the same direction, the output CPN (708) of third clock switch (103) and input CP (705) reversely, input port S1 (114) be low level, the output CPP (203) of first clock switch (101) and input CP (201) reversely, at first Clock system switchs the output CPN (204) and input CP (201) of (101) in the same direction, and the reinforcing of third dual redundant interlocking structure is deposited Device (106) captures data in rising edge, and the reinforcing register (104) of first dual redundant interlocking structure captures number in failing edge According to input port EN12 (120), EN22 (121) make second clock pulse generating circuit (109) in vain, input port EN11 (118), EN21 (119) makes first clock pulse generating circuit (108) export high impulse, input port in clock falling edge EN13 (122), EN23 (123) make third clock pulse generating circuit (110) export high impulse in rising edge clock, to make Entire circuit is operated in instead along double data rate edge triggered flip flop pattern；

(4) when input port S3 (116) is high level, output CPP (707) and the input of third clock switch (103) CP (705) in the same direction, the output CPN (708) of third clock switch (103) and input CP (705) reversely, input terminal S1 (114) be high level, the output CPP (203) of first clock switch (101) and input CP (201) in the same direction, at first Clock system switch (101) output CPN (204) with input CP (201) reversely, input port S2 (115) be low level, second The output CPP (703) of clock switch (102) and input CP (701) reversely, second clock switch (102) it is defeated Go out CPN (703) and input CP (701) in the same direction, the reinforcing register (106) of third dual redundant interlocking structure is captured in rising edge The reinforcing register (104) of data, first dual redundant interlocking structure captures data, second dual redundant interlocking knot in rising edge The reinforcing register (105) of structure captures the data of the reinforcing register (104) of first dual redundant interlocking structure in failing edge, defeated Inbound port EN11 (118), EN21 (119) make first clock pulse generating circuit (108) in vain, input port EN12 (120), EN22 (121) makes second clock pulse generating circuit (109) export high impulse, input port EN13 in clock falling edge (122), EN23 (123) makes third clock pulse generating circuit (110) export high impulse in rising edge clock, entire to make Circuit is operated in along double data rate edge triggered flip flop pattern.