CN108334700B - Equivalent circuit of fractional order memory container - Google Patents
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Abstract
The invention relates to an equivalent circuit of a fractional order memory capacitor. The technical scheme is as follows: input current i of equivalent circuit of fractional order memcapacitora(t) obtaining the voltage value V of the equivalent circuit charge signal through the action of a first resistor (25), a second resistor (26), a first capacitor (22), a first current transmitter (1) and a first amplification module (2)02，VEAmplifying the signal by a second amplification module (4) and shifting the phase by a voltage-controlled phase shifter (19); the introduced control signal alpha is calculated by a first operation module (7), a second operation module (15) and a third operation module (17) to obtain a corresponding voltage value K1, a voltage value K2 and a voltage value K3 respectively, and an input current i of an equivalent circuit of the fractional order memcapacitor is enabled to be an input current i of the equivalent circuit of the fractional order memcapacitor through a circuit formed by a first current transmitter (1), a second current transmitter (18), a third current transmitter (20) and a first capacitor (22)a(t) and the output current ib(t) are equal. The method can accurately simulate the electrical characteristics of the fractional order memcapacitor, and has the characteristics of convenience in order adjustment, easiness in control and high precision.
Description
Technical Field
The invention belongs to the technical field of an equivalent circuit of a memory capacitor. In particular to an equivalent circuit of a fractional order memcapacitor.
Background
In 2009 professor Ventra and mauritiu et al developed the concept of Memory Elements on the basis of Memristors (Ventra M D, persin Y V, Chua L o. circuit Elements With Memory: Memristors, memcappactors, and memmicroductors [ J ]. Proceedings of the IEEE,2009,97(10):1715 + 1716), and given the relevant definitions of Memory containers and Memory sensors, the characteristics of Memory Elements have attracted the attention of more researchers.
Pershin et al, according to the conversion relationship between a memristor and a memristor, design a circuit satisfying the conversion relationship by using existing circuit components, and convert the memristor into a memristor (Pershin Y V, Ventra M D. Memrive circuits complex memories and memories [ J ]. Electronics Letters,2010,46(7):517-518), but the realized circuit is relatively simple, and only the characteristics of the memristor can be approximately realized under specific simplified conditions, and the realized memristor contains parasitic resistance, so that the memristor is not accurate enough. After Biolek et al indicate the deficiency of a memcapacitor simulation circuit designed according to the conversion relationship between a memristor and a memcapacitor, a grounded charge control memcapacitor without a parasitic resistance is designed (Biolek D, Biolkova v. transformer for transforming a memcapacitor. J. Electronics Letters,2010,46(21): 1428-1429). Then, after a circuit simulator design of a charge-control memcapacitor and its basic characteristic analysis [ J ] electronic components and materials, 2016,35(7):98-104, pointed out the disadvantages of a grounded memcapacitor, Yanling et al (Yanling, Hupeng, Sujing, etc.), an equivalent circuit of a floating memcapacitor without a memristor was designed.
The inventor of Juntong et al in 2013 invented a realization circuit and a realization method of a memory container (CN103559328A), and then the inventor of Wangzui et al invented an equivalent circuit of a magnetic control memory container (CN105373677A) and an equivalent circuit of an exponential type magnetic control memory container (CN 105701306A). The invention is a simple analog circuit of the memory capacitor realized by conventional electronic components such as a resistor, a capacitor, an operational amplifier and the like according to a definition formula of the memory capacitor, and only some basic characteristics of the memory capacitor can be simulated. Therefore, in the east rise et al, "a flux linkage coupling type memcapacitor simulation circuit" (CN104811182A), which is a memcapacitor simulator implemented by using basic circuit elements and an active chip, and whose coupling coefficient can be smoothly adjusted, can well exhibit the dynamic and steady-state characteristics of the memcapacitor. The invention is an integer order memcapacitor analog circuit with order 1, and people of terrible interest and the like invented an "implementation circuit of memcapacitor and an implementation method of memcapacitor circuit with any order" (CN104573183A), which can simulate 1 order and integer order memcapacitors with order more than 1, in order to obtain memcapacitors with order more than one, equivalent circuits of a plurality of first order memcapacitors are required to be cascaded together as basic units, the memcapacitors with different orders have different equivalent circuits, and the higher the order is, the more complex the equivalent circuits are. Therefore, the implementation of different order memos containers is cumbersome.
The equivalent circuits of the memcapacitors simulate integer-order memcapacitors. However, the actual physical system is fractional order in nature, and the integral order calculus is difficult to accurately describe the actual physical system, so that the fractional order system can be better described only by a model established by the fractional order calculus theory (Zhang Yanzhu. fractional order calculus theory and application research [ D ] [ doctor paper ] northeast university, 2008, 7-34). Fractional calculus is a new tool in dealing with non-linearity problems in circuits and systems, particularly in analyzing the non-linear characteristics of memory elements such as memcapacitors.
In recent years, researchers have proposed a Fractional Memristor model (Pu F, Yuan x, Fractional-organic Memristor [ J ]. IEEE Access,2017,4: 1872-. If the model of the memristor is not accurate enough, the characteristics of the memristor are not accurate enough.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an equivalent circuit of a fractional order memcapacitor, which can accurately simulate the electrical characteristics of the fractional order memcapacitor, is convenient to adjust the fractional order, is easy to control and has high precision.
In order to achieve the purpose, the invention adopts the technical scheme that:
two ends of the equivalent circuit of the fractional order memcapacitor are respectively a terminal A of the equivalent circuit of the fractional order memcapacitor and a terminal B of the equivalent circuit of the fractional order memcapacitor; the control signal alpha is added between a terminal C of an equivalent circuit of the fractional order memcapacitor and a terminal GND of the equivalent circuit of the fractional order memcapacitor and is used for changing the order of the fractional order memcapacitor.
The terminal a of the equivalent circuit of the fractional order memcapacitor is connected with the terminal E1+ of the first current conveyor, the terminal Fi of the frequency/voltage converter and the terminal C12 of the first capacitor, respectively.
Terminal B of the equivalent circuit of the fractional order memcapacitor is connected to terminal E2-of the second current conveyor.
The terminal E1-of the first current conveyor is connected with the terminal R22 of the second resistor, the terminal E1i of the first current conveyor is respectively connected with the terminal R12 of the first resistor and the terminal W21 of the second amplifying module, and the terminal W22 of the second amplifying module is connected with the terminal phi 0 of the voltage-controlled phase shifter; the terminal E1o of the first current conveyor is connected to the terminal W11 of the first amplification block, the terminal W12 of the first amplification block is connected to the terminal X1 of the first multiplier, and the terminal Y1 of the first multiplier is connected to the terminal U0 of the voltage source.
The terminal P1 of the first multiplier is connected to the terminal X2 of the second multiplier, the terminal X5 of the fifth multiplier and the terminal B3 of the third adder, respectively, the terminal Y2 of the second multiplier is connected to the terminal K12 of the first arithmetic module, the terminal P2 of the second multiplier is connected to the terminal a1 of the first adder and the terminal X3 of the third multiplier, the terminal B1 of the first adder is connected to the terminal P3 of the third multiplier, the terminal S1 of the first adder is connected to the terminal X4 of the fourth multiplier, the terminal Y4 of the fourth multiplier is connected to the terminal Φ 2 of the voltage-controlled phase shifter, and the terminal P4 of the fourth multiplier is connected to the terminal a2 of the second adder; the terminal B2 of the second adder is connected to the terminal P5 of the fifth multiplier, and the terminal Y5 of the fifth multiplier is connected to the terminal K32 of the third arithmetic block.
The terminal S2 of the second adder is connected to the terminal X6 of the sixth multiplier, the terminal Y6 of the sixth multiplier is connected to the terminal K22 of the second arithmetic block, and the terminal P6 of the sixth multiplier is connected to the terminal A3 of the third adder; the terminal S3 of the third adder is connected to the terminal Hi of the analog inverter, the terminal Ho of the analog inverter is connected to the terminal E2+ of the second current conveyor, the terminal E2i of the second current conveyor is connected to the terminal E3i of the third current conveyor, and the terminal E3-of the third current conveyor is connected to the terminal C11 of the first capacitor.
The terminal Vo of the frequency/voltage converter is connected to the terminal K41 of the fourth operational block, the terminal K42 of the fourth operational block is connected to the terminal X7 of the seventh multiplier, and the terminal P7 of the seventh multiplier is connected to the terminal Y3 of the third multiplier.
The terminal C of the equivalent circuit of the fractional order memcapacitor is connected with the terminal K11 of the first operation module, the terminal K21 of the second operation module, the terminal K31 of the third operation module, the terminal Φ 1 of the voltage-controlled phase shifter and the terminal Y7 of the seventh multiplier respectively.
The terminal GND of the equivalent circuit of the fractional order memcapacitor is connected to the terminal E3+ of the third current conveyor, the terminal R21 of the second resistor, and the terminal R11 of the first resistor, respectively.
Capacitance value C of equivalent circuit of fractional order memory containerM：
DM＝D1+D2{1+K2[K3+K1(Fα+1)WR1Isin(2πft-π/2α)]} (2)
Formula (1) formula (2): dMA containment value representing an equivalent circuit of a fractional order memcapacitor;
D1representing a contained value of the first capacitance;
D2representing a voltage output value of a voltage source;
i denotes the input current Ia(t) magnitude;
K1the voltage output value of the first operation module is represented;
K2the voltage output value of the second operation module is represented;
K3the voltage output value of the third operation module is represented;
f represents the voltage output value of the fourth operation module;
w represents the voltage amplification factor of the second amplification module;
R1a resistance value representing a first resistance;
f denotes the input current ia(t) frequency value;
t represents a time value in seconds;
alpha represents the fractional order of the memcapacitor, which is equal to the voltage value of the control signal.
The first amplification module is composed of a third resistor, a fourth resistor, a first operational amplifier, a fifth resistor, a sixth resistor and a second operational amplifier.
The terminal R32 of the third resistor is connected to the terminal R41 of the fourth resistor and the terminal V1 of the first operational amplifier, respectively, the terminal V1o of the first operational amplifier is connected to the terminal R42 of the fourth resistor and the terminal R51 of the fifth resistor, respectively, and the terminal R52 of the fifth resistor is connected to the terminal R61 of the sixth resistor and the terminal V2 of the second operational amplifier, respectively; the terminal V2+ of the second operational amplifier and the terminal V1+ of the first operational amplifier are connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
The two ends of the first amplification block are a terminal W11 and a terminal W12, the terminal R31 of the third resistor is connected to the terminal W11 of the first amplification block, and the terminal R62 of the sixth resistor and the terminal V2o of the second operational amplifier are connected to the terminal W12 of the first amplification block.
The second amplification module is composed of a seventh resistor, an eighth resistor, a third operational amplifier, a ninth resistor, a tenth resistor and a fourth operational amplifier.
The terminal R72 of the seventh resistor is connected to the terminal R81 of the eighth resistor and the terminal V3 of the third operational amplifier, respectively, the terminal V3o of the third operational amplifier is connected to the terminal R82 of the eighth resistor and the terminal R91 of the ninth resistor, respectively, and the terminal R92 of the ninth resistor is connected to the terminal R101 of the tenth resistor and the terminal V4 of the fourth operational amplifier, respectively; the terminal V3+ of the third operational amplifier and the terminal V4+ of the fourth operational amplifier are connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
The second amplification block has terminals W21 and W22 at its two ends, a terminal R71 of the seventh resistor is connected to a terminal W21 of the second amplification block, and a terminal R102 of the tenth resistor and a terminal V4o of the fourth operational amplifier are connected to a terminal W22 of the second amplification block.
The first operation module is composed of a 1.2V power supply, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fifth operation amplifier and a fourteenth resistor.
The terminal R142 of the fourteenth resistor is connected to the terminal R131 of the thirteenth resistor and the terminal V5-of the fifth operational amplifier, respectively, the terminal V5+ of the fifth operational amplifier is connected to the terminal R112 of the eleventh resistor and the terminal R121 of the twelfth resistor, respectively, and the terminal R111 of the eleventh resistor is connected to the terminal U1 of the 1.2V power supply; the terminal R122 of the twelfth resistor is connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
The first operational block has terminals K11 and K12 at its two ends, a terminal R141 of the fourteenth resistor is connected to a terminal K11 of the first operational block, and a terminal V5o of the fifth operational amplifier and a terminal R132 of the thirteenth resistor are connected to a terminal K12 of the first operational block.
The second operational module consists of a fifteenth resistor, a sixth operational amplifier, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a seventh operational amplifier, a twentieth resistor, a-1V power supply and a sixteenth resistor.
The terminal R152 of the fifteenth resistor is connected to the terminal R161 of the sixteenth resistor and the terminal V6-of the sixth operational amplifier, respectively, the terminal V6o of the sixth operational amplifier is connected to the terminal R162 of the sixteenth resistor and the terminal R171 of the seventeenth resistor, the terminal R172 of the seventeenth resistor is connected to the terminal R181 of the eighteenth resistor and the terminal V7+ of the seventh operational amplifier, respectively, the terminal V7-of the seventh operational amplifier is connected to the terminal R191 of the nineteenth resistor and the terminal R202 of the twentieth resistor, respectively, and the terminal R201 of the twentieth resistor is connected to the terminal U2 of the-1V power supply; the terminal V6+ of the sixth operational amplifier and the terminal R182 of the eighteenth resistor are connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
The second operational block has terminals K21 and K22 at its two ends, a terminal R151 of the fifteenth resistor is connected to a terminal K21 of the second operational block, and a terminal R192 of the nineteenth resistor and a terminal V7o of the seventh operational amplifier are connected to a terminal K22 of the second operational block.
The third operational module is composed of a twenty-first resistor, an eighth operational amplifier, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a ninth operational amplifier, a twenty-sixth resistor, a 0.5V power supply and a twenty-second resistor.
The terminal R212 of the twenty-first resistor is respectively connected with the terminal R221 of the twenty-second resistor and the terminal V8-of the eighth operational amplifier, the terminal V8o of the eighth operational amplifier is respectively connected with the terminal R222 of the twenty-second resistor and the terminal R231 of the twenty-third resistor, the terminal R232 of the twenty-third resistor is respectively connected with the terminal R241 of the twenty-fourth resistor and the terminal V9+ of the ninth operational amplifier, the terminal V9-of the ninth operational amplifier is respectively connected with the terminal R251 of the twenty-fifth resistor and the terminal R262 of the twenty-sixth resistor, and the terminal R261 of the twenty-sixth resistor is connected with the terminal U3 of the 0.5V power supply; the terminal V8+ of the eighth operational amplifier and the terminal R242 of the twenty-fourth resistor are connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
The third operational module has terminals K31 and K32 at its two ends, a terminal R211 of the twenty-first resistor is connected to a terminal K31 of the third operational module, and a terminal R252 of the twenty-fifth resistor and a terminal V9o of the ninth operational amplifier are connected to a terminal K32 of the third operational module.
The fourth operational module is composed of a twenty-seventh resistor, a twenty-eighth resistor, a tenth operational amplifier, a thirty-first resistor, an eleventh operational amplifier, a thirty-second resistor, a thirty-third resistor, a twenty-ninth resistor and a 1V power supply.
A terminal R272 of the twenty-seventh resistor is respectively connected with a terminal R281 of the twenty-eighth resistor and a terminal V10+ of the tenth operational amplifier, a terminal V10-of the tenth operational amplifier is respectively connected with a terminal R301 of the thirty-fifth resistor and a terminal R292 of the twenty-ninth resistor, and a terminal R291 of the twenty-ninth resistor is connected with a terminal U4 of the 1V power supply; the terminal V10o of the tenth operational amplifier is connected to the terminal R302 of the thirtieth resistor and the terminal R311 of the thirty-first resistor, respectively, and the terminal R312 of the thirty-first resistor is connected to the terminal V11-of the eleventh operational amplifier and the terminal R321 of the thirty-second resistor, respectively; the terminal V11+ of the eleventh operational amplifier and the terminal R282 of the twenty-eighth resistor are connected to the terminal GND of the equivalent circuit of the fractional-order memcapacitor.
The fourth operational block has terminals K41 and K42 at its two ends, a terminal R271 of the twenty-seventh resistor is connected to a terminal K41 of the fourth operational block, and a terminal R322 of the thirty-second resistor and a terminal V11o of the eleventh operational amplifier are connected to a terminal K42 of the fourth operational block.
The analog inverter is composed of a thirty-third resistor, a thirty-fourth resistor and a twelfth operational amplifier.
The terminal R332 of the thirty-third resistor is connected to the terminal R341 of the thirty-fourth resistor and the terminal V12 ″ -of the twelfth operational amplifier, and the terminal V12+ of the twelfth operational amplifier is connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
The two ends of the analog inverter are a terminal Hi and a terminal Ho, a terminal R331 of the thirty-third resistor is connected to the terminal Hi of the analog inverter, and a terminal R342 of the thirty-fourth resistor and a terminal V12o of the twelfth operational amplifier are connected to the terminal Ho of the analog inverter.
The voltage-controlled phase shifter is composed of a first junction field effect transistor, a third capacitor, a thirty-fifth resistor, a thirteenth operational amplifier, a thirty-sixth resistor, a thirty-seventh resistor, a thirty-eighth resistor, a second junction field effect transistor and a second capacitor.
The terminal G13 of the first junction field effect transistor is connected to the terminal C31 of the third capacitor and the terminal R351 of the thirty-fifth resistor, the terminal R352 of the thirty-fifth resistor is connected to the terminal V13+ of the thirteenth operational amplifier and the terminal R361 of the thirty-sixth resistor, the terminal C22 of the second capacitor is connected to the terminal G21 of the second junction field effect transistor and the terminal R381 of the thirty-eighth resistor, and the terminal R382 of the thirty-eighth resistor is connected to the terminal V13-of the thirteenth operational amplifier and the terminal R of the thirty-seventh resistor.
The terminal GND of the equivalent circuit of the fractional order memcapacitor is connected to the terminal C32 of the third capacitor, the terminal G23 of the second junction field effect transistor, and the terminal R362 of the thirty-sixth resistor, respectively.
The voltage-controlled phase shifter is respectively provided with a terminal phi 0, a terminal phi 1 and a terminal phi 2; the terminal G11 of the first junction field effect transistor and the terminal C21 of the second capacitor are connected to the terminal Φ 0 of the voltage-controlled phase shifter, the terminal G12 of the first junction field effect transistor and the terminal G22 of the second junction field effect transistor are connected to the terminal Φ 1 of the voltage-controlled phase shifter, and the terminal V13o of the thirteenth operational amplifier and the terminal R372 of the thirty-seventh resistor are connected to the terminal Φ 2 of the voltage-controlled phase shifter.
Due to the adoption of the technical scheme, the invention has the following positive effects:
input current i of the inventiona(t) obtaining the voltage value V of the equivalent circuit charge signal through the action of a first resistor, a second resistor, a first capacitor, a first current transmitter and a first amplification module02，VEAmplifying the phase signal by a second amplifying module and shifting the phase of the voltage-controlled phase shifter; the introduced control signal alpha is respectively obtained through the operation of a first operation module, a second operation module and a third operation module to obtain a corresponding voltage value K1, a voltage value K2 and a voltage value K3, and a circuit formed by a first current transmitter, a second current transmitter, a third current transmitter and a first capacitor enables the input current i of an equivalent circuit of the fractional order memcapacitor to be inputa(t) and the output current ibAnd (t) are equal, the method can accurately simulate the electrical characteristics of the fractional order memcapacitor.
According to the invention, a control signal alpha is introduced into the circuit, so that the fractional order of the equivalent circuit of the fractional order memcapacitor is changed along with the change of the control signal alpha, the electrical characteristics of the fractional order memcapacitor are changed, the electrical characteristics of the fractional order memcapacitor can be conveniently simulated by the equivalent circuit, and the adjustment of the order can be completed only by changing the size of the control signal alpha.
The resistor, the capacitor and the control signal alpha adopted by the invention have high precision, and the frequency of the input signal can be accurately detected.
Therefore, the method can accurately simulate the electrical characteristics of the fractional order memcapacitor, and has the characteristics of convenience in order adjustment, easiness in control and high precision.
Drawings
FIG. 1 is a schematic diagram of an embodiment of the present invention;
fig. 2 is a schematic structural diagram of the first amplification module 2 in fig. 1;
fig. 3 is a schematic structural diagram of the second amplification module 4 in fig. 1;
fig. 4 is a schematic structural diagram of the first operation module 7 in fig. 1;
FIG. 5 is a schematic structural diagram of the second operation module 15 in FIG. 1;
FIG. 6 is a schematic structural diagram of the third operation module 17 in FIG. 1;
FIG. 7 is a schematic structural diagram of the fourth operation module 23 in FIG. 1;
fig. 8 is a schematic diagram of the structure of the analog inverter 16 in fig. 1.
Fig. 9 is a schematic diagram of the structure of voltage-controlled shifter 19 in fig. 1.
Detailed Description
The invention is further described with reference to the following figures and detailed description, without limiting the scope of the invention.
Example 1
An equivalent circuit of a fractional order memcapacitor. As shown in fig. 1: two ends of the equivalent circuit of the fractional order memcapacitor are respectively a terminal A of the equivalent circuit of the fractional order memcapacitor and a terminal B of the equivalent circuit of the fractional order memcapacitor; the control signal alpha is added between a terminal C of an equivalent circuit of the fractional order memcapacitor and a terminal GND of the equivalent circuit of the fractional order memcapacitor and is used for changing the order of the fractional order memcapacitor.
As shown in fig. 1: the terminal a of the equivalent circuit of the fractional order memcapacitor is connected to the terminal E1+ of the first current conveyor 1, the terminal Fi of the frequency/voltage converter 24 and the terminal C12 of the first capacitor 22, respectively.
As shown in fig. 1: terminal B of the equivalent circuit of the fractional order memcapacitor is connected to terminal E2-of the second current conveyor 18.
As shown in fig. 1: the terminal E1-of the first current conveyor 1 is connected to the terminal R22 of the second resistor 26, the terminal E1i of the first current conveyor 1 is connected to the terminal R12 of the first resistor 25 and the terminal W21 of the second amplification module 4, respectively, and the terminal W22 of the second amplification module 4 is connected to the terminal Φ 0 of the voltage-controlled phase shifter 19; the terminal E1o of the first current conveyor 1 is connected to the terminal W11 of the first amplification block 2, the terminal W12 of the first amplification block 2 is connected to the terminal X1 of the first multiplier 3, and the terminal Y1 of the first multiplier 3 is connected to the terminal U0 of the voltage source 5.
As shown in fig. 1: the terminal P1 of the first multiplier 3 is connected to the terminal X2 of the second multiplier 6, the terminal X5 of the fifth multiplier 12, and the terminal B3 of the third adder 14, the terminal Y2 of the second multiplier 6 is connected to the terminal K12 of the first arithmetic module 7, the terminal P2 of the second multiplier 6 is connected to the terminal a1 of the first adder 8 and the terminal X3 of the third multiplier 9, the terminal B1 of the first adder 8 is connected to the terminal P3 of the third multiplier 9, the terminal S1 of the first adder 8 is connected to the terminal X4 of the fourth multiplier 10, the terminal Y4 of the fourth multiplier 10 is connected to the terminal Φ 2 of the voltage-controlled phase shifter 19, and the terminal P4 of the fourth multiplier 10 is connected to the terminal a2 of the second adder 11), respectively; the terminal B2 of the second adder 11 is connected to the terminal P5 of the fifth multiplier 12, and the terminal Y5 of the fifth multiplier 12 is connected to the terminal K32 of the third operational block 17.
As shown in fig. 1: the terminal S2 of the second adder 11 is connected to the terminal X6 of the sixth multiplier 13, the terminal Y6 of the sixth multiplier 13 is connected to the terminal K22 of the second arithmetic block 15, and the terminal P6 of the sixth multiplier 13 is connected to the terminal A3 of the third adder 14; the terminal S3 of the third adder 14 is connected to the terminal Hi of the analog inverter 16, the terminal Ho of the analog inverter 16 is connected to the terminal E2+ of the second current conveyor 18, the terminal E2i of the second current conveyor 18 is connected to the terminal E3i of the third current conveyor 20, and the terminal E3-of the third current conveyor 20 is connected to the terminal C11 of the first capacitor 22.
As shown in fig. 1: the terminal Vo of the frequency/voltage converter 24 is connected to the terminal K41 of the fourth operational block 23, the terminal K42 of the fourth operational block 23 is connected to the terminal X7 of the seventh multiplier 21, and the terminal P7 of the seventh multiplier 21 is connected to the terminal Y3 of the third multiplier 9.
As shown in fig. 1: the terminal C of the equivalent circuit of the fractional order memcapacitor is connected to the terminal K11 of the first operation module 7, the terminal K21 of the second operation module 15, the terminal K31 of the third operation module 17, the terminal Φ 1 of the voltage-controlled phase shifter 19, and the terminal Y7 of the seventh multiplier 21, respectively.
As shown in fig. 1: the terminal GND of the equivalent circuit of the fractional order memcapacitor is connected to the terminal E3+ of the third current conveyor 20, the terminal R21 of the second resistor 26, and the terminal R11 of the first resistor 25, respectively.
As shown in fig. 2: the first amplifying module 2 is composed of a third resistor 27, a fourth resistor 28, a first operational amplifier 29, a fifth resistor 30, a sixth resistor 31 and a second operational amplifier 32.
As shown in fig. 2: the terminal R32 of the third resistor 27 is connected to the terminal R41 of the fourth resistor 28 and the terminal V1 of the first operational amplifier 29, respectively, the terminal V1o of the first operational amplifier 29 is connected to the terminal R42 of the fourth resistor 28 and the terminal R51 of the fifth resistor 30, respectively, and the terminal R52 of the fifth resistor 30 is connected to the terminal R61 of the sixth resistor 31 and the terminal V2 of the second operational amplifier 32, respectively; the terminal V2+ of the second operational amplifier 32 and the terminal V1+ of the first operational amplifier 29 are connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
As shown in fig. 2: the first amplification block 2 has terminals W11 and W12 at its two ends, the terminal R31 of the third resistor 27 is connected to the terminal W11 of the first amplification block 2, and the terminal R62 of the sixth resistor 31 and the terminal V2o of the second operational amplifier 32 are connected to the terminal W12 of the first amplification block 2.
As shown in fig. 3: the second amplifying module 4 is composed of a seventh resistor 33, an eighth resistor 34, a third operational amplifier 35, a ninth resistor 36, a tenth resistor 37 and a fourth operational amplifier 38.
As shown in fig. 3: the terminal R72 of the seventh resistor 33 is connected to the terminal R81 of the eighth resistor 34 and the terminal V3 of the third operational amplifier 35, respectively, the terminal V3o of the third operational amplifier 35 is connected to the terminal R82 of the eighth resistor 34 and the terminal R91 of the ninth resistor 36, respectively, and the terminal R92 of the ninth resistor 36 is connected to the terminal R101 of the tenth resistor 37 and the terminal V4 of the fourth operational amplifier 38, respectively; the terminal V3+ of the third operational amplifier 35 and the terminal V4+ of the fourth operational amplifier 38 are connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
As shown in fig. 3: the second amplification block 4 has terminals W21 and W22 at its two ends, a terminal R71 of the seventh resistor 33 is connected to a terminal W21 of the second amplification block 4, and a terminal R102 of the tenth resistor 37 and a terminal V4o of the fourth operational amplifier 38 are connected to a terminal W22 of the second amplification block 4.
As shown in fig. 4: the first operation module 7 is composed of a 1.2V power supply 39, an eleventh resistor 40, a twelfth resistor 41, a thirteenth resistor 42, a fifth operation amplifier 43 and a fourteenth resistor 44.
As shown in fig. 4: the terminal R142 of the fourteenth resistor 44 is connected to the terminal R131 of the thirteenth resistor 42 and the terminal V5-of the fifth operational amplifier 43, respectively, the terminal V5+ of the fifth operational amplifier 43 is connected to the terminal R112 of the eleventh resistor 40 and the terminal R121 of the twelfth resistor 41, respectively, and the terminal R111 of the eleventh resistor 40 is connected to the terminal U1 of the 1.2V power supply 39; the terminal R122 of the twelfth resistor 41 is connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
As shown in fig. 4: the first operational block 7 has terminals K11 and K12 at its two ends, a terminal R141 of the fourteenth resistor 44 is connected to a terminal K11 of the first operational block 7, and a terminal V5o of the fifth operational amplifier 43 and a terminal R132 of the thirteenth resistor 42 are connected to a terminal K12 of the first operational block 7.
As shown in fig. 5: the second operational module 15 is composed of a fifteenth resistor 45, a sixth operational amplifier 46, a seventeenth resistor 47, an eighteenth resistor 48, a nineteenth resistor 49, a seventh operational amplifier 50, a twentieth resistor 51, a-1V power supply 52 and a sixteenth resistor 53.
As shown in fig. 5: the terminal R152 of the fifteenth resistor 45 is connected to the terminal R161 of the sixteenth resistor 53 and the terminal V6-of the sixth operational amplifier 46, respectively, the terminal V6o of the sixth operational amplifier 46 is connected to the terminal R162 of the sixteenth resistor 53 and the terminal R171 of the seventeenth resistor 47, the terminal R172 of the seventeenth resistor 47 is connected to the terminal R181 of the eighteenth resistor 48 and the terminal V7+ of the seventh operational amplifier 50, respectively, the terminal V7-of the seventh operational amplifier 50 is connected to the terminal R191 of the nineteenth resistor 49 and the terminal R202 of the twentieth resistor 51, respectively, and the terminal R201 of the twentieth resistor 51 is connected to the terminal U2 of the-1V power supply 52; the terminal V6+ of the sixth operational amplifier 46 and the terminal R182 of the eighteenth resistor 48 are connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
As shown in fig. 5: the second operational block 15 has terminals K21 and K22 at its both ends, a terminal R151 of the fifteenth resistor 45 is connected to a terminal K21 of the second operational block 15, and a terminal R192 of the nineteenth resistor 49 and a terminal V7o of the seventh operational amplifier 50 are connected to a terminal K22 of the second operational block 15.
As shown in fig. 6: the third operational module 17 is composed of a twenty-first resistor 54, an eighth operational amplifier 55, a twenty-third resistor 56, a twenty-fourth resistor 57, a twenty-fifth resistor 58, a ninth operational amplifier 59, a twenty-sixth resistor 60, a 0.5V power supply 61 and a twenty-second resistor 62.
As shown in fig. 6: the terminal R212 of the twenty-first resistor 54 is connected to the terminal R221 of the twenty-second resistor 62 and the terminal V8-of the eighth operational amplifier 55, respectively, the terminal V8o of the eighth operational amplifier 55 is connected to the terminal R222 of the twenty-second resistor 62 and the terminal R231 of the twenty-third resistor 56, respectively, the terminal R232 of the twenty-third resistor 56 is connected to the terminal R241 of the twenty-fourth resistor 57 and the terminal V9+ of the ninth operational amplifier 59, the terminal V9-of the ninth operational amplifier 59 is connected to the terminal R251 of the twenty-fifth resistor 58 and the terminal R262 of the twenty-sixth resistor 60, respectively, and the terminal R261 of the twenty-sixth resistor 60 is connected to the terminal U3 of the 0.5V power supply 61; the terminal V8+ of the eighth operational amplifier 55 and the terminal R242 of the twenty-fourth resistor 57 are connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
As shown in fig. 6: the third operational block 17 has terminals K31 and K32 at its both ends, the terminal R211 of the twenty-first resistor 54 is connected to the terminal K31 of the third operational block 17, and the terminal R252 of the twenty-fifth resistor 58 and the terminal V9o of the ninth operational amplifier 59 are connected to the terminal K32 of the third operational block 17.
As shown in fig. 7: the fourth operational module 23 is composed of a twenty-seventh resistor 63, a twenty-eighth resistor 64, a tenth operational amplifier 65, a thirty-first resistor 66, an eleventh operational amplifier 67, a thirty-second resistor 68, a thirty-first resistor 69, a twenty-ninth resistor 70 and a 1V power supply 71.
As shown in fig. 7: a terminal R272 of the twenty-seventh resistor 63 is respectively connected with a terminal R281 of the twenty-eighth resistor 64 and a terminal V10+ of the tenth operational amplifier 65, a terminal V10-of the tenth operational amplifier 65 is respectively connected with a terminal R301 of the thirty-eighth resistor 69 and a terminal R292 of the twenty-ninth resistor 70, and a terminal R291 of the twenty-ninth resistor 70 is connected with a terminal U4 of the 1V power supply 71; the terminal V10o of the tenth operational amplifier 65 is connected to the terminal R302 of the thirtieth resistor 69 and the terminal R311 of the thirty-first resistor 66, respectively, and the terminal R312 of the thirty-first resistor 66 is connected to the terminals V11-of the eleventh operational amplifier 67 and the terminal R321 of the thirty-second resistor 68, respectively; the terminal V11+ of the eleventh operational amplifier 67 and the terminal R282 of the twenty-eighth resistor 64 are connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
As shown in fig. 7: the fourth operational block 23 has terminals K41 and K42 at its two ends, a terminal R271 of the twenty-seventh resistor 63 is connected to a terminal K41 of the fourth operational block 23, and a terminal R322 of the thirty-second resistor 68 and a terminal V11o of the eleventh operational amplifier 67 are connected to a terminal K42 of the fourth operational block 23.
As shown in fig. 8: the analog inverter 16 is composed of a thirty-third resistor 72, a thirty-fourth resistor 73, and a twelfth operational amplifier 74.
As shown in fig. 8: the terminal R332 of the thirty-third resistor 72 is connected to the terminal R341 of the thirty-fourth resistor 73 and the terminal V12 ″ -of the twelfth operational amplifier 74, and the terminal V12+ of the twelfth operational amplifier 74 is connected to the terminal GND of the equivalent circuit of the fractional order memcapacitor.
As shown in fig. 8: the two ends of the analog inverter 16 are a terminal Hi and a terminal Ho, the terminal R331 of the thirty-third resistor 72 is connected to the terminal Hi of the analog inverter 16, and the terminal R342 of the thirty-fourth resistor 73 and the terminal V12o of the twelfth operational amplifier 74 are connected to the terminal Ho of the analog inverter 16.
As shown in fig. 9: the voltage-controlled phase shifter 19 is composed of a first junction field effect transistor 75, a third capacitor 76, a thirty-fifth resistor 77, a thirteenth operational amplifier 78, a thirty-sixth resistor 79, a thirty-seventh resistor 80, a thirty-eighth resistor 81, a second junction field effect transistor 82 and a second capacitor 83.
As shown in fig. 9: a terminal G13 of the first junction field effect transistor 75 is connected to a terminal C31 of the third capacitor 76 and a terminal R351 of the thirty-fifth resistor 77, respectively, a terminal R352 of the thirty-fifth resistor 77 is connected to a terminal V13+ of the thirteenth operational amplifier 78 and a terminal R361 of the thirty-sixth resistor 79, respectively, a terminal C22 of the second capacitor 83 is connected to a terminal G21 of the second junction field effect transistor 82 and a terminal R381 of the thirty-eighth resistor 81, respectively, and a terminal R382 of the thirty-eighth resistor 81 is connected to a terminal V13-of the thirteenth operational amplifier 78 and a terminal R371 of the thirty-seventh resistor 80, respectively;
as shown in fig. 9: the terminal GND of the equivalent circuit of the fractional order memcapacitor is connected to the terminal C32 of the third capacitor 76, the terminal G23 of the second junction field effect transistor 82, and the terminal R362 of the thirty-sixth resistor 79, respectively.
As shown in fig. 9: the voltage-controlled phase shifter 19 is respectively provided with a terminal phi 0, a terminal phi 1 and a terminal phi 2; the terminal G11 of the first junction field effect transistor 75 and the terminal C21 of the second capacitor 83 are connected to the terminal Φ 0 of the voltage-controlled phase shifter 19, the terminal G12 of the first junction field effect transistor 75 and the terminal G22 of the second junction field effect transistor 82 are connected to the terminal Φ 1 of the voltage-controlled phase shifter 19, and the terminal V13o of the thirteenth operational amplifier 78 and the terminal R372 of the thirty-seventh resistor 80 are connected to the terminal Φ 2 of the voltage-controlled phase shifter 19.
In this embodiment: input current i of terminal A of equivalent circuit of fractional order memcapacitoraAnd (t) Isin (2 pi ft), wherein a control signal alpha is added between a terminal C of the equivalent circuit of the fractional order memcapacitor and a terminal GND of the equivalent circuit of the fractional order memcapacitor to change the order of the fractional order memcapacitor. Under the action of the first capacitor 22, the second current transmitter 18 and the third current transmitter 20, the terminal B of the equivalent circuit of the fractional order memcapacitor outputs a current ib (t) Isin (2 pi ft), and the voltage across the equivalent circuit of the fractional order memcapacitor is V (t) Va-Vb。
As can be seen from the characteristics of the current conveyor, the first resistor 25, the second resistor 26, the first capacitor 22 and the first current conveyor 1 together realize integral ^ i integral of the input current ia (t)a(t) dt ═ q (t), when the resistance value R of the first resistor 25 is exceeded1And the resistance R of the second resistor 262Equal capacitance value C of the first capacitor 221And a tolerance value of D1At the same time, the voltage V output from the terminal E1o of the first current conveyor 101Of terminal E1+ of the first current conveyor 1Voltage VE1+Voltage V at terminal a of equivalent circuit of fractional order memcapacitoraSatisfies the following conditions:
V01＝VE1+＝Va＝1/C1∫ia(t)dt＝D1q(t) (1)
voltage output value V of terminal W12 of first amplification block 202Comprises the following steps:
V02＝q(t) (2)
when the output voltage value of the voltage source 5 is D2The voltage output value V of the terminal P1 of the first multiplier 3P1Comprises the following steps:
VP1＝D2q(t) (3)
the voltage output value V of terminal P2 of the second multiplier 6P2Comprises the following steps:
VP2＝D2q(t)K1 (4)
voltage output value V of terminal P7 of seventh multiplier 21P7Comprises the following steps:
VP7＝Fα (5)
the voltage output value V of terminal P3 of the third multiplier 9P3Comprises the following steps:
VP3＝D2q(t)K1Fα (6)
the voltage output value V of the terminal S1 of the first adder 8S1Comprises the following steps:
VS1＝D2q(t)K1(Fα+1) (7)
voltage output value V of terminal Φ 2 of voltage-controlled phase shifter 1903Comprises the following steps:
V03＝WR1I sin(2πft-π/2α) (8)
the voltage output value V of terminal P4 of the fourth multiplier 10P4Comprises the following steps:
VP4＝D2q(t)K1(Fα+1)WR1I sin(2πft-π/2α) (9)
the voltage output value V of the terminal P5 of the fifth multiplier 12P5Comprises the following steps:
VP5＝D2q(t)K3 (10)
second addingVoltage output value V of terminal S2 of normal device 11S2Comprises the following steps:
VS2＝D2q(t)[K3+K1(Fα+1)WR1I sin(2πft-π/2α)] (11)
voltage output value V of terminal P6 of sixth multiplier 13P6Comprises the following steps:
VP6＝D2q(t)K2[K3+K1(Fα+1)WR1I sin(2πft-π/2α)] (12)
the voltage output value V of the terminal S3 of the third adder 14S3Comprises the following steps:
VS3＝D2q(t){1+K2[K3+K1(Fα+1)WR1I sin(2πft-π/2α)]} (13)
the voltage input value V corresponding to the terminal E2+ of the second current conveyor 18 and the terminal E2-of the second current conveyor 18 can be obtained by the characteristics of the current conveyorsE2+And a voltage output value VE2-Satisfies the following conditions:
VE2-＝VE2+＝-D2q(t){1+K2[K3+K1(Fα+1)WR1I sin(2πft-π/2α)]} (14)
voltage output value V of terminal B of equivalent circuit of fractional order memcapacitorbComprises the following steps:
Vb＝VE2-＝-D2q(t){1+K2[K3+K1(Fα+1)WR1I sin(2πft-π/2α)]} (15)
therefore, the voltage v (t) across the equivalent circuit of the fractional order memcapacitor is:
v(t)＝Va-Vb＝D1q(t)+D2q(t){1+K2[K3+K1(Fα+1)WR1I sin(2πft-π/2α)]} (16)
the voltage across the equivalent circuit of the fractional order memcapacitor satisfies v (t) DMq (t), the capacitance C of the equivalent circuit of the fractional order memory capacitorM：
DM＝D1+D2{1+K2[K3+K1(Fα+1)WR1Isin(2πft-π/2α)]} (18)
Formula (17) formula (18): dMA containment value representing an equivalent circuit of a fractional order memcapacitor;
D1represents the accommodated value of the first capacitance 22;
D2represents the voltage output value of the voltage source 5;
i represents the amplitude of the input current I (t);
K1represents the voltage output value of the first arithmetic block 7;
K2represents a voltage output value of the second operation module 15;
K3represents a voltage output value of the third operation block 17;
f represents a voltage output value of the fourth operation module 23;
w represents the voltage amplification of the second amplification module 4;
R1represents the resistance value of the first resistor 25;
f represents the frequency value of the input current i (t);
t represents a time value in seconds;
alpha represents the fractional order of the memcapacitor, which is equal to the voltage value of the control signal.
In this embodiment: the voltage output value K of the first operation module 7 is obtained after the introduced control signal alpha is operated by the first operation module 711.2- α; the introduced control signal alpha is calculated by the second operation module 15 to obtain the voltage output value K of the second operation module 1521-0.5 α; the introduced control signal alpha is calculated by the third operation module 17 to obtain the voltage output value K of the third operation module 173＝-0.25α-0.5；
In this embodiment: input current ia(t) obtaining the voltage output of the fourth operation module 23 by the operation of the frequency/voltage converter 24 and the fourth operation module 23The value F ═ 19 (1-F); the voltage amplification factor W of the second amplification module 4 is 10R1。
Then the value D accommodated by equation 18 for this embodimentM：
DM＝D1+D2{1+(1-0.5α)[(-0.25α-0.5) +(1.2-α)(1+1/9(1-f)α)10Isin(2πft-π/2α)]}
As can be seen, the equivalent circuit of the fractional order memcapacitor of the present embodiment is a fractional order memcapacitor.
Compared with the prior art, the specific implementation mode has the following positive effects:
input current i of the present embodimenta(t) obtaining the voltage value V of the equivalent circuit charge signal through the action of the first resistor 25, the second resistor 26, the first capacitor 22, the first current transmitter 1 and the first amplifying module 202，VEAmplifying the phase signal by a second amplifying module 4 and shifting the phase by a voltage-controlled phase shifter 19; the introduced control signal alpha is calculated by the first operation module 7, the second operation module 15 and the third operation module 17 to obtain a corresponding voltage value K1, a voltage value K2 and a voltage value K3 respectively, and an input current i of an equivalent circuit of the fractional order memcapacitor is enabled to be generated by a circuit formed by the first current transmitter 1, the second current transmitter 18, the third current transmitter 20 and the first capacitor 22a(t) and the output current ibAnd (t) are equal, and the electric characteristics of the fractional order memcapacitor can be accurately simulated by the specific implementation mode.
In the specific embodiment, a control signal alpha is introduced into the circuit, so that the fractional order of the equivalent circuit of the fractional order memcapacitor is changed along with the change of the control signal alpha, the electrical characteristics of the fractional order memcapacitor are changed, the electrical characteristics of the fractional order memcapacitor can be conveniently simulated by the equivalent circuit of the specific embodiment at different orders, and the adjustment of the order can be completed only by changing the size of the control signal alpha;
the resistor, the capacitor and the control signal alpha adopted by the embodiment have high precision, and the frequency of the input signal can be accurately detected.
Therefore, the method and the device can accurately simulate the electrical characteristics of the fractional order memcapacitor, and have the characteristics of convenience in order adjustment, easiness in control and high precision.
Claims (5)
1. An equivalent circuit of a fractional order memcapacitor is characterized in that two ends of the equivalent circuit of the fractional order memcapacitor are respectively a terminal A of the equivalent circuit of the fractional order memcapacitor and a terminal B of the equivalent circuit of the fractional order memcapacitor; the control signal alpha is added between a terminal C of an equivalent circuit of the fractional order memcapacitor and a terminal GND of the equivalent circuit of the fractional order memcapacitor;
the terminal A of the equivalent circuit of the fractional order memcapacitor is respectively connected with the terminal E1+ of the first current conveyor (1), the terminal Fi of the frequency/voltage converter (24) and the terminal C12 of the first capacitor (22);
the terminal B of the equivalent circuit of the fractional order memcapacitor is connected with the terminal E2-of the second current conveyor (18);
the terminal E1-of the first current conveyor (1) is connected with the terminal R22 of the second resistor (26), the terminal E1i of the first current conveyor (1) is respectively connected with the terminal R12 of the first resistor (25) and the terminal W21 of the second amplifying module (4), and the terminal W22 of the second amplifying module (4) is connected with the terminal phi 0 of the voltage-controlled phase shifter (19); the terminal E1o of the first current conveyor (1) is connected with the terminal W11 of the first amplification module (2), the terminal W12 of the first amplification module (2) is connected with the terminal X1 of the first multiplier (3), and the terminal Y1 of the first multiplier (3) is connected with the terminal U0 of the voltage source (5);
a terminal P1 of the first multiplier (3) is connected to a terminal X2 of the second multiplier (6), a terminal X5 of the fifth multiplier (12), and a terminal B3 of the third adder (14), a terminal Y2 of the second multiplier (6) is connected to a terminal K12 of the first arithmetic module (7), a terminal P2 of the second multiplier (6) is connected to a terminal a1 of the first adder (8) and a terminal X3 of the third multiplier (9), a terminal B1 of the first adder (8) is connected to a terminal P3 of the third multiplier (9), a terminal S1 of the first adder (8) is connected to a terminal X4 of the fourth multiplier (10), a terminal Y4 of the fourth multiplier (10) is connected to a terminal Φ 2 of the voltage-controlled phase shifter (19), and a terminal P4 of the fourth multiplier (10) is connected to a terminal a2 of the second multiplier (11); the terminal B2 of the second adder (11) is connected to the terminal P5 of the fifth multiplier (12), and the terminal Y5 of the fifth multiplier (12) is connected to the terminal K32 of the third arithmetic module (17);
the terminal S2 of the second adder (11) is connected to the terminal X6 of the sixth multiplier (13), the terminal Y6 of the sixth multiplier (13) is connected to the terminal K22 of the second arithmetic module (15), and the terminal P6 of the sixth multiplier (13) is connected to the terminal A3 of the third adder (14); the terminal S3 of the third adder (14) is connected to the terminal Hi of the analog inverter (16), the terminal Ho of the analog inverter (16) is connected to the terminal E2+ of the second current conveyor (18), the terminal E2i of the second current conveyor (18) is connected to the terminal E3i of the third current conveyor (20), and the terminal E3-of the third current conveyor (20) is connected to the terminal C11 of the first capacitor (22);
the terminal Vo of the frequency/voltage converter (24) is connected to the terminal K41 of the fourth arithmetic block (23), the terminal K42 of the fourth arithmetic block (23) is connected to the terminal X7 of the seventh multiplier (21), and the terminal P7 of the seventh multiplier (21) is connected to the terminal Y3 of the third multiplier (9);
the terminal C of the equivalent circuit of the fractional order memcapacitor is respectively connected with the terminal K11 of the first operation module (7), the terminal K21 of the second operation module (15), the terminal K31 of the third operation module (17), the terminal phi 1 of the voltage-controlled phase shifter (19) and the terminal Y7 of the seventh multiplier (21);
the terminal GND of the equivalent circuit of the fractional order memcapacitor is respectively connected with the terminal E3+ of the third current conveyor (20), the terminal R21 of the second resistor (26) and the terminal R11 of the first resistor (25);
capacitance value C of equivalent circuit of fractional order memory containerM：
DM＝D1+D2{1+K2[K3+K1(Fα+1)WR1I sin(2πft-π/2α)]} (2)
Formula (1) formula (2): dMA containment value representing an equivalent circuit of a fractional order memcapacitor;
D1represents the value of the first capacitance (22);
D2represents the voltage output value of the voltage source (5);
i denotes the input current Ia(t) magnitude;
K1represents the voltage output value of the first arithmetic module (7);
K2represents a voltage output value of the second arithmetic module (15);
K3represents a voltage output value of the third operation module (17);
f represents a voltage output value of the fourth operation module (23);
w represents the voltage amplification factor of the second amplification module (4);
R1represents the resistance value of the first resistor (25);
f denotes the input current ia(t) frequency value;
t represents a time value in seconds;
alpha represents the fractional order of the memcapacitor, and the fractional order is equal to the voltage value of the control signal;
the first operation module (7) is composed of a 1.2V power supply (39), an eleventh resistor (40), a twelfth resistor (41), a thirteenth resistor (42), a fifth operation amplifier (43) and a fourteenth resistor (44);
a terminal R142 of the fourteenth resistor (44) is connected with a terminal R131 of the thirteenth resistor (42) and a terminal V5-of the fifth operational amplifier (43), a terminal V5+ of the fifth operational amplifier (43) is connected with a terminal R112 of the eleventh resistor (40) and a terminal R121 of the twelfth resistor (41), and a terminal R111 of the eleventh resistor (40) is connected with a terminal U1 of the 1.2V power supply (39); a terminal R122 of the twelfth resistor (41) is connected with a terminal GND of an equivalent circuit of the fractional order memcapacitor;
the two ends of the first operational module (7) are a terminal K11 and a terminal K12, a terminal R141 of the fourteenth resistor (44) is connected with a terminal K11 of the first operational module (7), and a terminal V5o of the fifth operational amplifier (43) and a terminal R132 of the thirteenth resistor (42) are connected with a terminal K12 of the first operational module (7);
the second operational module (15) is composed of a fifteenth resistor (45), a sixth operational amplifier (46), a seventeenth resistor (47), an eighteenth resistor (48), a nineteenth resistor (49), a seventh operational amplifier (50), a twentieth resistor (51), -1V power supply (52) and a sixteenth resistor (53);
a terminal R152 of the fifteenth resistor (45) is respectively connected with a terminal R161 of the sixteenth resistor (53) and a terminal V6-of the sixth operational amplifier (46), a terminal V6o of the sixth operational amplifier (46) is respectively connected with a terminal R162 of the sixteenth resistor (53) and a terminal R171 of the seventeenth resistor (47), a terminal R172 of the seventeenth resistor (47) is respectively connected with a terminal R181 of the eighteenth resistor (48) and a terminal V7+ of the seventh operational amplifier (50), a terminal V7-of the seventh operational amplifier (50) is respectively connected with a terminal R191 of the nineteenth resistor (49) and a terminal R202 of the twentieth resistor (51), and a terminal R201 of the twentieth resistor (51) is connected with a terminal U2 of the-1V power supply (52); a terminal V6+ of a sixth operational amplifier (46) and a terminal R182 of an eighteenth resistor (48) are connected with a terminal GND of an equivalent circuit of the fractional order memcapacitor;
the two ends of the second operational module (15) are a terminal K21 and a terminal K22, a terminal R151 of a fifteenth resistor (45) is connected with a terminal K21 of the second operational module (15), a terminal R192 of a nineteenth resistor (49) and a terminal V7o of a seventh operational amplifier (50) are connected with a terminal K22 of the second operational module (15);
the third operational module (17) is composed of a twenty-first resistor (54), an eighth operational amplifier (55), a twenty-third resistor (56), a twenty-fourth resistor (57), a twenty-fifth resistor (58), a ninth operational amplifier (59), a twenty-sixth resistor (60), a 0.5V power supply (61) and a twenty-second resistor (62);
a terminal R212 of the twenty-first resistor (54) is respectively connected with a terminal R221 of the twenty-second resistor (62) and a terminal V8-of the eighth operational amplifier (55), a terminal V8o of the eighth operational amplifier (55) is respectively connected with a terminal R222 of the twenty-second resistor (62) and a terminal R231 of the twenty-third resistor (56), a terminal R232 of the twenty-third resistor (56) is respectively connected with a terminal R241 of the twenty-fourth resistor (57) and a terminal V9+ of the ninth operational amplifier (59), a terminal V9-of the ninth operational amplifier (59) is respectively connected with a terminal R251 of the twenty-fifth resistor (58) and a terminal R262 of the twenty-sixth resistor (60), and a terminal R261 of the twenty-sixth resistor (60) is connected with a terminal U3 of the 0.5V power supply (61); a terminal V8+ of the eighth operational amplifier (55) and a terminal R242 of the twenty-fourth resistor (57) are connected with a terminal GND of an equivalent circuit of the fractional order memcapacitor;
the two ends of the third operational module (17) are a terminal K31 and a terminal K32, a terminal R211 of the twenty-first resistor (54) is connected with a terminal K31 of the third operational module (17), and a terminal R252 of the twenty-fifth resistor (58) and a terminal V9o of the ninth operational amplifier (59) are connected with a terminal K32 of the third operational module (17);
the fourth operational module (23) is composed of a twenty-seventh resistor (63), a twenty-eighth resistor (64), a tenth operational amplifier (65), a thirty-first resistor (66), an eleventh operational amplifier (67), a thirty-second resistor (68), a thirty-first resistor (69), a twenty-ninth resistor (70) and a 1V power supply (71);
a terminal R272 of the twenty-seventh resistor (63) is respectively connected with a terminal R281 of the twenty-eighth resistor (64) and a terminal V10+ of the tenth operational amplifier (65), a terminal V10-of the tenth operational amplifier (65) is respectively connected with a terminal R301 of the thirty-eighth resistor (69) and a terminal R292 of the twenty-ninth resistor (70), and a terminal R291 of the twenty-ninth resistor (70) is connected with a terminal U4 of the 1V power supply (71); a terminal V10o of the tenth operational amplifier (65) is connected to a terminal R302 of the thirtieth resistor (69) and a terminal R311 of the thirty-first resistor (66), respectively, and a terminal R312 of the thirty-first resistor (66) is connected to a terminal V11-of the eleventh operational amplifier (67) and a terminal R321 of the thirty-second resistor (68), respectively; a terminal V11+ of the eleventh operational amplifier (67) and a terminal R282 of the twenty-eighth resistor (64) are connected with a terminal GND of an equivalent circuit of the fractional order memcapacitor;
the terminal K41 and the terminal K42 are arranged at two ends of the fourth operational module (23), the terminal R271 of the twenty-seventh resistor (63) is connected with the terminal K41 of the fourth operational module (23), and the terminal R322 of the thirty-second resistor (68) and the terminal V11o of the eleventh operational amplifier (67) are connected with the terminal K42 of the fourth operational module (23).
2. The equivalent circuit of a fractional order memcapacitor according to claim 1, characterized in that said first amplification block (2) is composed of a third resistor (27), a fourth resistor (28), a first operational amplifier (29), a fifth resistor (30), a sixth resistor (31) and a second operational amplifier (32);
a terminal R32 of the third resistor (27) is respectively connected with a terminal R41 of the fourth resistor (28) and a terminal V1-of the first operational amplifier (29), a terminal V1o of the first operational amplifier (29) is respectively connected with a terminal R42 of the fourth resistor (28) and a terminal R51 of the fifth resistor (30), and a terminal R52 of the fifth resistor (30) is respectively connected with a terminal R61 of the sixth resistor (31) and a terminal V2-of the second operational amplifier (32); the terminal V2+ of the second operational amplifier (32) and the terminal V1+ of the first operational amplifier (29) are connected with the terminal GND of the equivalent circuit of the fractional order memcapacitor;
the two ends of the first amplification module (2) are a terminal W11 and a terminal W12, a terminal R31 of the third resistor (27) is connected with a terminal W11 of the first amplification module (2), and a terminal R62 of the sixth resistor (31) and a terminal V2o of the second operational amplifier (32) are connected with a terminal W12 of the first amplification module (2).
3. The equivalent circuit of a fractional order memcapacitor according to claim 1, characterized in that said second amplification block (4) is composed of a seventh resistor (33), an eighth resistor (34), a third operational amplifier (35), a ninth resistor (36), a tenth resistor (37) and a fourth operational amplifier (38);
a terminal R72 of the seventh resistor (33) is connected with a terminal R81 of the eighth resistor (34) and a terminal V3-of the third operational amplifier (35), a terminal V3o of the third operational amplifier (35) is connected with a terminal R82 of the eighth resistor (34) and a terminal R91 of the ninth resistor (36), and a terminal R92 of the ninth resistor (36) is connected with a terminal R101 of the tenth resistor (37) and a terminal V4-of the fourth operational amplifier (38); the terminal V3+ of the third operational amplifier (35) and the terminal V4+ of the fourth operational amplifier (38) are connected with the terminal GND of the equivalent circuit of the fractional order memcapacitor;
the two ends of the second amplification module (4) are a terminal W21 and a terminal W22, a terminal R71 of the seventh resistor (33) is connected with a terminal W21 of the second amplification module (4), and a terminal R102 of the tenth resistor (37) and a terminal V4o of the fourth operational amplifier (38) are connected with a terminal W22 of the second amplification module (4).
4. The equivalent circuit of a fractional order memcapacitor of claim 1, wherein the analog inverter (16) is comprised of a thirty-third resistance (72), a thirty-fourth resistance (73), and a twelfth operational amplifier (74);
a terminal R332 of the thirty-third resistor (72) is respectively connected with a terminal R341 of the thirty-fourth resistor (73) and a terminal V12-of the twelfth operational amplifier (74), and a terminal V12+ of the twelfth operational amplifier (74) is connected with a terminal GND of an equivalent circuit of the fractional order memcapacitor;
the two ends of the analog inverter (16) are a terminal Hi and a terminal Ho, a terminal R331 of the thirty-third resistor (72) is connected with the terminal Hi of the analog inverter (16), and a terminal R342 of the thirty-fourth resistor (73) and a terminal V12o of the twelfth operational amplifier (74) are connected with the terminal Ho of the analog inverter (16).
5. The equivalent circuit of a fractional order memcapacitor of claim 1, wherein the voltage controlled phase shifter (19) is comprised of a first junction field effect transistor (75), a third capacitance (76), a thirty-fifth resistance (77), a thirteenth operational amplifier (78), a thirty-sixth resistance (79), a thirty-seventh resistance (80), a thirty-eighth resistance (81), a second junction field effect transistor (82), and a second capacitance (83);
a terminal G13 of the first junction field effect transistor (75) is connected with a terminal C31 of the third capacitor (76) and a terminal R351 of the thirty-fifth resistor (77), a terminal R352 of the thirty-fifth resistor (77) is connected with a terminal V13+ of the thirteenth operational amplifier (78) and a terminal R361 of the thirty-sixth resistor (79), a terminal C22 of the second capacitor (83) is connected with a terminal G21 of the second junction field effect transistor (82) and a terminal R381 of the thirty-eighth resistor (81), and a terminal R382 of the thirty-eighth resistor (81) is connected with a terminal V13-of the thirteenth operational amplifier (78) and a terminal R371 of the thirty-seventh resistor (80), respectively;
the terminal GND of the equivalent circuit of the fractional order memcapacitor is respectively connected with the terminal C32 of the third capacitor (76), the terminal G23 of the second junction field effect transistor (82) and the terminal R362 of the thirty-sixth resistor (79);
the voltage-controlled phase shifter (19) is respectively provided with a terminal phi 0, a terminal phi 1 and a terminal phi 2; the terminal G11 of the first junction field effect transistor (75) and the terminal C21 of the second capacitor (83) are connected to the terminal Φ 0 of the voltage-controlled phase shifter (19), the terminal G12 of the first junction field effect transistor (75) and the terminal G22 of the second junction field effect transistor (82) are connected to the terminal Φ 1 of the voltage-controlled phase shifter (19), and the terminal V13o of the thirteenth operational amplifier (78) and the terminal R372 of the thirty-seventh resistor (80) are connected to the terminal Φ 2 of the voltage-controlled phase shifter (19).
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| CN109308387B (en) * | 2018-09-12 | 2023-01-31 | 成都师范学院 | Voltage fractional order integral control type memory container |
| CN109308388B (en) * | 2018-09-12 | 2022-11-08 | 成都师范学院 | Current fractional order integral control type memory sensor |
| CN109271703B (en) * | 2018-09-12 | 2023-07-07 | 成都师范学院 | Current fractional order integral control type memristor |
| CN110147605B (en) * | 2019-05-15 | 2022-12-02 | 武汉科技大学 | Low-pass filter circuit based on fractional order memcapacitor equivalent circuit |
| CN110516352B (en) * | 2019-08-27 | 2023-05-19 | 杭州电子科技大学 | Equivalent circuit of chaotic oscillator based on logarithmic memcapacitor |
| CN112987081B (en) * | 2021-03-23 | 2024-02-06 | 重庆航天职业技术学院 | Analog circuit of unidirectional coupling fractional order self-sustaining electromechanical seismometer system |
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