CN108324308A - A kind of number PET system - Google Patents
A kind of number PET system Download PDFInfo
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- CN108324308A CN108324308A CN201810242260.8A CN201810242260A CN108324308A CN 108324308 A CN108324308 A CN 108324308A CN 201810242260 A CN201810242260 A CN 201810242260A CN 108324308 A CN108324308 A CN 108324308A
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B6/00—Apparatus or devices for radiation diagnosis; Apparatus or devices for radiation diagnosis combined with radiation therapy equipment
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Abstract
The present invention provides a kind of digital PET system, it pops one's head in clock distributing equipment, several pet detector modules, interchanger, computer and physiological signal, physiological signal is popped one's head in be communicated to connect with clock distributing equipment, clock distributing equipment is communicated to connect with multiple pet detector modules, pet detector module is connect with switch communication, clock distributing equipment is connect with switch communication, and interchanger is communicated to connect with computer；Each pet detector module includes scintillation pulse probe, acquisition subcard and FPGA motherboards, scintillation pulse probe is connect by acquisition subcard, FPGA motherboards with clock distributing equipment, it includes FPGA subcards, operational amplification circuit and D/A conversion circuit to acquire subcard, FPGA subcards are communicated to connect with operational amplification circuit and D/A conversion circuit respectively, and operational amplification circuit is communicated to connect with acquisition subcard and scintillation pulse probe respectively.The present invention can realize that the gate of PET system samples using specific physiological signal as trigger signal, and simple in structure, autgmentability is strong.
Description
Technical field
The present invention relates to medical instruments fields, relate more specifically to a kind of number PET (Positron Emission
Tomography, positron emission tomography) system.
Background technology
PET system is a kind of contrast apparatus of non-intrusion type, it in vivo takes in point of radioactive tracer by detecting
Cloth, metaboilic level, biochemical reaction, functional activity and perfusion noninvasive, that dynamically assess various organs in organism.As current
The sophisticated technology of nuclear medicine diagnostic and research, early diagnosis of the PET system in tumour, angiocarpy, nervous system etc., curative effect evaluation
And there is unique application value in the fields such as basic research.
What the probe of traditional PET system scintillation crystal array and photomultiplier composition released positron annihilation
Gammaphoton is converted to scintillation pulse, reuses digital signal processing circuit and obtains the energy information and location information of scintillation pulse
(including X of crystal item and Y information, crystal number, Energy Efficient mark etc.), using analog signal processing circuit by scintillation pulse
Trigger signal is converted to, trigger signal is square wave, and the rising edge of square wave can indicate scintillation pulse arrival time.Number and simulation letter
The output of number processing circuit, which is connected to, to be met plate and is matched to the scintillation pulse of acquisition, is filtered out the event that cannot be matched, is obtained
To really meeting event.When scintillation crystal array number increases, meeting the design of plate can become considerably complicated.Simultaneously as
Traditional PET system uses photomultiplier as electrooptical device, and photomultiplier needs the high pressure of kilovolt to drive
Dynamic, power-supply service is complicated, and volume is big, expensive, incompatible with magnetic field, and signal read circuit is complicated, while using photoelectricity times
It is not high enough to increase the scintillation pulse probe counting rate that pipe is realized, the not high enough quality that will will have a direct impact on image reconstruction of counting rate.
Fig. 1 is according to a kind of PET system of the prior art, including following components：Probe, by scintillation pulse array and
Photomultiplier forms, gammaphoton is converted to scintillation pulse；Digiboard, the scintillation pulse of probe output is amplified,
It is AD converted after shaping, handles transformed digital signal and obtains the energy and location information of the event of detecting, in the overall situation
The energy of event and location information are given the coincident circuit plate of rear end and meet and sentence choosing by polylith digiboard under the domination of clock；
Analog board, generates a gate enable signal when the 511kev electron volts peak positions of scintillation pulse arrive, which is the side TTL
Wave (transistor-transistor logic integrated circuit, transistor-transistor logic, abbreviation TTL), rising edge indicate
Scintillation pulse arrival time, for triggering the event matches process of coincident circuit plate；Coincident circuit plate, for summarizing digiboard
The example that meets occurred in the incoming event information of signal processing circuit is picked out, and will be met example and is passed through ICP/IP protocol
Or udp protocol (user datagram protocol, User Datagram Protocol, abbreviation udp protocol) is transferred at Back end data
Reason system；Clock distributing equipment, for providing global unified clock and global reset signal；Data processing system is used for data
Analysis, image reconstruction and processing.The scintillation pulse sampling of this number PET system and the processing of digital signal are in time
Continuously, i.e., detector continuously carries out scintillation pulse sampling, all collected data of PET system processing, at one section
Imaging in longer time, then the interested image of doctor is filtered out in imaging results.
Digitized PET system can effectively solve the problem that traditional PET system is easy to be corrected difficult problem by environmental disturbances,
Introducing Digital Signal Processing also brings a variety of advantages simultaneously, is the hot spot direction of current PET Instrument Designs.Digital PET systems
System samples scintillation pulse using multiple detectors, the collected data transmission of detector to computer, recycles corresponding
Data processing system the data of acquisition are handled, filter out and meet event, obtain scintillation pulse time and energy letter
Breath.
But the image significant to clinic diagnosis only occurs at the time of specific under normal conditions, it is clear that if can be with certain
Kind physiological signal is trigger signal, and the image of organ or tissue is formed using the data in trigger signal time of occurrence section, will
It can be significantly reduced data processing amount, shorten imaging time.By taking respiration gate control is imaged as an example, the respiratory rhythm of patient is converted into
Electro physiology waveform (can be obtained using pressure sensor chest compression movement being converted to electricity physiological signal, or use signal probe
Obtain bulbar neurons signal), there is certain rhythm and pace of moving things for the waveform, and the somewhere of waveform is the interested region of doctor, operator
The data that the place corresponds to time interval can be only acquired using PET system, the data for being enough to be imaged are reached by multiple repairing weld
Amount, this simplifies the processes of PET imaging datas processing, also enhance the functionality of PET imagings.For traditional PET system
Speech redesigns hardware coincident circuit, is allowed to have since its own degree of modularity is not high and meets the not expansibility of plate
Have gate sample function can bring system structure complexity, cost increase, for a variety of physiological signal poor compatibilities the problem of.
Invention content
It, can not be with to solve PET system in the prior art the object of the present invention is to provide for a kind of digital PET system
The problem of succinct structure carries out gate imaging according to specific electricity physiological signal waveform.
In order to solve the above-mentioned technical problem, the technical solution of the present invention is to provide a kind of digital PET system, the numbers
PET system has clock distributing equipment, several pet detector module, interchanger and computers, the number PET system
Further include physiological signal probe, wherein the physiological signal probe is communicated to connect with the clock distributing equipment, the clock point
It being communicated to connect with device and multiple pet detector modules, the pet detector module is connect with the switch communication,
The clock distributing equipment is also connect with the switch communication, and the interchanger is communicated to connect with the computer；Each institute
It includes scintillation pulse probe, acquisition subcard and FPGA motherboards to state pet detector module, and the scintillation pulse probe passes through institute
It states acquisition subcard to connect with the FPGA motherboards, the FPGA motherboards are communicated to connect with the clock distributing equipment, the acquisition
Subcard includes FPGA subcards, operational amplification circuit and D-A converting circuit, wherein the FPGA subcards respectively with institute
State operational amplification circuit and the D-A converting circuit communication connection, the operational amplification circuit respectively with the acquisition
Subcard and scintillation pulse probe communication connection.
According to one embodiment of present invention, the clock distributing equipment includes：There is source crystal oscillator, it is described to have source crystal oscillator generation
First clock signal；There is phaselocked loop, the phaselocked loop to have source crystal oscillator communication connection, institute with described for clock board, the clock board
It states phaselocked loop and receives and processes first clock signal to form second clock signal；Clock fan out buffer, the clock
Fan out buffer and the phaselocked loop communicate to connect, the clock fan out buffer receive and process the second clock signal with
Form synchronizing clock signals；Touch-switch, the touch-switch is connect with the clock board to be resetted with being sent to the clock board
Signal, the reset signal form synchronous reset signal after clock board processing；Input connector, the physiological signal
Probe is communicated to connect by the input connector and the clock board；At least two-way out connector, the out connector
Communicated to connect with the clock fan out buffer to receive synchronizing clock signals, the out connector simultaneously with the clock board
To receive the synchronous reset signal, the clock board passes through the out connector and the FPGA motherboards communication link for connection
It connects.
According to one embodiment of present invention, the scintillation pulse probe is matched with a public connector, acquisition
The both ends of card are matched with two public connectors respectively, with the scintillation pulse pop one's head in matched public connector and with the acquisition it is sub
Block and communicated to connect by a pair of of female connectors between a matched public connector, matched another is public with the acquisition subcard
Connector is connect by corresponding female connectors with the clock distributing equipment.
According to one embodiment of present invention, the scintillation pulse probe includes scintillation crystal array and silicon photomultiplier transit
Pipe, is coupled between the scintillation crystal array and the silicon photomultiplier by couplant, in the scintillation crystal array
Separated by barium sulfate coating between scintillation crystal, crystal array surface is wrapped up with masking foil, and the silicon photomultiplier is into one
Step passes through printed circuit board output signal.
According to one embodiment of present invention, several interfaces are provided on the FPGA motherboards, the FPGA motherboards are logical
The interface therein is crossed to connect with the acquisition subcard.
According to one embodiment of present invention, the phaselocked loop passes through a single ended input pin and a pair of of difference output pin
It is integrated on the clock board, described to there is source crystal oscillator to be connect with the phaselocked loop by the single ended input pin, the locking phase
Ring is connect by the difference output pin with the differential input end of the clock fan out buffer.
According to one embodiment of present invention, the clock fan out buffer in the form of PCB difference cablings at least two-way
The out connector connection.
According to one embodiment of present invention, the clock board has time measurement module, the time measurement module packet
Thick timer and thin timer are included, the thick timer calculates the thick time of the trigger signal, and the thin timer calculates institute
The thin time of trigger signal is stated, the time measurement module is according to trigger signal described in the thick time and the fine measurement
Edge arrival time.
According to one embodiment of present invention, the thin timer is an output temperature code inside the clock board
Delay line, the thermometer code include several continuously arranged 0 and 1, the thin timer puts in order according to described 0 and 1
And number calculates the edge arrival time of the trigger signal.
According to one embodiment of present invention, the delay line of the thin timer include several it is concatenated complete plus
Device, the thin timer calculate the thin time according to the thermometer code that the full adder exports.
According to one embodiment of present invention, there are two input terminals for each full adder tool, one of them is described defeated
Enter the binary constant that end input comes from the clock board, another input terminal inputs the trigger signal.
According to one embodiment of present invention, the synchronizing clock signals and the synchronous reset signal are differential level
Form.
According to one embodiment of present invention, the input connector is self-locking connector, the self-locking connector
Including stand and connector, the stand is connect with the field programmable gate array chip, the connector and the physiological signal
Probe connection.
According to one embodiment of present invention, the clock distributing equipment of the interchanger and the clock distributing equipment
Connected with socket by gigabit Ethernet physical chip with receive first clock signal, the second clock signal and
The synchronizing clock signals, the client are connect with the switch communication to receive the data that the interchanger is sent.
According to one embodiment of present invention, the out connector and the pet detector module are 12, often
A out connector is correspondingly connected with a pet detector module.
According to one embodiment of present invention, pass through six class cables between the pet detector module and the interchanger
It is connected with each other.
According to one embodiment of present invention, the touch-switch includes pressing and discharging both of which, is touched when described
When switch is pressed, the clock board generates 12 tunnel reset signals.
According to one embodiment of present invention, the slide switch has the switch of left and right two, when the slide switch quilt
When pushing left side, it is opposite low level that unit is 0, the clock board that the slide switch sends one to the clock board
By output after the low level reverse phase to the clock fan out buffer；When the slide switch is pushed right side, the cunning
Dynamic switch sends the opposite low level that a unit is 1 to the clock board, and the clock board will be after the high level reverse phase
It exports to the clock fan out buffer.
According to one embodiment of present invention, the digital PET system includes multiple clock distributing equipments, wherein one
The slide switch of a clock distributing equipment pushes left side, as host；The institute of remaining clock distributing equipment
It states slide switch and pushes right side, as slave；The input connector of the out connector of the host and the slave is one-to-one
Connection, the out connector of the slave are connect with each pet detector module.
According to one embodiment of present invention, the digital PET system includes multiple clock distributing equipments, wherein one
The slide switch of a clock distributing equipment pushes left side, as host；Clock distributing equipment described in another part
The slide switch pushes right side, and as slave, the slave includes the first slave and the second slave, wherein the host
The one-to-one connection of input connector of out connector and first slave, the out connector of first slave and described
The one-to-one connection of input connector of second slave, the out connector of second slave connect with each pet detector module
It connects.
Number PET system provided by the invention can carry out discontinuous flicker by trigger signal of specific physiological signal
Impulse sampling realizes the function of gate sampling so that digital PET system only samples scintillation pulse during being triggered.Together
When, trigger signal In-put design is a general-purpose interface by the present invention, and trigger signal can not be physiological signal, and user can be used
Arbitrary signal has extremely strong autgmentability as trigger signal.
It is provided by the invention number PET system, with digital pet detector module instead of digiboard in the prior art,
Analog board meets plate, simplifies the structure of PET system.The step of cancelling after meeting plate, meeting is completed on computers, is calculated
The algorithm flexibly configurable of machine；The function that trigger signal samples is integrated in clock distributing equipment by the present invention, no matter number PET systems
How small the scale of system have, and all has complete gate sampling functions, and without the additional sampling apparatus of introducing；And the present invention adopts
It with modular design, can arbitrarily increase and decrease the number of pet detector module, and correspondingly change the rule of clock distributing equipment
Mould has flexible characteristic, easy to repair and upgrading.
Description of the drawings
Fig. 1 is the structure arrangement schematic diagram of PET system according to prior art；
Fig. 2 is the structure arrangement schematic diagram of digital PET system according to an embodiment of the invention；
Fig. 3 is the connection diagram of the pet detector module and clock distributing equipment of digital PET system according to fig. 2；
Fig. 4 is the connection diagram of the acquisition subcard of digital PET system according to fig. 3；
Fig. 5 is the multivoltage threshold measurement principle schematic according to the digital PET system of Fig. 4；
Fig. 6 is the principle schematic of the delay line detection of the digital PET system of the present invention, and wherein delay line detects signal
Rising edge；
Fig. 7 is the principle schematic detected according to the delay line of the digital PET system of Fig. 6, and wherein delay line detects letter
Number failing edge；
Fig. 8 is the measuring principle schematic diagram according to the time measurement module of the digital PET system of Fig. 7；
Fig. 9 is the connection diagram according to the clock distributing equipment of the digital PET system of Fig. 1；
Figure 10 is the trigger signal edge measurements of arrival time schematic diagram of the digital PET system of the present invention；
Figure 11 is the veneer operation principle of the clock distributing equipment of digital PET system according to an embodiment of the invention
Schematic diagram, cascade stages number are 2；
Figure 12 is the principle signal of the scintillation pulse sampling of digital PET system according to another embodiment of the invention
Figure.
Specific implementation mode
Below in conjunction with specific embodiment, the present invention will be further described.It should be understood that following embodiment is merely to illustrate this
The range of invention and is not intended to limit the present invention.
Fig. 2 is according to the structure arrangement schematic diagram of the digital PET system of one embodiment of the present of invention, as shown in Figure 2, originally
The digital PET system of invention includes clock distributing equipment 1, physiological signal probe 2, several pet detector modules 3, interchanger 4
And computer 5, wherein physiological signal probe 2 and clock distributing equipment 1 communicate to connect, clock distributing equipment 1 and multiple PET
Detector module 3 communicates to connect, and pet detector module 3 is communicated to connect by cable and interchanger 4, and clock distributing equipment 1 is simultaneously
It is communicated to connect with interchanger 4, interchanger 4 is communicated to connect with computer 5.
Specifically, it is communicated to connect by input connector (Fig. 9) between physiological signal probe 2 and clock distributing equipment 1.
When clock distributing equipment 1 works, the electricity physiological signal of tested organism is converted to trigger signal by physiological signal probe 2 in real time
S, trigger signal s are single channel square-wave signal, only low level and high level two states, and trigger signal s further passes through input
Connector is sent to the field programmable gate array chip in clock distributing equipment 1.Clock distributing equipment 1 passes through out connector
(Fig. 9) carries out data transmission with multiple pet detector modules 3, specifically, two lines road is arranged in each pet detector module 3
To be respectively used to the transmission of synchronizing clock signals, synchronous reset signal, these circuits are connected with the output on clock distributing equipment 1
Device matches, i.e., circuit, the model of out connector are identical and cable is mating, and every cable can integrate two lines road, so that
One out connector is only correspondingly connected with a pet detector module 3 by single line cable.Pet detector module 3 and interchanger
It can be connected with transmission data by six class cables between 4.
Fig. 3 be according to the connection diagram of the pet detector module 3 and clock distributing equipment 1 of the digital PET system of Fig. 2,
From the figure 3, it may be seen that the digital PET system of the present invention includes multiple pet detector modules 3, each pet detector module 3 is wrapped
Include scintillation pulse probe 31 and acquisition subcard 32, wherein scintillation pulse probe 31 is matched with a public connector 33, acquires subcard
32 both ends are matched with two public connectors 33 respectively, with scintillation pulse pop one's head in 31 matched public connectors 33 and with acquisition subcard
It is communicated to connect by a pair of of female connectors 34 between a 32 matched public connectors 33.Further from the figure 3, it may be seen that the present invention
Further include FPGA (Field-Programmable Gate Array, field programmable gate array, abbreviation in digital PET system
FPGA) motherboard 11, are provided with several interfaces on FPGA motherboards 11, such as FPGA download interfaces 341, other interfaces 114, global
Clock and reset input interface 115, temperature sensor interface 116, eeprom chip interface 117 and FLASH interfaces 118,
By networked physics layer chip 112, (registered jack, RJ45 are 8 modular interfaces of standard to FPGA motherboards 11 with RJ45
Abbreviation) socket 113 connect, meanwhile, with acquisition another the matched public connector 33 of subcard 32 pass through corresponding female connectors
34 connect with FPGA motherboards 11 respectively, and FPGA download interfaces 341 are connect by the female connectors 34 with FPGA motherboards 11, meanwhile,
FPGA motherboards 11 are connect by global clock and reset input interface 115 with clock distributing equipment 1.
In an embodiment of the present invention, it acquires between subcard 32 and FPGA motherboards 11, scintillation pulse probe 31 and acquisition
All connected with male and female connector (i.e. connector to) between card 32, male and female connector may be designed as the form of plugs and sockets, and one
Aspect ensures the transmission and power supply of signal by male and female connector, on the other hand more by the modularized design of male and female connector
Add the repair and upgrade convenient for component.
In an embodiment of the present invention, scintillation pulse probe 31 include scintillation crystal array, SiPM (silicon photomultiplier),
Reading circuit is coupled between scintillation crystal array and SiPM by couplant (such as silicone grease), scintillation crystal array surface
Wrapped up with masking foil, be isolated with barium sulfate coating between each unit, SiPM further by printed circuit board output signal,
Operation principle is：The gammaphoton released when radioisotope decays is captured by the scintillation crystal in scintillation crystal array, is dodged
Gammaphoton is converted to optical photon by bright crystal, it is seen that photon is conducted to SiPM and captured by SiPM, to it will be seen that light
Son is converted to current signal output, and current signal handles through reading circuit, becomes that a rising edge is precipitous, failing edge index of coincidence
The voltage pulse signal of rule, the amplitude of the signal is related with the light output amount of crystal array, in several millivolts to dozens of milli
Between volt.Scintillation pulse signal is by male and female connector to being connected to acquisition subcard 32, and acquisition subcard 32 is to scintillation pulse signal
It is digitized sampling, then further by male and female connector to being input to FPGA motherboards 11.
Fig. 4 is the connection diagram of the acquisition subcard of digital PET system according to fig. 3, as shown in Figure 4, in the present invention
It includes FPGA subcards 321, operational amplification circuit 322 and D-A converting circuit 323 to acquire subcard 32, wherein FPGA
Card 321 is communicated to connect with operational amplification circuit 322 and D-A converting circuit 323 respectively, operational amplification circuit 322 with adopt
Collect a public connector 33 connection of 32 one end of subcard, and passes through 31 communication connection of the public connector 33 and scintillation pulse probe.
Scintillation pulse signal from scintillation pulse probe 31 passes through the amplification of operational amplification circuit 322, and amplitude is increased to hundreds of millivolts.
Include multiple pins on FPGA subcards 321, operational amplification circuit 322 and D-A converting circuit 323 are drawn by these respectively
Foot is communicated to connect with FPGA subcards 321.In addition, the other pin of FPGA subcards 321 also respectively with temperature sensor 116,
Eeprom chip and FLASH chip connection, the other ends of FPGA subcards 321 by public connector 33 and female connectors 34 with
FPGA motherboards 11 communicate to connect.
The shape of scintillation pulse signal is generally configured with certain rule, such as with relatively quick rising edge and relatively slowly
Failing edge, such scintillation pulse signal sampling should not carry out intensive equal interval sampling (i.e. traditional ADC, analog-to-
Digital converter, the analog-to-digital conversion method of sampling).Subcard sampling is acquired in the present invention using multivoltage threshold value
(MVT, multi-voltage threshold) method of sampling, the MVT method of samplings set the voltage threshold of some distribution gradients
Value, since voltage threshold is known, measure scintillation pulse when reaching voltage threshold the corresponding time can be obtained complete electricity
Pressure-time sampling information, the sampling interval can be changed in the size by adjusting voltage threshold, in the premise of known scintillation pulse shape
Under, the shape of scintillation pulse can be restored by these sampled points.The principle schematic of MVT methods is as shown in figure 5, voltage threshold
I.e. preset reference voltage level, during actual samples, the measurement result of time point t1-t8 is only sent to by acquisition subcard
Computer is handled.
In acquiring subcard 32, the part pin of FPGA subcards 321 is configured as LVDS (Low Voltage
Differential Signaling, low-voltage differential signal, LVDS are a kind of differential level standards) level standard.It is different from
The way of a traditional piece ground wire of a signal wire, LVDS use the signal wire transmission of one line letter that two are respectively the ends P and N-terminal
Number, when the ends P level is higher than N-terminal level, signal 1, on the contrary signal is 0.Amplified scintillation pulse is signally attached to FPGA
The ends P of the LVDS pins of subcard 321, the output of D-A converting circuit 323 are connected to the N-terminal of the LVDS pins of FPGA,
FPGA subcards 321 are programmed D-A converting circuit 323, the voltage that setting D-A converting circuit 323 exports
It is worth size, as preset reference voltage level.Because the number of the reference voltage level (or voltage threshold) of acquisition subcard 32 is 4, therefore
4 pairs of LVDS pins are corresponded to when per scintillation pulse signal sampling all the way, specific correspondence is：Amplified scintillation pulse signal one
It is divided into four, is connected to the ends P of 4 pairs of LVDS pins, D-A converting circuit 323 exports four reference voltage levels in gradient,
It is connected to the N-terminal of 4 pairs of LVDS pins.Per scintillation pulse signal all the way after LVDS pins input FPGA subcards 321, all by
4 road square waves are converted to, can indicate that scintillation pulse signal is turned over the time of reference voltage level from low to high on the rising edge of square wave,
As shown in the t1-t4 in Fig. 5；It can indicate that scintillation pulse signal is turned over reference voltage level from high to low on the failing edge of square wave
Time, as shown in the t5-t8 in Fig. 5.
Further, the acquisition subcard 32 in the present invention and FPGA motherboards 11 can be integrated in same FPGA plates, at this point,
Subcard 32 is acquired using logic unit makeup time-digital quantizer inside FPGA, when m- digital quantizer come for measuring
It from edge arrival time (including rising edge and failing edge) of the trigger signal s in physiological signal probe 2 and exports, and is sentenced with this
When disconnected trigger signal is high, when to be low, finally screens imaging data accordingly.
When m- digital quantizer be made of a coarse counter and a carefully counts device.By coarse counter output value and
The value of carefully counts device output is merged by certain relationship, so that it may to obtain the edge arrival time of trigger signal s.Specifically, slightly
Counter is driven by a clock signal, often spends a clock cycle, and the count value of coarse counter output adds 1, by current meter
Numerical value is multiplied by a clock cycle and the current thick time can be obtained.When trigger signal s edge arrive when, when it is m- number conversion
Device records the count value of coarse counter output this moment, and is denoted as N.If the clock cycle is denoted as Tc, then the edge of trigger signal s
The thick time reached can be expressed as N*Tc.The time resolution of coarse counter be as unit of the clock cycle, but for
For FPGA, the frequency of clock signal cannot be improved without limitation, to further increase time resolution, it is necessary to be introduced thin
Counter.Delay line of the realization of carefully counts device based on an output temperature code, thermometer code include several 0 and 1, on delay line
Thermometer code the characteristics of be side be 0 entirely, the other side be entirely 1,0 and 1 number there are shifting relationship, and 0 number
Mesh and 1 the sum of number are equal to the overall length of thermometer code, for example, 1110000 be the one section of thermometer code formed by 31 and 50,0
Boundary with 1 represents the edge of measured signal, by the number of number 0 or 1, multiplied by the time span represented with each 0 or 1, just
The thin time that the edge of measured signal transmits on delay line can be calculated.Therefore, the edge arrival time of trigger signal s is just etc.
In the sum of thick time and thin time.By delay line, when m- digital quantizer time resolution can be increased to and be better than
100 picoseconds.
Specifically in the present invention, as shown in fig. 6, clock distributing equipment forms delay line using the logic unit on FPGA,
The serial adder that the essence of delay line is made of several full adders 324, each full adder 324 have carry input and it is defeated
The port gone out, these ports join end to end, the carry-out of upper level full adder 324 be connected to next stage full adder 324 into
Position input.For convenience of description, it is shown in Fig. 6 be 8 bit of bit wide serial adder, which has
Two inputs 111 and 222, one of input 111 are set as 8 binary constants 11111111, another input 222 is number
Measured signal (such as trigger signal s), less than 0 polishing of part of 8 bits after change.When the rising edge of measured signal arrives
When, the digital level of measured signal changes to 1 from 0, and the result of calculation of serial adder is not to become full 0 at once, first to be measured
The result of calculation of that nearest full adder 324 of signal becomes 0, and then the carry signal of this full adder 324 becomes 1 simultaneously by 0
It is transmitted to next stage；The result of calculation for being subsequently positioned at the full adder 324 of the second level becomes 0, and carry signal becomes 1 by 0, then passes
It is delivered to next stage, and so on.The transmission of carry signal needs the time, and carry signal is generated to (n+1)th grade from n-th grade of full adder
Full adder generates carry signal interlude and is usually less than 100 picoseconds, and carry signal often transmits level-one, and thermometer code includes 0
Number just add 1.
Similarly, when the digital level of measured signal changes to 0 from 1, the result of calculation of serial adder is not to become at once
Complete 1, the result of calculation of that nearest from measured signal first full adder 324 becomes 1, and carry signal is become 0 by 1 and transmitted
To next stage, until the result of calculation of all full adders 324 all becomes 1, as shown in Figure 7.
When m- digital quantizer it is defeated using clock signal (identical with the clock signal of a coarse counter) sampling delay line
The thermometer code gone out.When side highest order (MSB) of a certain moment thermometer code is 1, and the side lowest order (LSB) is 0, show signal
Rising edge be detected, numerical value of 0 number as carefully counts in the thermometer code exported on statistical delay line.When a certain moment
Side highest order (MSB) of thermometer code is 0, when the side lowest order (LSB) is 1, shows that the failing edge of signal is detected, and is counted
1 number is as carefully counts in the thermometer code exported on delay line.For Fig. 6 and 8 thermometer codes shown in fig. 7, thermometer code
Including 1 or 0 number be 0 to 8, the binary number representation of 4 bits can be used, but in the actual realization process of the present invention
In, when m- digital quantizer use 128 thermometer codes, 1 or 0 number that thermometer code includes is 0 to 128, with 8 bits
Binary number representation.The transfer process of above-mentioned thermometer code to carefully counts is completed by encoder.
For the edge of each trigger signal s, when m- digital quantizer can all provide one and thick count and carefully counts.Such as
Shown in Fig. 8, the edge arrival time T=T of trigger signal sc×N-To× M, wherein the thick time is Tc× N, thin time are To×
M；TcIt is given value for a clock cycle；N is the count value slightly counted；ToIt is putting down per level-one thermometer code carry on delay line
The equal time；M is the count value of carefully counts.
Per the average time T of level-one thermometer code carry on delay lineoAligning step can be first passed through in advance to obtain.Due to carefully counts
It is to be latched once every a clock cycle, so the thin time maximum that carefully counts represent is a clock cycle.Therefore, Xiang Yan
Slow line inputs enough and the incoherent random signal of clock signal, the thermometer code counted and it is thin to find out maximum
Count value.Again with a clock cycle divided by this maximum carefully counts value can be obtained by delay line per level-one thermometer code into
The average time T of positiono。
Acquisition subcard 32 passes through several data lines transmission datas, wherein a data wire transmission data significance bit, one
Data line transfer synchronizing clock signals, two pairs of data lines for meeting differential level standard are received from the complete of clock distributing equipment 1
Office clock signal and global reset signal, these data lines are first connected with the terminal of corresponding male and female connector respectively, then pass through
The terminal and FPGA motherboards 11 of male and female connector are connected with clock distributing equipment 1.
FPGA on FPGA motherboards 11 plays the role of data check, processing, forwarding and instruction processing.From acquisition subcard
32 data are received by the FPGA on FPGA motherboards 11, eventually by network interface transfers to extraneous computer.Network interface
Physical layer include networked physics layer chip 112, carrying magnetic transformer six class RJ45 sockets 113 and six class cables, can be with 10
Million, the work of 100,000,000 or 1000 megabits/three kinds of rates per second.Instruction from computer can also pass through network interface transfers
FPGA onto FPGA motherboards 11, FPGA execute different operations according to command content, such as set voltage threshold, obtain real on plate
Shi Wendu etc., and return to corresponding parameter.
All make respective FPGA normal operations with some necessary peripheral circuits on acquisition subcard and motherboard.Periphery
Circuit include it is a piece of meet SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) agreement, capacity is not small
In 64 megabits of flash chips storing the firmware program of FPGA, a piece of EEPROM (electrically erasable
Programmable read-only memory, Electrically Erasable Programmable Read-Only Memory) chip 117 is storing acquisition subcard
Parameter, a piece of temperature sensor chip to detect in real time acquisition subcard temperature, these belong to the routine of this field
Technological means, herein no longer.
Fig. 9 be according to the connection diagram of the clock distributing equipment of the digital PET system of Fig. 1, as shown in Figure 9, the present invention
Clock distributing equipment 1 include a clock module, which includes that source crystal oscillator 13, clock board 18, clock are fanned out to buffering
Device 17, touch-switch 40, out connector 70 and input connector 50, wherein be provided on clock board 18 phaselocked loop 12 and when
Between measurement module, there is source crystal oscillator 13 to be connect by a pin of clock board 18 with phaselocked loop 12, have source crystal oscillator 13 generate first
First clock signal a is simultaneously sent to phaselocked loop 12 by clock signal a；A pair of of difference output that phaselocked loop 12 passes through clock board 18
Pin is connected to a pair of of differential input end of clock fan out buffer 17, and phaselocked loop 12 carries out again after receiving the first clock signal a
Frequently, scaling down processing and second clock signal b is formed, second clock signal b is Low Voltage Differential Signal (Low-Voltage
Differential Signaling, LVDS) form, phaselocked loop 12 by second clock signal b be sent to clock be fanned out to it is slow
Rush device 17；Phaselocked loop 12 is connect with time measurement module simultaneously, and the first clock signal a can be converted to third by phaselocked loop 12 simultaneously
Clock signal c is sent to time measurement module；Touch-switch 40 is connect with clock board 18 by a pair of pins, and touch-switch 40 exists
When pressing and discharging, the output of touch-switch 40 can switch between opposite high and low level f, and FPGA motherboards 11 can pass through lock
The first clock signal a that phase ring 12 receives samples the high and low level f that touch-switch 40 exports；Later, clock board 1811
Internal respective logic generates 12 tunnel reset signals, these reset signals are by the pin of clock board 18 with the second low-voltage differential
The form of signal n is exported to 12 out connectors 70；Input connector 50 is communicated to connect with time measurement module, physiology letter
Number probe 2 generate trigger signal s pass through input connector 50 enter clock board 18 time measurement module；Clock is fanned out to buffering
Device 17 is communicated to connect in the form of PCB difference cablings at least two-way out connector 70, and clock fan out buffer 17 is according to second
Clock signal b forms synchronizing clock signals e and exports synchronizing clock signals e by out connector 70, out connector 70
With on FPGA motherboards 11 global clock and reset input interface 115 connect with transmit synchronizing clock signals or synchronous reset letter
Number；
It is worth noting that, in the embodiment in fig. 9, phaselocked loop 12 is integrated on clock board 18, phaselocked loop 12 is connected to
Between the single ended input pin of clock board 18 and a pair of of difference output pin, there is source crystal oscillator 13 to pass through single ended input pin and locking phase
Ring 12 connects, and phaselocked loop 12 is connect by difference output pin with the one pair of which differential input end of clock fan out buffer 17,
So that phaselocked loop 12 can export second clock signal b to clock fan out buffer 17.
In the embodiment in fig. 9, clock distributing equipment 1 of the invention further includes other interfaces 114 (Fig. 3), such as gigabit
Ethernet interface 80 and serial ports 90, wherein gigabit Ethernet mouth 80 and serial ports 90 are communicated with field programmable gate array chip respectively
Connection, clock module connect by gigabit Ethernet mouth 80 and serial ports 90 with client communication so that user pass through it is mating
Upper computer software, clock module can be sent instructions to from client, in real time change phaselocked loop 12 parameter, when reaching modification
The purpose of the parameters such as frequency, phase, the duty ratio of clock signal.It is logical between gigabit Ethernet mouth 80 and serial ports 90 and clock board 18
Letter connection can be completed by arbitrary form, for example, several pins by field programmable gate array chip are first connected to communication
Then chip is connected to gigabit Ethernet mouth and serial ports by communication chip again, details are not described herein.
There are two types of operating modes for the clock distributing equipment tool of the present invention：Host mode and slave mode.Below in conjunction with the accompanying drawings
2, the operating mode of the clock distributing equipment of the present invention is described in detail in Fig. 9, Figure 11 and specific embodiment.
(1) host mode
The generation and output of clock signal：
There is source crystal oscillator 13 to generate the first clock signal that a frequency is 50MHz, first clock signal is defeated by pin
Enter phaselocked loop 12, phaselocked loop 12 carries out the clock signal processing of frequency multiplication, frequency dividing, passes through a pair of of difference of clock board 18 later
A pair of of differential input end of output pin and the first clock fan out buffer 17 is exported in the form of LVDS differential levels to
One clock fan out buffer 17.Under host mode, slide switch 14 is pushed left side, and output one is the phase that unit is " 1 "
To high level, which is exported from another pair pin to the first clock again by pin input clock plate 18, the high level
Fan out buffer 17 draws high the level of the strobe pin of the first clock fan out buffer 17.First clock fan out buffer 17
The clock signal for carrying out phase locked loop 12 is fanned out to as 12 tunnels, the output in the form of LVPECL differential levels, using some ends
Connecting resistance and capacitance are connected to 12 out connectors 70 finally by stringent PCB (printed circuit board) difference cabling.Together
When, clock distributing equipment can be communicated by serial ports 90 in figure and gigabit Ethernet mouth 80 and PC.User uses mating upper
Machine software sends instructions to clock module from PC, changes the parameter of phaselocked loop in real time, to reach the frequency of modification clock signal
The purpose of the parameters such as rate, phase, duty ratio.
The generation and output of reset signal：
Since phaselocked loop 12 is integrated on clock board 18, clock board 18 can latch the first low-voltage of the output of phaselocked loop 12
The rising edge of differential signal.When touch-switch 40 is pressed, which becomes low level from high level, passes through clock board 18
Internal respective logic generates 12 tunnel reset signals.These reset signals are by the pin of clock board 18, with LVDS level
Form exports, and reset signal is connected to 12 using some terminating resistors and capacitance, finally by stringent PCB difference cablings
A out connector 70.User can also use mating upper computer software, and reset instruction is sent to clock module from PC.It resets
Instruction include reset duration, therefore reset duration be can be customized.
The processing of trigger signal：
1 usage time of clock distributing equipment-digital quantizer measures trigger signal and is converted between low level and high level
Time, when m- digital quantizer principle had been described in above.As shown in Figure 10, each event is adjacent by two
Rising edge and failing edge composition, p1 and q1 are combined and represent one section of triggering level, defeated from Ethernet interface as an event
Go out.Computer receives the edge arrival time information of the trigger signal s of the transmission of clock distributing equipment 1, recovers trigger signal s
Shape, filter out trigger signal s be high period corresponding detector data.
(2) slave mode
The output of clock signal：
Clock signal from host passes through the input connector 50 in Fig. 9, is connected to second clock fan out buffer 60
And it is fanned out to and is in addition connected all the way for two-way wherein being connected to the first clock fan out buffer 17 by differential input end all the way
To the global clock input pin of clock board 18.Under slave mode, slide switch 14 is pushed right side, and one unit of output is
The opposite low level of " 0 ", the low level is by pin input clock plate 18, then exports to the first clock and fan from another pin
Go out buffer 17, the level of the strobe pin of the first clock fan out buffer 17 is dragged down.First clock fan out buffer 17
Clock signal from second clock fan out buffer 60 is fanned out to as 12 tunnels, the output in the form of LVPECL differential levels, then
By some terminating resistors and capacitance, 12 out connectors 70 are connected to finally by stringent PCB difference cablings.From
Under machine pattern, clock distributing equipment does not have the ability of independent output clock signal.
The output of reset signal：
Reset signal from host is sent to the clock board 18 of slave by pin after input connector 50, when
Clock plate 18 latches the reset signal with the clock signal that second clock fan out buffer 60 inputs, and is then passed through inside clock board 18
12 tunnel reset signals are generated after crossing respective logic processing, are exported in the form of LVDS differential levels.Reset signal passes through FPGA
The pin of chip is sent to out connector using some terminating resistors and capacitance finally by stringent PCB difference cablings
70.Under slave mode, clock distributing equipment does not have the ability of independent output reset signal.
Again as shown in Fig. 2, when the quantity of the pet detector module 3 worked at the same time is less than 12, PET system of the invention
It only include a clock distributing equipment 1.Single clock distributing equipment 1 includes 12 out connectors 70, when slide switch 14
At left side, single clock distributing equipment 1 itself is enough to provide the output of 12 road synchronised clocks/reset signal.Each output
Connector 70 has two pairs of pins, and since clock signal and reset signal export all in the form of differential level, a pair of pins is used
In output clock signal, another pair pin is used for output reset signal.There are one for same in each pet detector module 3
The input connector of clock/reset signal is walked, the input connector is identical with the model on clock distributing equipment 1, and has and match
The cable of set.When pet detector module 3 works normally, the clock signal that clock distributing equipment 1 exports is uninterrupted by cable
Ground is sent to pet detector module 3, its internal sequential logic work, reset signal is driven to maintain opposite height electricity always
It is flat.When initializing the working condition of pet detector module 3, reset signal is switched to low level, to reset pet detector
Sequential logic inside module 3.
Further, as shown in figure 11, according to another embodiment of the invention, when the pet detector mould worked at the same time
When the quantity of block 201 is more than 12, the fan-out capability of single clock distributing equipment has been insufficient for demand.At this point, PET system packet
The cascade of multiple clock distributing equipments is included, cascade herein refers to a kind of connection type, i.e. the output of host is connected to slave
Input.Reserved one input connector for synchronised clock/reset signal input on each clock distributing equipment, the input
Connector is identical with the model of the out connector for output.When the quantity of the pet detector module 103 worked at the same time is more than
12 be less than or equal to 144 when, need two-stage cascade.Wherein, a clock distributing equipment 110 is taken, its slide switch is pushed into left side,
As host；The slide switch of remaining clock module 111,112,113 pushes right side, as slave.By the output of host 110
The one-to-one connection of input connector cable of connector and slave 111,112,113, then by the defeated of slave 111,112,113
Go out the input connector that connector is connected to each pet detector module 103, as shown in solid arrow in Fig. 3.It is detected in PET
Device module 103 work normally when, host 110 export clock signal be sent to incessantly by cable slave 111,112,
113, then it is sent to each pet detector module 103 incessantly by cable via slave 111,112,113.It is detected in PET
When device module 103 works normally, reset signal maintains always opposite high level, when initialization pet detector module 103
When working condition, reset signal is switched to low level, to reset the sequential logic inside pet detector module 103.
Further, according to still another embodiment of the invention, when the quantity of the pet detector module worked at the same time is big
When 144, the fan-out capability of the clock distributing equipment of two-stage cascade composition has been insufficient for demand, needs correspondingly to increase at this time
Add cascade, such as three-stage cascade, can support most 1728 pet detector modules, is fully able to meet the need for building clinical PET
It asks.Specifically, a clock distributing equipment is taken, its slide switch is pushed into left side, as host；Remaining six clock distribution
The slide switch of device pushes right side, as slave, wherein three clock distributing equipments are as the first slave, the other three clock
For distributor as the second slave, the input connector of the out connector of host and the first slave uses the one-to-one company of cable
Connect, the input connector of the out connector of the first slave and the second slave uses the one-to-one connection of cable, the second slave it is defeated
Go out the input connector that connector is connected to each pet detector module.When pet detector module works normally, host is defeated
The clock signal gone out is sent to slave incessantly by cable, then is sent to PET spies incessantly by cable via slave
Survey device module.When pet detector module works normally, reset signal maintains always high level, when initialization pet detector mould
When the working condition of block, reset signal is switched to low level, to reset the sequential logic of pet detector inside modules.This field
Technical staff is it should be understood that the cascade in the present invention can continue to increase to required number of channels, it is not limited to three-level
Cascade, if cascade series is n, the maximum number of the drivable pet detector module of interconnection system is m, then m=12n。
(3) to the screening of digitlization pet detector output data
It is connected by input connector 50 between clock distributing equipment 1 and the physiological signal probe 2 of the present invention.The input connects
It connects device 50 and a pair of of self-locking connector (self-locking connector) can be used, self-locking connector includes stand and connects
Head, stand are installed on 1 side of clock distributing equipment, and connector is installed on the side of physiological signal probe 2, by self-locking connector
Connector is pushed into stand in an axial direction, and the bayonet inside self-locking connector meshes together, you can connects connector and stand；
By the both sides of crimp head, the connector of self-locking connector is released, you can disconnect.Input connector 50 ensure that physiology is believed
Number probe 2 and clock distributing equipment 1 between secured connection, be also convenient for physiological signal probe 2 dismounting and upgrading.It is inputting
Under the premise of the model of connector 50 determines, user can be the pluggable physiological signal probe of different application Scenario Design 2.
When clock distributing equipment 1 works, physiological signal probe 2 is converted to the electricity physiological signal of object to be measured in real time
Trigger signal s, trigger signal s are single pass square-wave signal, only opposite high level and low level two states.When specific
Electricity physiological signal, when occurring such as electrocardio, brain electricity, electromyography signal, the trigger signal s of 2 output of physiological signal probe becomes high electricity
It is flat, it is other in the case of trigger signal s maintain low level state.Trigger signal s is connected to FPGA motherboards by input connector 50
The time measurement module of 11 time measurement module, FPGA motherboards 11 receives and processes trigger signal s.Trigger signal s is symbol
The arbitrary signal of LVDS level standards is closed, such as the gate-control signal that signal generator generates.When trigger signal s is high level
Between in section, the data that pet detector module 3 acquires are effective, are low level time interval, pet detector in trigger signal s
The data invalid that module 3 acquires.
When pet detector module 3 works normally, the synchronizing clock signals that clock distributing equipment 1 exports pass through the company of output
It connects device and cable and is sent to pet detector module 3 incessantly, the sequential logic work inside driving pet detector module 3.
Synchronous reset signal maintains high level when pet detector module 3 works, and only is needing to initialize pet detector module
When working condition, synchronous reset signal can just be changed into low level, to reset the sequential logic of pet detector inside modules, together
Step reset signal is released after continuing for some time, and then becomes high level again.If connected with clock distributing equipment 1
The number of pet detector module is more than 1, after it experienced the change procedure of " high-low-high " of synchronous reset signal, multiple PET
It can reach between detector module synchronous.
Pet detector module continuously transmits data to interchanger 4, and interchanger 4 is continuously passed to client 5
After sending data, client to receive the edge arrival time information of the trigger signal s of clock distributing equipment transmission, recover tactile
The shape of signalling s filters out the period corresponding collected data of pet detector module that trigger signal s is high level,
Reuse the data imaging screened.
The interchanger used in the present invention has the socket and several gigabit Ethernet mouths of several 10,000,000,000 multimode fibres
To forward the data from pet detector module, clock distributing equipment and computer.Pet detector module and clock point
There are respective IP address and MAC Address with device, they are connected by category-six twisted pair with the gigabit Ethernet mouth of interchanger,
The local network that rate is 1000Mbps is established to connect.Computer tool there are one 10,000,000,000 optical network adapters and several 10,000,000,000
The socket of multimode fibre, interchanger and computer use SFP (Small Form Pluggable) optical module, pass through multimode light
Fibre connection.When digital PET system works, the scintillation pulse data of pet detector module acquisition and clock distributing equipment acquisition
Trigger signal data interchanger is sent to by category-six twisted pair, passing through SFP optical modules and multimode fibre by interchanger forwards
To computer.Computer disposal user instruction, is packaged into data packet, by 10,000,000,000 optical network adapters on computer and more
Director data packet is sent to interchanger by mode fiber according to ICP/IP protocol or udp protocol, and interchanger again turns director data packet
It is sent to pet detector module or clock distributing equipment.
Continuously output multi-channel synchronizing clock signals, every synchronizing clock signals all the way all connect the clock distributing equipment
PET is set to detect to drive the sequential logic of digitlization pet detector inside modules to a digitlization pet detector module
Device module works normally.Also exportable Multi-path synchronous reset signal, every synchronous reset signal all the way equally connect clock distributing equipment
It is connected to a digitlization pet detector module, but synchronous reset signal is not lasting, is needing to initialize pet detector
Reset signal just occurs when the working condition of module, and the internal timer of all pet detector modules is in synchronous reset signal
Effect is lower to reset, and data buffer storage empties.After synchronous reset signal disappears, all pet detector modules restart work, PET
The time shaft of detector module is aligned, into synchronous regime.
Multipath clock distributor provides reference clock for digitlization PET system, and clock distributing equipment itself is also with this
Clock is reference, records the time that specific electricity physiological signal occurs, then these temporal informations are transferred to client, client
The digitlization collected data of pet detector module are screened according to these temporal informations in end on a timeline, only retain
The data for the time interval that electricity physiological signal occurs, the data that PET system only handles after screening can be obtained interested image,
Which greatly enhances the efficiency of imaging.
In addition, the digital PET system in the present invention includes several pet detector modules, scale can pass through fluctuation number
The number of word pet detector module and the number of clock distributing equipment carry out arbitrary change；Digital PET system in the present invention
Pet detector module includes probe, acquisition subcard and FPGA motherboards, and probe and acquisition subcard pass through connector and FPGA motherboards
Connection, multiple probes can be connected on the same FPGA motherboards, and multiple subcards can be connected on the same FPGA motherboards.The present invention
In the pet detector module of digital PET system it is preferable to use silicon photomultipliers (SiPM) that gammaphoton is converted to flicker
Pulse, usage time-digital quantizer obtain time and the information of voltage of scintillation pulse signal.Using silicon photomultiplier
(SiPM) array reads scintillation pulse, is read respectively to each unit of SiPM arrays, and maximum count rate compares existing PET
System can be significantly increased.The mode of existing PET system generally use channel multiplexing, such as the SiPM arrays in 36 channels finally close
And at all the way, timesharing read output signal is especially penetrating source radiation activity height although so reducing hardware cost reduces counting rate
When.
It is provided by the invention number PET system, with digital pet detector module instead of digiboard in the prior art,
Analog board meets plate, simplifies the structure of PET system.The step of cancelling after meeting plate, meeting is completed on computers, is calculated
Calculation power and algorithm all flexibly configurables of machine；The function that trigger signal samples is integrated in clock distributing equipment by the present invention no matter
How small the scale of digital PET system have, and all has complete gate sampling functions, and without the additional sampling apparatus of introducing；And
And the trigger signal input that the present invention uses is a single pass square-wave signal, as long as the signal for meeting the standard can be used as
Trigger signal.The present invention uses modular design, can arbitrarily increase and decrease the number of pet detector module, and correspondingly change
The scale of clock distributing equipment has flexible characteristic, easy to repair and upgrading.
In addition, in the present invention, the scintillation pulse sampling section of digital pet detector module is alternatively at digital sample electricity
Road adds the structure of constant fraction discriminator discriminator, as shown in figure 12.First, the digital pet detector module of scintillation pulse input, number are adopted
For sample circuit to being AD converted after scintillation pulse amplification, shaping, the transformed digital signal of FPGA motherboards processing simultaneously obtains detection
To the energy information of event.Constant fraction discriminator discriminator generates one when the 511kev electron volts peak positions of scintillation pulse arrive and touches
It signals, which is TTL square waves, and rising edge indicates that the time that scintillation pulse arrives, FPGA motherboards measure the rising of the signal
Along arrival time, the temporal information of event is detected.Digital pet detector module passes the energy of event, position, temporal information
It is defeated to arrive computer, carry out image reconstruction and processing.
In addition to this, some components of PET system can be replaced with following scheme：Digital pet detector module and clock
The FPGA motherboards of distributor can use CPLD (Complex Programmable Logic Device, field-programmable gate array
Row) motherboard replacement；When m- digital quantizer can not use LE (Logic elements, the Altera Cyclone systems of FPGA
The basic logic unit of row low side FPGA) it realizes, the Carry4 (arithmetical unit that Xilinx FPGA have) of FPGA can be used
M- digital quantizer chip when realizing, or using individual；The level standard of trigger signal input can be other than LVDS
Other any levels.
Above-described, only presently preferred embodiments of the present invention is not limited to the scope of the present invention, of the invention is upper
Stating embodiment can also make a variety of changes.Made by i.e. every claims applied according to the present invention and description
Simply, equivalent changes and modifications fall within the claims of patent of the present invention.The not detailed description of the present invention is
Routine techniques content.
Claims (20)
1. a kind of number PET system, the number PET system has clock distributing equipment, several pet detector modules, hands over
It changes planes and computer, which is characterized in that
The number PET system further includes physiological signal probe, wherein the physiological signal probe and the clock distributing equipment
Communication connection, the clock distributing equipment are communicated to connect with multiple pet detector modules, the pet detector module with
The switch communication connection, the clock distributing equipment are also connect with the switch communication, the interchanger and the meter
Calculation machine communicates to connect；
Each pet detector module includes scintillation pulse probe, acquisition subcard and FPGA motherboards, the scintillation pulse
Probe is connect by the acquisition subcard with the FPGA motherboards, the FPGA motherboards and the clock distributing equipment communication link
It connects, the acquisition subcard includes FPGA subcards, operational amplification circuit and D-A converting circuit, wherein FPGA
Card is communicated to connect with the operational amplification circuit and the D-A converting circuit respectively, the operational amplification circuit difference
It is communicated to connect with the acquisition subcard and scintillation pulse probe.
2. number PET system according to claim 1, which is characterized in that the clock distributing equipment includes：
There is source crystal oscillator, it is described to there is source crystal oscillator to generate the first clock signal；
There is phaselocked loop, the phaselocked loop to have source crystal oscillator communication connection, the phaselocked loop to connect with described for clock board, the clock board
It receives and handles first clock signal to form second clock signal；
Clock fan out buffer, the clock fan out buffer are communicated to connect with the phaselocked loop, the clock fan out buffer
The second clock signal is received and processed to form synchronizing clock signals；
Touch-switch, the touch-switch are connect with the clock board to send reset signal, the reset to the clock board
Signal forms synchronous reset signal after clock board processing；
Input connector, the physiological signal probe are communicated to connect by the input connector and the clock board；
At least two-way out connector, when the out connector is communicated to connect with the clock fan out buffer to receive synchronous
Clock signal, the out connector are connect simultaneously with the clock board to receive the synchronous reset signal, and the clock board is logical
The out connector is crossed to communicate to connect with the FPGA motherboards.
3. number PET system according to claim 1, which is characterized in that the scintillation pulse probe is connect with a public affairs
Device matches, and the both ends of the acquisition subcard are matched with two public connectors respectively, even with the matched public affairs of scintillation pulse probe
It connects device and is communicated to connect by a pair of of female connectors between the matched public connector of the acquisition subcard, with the acquisition
Another matched public connector of subcard is connect by corresponding female connectors with the clock distributing equipment.
4. number PET system according to claim 1, which is characterized in that the scintillation pulse probe includes scintillation crystal
Array and silicon photomultiplier are coupled between the scintillation crystal array and the silicon photomultiplier by couplant, described
Separated by barium sulfate coating between scintillation crystal in scintillation crystal array, crystal array surface is wrapped up with masking foil, silicon light
Electric multiplier tube further passes through printed circuit board output signal.
5. number PET system according to claim 1, which is characterized in that be provided with several on the FPGA motherboards and connect
Mouthful, the FPGA motherboards are connect by the interface therein with the acquisition subcard.
6. number PET system according to claim 2, which is characterized in that the phaselocked loop passes through a single ended input pin
It is integrated on the clock board with a pair of of difference output pin, it is described to there is source crystal oscillator to pass through the single ended input pin and the lock
Phase ring connects, and the phaselocked loop is connect by the difference output pin with the differential input end of the clock fan out buffer.
7. number PET system according to claim 2, which is characterized in that the clock fan out buffer is walked with PCB difference
Line form is connect with out connector described at least two-way.
8. number PET system according to claim 2, which is characterized in that the clock board has time measurement module, institute
It includes thick timer and thin timer to state time measurement module, and the thick timer calculates the thick time of the trigger signal, institute
The thin time that thin timer calculates the trigger signal is stated, the time measurement module is according to the thick time and the thin time
Measure the edge arrival time of the trigger signal.
9. number PET system according to claim 8, which is characterized in that the thin timer is inside the clock board
An output temperature code delay line, the thermometer code include several continuously arranged 0 and 1, the thin timer according to
Described 0 and 1 put in order and number calculates edge arrival time of the trigger signal.
10. number PET system according to claim 9, which is characterized in that the delay line of the thin timer includes
Several concatenated full adders, the thin timer calculate the thin time according to the thermometer code that the full adder exports.
11. number PET system according to claim 10, which is characterized in that there are two defeated for each full adder tool
Enter end, one of them described input terminal input comes from the binary constant of the clock board, described in the input of another input terminal
Trigger signal.
12. number PET system according to claim 2, which is characterized in that the synchronizing clock signals with it is described synchronous multiple
Position signal is the form of differential level.
13. number PET system according to claim 2, which is characterized in that the input connector connects for self-locking
Device, the self-locking connector include stand and connector, and the stand is connect with the field programmable gate array chip, described
Connector is connected with physiological signal probe.
14. number PET system according to claim 2, which is characterized in that the interchanger and the clock distributing equipment
The clock distributing equipment connected with socket by gigabit Ethernet physical chip to receive first clock signal, institute
Second clock signal and the synchronizing clock signals are stated, the client is connect with the switch communication to receive the friendship
It changes planes the data of transmission.
15. number PET system according to claim 14, which is characterized in that the out connector and PET detections
Device module is 12, and each out connector is correspondingly connected with a pet detector module.
16. number PET system according to claim 14, which is characterized in that the pet detector module is exchanged with described
It is connected with each other by six class cables between machine.
17. number PET system according to claim 2, which is characterized in that the touch-switch includes pressing and discharging two
Kind pattern, when the touch-switch is pressed, the clock board generates 12 tunnel reset signals.
18. number PET system according to claim 2, which is characterized in that there is the slide switch left and right two to open
Close, when the slide switch pushed left side when, the slide switch to the clock board send one be unit be 0 it is opposite
Low level, the clock board will after the low level reverse phase output to the clock fan out buffer；When the slide switch
When being pushed right side, the slide switch sends the opposite low level that a unit is 1, the clock board to the clock board
By output after the high level reverse phase to the clock fan out buffer.
19. number PET system according to claim 18, which is characterized in that the number PET system includes multiple described
The slide switch of clock distributing equipment, one of them clock distributing equipment pushes left side, as host；Remaining institute
The slide switch for stating clock distributing equipment pushes right side, as slave；The out connector of the host and the slave
The one-to-one connection of input connector, the out connector of the slave connect with each pet detector module.
20. number PET system according to claim 18, which is characterized in that the number PET system includes multiple described
The slide switch of clock distributing equipment, one of them clock distributing equipment pushes left side, as host；Another part
The slide switch of the clock distributing equipment push right side, as slave, the slave include the first slave and second from
Machine, wherein the one-to-one connection of input connector of the out connector of the host and first slave, first slave
Out connector and second slave the one-to-one connection of input connector, the out connector of second slave with it is each
A pet detector module connection.
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| CN110544283A (en) * | 2019-09-06 | 2019-12-06 | 上海联影医疗科技有限公司 | PET reconstruction data screening method, device, terminal and storage medium |
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