CN108322679B - Circuit and system for eliminating dark current - Google Patents
Circuit and system for eliminating dark current Download PDFInfo
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- CN108322679B CN108322679B CN201711470532.1A CN201711470532A CN108322679B CN 108322679 B CN108322679 B CN 108322679B CN 201711470532 A CN201711470532 A CN 201711470532A CN 108322679 B CN108322679 B CN 108322679B
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
Abstract
The invention provides a circuit for eliminating dark current and an image sensor system, which are provided with a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, a fourth sampling capacitor and two auxiliary capacitors Cb1 and Cb2, wherein the dark current value is adjusted by matching the difference value of a coarse adjustment converter and a fine adjustment converter, the coarse adjustment converter and the fine adjustment converter can be circuit structures with any frameworks, and the coarse adjustment converter realizes coarse adjustment and the fine adjustment. By reading out the digital value of the dark current noise level of the dark pixel and feeding back the digital signal value to the coarse adjustment converter and the fine adjustment converter, when the effective pixel is read out, the noise level of the dark current is corrected by the coarse adjustment converter and the fine adjustment converter, so that the read data of the effective pixel does not contain the dark current noise, the dark current noise is effectively eliminated, the reduction of the dynamic range of the image sensor caused by the dark current is reduced, and the image quality of the image sensor is effectively improved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a circuit and a system for eliminating dark current.
Background
In a CMOS Image Sensor (CIS), dark current seriously affects the image quality of the image sensor, and the influence of the dark current on the imaging quality of the image sensor is mainly embodied in two aspects, namely firstly, the nonuniformity of the dark current is an important source of fixed mode noise in the CIS, so that the permeability of the image sensor is poor; secondly, the dark current can increase the average value of the whole image, especially at high temperature, the dark current value is increased significantly, so that the dynamic range of the image is reduced, and although the intrinsic dark current of the photodiode can be reduced in the manufacturing process and the uniformity is improved, the dark current noise still needs to be eliminated or suppressed during the later image processing to improve the image quality.
In a conventional circuit structure, DARK current correction is usually performed on a digital side, that is, an output average value of DARK Pixel array is firstly counted, and a DARK Pixel digital signal average value is subtracted from each Active Pixel digital signal, and the conventional DARK current correction causes a dynamic range of an image to be reduced, and especially under a high temperature condition, a DARK current value is increased.
The CMOS image sensor overall frame diagram is shown in fig. 1, where pixels include Dark pixels and Active pixels, and the average value of the digital signals output by the Dark pixels is subtracted from the digital signals finally output by each Active Pixel by conventional Dark current correction, which leads to a reduction in the dynamic range of the image.
A conventional Column-structured CMOS image sensor Column readout circuit (Read out circuit) is shown in fig. 2, and a timing diagram is shown in fig. 3, and its operation principle is as follows: when the row selection signal SEL is high, the Pixel (Pixel) signal value of a certain row is selected and output, the signal RX is high, the MOS transistor controlled by the signal RX is turned on, the signal of the Vfd node is reset to the PVDD voltage value, the signal RX is turned off, the clock feedthrough is performed due to the channel charge injection effect, and the node Vfd has no path to ground, the node Vfd will be kept lower than the PVDD voltage value, the reset signal Vrst of the Pixel (Pixel) is output, the signal RST _ COUNT is high, the counter is reset, when the first switch S1 is high, the comparator is reset, Vinp1 is vmm 1 which is the Vcm voltage Vcm (the comparator common mode voltage value), the Pixel output reset signal Vrst is sampled on the sampling capacitor Cs1, the signal TX Vsig is turned on, the voltage value of the Vinp1 is Vcm- (st-Vsig) is output, when the signal EN _ COUNT is high, and the counter starts to COUNT the ramp signal changes, the Vinm signal changes along with the ramp signal, when the comparator overturns, the counter stops counting, and outputs a digital signal D, wherein the output digital signal D is the photosensitive signal value of the PIXEL.
Disclosure of Invention
In order to overcome the above problems, the present invention is directed to provide a circuit for eliminating dark current, which performs dark current correction in the analog domain, thereby improving the dynamic range of an image.
In order to achieve the above object, the present invention provides a circuit for eliminating dark current, comprising:
the grid end of the first transistor is connected with the signal end TX, and the source end of the first transistor is grounded through a diode;
a gate end of the second transistor is connected with the signal end RX, and a source end of the second transistor is connected with a drain end of the first transistor and a gate end of the third transistor to a node Vfd; the drain end of the first transistor is connected with the drain end of the second transistor;
a source end of the third transistor is connected with a drain end of the fourth transistor;
a gate end of the fourth transistor is connected with the signal end SEL, and a source end of the fourth transistor is commonly connected with one end of the first sampling capacitor and grounded;
the other end of the first sampling capacitor, one end of the first auxiliary capacitor and one end of the first switch are connected to the input end of the amplifier;
the other end of the first auxiliary capacitor is connected with a fine regulation converter (fine dark); the other end of the first switch is connected with a VCM signal end;
one end of the second sampling capacitor is connected with the ramp generator, and the other end of the second sampling capacitor, one end of the second auxiliary capacitor and one end of the second switch are connected to the input end of the amplifier;
the other end of the second auxiliary capacitor is connected with a coarse regulation converter (coarse dark); the other end of the second switch is connected with a VCM signal end;
the first output end of the amplifier is connected with one end of the third sampling capacitor, and the second output end of the amplifier is connected with one end of the fourth sampling capacitor;
the other end of the third sampling capacitor is connected with a first input end of a comparator and one end of a third switch together;
the other end of the fourth sampling capacitor is connected with the second input end of the comparator and one end of the fourth switch together;
the first output end of the comparator is connected with the other end of the third switch;
the second output end of the comparator and the other end of the fourth switch are connected to the input end of a reverse diode;
the output end of the backward diode is connected with the input end of the counter;
the counter is connected with an EN _ COUNT signal end and an RST _ COUNT signal end and is provided with an output signal end.
In an embodiment, the first transistor, the second transistor, the third transistor and the fourth transistor are all MOS transistors of the same conductivity type.
In an embodiment, the first transistor, the second transistor, the third transistor and the fourth transistor are all NMOS transistors.
In one embodiment, the coarse adjustment converter implements coarse adjustment for rapidly adjusting the luminance value (DN value) of the dark current output, enabling rapid correction of the dark current noise level; the fine adjustment converter realizes fine adjustment, the amplitude of the fine adjustment is smaller than that of the coarse adjustment, and the fine adjustment converter is used for enabling the amplitude value of dark current output to be more accurate.
In order to achieve the above object, the present invention also provides an image sensor system for eliminating a dark current, comprising: a dark pixel array, an active pixel array, and the dark current elimination circuit of claim 1; the circuit for eliminating the dark current is connected with the dark pixel array and the effective pixel array;
the image sensor system counts the average value (Db) of the signals of the dark pixel array and outputs a digital signal.
When the signal terminal SEL is high, the circuit for eliminating the dark current outputs a pixel signal value of a certain row of the effective pixel array;
when the signal terminal RX is high, a first transistor controlled by the signal terminal RX is turned on, the node Vfd is reset to the voltage value PVDD, then the signal terminal RX is turned off, at the moment, the node Vfd does not have any path to the ground, the node Vfd is kept lower than the voltage value PVDD, the output reset signal of the pixel is set to Vrst, the RST _ COUNT signal terminal is high, and the counter is reset;
when the voltage of the first switch S1 is high, the comparator is reset, the voltage signal Vinp1 at the first input end is the voltage signal Vinm1 at the second input end is the voltage signal Vcm, and Vcm is the common-mode voltage value of the comparator;
the circuit for eliminating the dark current outputs a reset signal Vrst to be sampled to a first sampling capacitor Cs1, and initial voltage values of a coarse adjustment converter and a fine adjustment converter are sampled to a first auxiliary capacitor Cb1 and a second auxiliary capacitor Cb 2;
the signal terminal TX is opened, a photosensitive signal (Vsig) of the effective pixel array is output, and the coarse adjustment converter and the fine adjustment converter output a voltage signal difference value (Vdiff) needing to be adjusted; at the same time, the voltage value (Vinp1) at the first signal input terminal of the comparator jumps to Vcm- (Vrst-Vsig) -Vdiff;
when the signal end of the signal EN _ COUNT is high, the counter starts counting, the ramp signal (Vramp) sent by the ramp generator starts changing, the signal (Vinm) at the second input end changes along with the ramp signal, when the comparator turns over, the counter stops counting and outputs a digital signal (D), and the output digital signal (D) is the photosensitive signal value of the effective pixel array.
In one embodiment, when the image sensor system counts the average value (Db) of the signal of the dark pixel array, the digital output is not 0 and varies with the temperature.
In one embodiment, the voltage signal interpolation (Vdiff) is calculated by the formula Vdiff ═ Db × DRAD ÷ (2 × NAD); wherein, DRAD is the amplitude of the image sensor system, NAD is the precision of the image sensor system, and Db is the dark current noise digital signal output by the dark pixel.
In one embodiment, the coarse adjustment converter implements coarse adjustment for rapidly adjusting the luminance value (DN value) of the dark current output, enabling rapid correction of the dark current noise level; the fine adjustment converter realizes fine adjustment, the amplitude of the fine adjustment is smaller than that of the coarse adjustment, and the fine adjustment converter is used for enabling the amplitude value of dark current output to be more accurate.
In one embodiment, the fine adjustment is at a step size of no more than 1SLB of the image sensor system.
In one embodiment, the output voltage ranges of the coarse-adjustment converter and the fine-adjustment converter are both maximum amplitude values of dark current noise.
The circuit for eliminating the dark current is provided with a first sampling capacitor, a second sampling capacitor, a third sampling capacitor, a fourth sampling capacitor and two auxiliary capacitors Cb1 and Cb2, and the dark current value is adjusted by matching the difference value of a Coarse DAC (Coarse adjustment converter) and a Fine DAC (Fine adjustment converter), wherein the Coarse DAC and the Fine DAC can be circuit structures with any frameworks, the Coarse adjustment of the Coarse DAC is realized, and the Fine adjustment of the Fine DAC is realized. By reading out the digital value of the Dark current noise level of the Dark Pixel (Dark Pixel) and feeding back the digital signal value to the Coarse DAC and the Fine DAC, when the Active Pixel (Active Pixel) is read out, the noise level of the Dark current is recorded by the Coarse DAC and the Fine DAC, so that the read data of the Active Pixel does not contain the Dark current noise, the Dark current noise is effectively eliminated, the reduction of the dynamic range of the image sensor caused by the Dark current is reduced, and the image quality of the image sensor is effectively improved.
Drawings
FIG. 1 is a block diagram of a CMOS image sensor
FIG. 2 is a diagram of a conventional column readout circuit
FIG. 3 is a schematic diagram of the timing and significant node voltage output of the sensing circuit of FIG. 2
FIG. 4 is a diagram of a column readout circuit according to a preferred embodiment of the present invention
FIG. 5 is a timing diagram of the readout circuit of FIG. 4
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The present invention will be described in further detail with reference to the accompanying drawings 4 to 5 and specific embodiments. It should be noted that the drawings are in a simplified form and are not to precise scale, and are only used for conveniently and clearly achieving the purpose of assisting in describing the embodiment.
Referring to fig. 4, a circuit for eliminating dark current in the present embodiment includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a first sampling capacitor Cs1, a second sampling capacitor Cs2, a third sampling capacitor Cs3, a fourth sampling capacitor Cs4, a comparator, an amplifier, a diode, an inverse diode, a counter, a first auxiliary capacitor Cb1 and a second auxiliary capacitor Cb2, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and the like; in this embodiment, the first transistor to the fourth transistor are all MOS transistors of the same type, such as NMOS transistors.
Specifically, a gate terminal of the first transistor is connected to the signal terminal TX, and a source terminal of the first transistor is grounded through a diode; the grid end of the second transistor is connected with the signal end RX, and the source end of the second transistor, the drain end of the first transistor and the grid end of the third transistor are connected to a node Vfd; the drain end of the second transistor is connected with the drain end of the third transistor; the source end of the third transistor is connected with the drain end of the fourth transistor;
the gate end of the fourth transistor is connected with the signal end SEL, and the source end of the fourth transistor is commonly connected with one end of the first sampling capacitor Cs1 and is grounded; the other end of the first sampling capacitor Cs1, one end of the first auxiliary capacitor and one end of the first switch S1 are commonly connected to the input end inm of the amplifier; the other end of the first auxiliary capacitor Cb1 is connected to a FINE adjustment converter (FINE DAC); the other end of the first switch S1 is connected with a VCM signal end;
one end of the second sampling capacitor Cs2 is connected to the ramp generator, and the other end of the second sampling capacitor Cs2 is connected to the input terminal inp of the amplifier in common with one end of the second auxiliary capacitor Cb2 and one end of the second switch S2; the other end of the second auxiliary capacitor Cb2 is connected to a coarse adjustment converter (coarse dark); the other end of the second switch S2 is connected to the VCM signal terminal. Here, the coarse adjustment converter implements coarse adjustment for quickly adjusting the luminance value (DN value) of the dark current output, enabling quick correction of the dark current noise level; the fine adjustment converter realizes fine adjustment, and the amplitude of the fine adjustment is smaller than that of the coarse adjustment, so that the amplitude value of dark current output is more accurate. For example, the dark current output digital value Db is 100, and the voltage signal interpolation Db is drd/2 NAD to be adjusted, i.e., Vdiff (Db drd) ÷ (2 NAD), is converted according to a formula; wherein, DRAD is the amplitude of the image sensor system, NAD is the precision of the image sensor system, and Db is the dark current noise digital signal output by the dark pixel. For example, the sensor system is a 1V full-amplitude voltage 10-bit valid bit, the amplitude voltage calculated by the formula is about 97mV, that is, the difference between the output voltages of the coarse adjustment DAC and the fine adjustment DAC is 97mV, the coarse adjustment DAC adjusts, for example, 20mV for 1LSB because the amplitude range of the adjusted voltage is large, that is, it is necessary to adjust 4 steps of dark current to reach 80mV, of course, 2 steps are only required for 40mV for 1LSB, the amplitude range of the fine adjustment DAC is small, the voltage value of 1LSB (the 10 th power of 1/2 for 1LSB is about 1mV for 10 LSB for 10 valid bits of the sensor system for 1V full-amplitude voltage), 17 steps need to be adjusted, and 21 steps need to be adjusted in total. If all only fine adjustments require 97 steps and only coarse adjustments, then a very accurate voltage value is not achieved.
The first output end outp of the amplifier is connected with one end of the third sampling capacitor Cs3, and the second output end outm of the amplifier is connected with one end of the fourth sampling capacitor Cs 4; the other end of the third sampling capacitor Cs3 is commonly connected to a first input terminal inm of a comparator and one end of a third switch S3; the other end of the fourth sampling capacitor Cs4 is commonly connected with the second input terminal inp of the comparator and one end of the fourth switch S4;
a first output end of the comparator is connected with the other end of the third switch S3; the second output end of the comparator and the other end of the fourth switch S4 are commonly connected to an input end Vcom out of an inverse diode; the output end of the backward diode is connected with the input end of the counter;
the counter is connected with an EN _ COUNT signal end and an RST _ COUNT signal end and is provided with an output signal end.
The image sensor system of the present embodiment is described in detail next with reference to fig. 5. Fig. 5 is a timing diagram of the circuit for eliminating dark circuit according to the present embodiment.
An image sensor system for eliminating dark current of the present embodiment includes: a dark pixel array, an effective pixel array, and the circuit for eliminating dark current of the present embodiment; the circuit for eliminating dark current is respectively connected with the dark pixel array and the effective pixel array.
In this embodiment, the image sensor system obtains a signal average Db of the dark pixel array by statistics, and outputs a digital signal; it should be noted that this digital signal should ideally be 0, but in practice, due to the influence of dark current noise, the output of this digital signal is not 0 and varies with temperature.
Here, when the signal terminal SEL is high, the dark current eliminating circuit outputs a pixel signal value of a certain row of the effective pixel array; when the signal terminal RX is high, the first transistor controlled by the signal terminal RX is turned on to reset the node Vfd to the voltage value PVDD, and then the signal terminal RX is turned off, and due to the channel charge injection effect and clock feed-through, the node Vfd does not have any path to ground, the node Vfd will be kept lower than the voltage value PVDD, the output reset signal Vrst of the pixel is set, the RST _ COUNT signal terminal is high, and the counter is reset.
When the voltage of the first switch S1 is high, the comparator is reset, and the voltage signal Vinp1 at the first input terminal is equal to the voltage signal Vinm1 at the second input terminal is equal to the voltage Vcm, which is the common-mode voltage value of the comparator. The circuit output reset signal Vrst for eliminating the dark current is sampled to the first sampling capacitor Cs1, and the initial voltage values of the coarse adjustment converter and the fine adjustment converter are sampled to the first auxiliary capacitor Cb1 and the second auxiliary capacitor Cb 2. Then, the signal TX is turned on, a photosensitive signal (Vsig) of the effective pixel array is output, and the coarse adjustment converter and the fine adjustment converter output a voltage signal difference (Vdiff) needing to be adjusted; at the same time, the voltage value (Vinp1) at the first signal input terminal of the comparator jumps to Vcm- (Vrst-Vsig) -Vdiff. In this embodiment, the voltage signal interpolation (Vdiff) is calculated by the formula Db × DRAD/2NAD, i.e., Vdiff ═ (Db × DRAD) ÷ (2 × NAD); wherein, DRAD is the amplitude of the image sensor system, NAD is the precision of the image sensor system, and Db is the dark current noise digital signal output by the dark pixel. Here, the coarse adjustment converter realizes coarse adjustment, and the fine adjustment converter realizes fine adjustment; the fine adjustment step is not more than 1SLB of the image sensor system, and the fine adjustment step is 1 or 0.5LSB of the image sensor system. The output voltage ranges of the coarse-adjustment converter and the fine-adjustment converter are the maximum amplitude values of the dark current noise.
When the signal end of the signal EN _ COUNT is high, the counter starts counting, the ramp signal (Vramp) sent by the ramp generator starts changing, the signal (Vinm) at the second input end changes along with the ramp signal, when the comparator turns over, the counter stops counting and outputs a digital signal (D), and the output digital signal (D) is the photosensitive signal value of the effective pixel array.
In summary, the signal output by the effective pixel is calculated and adjusted by the coarse adjustment converter and the fine adjustment converter, and the dark current noise is subtracted in the analog domain, so that the phenomenon that the output caused by the dark current noise is not 0 is corrected, and the method for correcting the dark current noise level of the image sensor in real time is realized.
Although the present invention has been described with reference to preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments, but rather, may be embodied in many different forms and modifications without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (9)
1. A circuit for eliminating dark current, comprising:
the grid end of the first transistor is connected with a signal (TX), and the source end of the first transistor is grounded through a diode;
a second transistor, wherein the grid end of the second transistor is connected with a signal (RX), and the source end of the second transistor is connected with the drain end of the first transistor and the grid end of the third transistor to a node (Vfd); the drain end of the first transistor is connected with the drain end of the second transistor;
a source end of the third transistor is connected with a drain end of the fourth transistor;
a fourth transistor, a gate terminal of which is connected with a Signal (SEL), and a source terminal of which is commonly connected with one end of the first sampling capacitor and is grounded;
the other end of the first sampling capacitor, one end of the first auxiliary capacitor and one end of the first switch are connected to the input end of the amplifier;
the other end of the first auxiliary capacitor is connected with a FINE adjustment converter (FINE DAC); the other end of the first switch is connected with a (VCM) signal end;
one end of the second sampling capacitor is connected with the ramp generator, and the other end of the second sampling capacitor, one end of the second auxiliary capacitor and one end of the second switch are connected to the input end of the amplifier;
the other end of the second auxiliary capacitor is connected with a COARSE adjustment converter (COARSE DAC); the other end of the second switch is connected with a (VCM) signal end;
the first output end of the amplifier is connected with one end of the third sampling capacitor, and the second output end of the amplifier is connected with one end of the fourth sampling capacitor;
the other end of the third sampling capacitor is connected with a first input end of a comparator and one end of a third switch together;
the other end of the fourth sampling capacitor is connected with the second input end of the comparator and one end of the fourth switch together;
the first output end of the comparator is connected with the other end of the third switch;
the second output end of the comparator and the other end of the fourth switch are connected to the input end of a reverse diode;
the output end of the backward diode is connected with the input end of the counter;
the counter is connected with an EN _ COUNT signal end and an RST _ COUNT signal end and is provided with an output signal end.
2. The dark current eliminating circuit according to claim 1, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are all MOS transistors of the same conductivity type.
3. The dark current eliminating circuit according to claim 2, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are all NMOS transistors.
4. The dark current cancellation circuit of claim 1, wherein the coarse adjustment converter implements coarse adjustment for fast adjustment of the magnitude (DN value) of the dark current output to enable fast correction of the dark current noise level; the fine adjustment converter realizes fine adjustment, the amplitude of the fine adjustment is smaller than that of the coarse adjustment, and the fine adjustment converter is used for enabling the amplitude value of dark current output to be more accurate.
5. An image sensor system for eliminating dark current, comprising: a dark pixel array, an active pixel array, and the dark current elimination circuit of claim 1; the circuit for eliminating the dark current is connected with the dark pixel array and the effective pixel array;
the image sensor system counts a signal average value (Db) of the dark pixel array and outputs a digital signal;
when a signal terminal (SEL) is high, the circuit for eliminating the dark current outputs a pixel signal value of a certain row of the effective pixel array;
when the signal terminal (RX) is high, a first transistor controlled by the signal terminal (RX) is conducted to reset the node (Vfd) to the voltage value (PVDD), and then the signal terminal (RX) is disconnected, at the moment, the node (Vfd) has no path to the ground, the node (Vfd) is kept lower than the voltage value (PVDD), the output reset signal of the pixel is set to Vrst, the RST _ COUNT signal terminal is high, and the counter is reset;
when the voltage of the first switch (S1) is high, the comparator is reset, the voltage signal (Vinp1) of the first input end is equal to the voltage signal (Vinm1) of the second input end is equal to the voltage signal Vcm, and the Vcm is the common-mode voltage value of the comparator;
the circuit for eliminating the dark current outputs a reset signal (Vrst) to be sampled to a first sampling capacitor (Cs1), and initial voltage values of a coarse adjustment converter and a fine adjustment converter are sampled to a first auxiliary capacitor (Cb1) and a second auxiliary capacitor (Cb 2);
a signal end (TX) is opened, a photosensitive signal (Vsig) of the effective pixel array is output, and a coarse adjustment converter and a fine adjustment converter output a voltage signal difference (Vdiff) needing to be adjusted; the voltage signal interpolation (Vdiff) is calculated from the formula (Vdiff) ═ ((Db) × DRAD) ÷ (2 × NAD); wherein, DRAD is the amplitude of the image sensor system, NAD is the precision of the image sensor system, and Db is the dark current noise digital signal output by the dark pixel; at the same time, the voltage value (Vinp1) at the first signal input terminal of the comparator jumps to Vcm- (Vrst-Vsig) - (Vdiff);
when the EN _ COUNT signal end is high, the counter starts counting, a ramp signal (Vramp) sent by the ramp generator starts changing, a signal (Vinm) at the second input end changes along with the ramp signal, when the comparator turns over, the counter stops counting and outputs a digital signal (D), and the output digital signal (D) is the photosensitive signal value of the effective pixel array.
6. The dark current eliminating image sensor system according to claim 5, wherein when the image sensor system counts the average value (Db) of the signals of the dark pixel array, the digital output is not 0 and varies with the temperature.
7. The dark current canceling image sensor system according to claim 5, wherein the coarse adjustment converter implements coarse adjustment for fast adjustment of a luminance value (DN value) of the dark current output, enabling fast correction of the dark current noise level; the fine adjustment converter realizes fine adjustment, the amplitude of the fine adjustment is smaller than that of the coarse adjustment, and the fine adjustment converter is used for enabling the amplitude value of dark current output to be more accurate.
8. The dark current eliminating image sensor system according to claim 7, wherein the fine adjustment is performed at a pitch of not more than 1LSB as compared to the image sensor system.
9. The dark current canceling image sensor system according to claim 7, wherein the output voltage ranges of the coarse adjustment converter and the fine adjustment converter are each a maximum amplitude value of dark current noise.
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| CN110545388B (en) * | 2019-08-28 | 2022-04-01 | 上海集成电路研发中心有限公司 | Device and method for removing image dark current |
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| US11785358B1 (en) | 2022-05-19 | 2023-10-10 | Chengdu Image Design Technology Co., Ltd. | Method and system for reducing column noise of image sensor |
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