CN108322410B - Time domain equalizer and signal processing method thereof - Google Patents

Time domain equalizer and signal processing method thereof Download PDF

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CN108322410B
CN108322410B CN201710037252.5A CN201710037252A CN108322410B CN 108322410 B CN108322410 B CN 108322410B CN 201710037252 A CN201710037252 A CN 201710037252A CN 108322410 B CN108322410 B CN 108322410B
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signal
weights
mth
symbol
delayed
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CN108322410A (en
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周禹伸
魏逢时
赖科印
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MediaTek Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03114—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
    • H04L25/03146—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03592—Adaptation methods
    • H04L2025/03598—Algorithms
    • H04L2025/03611—Iterative algorithms

Abstract

The invention providesThe time domain equalizer comprises a delay circuit, a weighting circuit, a controller and a summing circuit. The delay circuit generates M delayed signals for the equalized signal. The weighting circuit applies an mth weight of the M weights to an mth delayed signal of the M delayed signals to generate an mth weighted signal. The summing circuit sums the M weighted signals for the time domain equalizer to update the equalized signals accordingly. The controller is based on the vector
Figure DDA0001212519410000011
Iteratively updating the M weights, wherein the symbol en,p,jIs defined as: e.g. of the typen,p,j＝∑k(z[k]*[k‑Dp,j]*) The symbol n is an index of the number of iterations, k is an index of the sampling, z [ k ]]For the kth sample of the equalized signal, j is an integer index ranging from 1 to M, Dp,jAnd the time delay amount corresponding to the j-th delayed signal in the M delayed signals is shown.

Description

Time domain equalizer and signal processing method thereof
Technical Field
The present invention relates to time-domain equalizers, and more particularly to the manner in which the weight coefficients are determined in a time-domain equalizer.
Background
Orthogonal Frequency Division Multiplexing (OFDM) technology has the advantages of high spectrum utilization rate and simple hardware architecture, and is widely used in communication systems in recent years. The ofdm signal is composed of a plurality of symbols (symbols). In order to avoid inter-symbol interference (ISI) caused by echo signals (echo) in multipath (multipath), a guard interval (guard interval) is provided at the front end of each symbol. However, in more complex communication environments, propagation delay exceeding the guard interval length may still occur, thereby causing intersymbol interference and resulting in a decrease in overall system performance. This problem cannot be solved by the frequency domain equalization technique, but an additional time domain equalizer must be provided before the frequency domain equalizer at the receiving end to eliminate or minimize the echo signal in the received signal.
The original signal sent by the transmitting end is represented as symbol x, and the signal received by the receiving end is represented as symbol y. Without considering the symbol time offset (timing offset) and frequency offset (frequency offset), the received signal y after multiple propagation paths can be represented as follows:
Figure GDA0002641616850000011
where k represents a sample index, the symbol x k]Representing the kth sample of the original signal x, the symbol y k]Representing the kth sample of the received signal y, n [ k ]]Representing the kth sample of the noise signal. As can be seen from equation one, the received signal y is the sum of the original signal x and the P echo signals. The positive integer P represents the total number of echo signals caused by multiple propagation paths of the transmission channel from the transmitting end to the receiving end; the receiving end can obtain the value of P by analyzing the received signal y. Symbol ap、θp,k、ΔpRespectively representing the amplitude amplification factor, the phase offset and the arrival time offset (P is an integer index ranging from 1 to P) of the P-th echo signal of the P echo signals relative to the original signal x.
FIG. 1A is a block diagram of a time domain equalizer. The time domain equalizer 100 includes P approximation signal generating circuits (denoted by 110)1、1102、…、110PCollectively referred to as the approximation signal generating circuit 110) and a subtracting circuit 120. After the receiving end analyzes the value of P, the time domain equalizer 100 can be configured to include P approximation signal generating circuits 110. Each of the approximation signal generating circuits 110 is assigned to correspond to one of the P echo signals, and is responsible for generating an approximation signal s that is substantially identical to the echo signal. The subtracting circuit 120 is used to subtract the P approximation signals s generated by the P approximation signal generating circuits 110 from the received signal y, and the output signal z is the equalized signal. The more similar these P approximation signals s are to the respective echo signals, the closer the equalized signal z is to the original signal x.
The following explains the approximate signal generating circuit 110 corresponding to the p-th echo signalpHow to generate an approximation signal sp. FIG. 1B shows an approximation signal generating circuit 110pIncludes a delay circuit 111pA weighting circuit 112pAnd aSumming circuit 113p。
Delay circuit 111pIncludes M delay elements (denoted as L)p,1、Lp,2、…、Lp,M) The output terminals are each a tapping terminal. M is a positive integer greater than one, and M is an integer index ranging from 1 to M. Delay circuit 111pThe M delay elements are used to generate M different delayed signals for the equalized signal z. The mth tap node of the M tap nodes is opposite to the delay circuit 111pHas an m-th time delay amount Dp,m. In other words, the delay element Lp,mProvides a delayed signal z k-Dp,m]。
Weighting circuit 112pIncludes M multipliers (denoted by 112)p,1、112p,2、…、112p,M) Of which the mth multiplier 112p,mResponsible for delaying the circuit 111pResulting delayed signal z k-Dp,m]Multiplying by an m-th weight wp,mTo generate a weighted signal. The M weighted signals are added in the adding circuit 113pIs summed up, the result of which can be expressed as:
Figure GDA0002641616850000021
according to the architecture presented in fig. 1A and 1B, the output signal z of the time-domain equalizer 100 can be represented as:
Figure GDA0002641616850000022
disclosure of Invention
The time-domain equalizer and the signal processing method define a new cost function (costfunction) and perform operation based on a least mean square (least mean square) algorithm, thereby finding out the weight w capable of effectively eliminating echo signals for each weighting circuit in the time-domain equalizerp,mAnd further solve the problem caused by intersymbol interference at the receiving end.
According to an embodiment of the present invention, a time domain averagingThe weighing apparatus includes a delay circuit, a weighting circuit, a controller and a summing circuit. The delay circuit is used for receiving an equalized signal and generating M delayed signals for the equalized signal, wherein M is a positive integer greater than one. The weighting circuit applies M weights to an mth delayed signal of the M delayed signals to generate an mth weighted signal, wherein M is an integer index ranging from 1 to M. The summing circuit is used for summing the M weighted signals, and the time domain equalizer updates the equalized signals accordingly. The controller is based on a vector
Figure GDA0002641616850000031
Iteratively updating the M weights employed by the weighting circuit, wherein the symbol en,p,jIs defined as:
Figure GDA0002641616850000032
the symbol n represents an iteration index, k represents a sampling index, z [ k ]]Is the k-th sample of the equalized signal, j is an integer index ranging from 1 to M, Dp,jIndicating a jth delay amount corresponding to a jth delayed signal in the M delayed signals; a summation circuit for summing the M weighted signals, the time domain equalizer updating the equalized signal accordingly;
the controller updates the M weights used by the weighting circuit according to the following operational formula:
Figure GDA0002641616850000033
where μ represents an adjustable parameter in the least mean square algorithm and the vector
Figure GDA0002641616850000034
Comprises the following steps:
Figure GDA0002641616850000035
wherein the symbol Dp,mRepresenting an mth delay amount.
Another embodiment according to the present invention is a signal processing method. First, M delayed signals of an equalized signal are generated, where M is a positive integer greater than one. Then, M weights are applied, and an mth delayed signal of the M delayed signals is applied with an mth weight of the M weights to generate an mth weighted signal, wherein M is an integer index ranging from 1 to M. The M weighted signals are then summed as a basis for updating the equalized signal. In the signal processing method, the M weights are based on a vector
Figure GDA0002641616850000036
Is updated iteratively, wherein the symbol en,p,jIs defined as:
Figure GDA0002641616850000041
the symbol n represents an iteration index, k represents a sampling index, z [ k ]]For the kth sample of these quantized signals, j is an integer index ranging from 1 to M, Dp,jIndicating a jth delay amount corresponding to a jth delayed signal in the M delayed signals; and adding the M weighted signals and updating the equalized signal accordingly;
iteratively updating the M weights comprises updating the M weights according to the following equations:
Figure GDA0002641616850000042
where μ represents an adjustable parameter in the least mean square algorithm and the vector
Figure GDA0002641616850000043
Comprises the following steps:
Figure GDA0002641616850000044
wherein the symbol Dp,mRepresenting an mth delay amount.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1A is a block diagram of a time domain equalizer.
FIG. 1B is a block diagram of an approximate signal generation circuit in a time domain equalizer.
Fig. 2 is a functional block diagram of a time-domain equalizer according to an embodiment of the present invention.
Fig. 3 and 4 are partial functional block diagrams of a controller according to the present invention.
Fig. 5 is a flow chart of a signal processing method according to an embodiment of the invention.
It is noted that the drawings of the present invention include functional block diagrams that represent various functional blocks that can be associated with each other. These drawings are not detailed circuit diagrams, and the connecting lines are only used to indicate signal flows. The various interactions between functional elements and/or processes need not be achieved through direct electrical connections. In addition, the functions of the individual elements do not have to be distributed as shown in the drawings, and the distributed blocks do not have to be implemented by distributed electronic elements.
The element numbers in the figures are illustrated as follows:
100: time domain equalizer 110: approximate signal generating circuit
111p: delay circuit Lp,1、Lp,2、…、Lp,M: delay element
112p: weighting circuit 112p,1、112p,2、…、112p,M: multiplier and method for generating a digital signal
113p: the summing circuit 120: subtracting circuit
130: controllers 131, 132: arithmetic circuit
133. 134, 137: the multiplier 135: adder
136: the adaptive adjusting circuits S501-S504: procedure step
Detailed Description
The time domain equalizer and the signal processing method define a new cost function and take the advantage of the least mean square algorithm to carry out operation, thereby finding out the weight capable of effectively eliminating the echo signal for each weighting circuit in the time domain equalizer.
First, the application of the inventive concept to the time domain equalizer 100 presented in fig. 1A and 1B will be described. As previously mentioned, the output signal z of the time domain equalizer 100 can be represented as:
Figure GDA0002641616850000051
the time domain equalizer 100 of the present invention is designed with the goal of generating a circuit 110 for the approximation signalpSelecting an appropriate time delay amount Dp,mAnd a weight wp,mSo as to approximate the signal spThe same as possible is obtained for the p-th echo signal, so that the equalized signal z generated by the time domain equalizer 100 according to equation three is close to the original signal x, i.e., the influence of each echo signal is eliminated.
First, a time delay D that can be usedp,mThe determination method is described below. In practice, through the inverse fast fourier transform, the receiving end to which the time domain equalizer belongs can find the actual time delay ΔpRough value of (1) (hereinafter, denoted by symbol D)pExpressed), it is difficult to grasp the actual arrival time delay amount ΔpAnd a coarse delay DpThe exact difference in time. In the embodiment of the present invention, the approximate delay D is obtainedpThen (the calculation method is known in the art and not described herein), the delay circuit 111pThe respective time delay amounts of the M delay elements can be determined according to the approximate delay amount DpTo set it. For example, the circuit designer may select a reasonable lower bound τ on the basis of practical experienceminAnd difference upper limit τmax. More specifically, the time delay of arrival amount ΔpIs assumed to fall on (D)p-τmin)～(Dp+τmax) Within this range, the circuit designer can select the amount of time delay provided by the M delay elements within this range. Taking the case where M equals eight as an example, if the delay element L isp,mAmount of time delay D providedp,mIs represented by (D)p+dp,m) A delay element Lp,1Amount of time delay (D) providedp+dp,1) Can be set to (D)p-τmin) A delay element Lp,8Amount of time delay (D) providedp+dp,8) Can be set to (D)p+τmax) And the other six time delay amounts (D)p+dp,2)～(Dp+dp,7) Is set to be at (D)p-τmin) And (D)p+τmax) The result of equidistant interpolation between them.
Next, the weight w proposed by the present invention is introducedp,mA method is determined. The inventors define a cost function for the pth echo signal of the P echo signals as follows:
Figure GDA0002641616850000061
wherein the symbol n represents an iteration index, j is an integer index ranging from 1 to M, and the symbol en,p,jRepresents a correlation factor (correlation factor) defined as:
Figure GDA0002641616850000062
wherein the delay amount Dp,jCan also be rewritten as (D)p+dp,j) Symbol DpThe delay amount is the above-mentioned approximate delay amount.
The operation of equation five is to calculate the correlation between the equalized signal z and the delayed signal z, and accumulate the correlation operation results for a period of time (for example, accumulate the correlation operation results corresponding to five thousand sampling indexes k). An ideal time domain equalizer would substantially eliminate the echo signal in the received signal yThe signal, i.e. the output signal z of the time domain equalizer 100, is substantially the same as the original signal x. Theoretically, if the front and back signals in the original signal x have no correlation in time, the correlation in the original signal x and its delayed signal will be close to zero. Therefore, if the front and back signals in the original signal x have no correlation in time, the correlation between the ideal equalized signal z and its delayed signal will be close to zero. In summary, the more ideal the time domain equalizer is, the closer the operation result of equation five is to zero, the smaller the operation result of equation four is. The time domain equalizer according to the present invention is designed to find the enabling cost function through successive iterations of the least mean square algorithm
Figure GDA0002641616850000063
Minimized weight wp,m. The derivation and implementation are described in detail below.
First, the formula is substituted into formula three, and the weight w is setp,mIs replaced by wn,p,m(the iteration index n is indicated), the formula III can be rewritten as follows:
Figure GDA0002641616850000064
wherein the delay amount Dp,mCan also be rewritten as (D)p+dp,m) Symbol DpThe delay amount is the above-mentioned approximate delay amount.
Then, substituting formula six into operation formula z [ k]*z[k-Dp,j]*The following can be obtained:
Figure GDA0002641616850000065
Figure GDA0002641616850000071
it is assumed that the front and back signals in the original signal x have no correlation in time and have an average value of zero. In addition, it is also assumed that the average value of the noise signal is also zero. If the formula seven is substituted into the formula five, after a period of accumulation, the accumulated value of some terms in the formula seven approaches to zero, so that the operation result of the formula five can be simplified and approximated as:
Figure GDA0002641616850000072
according to the concept of the least mean square algorithm, each weight w is usedn,p,mApplying partial differential to the equation four as partial derivative to obtain the cost function
Figure GDA0002641616850000073
Minimized weight wn,p,m. If the equation eight is substituted in the partial differential operation process, we get:
Figure GDA0002641616850000074
wherein the vector
Figure GDA0002641616850000075
(see formula five for definition), and vectors
Figure GDA0002641616850000076
Comprises the following steps:
[∑kz[k-Dp,m]*z[k-Dp,1]*…∑kz[k-Dp,m]*z[k-Dp,M]*]. (formula ten)
According to the least mean square algorithm and the derivation result of the formula nine, the following formula is used to iteratively update each weight wn,pThen, the cost function can be made step by step
Figure GDA0002641616850000081
Is minimized:
Figure GDA0002641616850000082
wherein μ represents an adjustable parameter in the least mean square algorithm, which is related to the speed of the iterative update, and can be determined by the circuit designer, without being limited to a specific value.
As shown in FIG. 2, if the concept of the present invention is applied to the time-domain equalizer shown in FIG. 1A and FIG. 1B, the time-domain equalizer 100 may comprise a controller 130 for determining the cost function corresponding thereto
Figure GDA0002641616850000083
Vector of (2)
Figure GDA0002641616850000084
And iteratively updates the weight w used by each weighting circuit 112 in the approximate signal generating circuit 110p,m。
In one embodiment, the controller 130 updates the weight w according to the formula elevenp,m. More specifically, the controller 130 may first calculate the vectors respectively
Figure GDA0002641616850000085
Sum vector
Figure GDA0002641616850000086
Then the vector is transformed
Figure GDA0002641616850000087
And vector
Figure GDA0002641616850000088
The product of (d) is multiplied by 2 mu to obtain the last term in the eleven equation. The item is compared with the current weight
Figure GDA0002641616850000089
Adding to generate an updated set of weights
Figure GDA00026416168500000810
FIG. 3 is a partial functional block diagram of the controller 130 in this embodiment, showing how the controller 130 can use the signal z [ k ]]And a delay circuit 111pResulting delayed signal z k-Dp,j]Performs an operation to weight the circuit 112pThe weight of the first multiplier (m ═ 1) is represented by wn,p,1Is updated to wn+1,p,1. The operation circuit 131 is used to perform the operation corresponding to the formula five, thereby finding out the vector
Figure GDA00026416168500000811
The operation circuit 132 is used to perform the operation corresponding to the formula ten, thereby finding the vector
Figure GDA00026416168500000812
The multiplier 133 is responsible for multiplying the output signals of the arithmetic circuits 131, 132. The multiplier 134 is responsible for multiplying the output signal of the multiplier 133 by 2 μ. The adder 135 is used to combine the output signal of the multiplier 134 with the weight
Figure GDA00026416168500000813
And (4) adding. In practice, the operation circuits 131, 132 can receive the delay circuit 111pResulting delayed signal z k-Dp,j]As its input signal.
It will be appreciated by those skilled in the art that a variety of other circuit configurations and components can implement the controller 130 without departing from the spirit of the present invention. In practice, the controller 130 may be implemented using a variety of control and processing platforms, including fixed and programmable logic circuits such as programmable gate arrays, application specific integrated circuits, microcontrollers, microprocessors, digital signal processors, among others. In addition, the controller 130 may also be configured to perform its computational tasks by executing processor instructions stored in memory. It should be noted that the processing procedures of signal delay, vector transposition, addition, multiplication, accumulation and the like are known to those skilled in the art, and the details thereof are not described herein.
In addition to the typical least mean square algorithm, the time-domain equalizer according to the present invention can also use its variation to determine the cost function
Figure GDA0002641616850000091
Minimized weight wn,p,m. Take an Improved Proportional Normalized Least Mean Square (IPNLMS) algorithm as an exampleThe controller 130 may further determine the weight [ w ]n,p,1…wn,p,M]Determining an adaptive adjustment vector
Figure GDA0002641616850000092
And vector
Figure GDA0002641616850000093
M parameters k of the product ofn,p,1…kn,p,M]That is, each weight w is updated iteratively according to the following operation formulan,p：
Figure GDA0002641616850000094
And the M parameters [ k ]n,p,1…kn,p,M]Is generated according to the following operational formula:
Figure GDA0002641616850000095
Figure GDA0002641616850000096
wherein for an adjustable parameter in the improved proportional normalized least mean square algorithm, l is an integer index ranging from 1 to M
Figure GDA0002641616850000097
As shown in fig. 4, the controller 130 further includes an adaptive adjusting circuit 136 and a multiplier 137. The adaptive adjustment circuit 136 is used to generate the parameter [ k ]n,p,1…kn,p,M]. The multiplier 137 is responsible for adjusting the parameter k generated by the adaptive adjusting circuit 136n,p,1Multiplying the output signal of the multiplier 133, thereby making the vector
Figure GDA0002641616850000098
And vector
Figure GDA0002641616850000099
The product of (d) is adaptively adjusted.
Another embodiment of a signal processing method according to the present invention is a flowchart shown in fig. 5. First, in step S501, an equalized signal is received, and M delayed signals are generated for the equalized signal, where M is a positive integer greater than one. Step S502 is to apply M weights to an mth delayed signal of the M delayed signals to generate an mth weighted signal, wherein M is an integer index ranging from 1 to M. In step S503, the M weighted signals are added together to serve as the basis for updating the signals. Step S504 is based on the vector
Figure GDA00026416168500000910
Iteratively updating the M weights used in step S502, wherein the symbol en,p,jIs defined as:
en,p,j＝∑k(z[k]*z[k-Dp,j]*) (sixteen formula)
The symbol n represents an iteration index, k represents a sampling index, z [ k ]]Is the k-th sample of the equalized signal, j is an integer index ranging from 1 to M, Dp,jThe j-th delay amount corresponding to the j-th delayed signal in the M delayed signals is represented.
It can be understood by those skilled in the art that the various operation variations that can be applied to the time domain equalizer 100 described above can also be applied to the signal processing method in fig. 5, and the details thereof are not repeated.
It should be noted that the mathematical expressions in the present application are used to explain the principles and logic associated with the embodiments of the present invention, and do not limit the scope of the present invention unless otherwise specified. Those skilled in the art will appreciate that there are many techniques for implementing the physical representations to which these equations correspond.
Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (4)

1. A time domain equalizer, comprising:
a delay circuit receiving an equalized signal and generating M delayed signals for the equalized signal, M being a positive integer greater than one;
a weighting circuit, using M weights, applying an mth weight of the M weights to an mth delayed signal of the M delayed signals to generate an mth weighted signal, wherein M is an integer index ranging from 1 to M;
a controller for controlling the operation of the display according to a vector
Figure FDA0002641616840000011
Iteratively updating the M weights employed by the weighting circuit, wherein the symbol en,p,jIs defined as:
Figure FDA0002641616840000012
the symbol n represents an iteration index, k represents a sampling index, z [ k ]]Is the k-th sample of the equalized signal, j is an integer index ranging from 1 to M, Dp,jIndicating a jth delay amount corresponding to a jth delayed signal in the M delayed signals; and
a summation circuit for summing the M weighted signals, the time domain equalizer updating the equalized signal accordingly;
the controller updates the M weights used by the weighting circuit according to the following operational formula:
Figure FDA0002641616840000013
where μ represents an adjustable parameter in the least mean square algorithm and the vector
Figure FDA0002641616840000014
Comprises the following steps:
Figure FDA0002641616840000015
wherein the symbol Dp,mRepresenting an mth delay amount.
2. The time-domain equalizer of claim 1, wherein the controller further comprises:
an adaptive adjustment circuit for adjusting the M weights [ w ]n,p,1…wn,p,M]Determining M parameters [ k ]n,p,1…kn,p,M]，
And the controller updates the M weights used by the weighting circuit according to the following operational formula:
Figure FDA0002641616840000016
where μ represents an adjustable parameter in the least mean square algorithm and the vector
Figure FDA0002641616840000021
Comprises the following steps:
Figure FDA0002641616840000022
wherein the symbol Dp,mRepresenting an mth delay amount.
3. A method of signal processing, comprising:
receiving an equalized signal and generating M delayed signals for the equalized signal, wherein M is a positive integer greater than one;
applying an mth weight of the M weights to an mth delayed signal of the M delayed signals by using the M weights to generate an mth weighted signal, wherein M is an integer index ranging from 1 to M;
according to a vector
Figure FDA0002641616840000023
Iteratively updating the M weights, wherein the symbol en,p,jIs defined as:
Figure FDA0002641616840000024
the symbol n represents an iteration index, k represents a sampling index, z [ k ]]Is the k-th sample of the equalized signal, j is an integer index ranging from 1 to M, Dp,jIndicating a jth delay amount corresponding to a jth delayed signal in the M delayed signals; and
adding the M weighted signals and updating the equalized signal accordingly;
iteratively updating the M weights comprises updating the M weights according to the following equations:
Figure FDA0002641616840000025
where μ represents an adjustable parameter in the least mean square algorithm and the vector
Figure FDA0002641616840000026
Comprises the following steps:
Figure FDA0002641616840000027
wherein the symbol Dp,mRepresenting an mth delay amount.
4. The signal processing method of claim 3, further comprising:
according to the M weights [ wn,p,1…wn,p,M]Determining M parameters [ k ]n,p,1…kn,p,M]，
And iteratively updating the M weights comprises updating the M weights according to the following equations:
Figure FDA0002641616840000028
where μ represents an adjustable parameter in the least mean square algorithm and the vector
Figure FDA0002641616840000031
Comprises the following steps:
Figure FDA0002641616840000032
wherein the symbol Dp,mRepresenting an mth delay amount.
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