CN108322305A - The implementation method of hardware module is replaced for the quantum byte of AES encryption hardware system - Google Patents
The implementation method of hardware module is replaced for the quantum byte of AES encryption hardware system Download PDFInfo
- Publication number
- CN108322305A CN108322305A CN201810469137.XA CN201810469137A CN108322305A CN 108322305 A CN108322305 A CN 108322305A CN 201810469137 A CN201810469137 A CN 201810469137A CN 108322305 A CN108322305 A CN 108322305A
- Authority
- CN
- China
- Prior art keywords
- data
- hardware
- compositum
- transformation
- finite field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Optical Communication System (AREA)
Abstract
The present invention relates to the implementation methods that a kind of quantum byte for AES encryption hardware system replaces hardware module, by the way that the data in galois field in finite field are transformed on compositum, switch back to finite field after being inverted on compositum again, reaches to the encrypted purpose of data.Using in electronic circuit XOR gate, with the devices such as door realize the transformation of Quantum logic gates, it is final realize building for hardware module.Simple gate circuit in present invention quantum wire is realized, the operating pressure of CPU in encryption system can be effectively alleviated, and has speed faster, the more preferable advantage of cipher round results.
Description
Technical field
The present invention relates to quantum cryptography algorithm and a kind of hardware realizations of encrypting step, belong to information security technology neck
Domain.
Background technology
With the arrival in big data epoch, the data of magnanimity are needed to transmit and be stored, information leakage, the information thus brought
The problems such as usurping is increasingly severe, therefore, studies a kind of speed faster, the better encryption technology of effect is instantly urgently to be resolved hurrily
Problem.
AES is widely used, data group is fixed as 128 state matrixes by it, in classics from after being suggested
Realize that byte replacement can consume a large amount of memory space in computer, Ye Feng et al. is directed to the byte in AES encryption algorithm and replaces
It proposes that the operable model of quantum, the transformation pertain only to the add operation on galois field, the simple door electricity in quantum wire can be used
It realizes on road.
Invention content
The object of the present invention is to provide a kind of simple gate circuit realizations in quantum wire, can effectively alleviate encryption system
The operating pressure of CPU in system has speed faster, and the quantum byte that cipher round results are preferably used for AES encryption system replaces mould
Block.
A kind of quantum byte for AES encryption hardware system replaces the implementation method of hardware module, includes the following steps：
A) 128 state matrixes of the hardware module pair carry out integrated operation, pass through the transformation on galois field, realization pair
The nonlinear transformation of state matrix, it is by finite field gf (28) on data transform to its compositum GF ((24)2) in, and multiple
It closes after carrying out inversion operation on domain, data is switched back in finite field again, finally carry out reversible affine transformation again；
B it) is built by XOR gate in electronic circuit, with the logic gates such as door, realizes Hardware.
The step A) specifically include following steps
A, data in finite field are transformed on compositum：
8 quantum bits of the step pair operate, and formula is： The operation can use 11 CNOT
Door realizes that Hardware is carried out to it can use the XOR gate cascade in 11 electronic circuits to constitute.
B, it inverts on compositum to data：
The step for previous step output come compositum on 8 data operated, transformation for mula is： 8 CNOT gates of the operation
With 36 Toffi realization, it is carried out Hardware can use electronic circuit in XOR gate and with door according to above-mentioned formula
Build composition.
C, the data after inverting on compositum switch back in finite field：
8 data after the step is inverted for previous step on compositum are operated, and transformation for mula is： The operation can realize that carrying out Hardware to it can with 12 CNOT gates
It is constituted with using the XOR gate in 12 electronic circuits to cascade.
D, affine transformation is carried out to the data in finite field after transformation：
The step is operated for 8 data in the finite field after previous step transformation, and transformation for mula is： Need prepare original state be
|11000110>Ancillary qubit, and realized using 40 CNOT gates, Hardware is carried out to it to be used in electronic circuit
High level indicate quantum service bit | 1>, indicate quantum service bit using low level | 0>, CNOT is replaced using XOR gate
Door, hardware circuit is built by above formula.
Compared with the prior art, the present invention has the following advantages：
It is realized with the simple gate circuit in quantum wire, can effectively alleviate the operating pressure of CPU in encryption system, have
Speed faster, the more preferable advantage of cipher round results.
Description of the drawings
Fig. 1：Finite field gf (28) arrive compositum GF ((24)2) transformation quantum wire structure
Fig. 2：Finite field gf (28) arrive compositum GF ((24)2) transformation hardware realization
Fig. 3：Compositum GF ((24)2) arrive finite field gf (28) transformation quantum wire structure
Fig. 4：Compositum GF ((24)2) arrive finite field gf (28) transformation hardware realization
Fig. 5：The structure of affine transformation quantum wire
Fig. 6：The hardware realization of affine transformation
Fig. 7：Byte replaces the corresponding table of input and output
Fig. 8：Byte replaces concrete operations display diagram
Specific implementation mode
In order to deepen the understanding of the present invention, below in conjunction with embodiment, the invention will be further described, the embodiment
It is only used for explaining the present invention, be not intended to limit the scope of the present invention..
A kind of quantum byte for AES encryption hardware system replaces the implementation method of hardware module as Figure 1-Figure 8
Specific implementation mode：Include the following steps：
A) 128 state matrixes of the hardware module pair carry out integrated operation, pass through the transformation on galois field, realization pair
The nonlinear transformation of state matrix.It is by finite field gf (28) on data transform to its compositum GF ((24)2) in, and multiple
It closes after carrying out inversion operation on domain, data is switched back in finite field again, finally carry out reversible affine transformation again；
B it) is built by XOR gate in electronic circuit, with the logic gates such as door, realizes Hardware；
The step A) specifically include following steps
A, data in finite field are transformed on compositum：
8 quantum bits of the step pair operate, and formula is： The operation can use 11 CNOT
Door realizes that Hardware is carried out to it can use the XOR gate cascade in 11 electronic circuits to constitute.
B, it inverts on compositum to data：
The step for previous step output come compositum on 8 data operated, transformation for mula is： 8 CNOT gates of the operation
With 36 Toffi realization, it is carried out Hardware can use electronic circuit in XOR gate and with door according to above-mentioned formula
Build composition.
C, the data after inverting on compositum switch back in finite field：
8 data after the step is inverted for previous step on compositum are operated, and transformation for mula is： The operation can realize that carrying out Hardware to it can with 12 CNOT gates
It is constituted with using the XOR gate in 12 electronic circuits to cascade.
D, affine transformation is carried out to the data in finite field after transformation：
The step is operated for 8 data in the finite field after previous step transformation, and transformation for mula is： Need prepare original state be
|11000110>Ancillary qubit, and realized using 40 CNOT gates, Hardware is carried out to it to be used in electronic circuit
High level indicate quantum service bit | 1>, indicate quantum service bit using low level | 0>, CNOT is replaced using XOR gate
Door, hardware circuit is built by above formula.
The present invention is mainly introduced based on the byte replacement module in reversible logic hardware encryption system；Byte replaces main needle
Octet is operated, by high four values as row, low four values as row are carried out by combinations of the above circuit
One byte conversion is corresponding numerical value in table, achievees the purpose that byte is encrypted by nonlinear transformation, it decrypted
Journey is data after converting again by said combination circuit, the data that will be restored.As shown in figure 8, input data
It is 00100011, it is 11110001 to obtain output by byte replacement module, meets byte and replaces mapping table relationship.
Simple gate circuit in present invention quantum wire is realized, the operation pressure of CPU in encryption system can be effectively alleviated
Power has speed faster, the more preferable advantage of cipher round results.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.
Therefore, the present invention is not intended to be limited to the embodiments shown herein, and be to fit to it is disclosed herein
Principle and the consistent widest range of features of novelty.
Claims (2)
1. a kind of quantum byte for AES encryption hardware system replaces the implementation method of hardware module, it is characterised in that：Including
Following steps：A integrated operation) is carried out by 128 bit data stream of hardware module pair, passes through finite field on galois field and compositum
Between conversion and to data carry out inversion operation, reach to data carry out nonlinear transformation feature, by finite field gf (28)
On data transform to its compositum GF ((24)2) in, and switch back to data again after progress inversion operation on compositum
In finite field, reversible affine transformation is finally carried out again；
B it) is built by XOR gate in electronic circuit, with the logic gates such as door, realizes Hardware.
2. a kind of quantum byte for AES encryption hardware system according to claim 1 replaces the realization of hardware module
Method, it is characterised in that：Step A) specifically include following steps：
A) data in finite field are transformed on compositum：
8 quantum bits are operated, formula is： Above-mentioned operation can use 11 CNOT gate realities
Existing, Hardware is carried out to it can use the XOR gate cascade in 11 electronic circuits to constitute；
B) it inverts on compositum to data：
Described invert is operated for 8 data on the compositum of step a) outputs, and transformation for mula is： Operation uses 8 CNOT gates
With 36 Toffi realizations, it is carried out Hardware using in electronic circuit XOR gate and built according to above-mentioned formula with door
It constitutes；
C) data after inverting on compositum switch back in finite field：
8 data after inverting for step b) on compositum are operated, and transformation for mula is： Operation realizes that carrying out Hardware to it can use using 12 CNOT gates
XOR gate cascade in 12 electronic circuits is constituted；
D) affine transformation is carried out to the data in finite field after transformation：
It is operated for 8 data in the finite field after step c) transformation, transformation for mula is：Preparing original state is |
11000110>Ancillary qubit, and realized using 40 CNOT gates, Hardware is carried out to it to be used in electronic circuit
High level indicates quantum service bit | 1>, indicate quantum service bit using low level | 0>, CNOT gate is replaced using XOR gate,
Hardware circuit is built by above-mentioned formula.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810469137.XA CN108322305A (en) | 2018-05-16 | 2018-05-16 | The implementation method of hardware module is replaced for the quantum byte of AES encryption hardware system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810469137.XA CN108322305A (en) | 2018-05-16 | 2018-05-16 | The implementation method of hardware module is replaced for the quantum byte of AES encryption hardware system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108322305A true CN108322305A (en) | 2018-07-24 |
Family
ID=62896290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810469137.XA Pending CN108322305A (en) | 2018-05-16 | 2018-05-16 | The implementation method of hardware module is replaced for the quantum byte of AES encryption hardware system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108322305A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110113149A (en) * | 2019-04-29 | 2019-08-09 | 南通大学 | A kind of implementation method of the quantum key expansion module for AES hardware encryption system |
| CN110120867A (en) * | 2019-04-29 | 2019-08-13 | 南通大学 | A kind of implementation method of the AES hardware encryption system based on quantum reversible link |
-
2018
- 2018-05-16 CN CN201810469137.XA patent/CN108322305A/en active Pending
Non-Patent Citations (3)
| Title |
|---|
| KAMALIKA DATTA 等: "Reversible Logic Implementation of AES Algorithm", 《2013 8TH INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS)》 * |
| 刘瑶 等: "AES中S盒变换的量子线路实现", 《信息安全与通信保密》 * |
| 高磊 等: "AES 算法中SubBytes 变换的高速硬件实现", 《微电子学与计算机》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110113149A (en) * | 2019-04-29 | 2019-08-09 | 南通大学 | A kind of implementation method of the quantum key expansion module for AES hardware encryption system |
| CN110120867A (en) * | 2019-04-29 | 2019-08-13 | 南通大学 | A kind of implementation method of the AES hardware encryption system based on quantum reversible link |
| CN110120867B (en) * | 2019-04-29 | 2022-02-22 | 南通大学 | Implementation method of AES hardware encryption system based on quantum reversible line |
| CN110113149B (en) * | 2019-04-29 | 2022-02-22 | 南通大学 | Implementation method of quantum key expansion module for AES hardware encryption system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103516512A (en) | Encryption and decryption method and encryption and decryption device based on AES (advanced encryption standard) algorithm | |
| TW201826162A (en) | Method and system for generation of cipher round keys by bit-mixers | |
| CN108650076A (en) | The implementation method of AES encryption system hardware module based on Quantum Reversible Logic | |
| CN103812641A (en) | System for realizing SM4 block symmetric cipher algorithm | |
| CN109981249B (en) | Encryption and decryption method and device based on zipper type dynamic hash and NLFSR | |
| CN105324956A (en) | Method and apparatus to encrypt plaintext data | |
| CN101739889A (en) | Cryptographic processing apparatus | |
| CN100382485C (en) | Method of designing optimum encryption function and optimized encryption apparatus in a mobile communication system | |
| CN101702709A (en) | AES encryption unit for MIPS processor | |
| TW201545524A (en) | Technologies for modifying a first cryptographic cipher with operations of a second cryptographic cipher | |
| CN112513856A (en) | Memory efficient hardware encryption engine | |
| Mi et al. | A novel chaotic encryption scheme based on arithmetic coding | |
| CN108322305A (en) | The implementation method of hardware module is replaced for the quantum byte of AES encryption hardware system | |
| CN110120867B (en) | Implementation method of AES hardware encryption system based on quantum reversible line | |
| WO2016026287A1 (en) | Encryption device, encryption method and computer storage medium | |
| CN106982116B (en) | Local file encryption method of AES (advanced encryption Standard) based on reversible logic circuit | |
| El-meligy et al. | 130nm Low power asynchronous AES core | |
| Perepechaenko et al. | Quantum encrypted communication between two IBMQ systems using quantum permutation pad | |
| CN100561911C (en) | Sbox module optimization method and optimization circuit in a kind of AES decipher circuit | |
| CN114422130B (en) | Quantum encryption method based on quantum power function confusion | |
| WO2008017261A1 (en) | High-efficient encryption and decryption processing method for implementing sms4 algorithm | |
| Cui et al. | A new image encryption algorithm based on DNA dynamic encoding and hyper-chaotic system | |
| TWI728933B (en) | Hybrid multistage algorithm encryption and decryption system, transmitting device thereof, and receiving device thereof | |
| CN115811398A (en) | Dynamic S-box-based block cipher algorithm, device, system and storage medium | |
| Kun et al. | An improved AES algorithm based on chaos |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180724 |
|
| RJ01 | Rejection of invention patent application after publication |