CN108650076A - The implementation method of AES encryption system hardware module based on Quantum Reversible Logic - Google Patents

Abstract

The invention relates to a realization method of an AES encryption system hardware module based on quantum reversible logic. The reversible calculation in the quantum circuit is realized through the algorithm on the Galois field, and the XOR gate cascaded in the electronic circuit is used. Realize the construction of multiplied by 2 devices, realize the reversible encryption operation on a whole column in the 128-bit state matrix through matrix operations on the Galois field, use multiplied by 2 devices and XOR gates to build column-mixed hardware circuits, based on Galois The matrix operation on the Luohua domain uses multiplication by 2 devices and electronic logic gates to build an inverse-column hybrid hardware circuit to realize the decryption operation of the column-mixed encrypted data stream. The invention can effectively improve the anti-attack capability of files, greatly reduce energy consumption and CPU occupation, and improve encryption efficiency.

Description

Implementation method of hardware module of AES encryption system based on quantum reversible logic

technical field

The invention relates to a quantum encryption algorithm and a hardware realization of an encryption step, belonging to the technical field of information security.

Background technique

The theft and secrecy of information is an eternal topic in the information society. How to design an encryption technology or algorithm with good encryption effect and low encryption cost has always been a research problem in the field of cryptography. Most of the current encryption technologies are based on mathematical problems to increase the complexity of the algorithm, the difficulty and time of deciphering. In this case, the study of better encryption and more convenient and practical encryption technology has become an urgent problem to be solved in information security.

Classical calculations can be performed using quantum reversible logic circuits. The circuit is used in encryption technology, and the quantum reversible logic gate is used to construct the multiplication operation circuit on the Galois field, and the types of keys can reach 2 ⁿ ! Compared with the traditional encryption method, it can be improved by (2 ⁿ -1)! times. In 2013, Professor Indranil Sengupta gave the original idea of using binary reversible logic to realize the AES algorithm. For the S-box transformation in the AES encryption algorithm, Ye Feng and others proposed an operable quantum logic circuit implementation scheme. After analyzing the SubBytes transformation in the S-box in detail, they obtained the Galois field _GF( 2 ⁸ ₎ The elements in are transformed into its composite field GF(2 ⁴ ₎ ² , and then transformed back to the Galois field _GF( 2 ⁸ ₎ for affine transformation after realizing the inversion. This transformation only involves Galois field addition, which can be realized by using XOR units, that is, CNOT gates and TOFFOLI gates in quantum circuits.

Invention content:

The purpose of the present invention is to provide a kind of hardware that effectively improves the anti-attack ability of files, and can greatly reduce the consumption of energy and the occupation of CPU, and improve the encryption efficiency of the AES encryption system based on quantum reversible logic. module.

A method for realizing a hardware module of an AES encryption system based on quantum reversible logic, comprising the following steps:

A, the quantum basic gate CNOT gate and the SWAP gate are cascaded into AES encryption hardware system by the quantum encryption algorithm and multiplied by 2 devices through the quantum encryption algorithm, and the 8-bit data stream in the state matrix is used as input to obtain the output of the 8-bit data stream; According to the multiplication algorithm on the Galois field, the quantum multiplication 2 device is formed by cascading CNOT gates and SWAP gates. Since it is based on the Galois field GF(2 ⁸ ), 8 quantum wires are used, and the input is b ₇ b ₆ b ₅ b ₄ b ₃ b ₂ b ₁ b ₀ , realize the most basic multiplication by 00000010 operation on the Galois field, first rotate the eight-bit data to the left by one bit, and then judge whether the last bit is 1, as When it is 1, perform XOR operation with 00011010, otherwise it remains unchanged. The logical expression is:

In the hardware implementation process, in the first half of the shift operation, the input needs to be output in the order after the shift during wiring, and then the multiplication operation is constructed through the XOR gate.

B. Quantum multiplying 2 devices and CNOT gates of multiple AES encryption hardware systems are cascaded into quantum column hybrid hardware modules through quantum encryption operation rules, and operate on 128-bit data streams to achieve data encryption. It is converted into an electronic circuit to realize hardware; the quantum inverse column hybrid hardware module realizes the encryption operation on the 128-bit state matrix through matrix multiplication, and the operation of matrix multiplication is based on the irreducible polynomial m(x)=x ⁸ +x The reversible operation on the finite field GF(2 ⁸ ) constructed by ⁴ +x ³ +x+1 is written in the form of polynomial multiplication: s′(x)=w(x)⊙s(x), where w( x) is a polynomial over the Galois Field, denoted as:

w(x)＝{03}x ³ +{01}x ² +{01}x+{02}

Write w(x) in matrix form and calculate it by matrix multiplication. Each byte in each column is represented by a polynomial:

here i∈[0,3] represents the i-th row and the c-th column byte in the state matrix, i∈[0,3] represents the i-th row and the c-th column byte in the state matrix after column mixing transformation, {03}A can be expressed as It is realized by multiplication by 2 operation and addition; in the implementation process of the quantum inverse hybrid hardware module, a low level is used to represent the auxiliary bit whose initial state is |0> in the quantum circuit, and a 32-bit XOR gate is used to correspond to the quantum circuit The CNOT gate in the circuit is formed by cascading 4 by 2 devices.

C. Use the CNOT gate to cascade into a quantum inverse column hybrid hardware module through quantum encryption operations, corresponding to the quantum column hybrid hardware module, and operate on the 128-bit data stream to achieve the decryption of the data and convert it into an electronic circuit. Realize the hardware design; the step C specifically includes the following steps: the quantum inverse column mixing hardware module realizes the decryption operation to the 128-bit state matrix through matrix multiplication, and the inverse column mixing is also realized by matrix multiplication. The polynomial formula is: s′=(x)=w- ¹ (x)⊙s(x), where w- ¹ (x) is: w- ¹ (x)={0e}x ³ +{0b}x ² +{0d}x+{02}

Written in the form of matrix multiplication, by calculating it through matrix multiplication, the four bytes in a column can be expressed in polynomial form:

where {0b}·A is expressed as The rest of the expressions are the same.

The hardware implementation process of inverse mixing also uses a low level to indicate the auxiliary bit whose initial state is |0> in the quantum circuit, and uses a 32-bit XOR gate to correspond to the CNOT gate in the quantum circuit, and is composed of 12 U device-level joint composition.

Compared with the prior art, the present invention has the following advantages:

Effectively improve the anti-attack ability of files, and can greatly reduce energy consumption and CPU occupation, and improve encryption efficiency.

Description of drawings

Figure 1: Quantum circuit of a multiply-by-two device

Figure 2: Hardware implementation circuit of a multiply-by-2 device

Figure 3: Construction of column-hybrid quantum circuits

Figure 4: Construction of column hybrid hardware module

Figure 5: Construction of inverse hybrid quantum circuits

Figure 6: Column mixing specific implementation steps

Figure 7: The specific implementation steps of inverse column mixing

Detailed ways

In order to deepen the understanding of the present invention, the present invention will be further described below in conjunction with examples, which are only used to explain the present invention and do not constitute a limitation to the protection scope of the present invention.

As shown in Figures 1-7, a method for implementing a hardware module of an AES encryption system based on quantum reversible logic comprises the following steps:

A, the quantum basic gate CNOT gate and the SWAP gate are cascaded into AES encryption hardware system by the quantum encryption algorithm and multiplied by 2 devices through the quantum encryption algorithm, and the 8-bit data stream in the state matrix is used as input to obtain the output of the 8-bit data stream; According to the multiplication algorithm on the Galois field, the quantum multiplication 2 device is formed by cascading CNOT gates and SWAP gates. Since it is based on the Galois field GF(2 ⁸ ), 8 quantum wires are used, and the input is b ₇ b ₆ b ₅ b ₄ b ₃ b ₂ b ₁ b ₀ , realize the most basic multiplication by 00000010 operation on the Galois field, first rotate the eight-bit data to the left by one bit, and then judge whether the last bit is 1, as When it is 1, perform XOR operation with 00011010, otherwise it remains unchanged. The logical expression is:

In the hardware implementation process, in the first half of the shift operation, the input needs to be output in the order after the shift during wiring, and then the multiplication operation is constructed through the XOR gate.

B. Quantum multiplying 2 devices and CNOT gates of multiple AES encryption hardware systems are cascaded into quantum column hybrid hardware modules through quantum encryption operation rules, and operate on 128-bit data streams to achieve data encryption. It is converted into an electronic circuit to realize hardware; the quantum inverse column hybrid hardware module realizes the encryption operation on the 128-bit state matrix through matrix multiplication, and the operation of matrix multiplication is based on the irreducible polynomial m(x)=x ⁸ +x The reversible operation on the finite field GF(2 ⁸ ) constructed by ⁴ +x ³ +x+1 is written in the form of polynomial multiplication: s′(x)=w(x)⊙s(x), where w( x) is a polynomial over the Galois Field, denoted as:

w(x)＝{03}x ³ +{01}x ² +{01}x+{02}

Write w(x) in matrix form and calculate it by matrix multiplication. Each byte in each column is represented by a polynomial:

here i∈[0,3] represents the i-th row and the c-th column byte in the state matrix, i∈[0,3] means the i-th row and the c-th column byte in the state matrix after the column mixing transformation, {03}A can be expressed as {02}A⊕A, which is realized by multiplying by 2 and adding ; In the implementation process of the quantum inverse hybrid hardware module, a low level is used to represent the auxiliary bit whose initial state is |0> in the quantum circuit, and a 32-bit XOR gate is used to correspond to the CNOT gate in the quantum circuit, and 4 A multiplied by 2 devices are cascaded.

C. Use the CNOT gate to cascade into a quantum inverse column hybrid hardware module through quantum encryption operations, corresponding to the quantum column hybrid hardware module, and operate on the 128-bit data stream to achieve the decryption of the data and convert it into an electronic circuit. Realize the hardware design; the step C specifically includes the following steps: the quantum inverse column mixing hardware module realizes the decryption operation to the 128-bit state matrix through matrix multiplication, and the inverse column mixing is also realized by matrix multiplication. The polynomial formula is: s′=(x)=w- ¹ (x)⊙s(x), where w- ¹ (x) is: w- ¹ (x)={0e}x ³ +{0b}x ² +{0d}x+{02}

Written in the form of matrix multiplication, by calculating it through matrix multiplication, the four bytes in a column can be expressed in polynomial form:

where {0b}·A is expressed as The rest of the expressions are the same.

The hardware implementation process of inverse mixing also uses a low level to indicate the auxiliary bit whose initial state is |0> in the quantum circuit, and uses a 32-bit XOR gate to correspond to the CNOT gate in the quantum circuit, and is composed of 12 U device-level joint composition.

Column mixing is an operation performed in units of columns. Four identical modules operate on the entire state matrix, and each module corresponds to a column. As shown in Figure 6, the input of a column of 32-bit data stream is: 11111111000000001111111100000000, after the operation of the column mixing hardware module, the encrypted data stream is:

00011010111001010001101011100101, the four encryption modules are juxtaposed, and the entire 128-bit state matrix is encrypted.

Inverse column mixing corresponds to column mixing, which is also an overall operation on the column, and four identical modules operate on the entire state matrix to achieve the purpose of restoration. Use the encrypted data stream: 00011010111001010001101011100101 as the input of the inverse column mixing module, and output the data stream after inverse column mixing:

11111111000000001111111100000000, which is consistent with the data before encryption, so as to achieve the effect of data restoration.

The invention effectively improves the anti-attack ability of files, can greatly reduce energy consumption and CPU occupation, and improves encryption efficiency.

Claims (4)

1. a kind of implementation method of the AES encryption system hardware module based on Quantum Reversible Logic, it is characterised in that：Including following Step：

A, the quantum for being cascaded into AES encryption hardware system by quantum Encryption Algorithm by quantum elementary gate CNOT gate and SWAP multiplies 2 devices obtain the output of 8 bit data streams using 8 bit data streams in state matrix as input；

B, multiply 2 devices and CNOT gate by the quantum of multiple AES encryption hardware systems to be cascaded by the encrypted operation rule of quantum Quantum row mixed hardware module, is operated for 128 data flows, is reached to the encrypted effect of data, and be converted At electronic circuit, Hardware is realized；

C, quantum is cascaded into against row mixed hardware module, with quantum row mixed hardware mould by quantum cryptographic calculation using CNOT gate Block corresponds to, and is operated for 128 bit data streams, reaches the decryption effect to data, and convert thereof into electronic circuit, realizes Hardware design.

2. the implementation method of the AES encryption system hardware module according to claim 1 based on Quantum Reversible Logic, special Sign is：The step A specifically includes following steps：The quantum multiplies 2 devices according to the multiplying rule on galois field, It is made up of CNOT gate and SWAP gate leves connection, by being then based on galois field GF (2⁸), using 8 quantum wires, order input is b₇b₆b₅b₄b₃b₂b₁b₀, realize it is most basic on galois field be multiplied by 00000010 operation, first by eight bit data ring shift left One, then judge whether last position is 1, be 1 when, then with 00011010 carry out xor operation, otherwise constant, logical expression Formula is：

During hardware realization, in the shifting function of first half, it need to will be inputted in wiring defeated according to the sequence after displacement Go out, multiplying then builds composition by XOR gate.

3. the implementation method of the AES encryption system hardware module according to claim 1 based on Quantum Reversible Logic, special Sign is：The step B specifically includes following steps：The quantum passes through matrix multiplication, realization pair against row mixed hardware module Operation is encrypted in 128 state matrixes, and the operation of matrix multiplication is to be based on irreducible function m (x)=x⁸+x⁴+x³+ x+1 structures The finite field gf (2 made⁸) on can inverse operation, write as the form of polynomial multiplications:S ' (x)=w (x) ⊙ s (x), wherein w (x) it is multinomial on galois field, is denoted as：

W (x)={ 03 } x³+{01}x²+{01}x+{02}

It is write w (x) as matrix forms, it is calculated by matrix multiplication, one multinomial of each byte in each row To indicate：

S′_0,c=({ 02 } S_0,c)⊕({0 3}·S_1,c)⊕S_2,c⊕S_3,c

S′_1,c=S_0,c⊕({0 2}·S_1,c)⊕({0 3}·S_2,c)⊕S_3,c

S′_2,c=S_0,c⊕S_1,c⊕({0 2}·S_2,c)⊕({0 3}·S_3,c)

S′_3,c=({ 03 } S_0,c)⊕S_1,c⊕S_2,c⊕({0 2}·S_3,c)

S herein_i,c, i ∈ [0,3] indicate the i-th row in state matrix, c row bytes, S '_i,c, i ∈ [0,3] expression pass through The i-th row after mixcolumns in state matrix, c row bytes, { 03 } A can be expressed as { 02 } A ⊕ A, with multiplying 2 operations It is realized with addition；The quantum using low level indicates the shape that begins in quantum wire during being realized against row mixed hardware module State is | 0>Overhead bit, using 32 XOR gates to correspond to the CNOT gate in quantum wire, and multiply 2 device levels using 4 Connection is constituted.

4. the implementation method of the AES encryption system hardware module according to claim 1 based on Quantum Reversible Logic, special Sign is：The step C specifically includes following steps：The quantum passes through matrix multiplication, realization pair against row mixed hardware module Operation is decrypted in 128 state matrixes, and inverse row mixing realizes that polynomial equation is also by the mode of matrix multiple： S '=(x)=w^-1(x) ⊙ s (x), wherein w^-1(x) it is：w^-1(x)={ 0e } x³+{0b}x²+{0d}x+{02}

The form for being write as matrix multiplication calculates it by matrix multiplication, and four bytes in a row can be with polynomial Form indicates：

S′_0,c=({ 0e } S_0,c)⊕({0b}·S_1,c)⊕({0d}·S_2,c)⊕({09}·S_3,c)

S′_1,c=({ 09 } S_0,c)⊕({0e}·S_1,c)⊕({0b}·S_2,c)⊕({0d}·S_3,c)

S′_2,c=({ 0d } S_0,c)⊕({09}·S_1,c)⊕({0e}·S_2,c)⊕({0b}·S_3,c)

S′_3,c=({ 0b } S_0,c)⊕({0d}·S_1,c)⊕({09}·S_2,c)⊕({0e}·S_3,c)

{ 0b } A is expressed as ({ 02 } { 02 } { 02 } A) ⊕ ({ 02 } A) ⊕ A in formula, remaining each expression formula is identical；It is inverse The mixed hardware realization process of row equally indicates that beginning state is in quantum wire using low level | 0>Overhead bit, use 32 XOR gates are made of to correspond to the CNOT gate in quantum wire 12 U devices cascades.