CN108322064B

CN108322064B - Multi-output rectifier and operation method thereof

Info

Publication number: CN108322064B
Application number: CN201710039967.4A
Authority: CN
Inventors: 陈柏宏; 谢胜凯
Original assignee: Leadtrend Technology Corp
Current assignee: Leadtrend Technology Corp
Priority date: 2017-01-18
Filing date: 2017-01-18
Publication date: 2020-07-17
Anticipated expiration: 2037-01-18
Also published as: CN108322064A

Abstract

The invention discloses a multi-output rectifier and a method for operating the same. The multi-output rectifier includes an active rectifier circuit of a comparator architecture and a controller, wherein the controller is coupled to the active rectifier circuit. The active rectifying circuit is used for generating and outputting each output voltage according to an input voltage, each output voltage in a plurality of output voltages output by the multi-output rectifier and a control signal corresponding to each output voltage; the controller is used for generating the control signal according to each output voltage and a reference voltage corresponding to each output voltage. Therefore, the present invention can eliminate the need for the additional dc-dc converter and the discrete components, so that the present invention can not only reduce the cost of the multi-output rectifier, but also be easily integrated into other applications.

Description

Multi-output rectifier and operation method thereof

Technical Field

The present invention relates to a multi-output rectifier and a method for operating the same, and more particularly, to a multi-output rectifier and a method for operating the same without an additional dc-dc converter and discrete components.

Background

In the prior art, the wireless charging receiver rectifies an ac voltage induced by a coil by a bridge rectifier and then stabilizes the rectified ac voltage to a target voltage by an inductive DC-DC converter (DC-DC converter). Although the inductive dc-dc converter can provide a stable output voltage with high efficiency, several discrete (discrete) inductor or capacitor components are required. Therefore, the inductive dc-dc converter not only increases the cost of the wireless charging receiver, but also is not easy to be integrated into a wearable device due to the large size of the discrete inductive or capacitive components. In addition, although the linear dc-dc converter can avoid the use of discrete components, the linear dc-dc converter has lower power conversion efficiency at high conversion ratio. Therefore, none of the prior art is a good choice for the wireless charging receiver.

Disclosure of Invention

An embodiment of the invention discloses a multi-output rectifier. The multi-output rectifier comprises an active rectifying circuit of a comparator architecture, wherein the active rectifying circuit is used for generating and outputting each output voltage according to an input voltage, each output voltage in a plurality of output voltages output by the multi-output rectifier and a control signal corresponding to each output voltage.

Another embodiment of the invention discloses a multi-output rectifier. The multi-output rectifier includes an active rectifier circuit of a comparator architecture and a controller, wherein the controller is coupled to the active rectifier circuit. The active rectifying circuit is used for generating and outputting each output voltage according to an input voltage, each output voltage in a plurality of output voltages output by the multi-output rectifier and a control signal corresponding to each output voltage; the controller is used for generating the control signal according to each output voltage and a reference voltage corresponding to each output voltage.

Another embodiment of the present invention discloses a method for operating a multi-output rectifier, wherein the multi-output rectifier includes an active rectifier circuit having a comparator architecture, and the active rectifier circuit includes a circuit having a comparator architecture and a plurality of turn-on circuits. The operation method comprises the step that the active rectifying circuit generates and outputs each output voltage according to an input voltage, each output voltage in a plurality of output voltages output by the multi-output rectifier and a control signal corresponding to each output voltage.

Another embodiment of the present invention discloses a method for operating a multi-output rectifier, wherein the multi-output rectifier includes an active rectifier circuit of a comparator architecture and a controller, and the active rectifier circuit includes a circuit of the comparator architecture and a plurality of start-up circuits. The operation method comprises the steps that the controller generates a control signal according to each output voltage in a plurality of output voltages output by the multi-output rectifier and a reference voltage corresponding to each output voltage; and the active rectifying circuit generates and outputs each output voltage according to an input voltage, each output voltage and the control signal.

The invention discloses a multi-output rectifier and an operation method thereof. Because the multi-output rectifier can provide a plurality of stable output voltages for the circuit system of the next stage, the invention is applicable to a wireless charging receiver. In addition, compared to the prior art, the multi-output rectifier disclosed in the present invention can stabilize the output voltages at their corresponding predetermined values by controlling the on-time of the transistors in the circuit of the comparator architecture included in the multi-output rectifier, so that the present invention can eliminate the need for additional dc-dc converters and discrete components. Therefore, the invention can not only reduce the cost of the multi-output rectifier, but also be easily integrated into other application devices, because the invention can not need the additional DC-DC converter and the discrete components.

Drawings

Fig. 1 is a schematic diagram of a multi-output rectifier according to a first embodiment of the present invention.

Fig. 2 is a schematic diagram of the operational timing sequence of the multi-output rectifier during the positive half cycle of the input voltage.

Fig. 3 is a schematic diagram of the timing of the operation of the multi-output rectifier during the negative half-cycle of the input voltage.

Fig. 4 is a schematic diagram illustrating an active rectifier circuit outputting an output voltage in a first positive half-cycle of an input voltage and outputting the output voltage in a second positive half-cycle of the input voltage according to another embodiment of the present invention.

Fig. 5 is a schematic diagram illustrating an active rectifier circuit outputting an output voltage in a first negative half cycle of an input voltage and outputting the output voltage in a second negative half cycle of the input voltage according to another embodiment of the present invention.

Fig. 6 is a schematic diagram of a multi-output rectifier according to a second embodiment of the disclosure.

Fig. 7 is a flow chart of a method of operating a multi-output rectifier according to a third embodiment of the present invention.

Fig. 8 is a flow chart of a method of operating a multi-output rectifier according to a fourth embodiment of the present disclosure.

Fig. 9 is a flow chart of a method of operating a multi-output rectifier as disclosed in a fifth embodiment of the present invention.

Fig. 10 is a flow chart of a method of operating a multi-output rectifier as disclosed in a sixth embodiment of the present invention.

Wherein the reference numerals are as follows:

100. 600 multi-output rectifier

102 active rectifier circuit

104 supply circuit

106. 602 controller

108 second capacitance

110 first capacitance

1022 comparator architecture circuit

1024-1030 turn-on circuit

10222 first P-type metal oxide semiconductor transistor

10224 second P-type MOS transistor

10226 third P-type MOS transistor

10228 fourth PMOS transistor

10230 first N-type MOS transistor

10232 second N-type MOS transistor

10242 first comparator

10244 first logic circuit

10262 second comparator

10264 second logic circuit

10282 third comparator

10284 third logic circuit

10302 fourth comparator

10304 fourth logic Circuit

200. 300 load

6022 first subcontroller

6024 second subcontroller

INP, INP1, INP2, INN1 and INN2 DC voltages

PTV1, PTV2 predetermined time interval

Positive half period of TP

TP1 first Positive half cycle

TP2 second Positive half cycle

TN half negative period

TN1 first negative half cycle

TN2 second negative half-cycle

VOUT1, VOUT2 output voltage

VIN AC input voltage

VCC supply voltage

VCOMP1, VCOMP2, VCOMP3, comparison signal

VCOMP4

VCRT L1, VCRT L2 control signals

VGP1, VGP2, VGP3, VGP4 turn-on signals

VREF1 first reference voltage

VREF2 second reference voltage

Steps of 700, 800, 808, 900, 910, 1000, 1010

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of a multi-output rectifier 100 according to a first embodiment of the disclosure, in which the multi-output rectifier 100 includes an active rectifier circuit 102 with a comparator structure and a power supply circuit 104, the active rectifier circuit 102 includes a circuit 1022 with a comparator structure and 4 start-up circuits 1024-. In addition, as shown in fig. 1, the power supply circuit 104 is coupled to the active rectifier circuit 102, and is configured to generate a power supply voltage VCC applied to the start-up

circuit

1024 and 1030 according to an ac input voltage VIN. As shown in fig. 1, the turn-on

circuits

1024 and 1026 correspond to the output voltage VOUT1 outputted by the multi-output rectifier 100, and the turn-on

circuits

1028 and 1030 correspond to the output voltage VOUT2 outputted by the multi-output rectifier 100, wherein the output voltage VOUT1 is applied to the load 200 and the output voltage VOUT2 is applied to the load 300. However, the present invention is not limited to the multi-output rectifier 100 only outputting the output voltages VOUT1 and VOUT2, that is, the multi-output rectifier 100 can output at least two output voltages, and the number of the on circuits included in the active rectifier circuit 102 will change the number of the output voltages outputted by the multi-output rectifier 100 correspondingly. As shown in fig. 1, the comparator-structured circuit 1022 includes a first pmos transistor 10222, a second pmos transistor 10224, a third pmos transistor 10226, a fourth pmos transistor 10228, a first nmos transistor 10230 and a second nmos transistor 10232, wherein the coupling relationship among the first pmos transistor 10222, the second pmos transistor 10224, the third pmos transistor 10226, the fourth pmos transistor 10228, the first nmos transistor 10230 and the second nmos transistor 10232 is not repeated with reference to fig. 1. In addition, as shown in fig. 1, the enabling circuit 1024 includes a first comparator 10242 and a first logic circuit 10244; the turn-on circuit 1026 includes a second comparator 10262 and a second logic 10264; the enabling circuit 1028 includes a third comparator 10282 and a third logic 10284; the turn-on circuit 1030 includes a fourth comparator 10302 and a fourth logic circuit 10304, wherein the coupling relationship among the first comparator 10242, the first logic circuit 10244, the second comparator 10262, the second logic circuit 10264, the third comparator 10282, the third logic circuit 10284, the fourth comparator 10302 and the fourth logic circuit 10304 is please refer to fig. 1, which is not repeated herein. In addition, when the amplitude of the ac input voltage VIN is larger, the supply voltage VCC still enables the multi-output rectifier 100 to operate normally, that is, the present invention provides the supply voltage VCC with a higher level to the turn-on circuit 1024-.

Referring to fig. 2, fig. 2 is a schematic diagram of an operation timing of the multi-output rectifier 100 in a positive half cycle TP of an ac input voltage VIN, as shown in fig. 2, when a dc voltage INP (where the dc voltage INP is a voltage signal obtained by half-wave or full-wave rectifying the ac input voltage VIN) corresponding to the positive half cycle TP of the ac input voltage VIN is greater than an output voltage VOUT2, the third comparator 10282 generates a comparison signal VCOMP3, the third logic circuit 10284 performs a logic operation on the comparison signal VCOMP3 and a control signal VCTR L corresponding to the output voltage VOUT2 to generate a turn-on signal VGP3, where the control signal VCTR L2 is generated by a controller 106 further included in the multi-output rectifier 100, the controller 106 is coupled to the active rectifier circuit 102, and the comparison signal VCOMP3 corresponds to a predetermined time interval of the positive half cycle of the ac input voltage VIN, the comparison signal VCTR 462 is a predetermined time interval ptp 2 v — vWhen the dc voltage INP is greater than the output voltage VOUT2, the third comparator 10282 generates the comparison signal VCOMP3, that is, in another embodiment of the invention, the third comparator 10282 generates the comparison signal VCOMP3 when the dc voltage INP is less than the output voltage VOUT2, and then the third logic circuit 10284 generates an inverted comparison signal VCOMP3

The logical operation is performed with the control signal VCTR L2 to generate the turn-on signal VGP 3.

As shown in fig. 2, when the dc voltage INP is greater than the output voltage VOUT1, the first comparator 10242 generates a comparison signal VCOMP1, then the first logic circuit 10244 performs the logic operation on the comparison signal VCOMP1 and a control signal VCTR L corresponding to the output voltage VOUT1 to generate a turn-on signal VGP1, wherein the control signal VCTR L1 is generated by the controller 106, and the comparison signal VCOMP1 corresponds to a predetermined time interval ptv1 of a positive half cycle TP of the ac input voltage VIN, further, the first logic circuit 10244 is an or gate, and the logic operation performed by the first logic circuit 10244 is an or operation, as shown in fig. 1, after the first logic circuit 10244 generates the turn-on signal VGP1, the first P-type mos transistor 10222 may be turned on according to the turn-on signal VGP1, wherein when the first P-type mos transistor 10222 is turned on according to the turn-on signal VGP1, the comparison signal VCOMP 1022 is greater than the first logic circuit VOUT 6326, when the first logic circuit generates the comparison signal VCOMP 1026, which is also includes a comparison signal VCOMP 1028 that is greater than the first analog output voltage VOUT 6327, and is not less than the first comparison signal VOUT P19, which is provided by the first comparator output voltage VOUT equivalent to the first logic circuit 1, when the first logic circuit 1, which is also includes a comparison signal VCOMP 6321, which is provided by the first comparison signal VCOMP, which is greater than the first logic circuit for the first analog output voltage VOUT equivalent to the first output voltage VOUT 636, and the first logic circuit for the first comparator circuit for the first output voltage VOUT 6327, which is greater than the first charge circuit for the first charge circuit 1, or for the output voltage VOUT equivalent to the first charge circuit, which is not for the output voltage VOUT equivalent,the first logic circuit 10244 then compares an inverted comparison signal

The logical operation is performed with the control signal VCTR L1 to generate the turn-on signal VGP 1.

As shown in FIG. 2, since the first PMOS transistor 10222 is turned on according to the turn-on signal VGP1, and the turn-on signal VGP1 is determined by the comparison signal VCOMP1 and the control signal VCTR L1, the user can control the turn-on time of the first PMOS transistor 10222 by the predetermined time interval PTV1 (because the comparison signal VCOMP1 corresponds to the predetermined time interval PTV1) and the length of the control signal VCTR L1. similarly, the user can control the turn-on time of the third PMOS transistor 10226 by the predetermined time interval PTV2 (because the comparison signal VCOMP3 corresponds to the predetermined time interval PTV2) and the length of the control signal VCTR L2. in addition, the present invention is not limited to the first logic circuit 10244 and the third logic circuit 10284 being OR gates, that the first logic circuit 102P 1 and the turn-on signal VGP3 generated by the first logic circuit 10244 and the third logic circuit 10284 are not overlapped.

Referring to fig. 3, fig. 3 is a schematic diagram of an operation timing of the multi-output rectifier 100 in the negative half-cycle TN of the ac input voltage VIN, as shown in fig. 3, when the dc voltage INN (where the dc voltage INN is a voltage signal obtained by half-wave or full-wave rectifying the ac input voltage VIN) corresponding to the negative half-cycle TN of the ac input voltage VIN is greater than the output voltage VOUT2, the fourth comparator 10302 generates a comparison signal VCOMP4, and then the fourth logic 10304 performs the logic operation on the comparison signal VCOMP4 and the control signal VCTR L2 to generate a turn-on signal VGP4, where the comparison signal VCOMP4 corresponds to a predetermined time interval ptv8652 of the negative half-cycle of the ac input voltage VIN, and the fourth logic 10304 is an or gate, and the logic operation performed by the fourth logic 10304 is also an or operation, as shown in fig. 1, after the fourth logic 10304 generates the turn-on signal VGP4, the fourth logic 1036 generates the turn-on signal VGP 10324 according to the principle that the turn-on signal of the first and the second comparator circuit may output transistor 102324 when the fourth comparator 10323 generates the turn-on signal VGP 10228 and the second comparator circuit according to the principle that the output transistor.

As shown in fig. 3, when the dc voltage INN is greater than the output voltage VOUT1, the second comparator 10262 generates a comparison signal VCOMP2, and then the second logic circuit 10264 performs the logic operation on the comparison signal VCOMP2 and the control signal VCTR L1 to generate a turn-on signal VGP2, wherein the comparison signal VCOMP2 corresponds to a predetermined time interval ptv1 of the negative half-cycle TN of the ac input voltage VIN, and further, the second logic circuit 10264 is also an or gate, and the logic operation performed by the second logic circuit 10264 is also an or operation, as shown in fig. 1, after the second logic circuit 10264 generates the turn-on signal VGP2, the second pmos transistor 10224 is turned on according to the turn-on signal VGP2, wherein when the second pmos transistor 10224 is turned on according to the turn-on signal VGP2, the first pmos transistor 10224 and the first nmos transistor 1022 in the circuit of the comparator structure are both turned on, and the first and second pmos transistor 10224 and the output voltage VOUT and the second transistor 102324 are no longer operated according to the principle of the turn-on output voltage VOUT P circuit VOUT P1, and the output voltage VOUT P circuit 1023110.

As shown in FIG. 3, the user can control the turn-on time of the second PMOS transistor 10224 by the predetermined time interval PTV1 (since the comparison signal VCOMP2 corresponds to the predetermined time interval PTV1) and the length of the control signal VCTR L1. similarly, the user can also control the turn-on time of the fourth PMOS transistor 10228 by the predetermined time interval PTV2 (since the comparison signal VCOMP4 corresponds to the predetermined time interval PTV2) and the length of the control signal VCTR L2. in addition, the present invention is not limited to the second logic circuit 10264 and the fourth logic circuit 10304 being OR gates, that is, as long as the turn-on signal VGP2 generated by the second logic circuit 10264 and the turn-on signal VGP4 generated by the fourth logic circuit 10304 do not overlap with each other, the second logic circuit 10264 and the fourth logic circuit 10304 fall within the scope of the present invention.

In addition, as shown in fig. 2, the active rectifier circuit 102 generates and outputs the output voltages VOUT1, VOUT2 in one same period of the ac input voltage VIN (i.e., in the positive half period TP), or as shown in fig. 3, outputs the output voltages VOUT1, VOUT2 in another same period of the ac input voltage VIN (i.e., in the negative half period TN).

Referring to fig. 4, fig. 4 is a schematic diagram illustrating an active rectifier circuit 102 outputting an output voltage VOUT at a first positive half-cycle TP of an ac input voltage VIN and outputting the output voltage VOUT at a second positive half-cycle TP of the ac input voltage VIN, wherein the first positive half-cycle TP and the second positive half-cycle TP are consecutive positive half-cycles of the ac input voltage VIN, as shown in fig. 4, when a dc voltage INP corresponding to the first positive half-cycle TP of the ac input voltage VIN (where the dc voltage INP is a voltage signal of the ac input voltage VIN after half-wave or full-wave rectification) is greater than the output voltage VOUT, a third comparator 10282 generates a comparison signal VCOMP, and then the third logic circuit 10284 performs the logic operation with the comparison signal VCOMP and a control signal VCTR 2 corresponding to the output voltage VOUT to generate a turn-on signal VGP, wherein the comparison signal VCOMP corresponds to a predetermined time interval vptp of the first positive half-cycle of the ac input voltage VIN, as shown in fig. 1, after the third logic circuit generates the turn-on signal VGP, the turn-on signal vcmp corresponds to a first positive half-on signal vcp, wherein the output voltage VOUT is generated by comparing the output voltage VOUT when the comparison signal vcmp corresponding to the first positive half-on signal vcp, the output voltage VOUT is greater than the output voltage VOUT, and the second half-on signal vcp, and the output voltage VOUT, when the comparison signal vcp corresponding semiconductor transistor VOUT is generated by the comparison signal vcp, the comparison signal vcmp, the output voltage VOUT is generated by the output transistor output voltage VOUT, and the output voltage VOUT, wherein the output voltage VOUT, the comparison circuit generates a comparison signal vcmp, and the output voltage VOUT, the output voltage output transistor output voltage output transistor output voltage.

As shown in FIG. 4, the user can control the turn-on time of the first PMOS transistor 10222 by the predetermined time interval PTV1 (because the comparison signal VCOMP1 corresponds to the predetermined time interval PTV1) and the length of the control signal VCTR L1, and similarly, the user can control the turn-on time of the third PMOS transistor 10226 by the predetermined time interval PTV2 (because the comparison signal VCOMP3 corresponds to the predetermined time interval PTV2) and the length of the control signal VCTR L2.

Referring to fig. 5, fig. 5 is a schematic diagram illustrating the active rectifier circuit 102 outputting the output voltage VOUT at a first negative half-cycle TN of the ac input voltage VIN and outputting the output voltage VOUT at a second negative half-cycle TN of the ac input voltage VIN, wherein the first negative half-cycle TN and the second negative half-cycle TN are consecutive negative half-cycles of the ac input voltage VIN, as shown in fig. 5, when the dc voltage INN corresponding to the first negative half-cycle of the ac input voltage VIN (wherein the dc voltage INN is a voltage signal of the ac input voltage VIN after half-wave or full-wave rectification) is greater than the output voltage VOUT, the fourth comparator 10302 generates the comparison signal VCOMP, and then the fourth logic 10304 performs the logic operation with the comparison signal VCOMP and the control signal VCTR 2 to generate the turn-on signal VGP, wherein the comparison signal VCOMP generates the turn-on signal VGP at a predetermined time interval ptp 2 corresponding to the first negative half-cycle of the ac input voltage VIN, as shown in fig. 1, after the fourth logic circuit generates the turn-on signal VGP, wherein the comparison signal VCOMP is generated by comparing the semiconductor transistor VOUT with the second half-on signal VCOMP corresponding to generate the second half-on signal VCOMP, and the second half-on signal vcop, wherein the comparison signal VCOMP is generated when the comparison signal VCOMP is greater than the second half-off signal VCOMP generated by the second logic circuit according to the comparison signal vcop 1, wherein the comparison signal VCOMP, the comparison signal vcn is generated by the comparison signal vcn, the comparison signal vcp, the comparison signal vcn is generated by the comparison signal vcn, the comparison signal vcp, and the comparison signal vcn is generated by the comparison signal vcn, and the comparison signal vcp, and the comparison signal vcn, and.

As shown in FIG. 5, the user can control the turn-on time of the second PMOS transistor 10224 by the predetermined time interval PTV1 (because the comparison signal VCOMP2 corresponds to the predetermined time interval PTV1) and the length of the control signal VCTR L1, and similarly, the user can control the turn-on time of the fourth PMOS transistor 10228 by the predetermined time interval PTV2 (because the comparison signal VCOMP4 corresponds to the predetermined time interval PTV2) and the length of the control signal VCTR L2.

In addition, as shown in fig. 4, the active rectifier circuit 102 generates and outputs the output voltage VOUT2 in the first positive half period TP1 of the ac input voltage VIN (i.e., corresponding to the dedicated half period of the output voltage VOUT2) and the output voltage VOUT1 in the second positive half period TP2 of the ac input voltage VIN (i.e., corresponding to the dedicated half period of the output voltage VOUT 1); as shown in fig. 5, the active rectifier circuit 102 generates and outputs the output voltage VOUT2 during a first negative half-cycle TN1 of the ac input voltage VIN (i.e., corresponding to a dedicated half-cycle of the output voltage VOUT2) and the output voltage VOUT1 during a second negative half-cycle TN2 of the ac input voltage VIN (i.e., corresponding to a dedicated half-cycle of the output voltage VOUT 1).

Referring to fig. 6, fig. 6 is a schematic diagram of a multi-output rectifier 600 according to a second embodiment of the present invention, as shown in fig. 6, a controller 602 of the multi-output rectifier 600 includes a first sub-controller 6022 and a second sub-controller 6024, so the difference between the output rectifier 600 and the multi-output rectifier 100 is that the first sub-controller 6022 generates a control signal VCTR L corresponding to an output voltage VOUT1 according to a first reference voltage VREF1 and an output voltage VOUT1, and the second sub-controller 6024 generates a control signal VCTR L corresponding to an output voltage VOUT2 according to a second reference voltage VREF2 and an output voltage VOUT2, wherein the first sub-controller 6022 and the second sub-controller 6024 are Pulse Width Modulation (PWM) controllers or pulse frequency modulation (pulse frequency modulation, PFM) controllers, and the control signal VREF L generated by the first sub-controller 6022 and the second sub-controller VCTR 6 can be controlled by the output voltage VREF 10226 according to the principle of the first reference voltage VREF 1022 and the second sub-controller output voltage VREF 10226, and the output voltage of the second sub-rectifier 600 can be controlled by the same principle as the output voltage of the first sub-rectifier 60226, so that the output voltage VREF 1022 and the output voltage of the output of the second sub-output rectifier 600 can be controlled by the output transistor 6026, the output voltage of the first sub-rectifier 600 can be controlled by the same as the output voltage of the first sub-output rectifier 600, the first sub-output rectifier 11, the second sub-rectifier 600, the output rectifier 11, the output voltage of the output rectifier 600 can be described again with the principle of the first sub-output voltage of the second sub-output rectifier 11, the second sub-output voltage of the first sub-controller 6022, the second sub-rectifier 11, the same principle, the second sub-output rectifier 11, the principle, the first sub-rectifier can be controlled by the.

Referring to fig. 1-3 and fig. 7, fig. 7 is a flowchart illustrating a method for operating a multi-output rectifier according to a third embodiment of the present invention. The method of operation of fig. 7 is illustrated using the multi-output rectifier 100 of fig. 1, with the detailed steps as follows:

step 700: starting;

step 702: in the same half period of the alternating-current input voltage VIN, a starting circuit corresponding to each output voltage in the starting circuits 1024-1030 generates a corresponding comparison signal according to the alternating-current input voltage VIN and each output voltage;

step 704: the starting circuit generates a corresponding starting signal according to the corresponding comparison signal and the control signal corresponding to each output voltage;

step 706: the comparator-structured circuit 1022 generates and outputs each output voltage according to the corresponding turn-on signal;

step 708: and (6) ending.

Taking the output voltage VOUT2 of the multi-output rectifier 100 as an example, in step 702, as shown in fig. 2, when the dc voltage INP is greater than the output voltage VOUT2, the third comparator 10282 (corresponding to the output voltage VOUT2) in the turn-on circuit 1028 generates the comparison signal VCOMP 3. then, in step 704, the third logic circuit 10284 in the turn-on circuit 1028 performs the logic operation on the comparison signal VCOMP3 and the control signal VCTR L corresponding to the output voltage VOUT2 to generate the turn-on signal VGP3, wherein the control signal VCTR L is generated by the controller 106 additionally included in the multi-output rectifier 100, and the comparison signal VCOMP 5 387 corresponds to the predetermined time interval ptv2 of the positive TP half cycle of the ac input voltage VIN. in step 706, as shown in fig. 1, after the third logic circuit 10284 generates the turn-on signal VGP3, the third pmos transistor 10226 of the comparator circuit may be turned on according to the turn-on signal VGP3, wherein when the third comparator 10226 generates the turn-on signal VGP 1022 corresponding to the third comparator circuit 102324 and the second comparator circuit may provide the comparison signal VCOMP 26 according to the turn-on signal VGP 1023n 24, wherein the third comparator circuit 102326 and the third comparator circuit opens the third comparator circuit 102326 in the third comparator circuit opens the third comparator circuit may provide the third comparator circuit on signal VGP 26 according to the third comparator circuit 1023p 26The oxide semiconductor transistor 10226 generates and outputs the output voltage VOUT2 when turned on. In addition, the invention is not limited to the case where the third comparator 10282 generates the comparison signal VCOMP3 when the dc voltage INP is greater than the output voltage VOUT2, that is, in another embodiment of the invention, the third comparator 10282 generates the comparison signal VCOMP3 when the dc voltage INP is less than the output voltage VOUT2, and then the third logic 10284 generates an inverted comparison signal VCOMP3

Taking the output voltage VOUT1 of the multi-output rectifier 100 as an example, in step 702, as shown in fig. 2, when the dc voltage INP is greater than the output voltage VOUT1, the first comparator 10242 (corresponding to the output voltage VOUT1) of the turn-on circuit 1024 generates the comparison signal VCOMP 1. then, in step 704, the first logic circuit 10244 of the turn-on circuit 1024 may perform the logic operation on the comparison signal VCOMP1 and the control signal VCTR L corresponding to the output voltage VOUT1 to generate the turn-on signal VGP1, wherein the control signal VCTR L is generated by the controller 106, and the comparison signal VCOMP1 corresponds to the predetermined time interval ptvvvp 1 of the positive half-cycle TP of the ac input voltage VIN, in step 706, as shown in fig. 1, after the first logic circuit 10244 generates the turn-on signal VGP1, the first pmos transistor 10222 of the comparator configuration may be turned on according to the turn-on signal VGP1 when the first logic circuit 10244 generates the turn-on signal VGP 102p 1, when the first comparator output voltage VOUT is greater than the first comparator output voltage VOUT 34, which is limited by the comparison signal VOUT P of the first comparator 100, i.e.g. when the comparison circuit 110 and the comparison circuit 110, which may not be provided by the first comparator output voltage VOUT P19, which, the comparison circuit 110, which is greater than the first comparator output voltage VOUT P19, which is greater than the first comparator output voltage VOUT 11, which is greater than the first comparator output voltage VOUT1, which is generated by the first comparator circuit 110, which is not limited by the first comparator circuit 110, which is generated by the first comparator circuit according to the first comparator circuit of the firstWhen INP is less than VOUT1, the comparison signal VCOMP1 is generated, and then the first logic circuit 10244 generates an inverted comparison signal

Therefore, as shown in fig. 2, the active rectifier circuit 102 generates and outputs the output voltages VOUT1 and VOUT2 during the same period (i.e., during the positive half period TP) of the ac input voltage VIN. In addition, as shown in fig. 3, the active rectifier circuit 102 may also output the output voltages VOUT1 and VOUT2 in another same period of the ac input voltage VIN (i.e., in the negative half period TN), which is not described herein again.

Referring to fig. 1, 4, 5 and 8, fig. 8 is a flowchart illustrating a method for operating a multi-output rectifier according to a fourth embodiment of the present invention. The method of operation of fig. 8 is illustrated using the multi-output rectifier 100 of fig. 1, with the detailed steps as follows:

step 800: starting;

step 802: in a special half period of the ac input voltage VIN corresponding to each output voltage, a start circuit corresponding to each output voltage in the start circuit 1024-;

step 804: the starting circuit generates a corresponding starting signal according to the corresponding comparison signal and the control signal corresponding to each output voltage;

step 806: the comparator-structured circuit 1022 generates and outputs each output voltage according to the corresponding turn-on signal;

step 808: and (6) ending.

Taking the output voltage VOUT2 of the multi-output rectifier 100 as an example, in step 802, as shown in fig. 4, when the dc voltage INP1 is greater than the output voltage VOUT2, the third comparator 10282 (corresponding to the output voltage VOUT2) in the turn-on circuit 1028 generates the comparison signal vcomp3, then in step 804, the third logic circuit 10284 in the turn-on circuit 1028 performs the logic operation on the comparison signal VCOMP3 and the control signal VCTR L corresponding to the output voltage VOUT2 to generate the turn-on signal VGP3, wherein the comparison signal VCOMP3 corresponds to the predetermined time interval ptv2 of the first positive half-period TP1 of the ac input voltage VIN, in step 806, as shown in fig. 1, after the third logic circuit 10284 generates the turn-on signal VGP3, the third P-type mos transistor 10226 of the comparator-based circuit 1022 may be turned on according to the turn-on signal VGP3, wherein when the third P-type mos transistor 10226 is turned on according to the turn-on signal VGP3, the comparison signal VOUT 1022 and the output voltage VOUT 2.

In addition, taking the output voltage VOUT1 of the multi-output rectifier 100 as an example, in step 802, as shown in fig. 4, when the dc voltage INP2 is greater than the output voltage VOUT1, the first comparator 10242 (corresponding to the output voltage VOUT1) in the turn-on circuit 1024 generates the comparison signal vcomp1, then in step 804, the first logic circuit 10244 in the turn-on circuit 1024 performs the logic operation on the comparison signal VCOMP1 and the control signal VCTR L1 corresponding to the output voltage VOUT1 to generate the turn-on signal VGP1, wherein the comparison signal VCOMP1 corresponds to the predetermined time interval ptv1 of the second positive 685tp half period 2 of the ac input voltage, in step 806, as shown in fig. 1, after the first logic circuit 10244 generates the turn-on signal VGP1, the first pmos transistor 10222 of the comparator-based circuit may be turned on according to the turn-on signal VGP 1023, wherein when the first pmos transistor 102p 22 outputs the comparison signal VOUT1 and the comparison signal VOUT 73784.

Taking the example of the multi-output rectifier 100 outputting the output voltage VOUT2, in step 802, as shown in fig. 5, when the dc voltage INN1 is greater than the output voltage VOUT2, the fourth comparator 10302 (corresponding to the output voltage VOUT2) in the turn-on circuit 1030 generates the comparison signal vcomp4. then, in step 804, the fourth logic circuit 10304 in the turn-on circuit 1030 performs the logic operations on the comparison signal VCOMP4 and the control signal VCTR L to generate the turn-on signal VGP4, wherein the comparison signal VCOMP4 corresponds to the predetermined time interval ptv2 of the first negative half-cycle TN 7 of the ac input voltage VIN. in step 806, as shown in fig. 1, after the fourth logic circuit 10304 generates the turn-on signal VGP4, the fourth P-type mos transistor 10228 of the comparator configuration circuit 1022 is turned on according to the turn-on signal VGP4, wherein when the fourth P-type mos transistor 1033 is turned on according to the turn-on signal VGP4, the comparator configuration circuit 1022 and the output voltage VOUT2 are turned on according to the turn-on signal VGP 4.

In addition, taking the output voltage VOUT1 of the multi-output rectifier 100 as an example, in step 802, as shown in fig. 5, when the dc voltage INN2 is greater than the output voltage VOUT1, the second comparator 10262 (corresponding to the output voltage VOUT1) in the turn-on circuit 1026 generates the comparison signal vcomp2, then in step 804, the second logic circuit 10264 in the turn-on circuit 1026 may perform the logic operation on the comparison signal VCOMP2 and the control signal VCTR L to generate the turn-on signal VGP2, wherein the comparison signal VCOMP2 corresponds to the predetermined time interval ptv1 of the second negative half-cycle TN2 of the ac input voltage VIN, in step 806, as shown in fig. 1, after the second logic circuit 10264 generates the turn-on signal VGP2, the second pmos transistor 10224 of the comparator-based circuit 1022 may be turned on according to the turn-on signal VGP 463, wherein when the second pmos transistor 10224 is turned on according to the turn-on signal VGP2, the comparison circuit 1022 and the output voltage VOUT1 may be output by the comparator-based on circuit 4673784.

Therefore, as shown in fig. 4, the active rectifier circuit 102 generates and outputs the output voltage VOUT2 during the first positive half-cycle TP1 of the ac input voltage VIN (i.e., corresponding to the dedicated half-cycle of the output voltage VOUT2) and the output voltage VOUT1 during the second positive half-cycle TP2 of the ac input voltage VIN (i.e., corresponding to the dedicated half-cycle of the output voltage VOUT 1); as shown in fig. 5, the active rectifier circuit 102 generates and outputs the output voltage VOUT2 during a first negative half-cycle TN1 of the ac input voltage VIN (i.e., corresponding to a dedicated half-cycle of the output voltage VOUT2) and the output voltage VOUT1 during a second negative half-cycle TN2 of the ac input voltage VIN (i.e., corresponding to a dedicated half-cycle of the output voltage VOUT 1).

Referring to fig. 2, 3, 6 and 9, fig. 9 is a flowchart illustrating a method for operating a multi-output rectifier according to a fifth embodiment of the present invention. The method of operation of fig. 9 is illustrated using the multi-output rectifier 600 of fig. 6, with the detailed steps as follows:

step 900: starting;

step 902: the controller 602 generates a control signal according to each of the output voltages outputted from the multi-output rectifier 600 and a reference voltage corresponding to the output voltage;

step 904: in the same half period of the alternating-current input voltage VIN, a starting circuit corresponding to each output voltage in the starting circuits 1024-1030 generates a corresponding comparison signal according to the alternating-current input voltage VIN and each output voltage;

step 906: the starting circuit generates a corresponding starting signal according to the corresponding comparison signal and the control signal corresponding to each output voltage;

step 908: the comparator-structured circuit 1022 generates and outputs each output voltage according to the corresponding turn-on signal;

step 910: and (6) ending.

The difference between the embodiment of fig. 9 and the embodiment of fig. 7 is that in step 902, as shown in fig. 6, a first sub-controller 6022 in the controller 602 generates a control signal VCTR L1 corresponding to the output voltage VOUT1 according to the first reference voltage VREF1 and the output voltage VOUT1, and a second sub-controller 6024 in the controller 602 generates a control signal VCTR L2 corresponding to the output voltage VOUT2 according to the second reference voltage VREF2 and the output voltage VOUT2, wherein the operation principle of the control signal VCTR L1 generated by the first sub-controller 6022 and the operation principle of the control signal VCTR L2 generated by the second sub-controller 6024 are repeated with reference to fig. 2 and 3, and are not repeated here.

Referring to fig. 4, 5, 6 and 10, fig. 10 is a flowchart illustrating a method for operating a multi-output rectifier according to a sixth embodiment of the present invention. The method of operation of fig. 10 is illustrated using the multi-output rectifier 600 of fig. 6, with the detailed steps as follows:

step 1000: starting;

step 1002: the controller 602 generates a control signal according to each of the output voltages outputted from the multi-output rectifier 600 and a reference voltage corresponding to the output voltage;

step 1004: in a dedicated half period of the ac input voltage VIN corresponding to each output voltage, a start circuit corresponding to each output voltage in the start circuit 1024-;

step 1006: the starting circuit generates a corresponding starting signal according to the corresponding comparison signal and the control signal corresponding to each output voltage;

step 1008: the comparator-structured circuit 1022 generates and outputs each output voltage according to the corresponding turn-on signal;

step 1010: and (6) ending.

The difference between the embodiment of fig. 10 and the embodiment of fig. 8 is that in step 1002, as shown in fig. 6, a first sub-controller 6022 in the controller 602 generates a control signal VCTR L1 corresponding to the output voltage VOUT1 according to the first reference voltage VREF1 and the output voltage VOUT1, and a second sub-controller 6024 in the controller 602 generates a control signal VCTR L2 corresponding to the output voltage VOUT2 according to the second reference voltage VREF2 and the output voltage VOUT2, wherein the operation principle of the control signal VCTR L1 generated by the first sub-controller 6022 and the control signal VCTR L2 generated by the second sub-controller 6024 can refer to fig. 4 and 5, and will not be described herein again.

In summary, the multi-output rectifier and the operating method thereof disclosed in the present invention can provide a plurality of stable output voltages for the circuit system of the next stage, so the present invention is applicable to a wireless charging receiver. In addition, compared to the prior art, the multi-output rectifier disclosed in the present invention can stabilize the plurality of output voltages at their corresponding predetermined values by controlling the on-time of the transistors in the circuit of the comparator architecture included in the multi-output rectifier, so that the present invention can eliminate the need for additional dc-dc converters and discrete components. Therefore, the invention can not only reduce the cost of the multi-output rectifier, but also be easily integrated into other application devices, because the invention can not need additional DC-DC converter and discrete components.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A multiple output rectifier, comprising:

an active rectifier circuit with a comparator architecture is used for generating a corresponding comparison signal according to an input voltage and each output voltage of a plurality of output voltages output by a multi-output rectifier in a same half period of the input voltage, generating a corresponding starting signal according to the corresponding comparison signal and a control signal corresponding to each output voltage, and generating and outputting each output voltage according to the corresponding starting signal, wherein the corresponding comparison signal corresponds to a preset time interval of the same half period, and each output voltage is smaller than the input voltage in the preset time interval.

2. The multi-output rectifier of claim 1 wherein: the active rectifier circuit includes:

a comparator configured to generate and output each of the output voltages according to the corresponding turn-on signal; and

and a plurality of start-up circuits coupled to the circuitry of the comparator architecture, wherein a start-up circuit of the plurality of start-up circuits corresponding to each output voltage is configured to generate the corresponding comparison signal according to the input voltage and each output voltage, and to generate the corresponding start-up signal according to the corresponding comparison signal and the control signal.

3. The multi-output rectifier of claim 2 wherein: further comprising:

the active rectifying circuit is coupled to the power supply circuit and used for generating a power supply voltage applied to the plurality of starting circuits according to the input voltage.

4. The multi-output rectifier of claim 1 wherein: further comprising:

and the controller is coupled with the active rectifying circuit and used for generating a control signal corresponding to each output voltage.

5. A multiple output rectifier, comprising:

an active rectifier circuit with a comparator architecture is used for generating a corresponding comparison signal according to an input voltage and each output voltage of a plurality of output voltages output by a multi-output rectifier in a special half period of the input voltage, generating a corresponding starting signal according to the corresponding comparison signal and a control signal corresponding to each output voltage, and generating and outputting each output voltage according to the corresponding starting signal, wherein the corresponding comparison signal corresponds to a preset time interval of the special half period, and each output voltage is smaller than the input voltage in the preset time interval.

6. The multi-output rectifier of claim 5 wherein: the active rectifier circuit includes:

7. The multi-output rectifier of claim 6 wherein: further comprising:

8. The multi-output rectifier of claim 5 wherein: further comprising:

9. A method of operating a multi-output rectifier, wherein the multi-output rectifier includes an active rectifier circuit of a comparator architecture, and the active rectifier circuit includes a circuit of the comparator architecture and a plurality of turn-on circuits, comprising:

during a same half period of an input voltage, a starting circuit of the starting circuits corresponding to each output voltage of a plurality of output voltages output by the multi-output rectifier generates a corresponding comparison signal according to the input voltage and each output voltage;

the starting circuit generates a corresponding starting signal according to the corresponding comparison signal and the control signal corresponding to each output voltage; and

the circuit of the comparator framework generates and outputs each output voltage according to the corresponding starting signal;

wherein the corresponding comparison signal corresponds to a predetermined time interval of the same half period, and each output voltage is smaller than the input voltage in the predetermined time interval.

10. A method of operating a multi-output rectifier, wherein the multi-output rectifier includes an active rectifier circuit of a comparator architecture, and the active rectifier circuit includes a circuit of the comparator architecture and a plurality of turn-on circuits, comprising:

during a dedicated half period of an input voltage, a starting circuit of the plurality of starting circuits corresponding to each output voltage of a plurality of output voltages output by the multi-output rectifier generates a corresponding comparison signal according to the input voltage and each output voltage;

wherein the corresponding comparison signal corresponds to a predetermined time interval of the dedicated half cycle, and each output voltage is smaller than the input voltage in the predetermined time interval.

11. A method of operating a multi-output rectifier, wherein the multi-output rectifier includes an active rectifier circuit of a comparator architecture and a controller, and the active rectifier circuit includes a circuit of the comparator architecture and a plurality of turn-on circuits, the method comprising:

the controller generates a control signal according to each output voltage of a plurality of output voltages output by the multi-output rectifier and a reference voltage corresponding to each output voltage;

in a same half period of an input voltage, a starting circuit corresponding to each output voltage in the starting circuits generates a corresponding comparison signal according to the input voltage and each output voltage;

the starting circuit generates a corresponding starting signal according to the corresponding comparison signal and the control signal; and

12. A method of operating a multi-output rectifier, wherein the multi-output rectifier includes an active rectifier circuit of a comparator architecture and a controller, and the active rectifier circuit includes a circuit of the comparator architecture and a plurality of turn-on circuits, the method comprising:

in a special half period of an input voltage, a starting circuit corresponding to each output voltage in the starting circuits generates a corresponding comparison signal according to the input voltage and each output voltage;