CN108306533B - A kind of single-phase three-level inverter circuit - Google Patents
A kind of single-phase three-level inverter circuit Download PDFInfo
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- CN108306533B CN108306533B CN201810050577.1A CN201810050577A CN108306533B CN 108306533 B CN108306533 B CN 108306533B CN 201810050577 A CN201810050577 A CN 201810050577A CN 108306533 B CN108306533 B CN 108306533B
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- diode
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
Abstract
The invention discloses a kind of single-phase three-level inverter circuits, using three level designs, inverter output voltage in each switch periods only has zero level and a positive or negative level, compared with two level circuits, it shows more excellent on output voltage and current harmonics performance, simultaneously because the variation of each switch periods inverter output voltage is the half of two level circuits, therefore the parameter of its output filter will be obviously reduced；It is simpler using single phase design, facilitate analysis to handle.Therefore, the invention has the following advantages that design is simple, facilitate analysis, the parameter of output filter is smaller, and in terms of output voltage and the performance of harmonic wave aspect of performance is preferable, can satisfy low EMI and low ripple electric current, interferes smaller.
Description
Technical field
The present invention relates to the convertor circuit in field of power electronics, especially a kind of single-phase three-level inverter circuit.
Background technique
Inverter, which refers to, turns on and off effect converting direct-current power into alternating-current power by semiconductor power IGBT pipe
A kind of converter.Common inverter circuit includes topological full-bridge circuit, half-bridge circuit and half-bridge mid point clamp circuit etc.；It presses
According to the difference of output level, inverter circuit can be divided into two level circuits, tri-level circuit and multi-level circuit.Wherein,
Two level circuits refer to that under PWM modulation mode, the waveform of inverter output voltage can occur positive and negative two in each switch periods
The polar level of kind, each of which switch periods inverter output voltage changes greatly, therefore the parameter of output filter is larger, whole
The volume and weight of a circuit device is larger, performs poor in terms of output voltage with harmonic wave aspect of performance, especially EMI and line
Wave electric current is higher, and there is biggish interference.
Summary of the invention
To solve the above-mentioned problems, the object of the present invention is to provide a kind of single-phase three-level inverter circuit, the circuit designs
Simply, facilitate processing, the parameter of output filter is smaller, and in terms of output voltage and the performance of harmonic wave aspect of performance is preferable.
In order to make up for the deficiencies of the prior art, the technical solution adopted by the present invention is that:
A kind of single-phase three-level inverter circuit, including inversion element, the first inductance, the second inductance, first capacitor, the second electricity
Appearance and Input voltage terminal；Inversion element includes the first inversion element, the second inversion element, third inversion element, the 4th inversion member
Part, the 5th inversion element, the 6th inversion element and the 7th inversion element；The emitter of 5th inversion element is arranged in the first inversion
On the intersection node of element, third inversion element and the first inductance, the collector of the 5th inversion element is connect in the 7th inversion element
Collector and the 6th inversion element collector intersection node on；The emitter of 6th inversion element is arranged in the second inversion
On the intersection node of element, the 4th inversion element and the second inductance, the collector of the 6th inversion element is connect in the 7th inversion element
Collector and the 5th inversion element collector intersection node on；First inversion element and third inversion element are connected in series
And be connected in series respectively with the first inductance connection, the second inversion element and the 4th inversion element and respectively with the second inductance connection；
First capacitor and the second capacitor are connected in series, and the collector of the 7th inversion element is connected respectively to the 5th inversion element and the 6th inverse
Dependent element, the emitter of the 7th inversion element are connected to the intersection node of first capacitor and the second capacitor；The setting of first inductance exists
Connect on firewire and with the emitter of the 5th inversion element, the transmitting on zero curve and with the 6th inversion element is arranged in the second inductance
Pole connects；The anode of first capacitor is connected to the anode of Input voltage terminal, and the cathode of the second capacitor is connected to the negative terminal of Input voltage terminal.
Further, the first inversion element includes the first internal diode of the first IGBT pipe and reverse parallel connection, the second inversion
Element includes the second internal diode of the 2nd IGBT pipe and reverse parallel connection, and third inversion element includes the 3rd IGBT pipe and reversed
Diode in third body in parallel, the 4th inversion element include the 4th internal diode of the 4th IGBT pipe and reverse parallel connection, the
Five inversion elements include the 5th internal diode of the 5th IGBT pipe and reverse parallel connection, and the 6th inversion element is managed including the 6th IGBT
With diode in the hexasomic of reverse parallel connection, the 7th inversion element includes the 7th internal two pole of the 7th IGBT pipe and reverse parallel connection
Pipe；
The collector of first IGBT pipe is connected to the collector of the 2nd IGBT pipe, and the anode of the first internal diode is connected to
The anode of the emitter of 5th IGBT pipe and the collector of the 3rd IGBT pipe, the second internal diode is connected to the 6th IGBT pipe
The collector of the collector of emitter and the 4th IGBT pipe, the 7th IGBT pipe is connected to the cathode and the 6th of the 5th internal diode
The cathode of internal diode, the anode of the 7th internal diode are connected to the intersection node of first capacitor Yu the second capacitor, third
The anode of internal diode is connected to the anode of the 4th internal diode.
Further, the invention also includes filter capacitor, filter capacitor is arranged between firewire and zero curve and is connected respectively to
First inductance and the second inductance, the both ends of filter capacitor connect with load.
Further, when the present invention works under a duty cycle, including the following course of work, detect Input voltage terminal
The input voltage VI and load voltage VO for loading both ends:
It works in positive half period, as VO < 0.5VI, the 5th inversion element is in normal open state, at the 4th inversion element
In pulsewidth modulation state, other inversion elements are in off state；
It works in positive half period, as VO > 0.5VI, the first inversion element, the 4th inversion element and the 7th inversion element
In pulsewidth modulation state, other inversion elements are in off state；
It works in negative half-cycle, as VO < 0.5VI, the 6th inversion element is in normal open state, at third inversion element
In pulsewidth modulation state, other inversion elements are in off state；
It works in negative half-cycle, as VO > 0.5VI, the second inversion element, third inversion element and the 7th inversion element
In pulsewidth modulation state, other inversion elements are in off state.
Further, it works in positive half period, as VO < 0.5VI, the 5th inversion element is in normal open state, and the 4th is inverse
Dependent element is in pulsewidth modulation state, including the 4th inversion element ON or shutdown:
When the 4th inversion element ON, electric current successively flows into the second capacitance cathode, the 7th internal diode, the 5th inversion
Element, the first inductance, load, the second inductance, the 4th inversion element and capacitor cathode；
When the 4th inversion element OFF, electric current successively flows into the first inductance, load, the second inductance, two poles in hexasomic
Pipe, the 5th inversion element and the first inductance.
Further, it works in positive half period, as VO > 0.5VI, the first inversion element, the 4th inversion element and the 7th
Inversion element is in pulsewidth modulation state, including turns off the 7th inversion element and open the first inversion element and the 4th inversion member
Part, or open the 7th inversion element and the first inversion element of shutdown and the 4th inversion element:
When turning off the 7th inversion element and opening the first inversion element and the 4th inversion element, electric current successively flows into defeated
Enter the anode of voltage end, the first inversion element, the first inductance, load, the second inductance, the 4th inversion element and Input voltage terminal
Negative terminal；
When opening the 7th inversion element and the first inversion element of shutdown and when the 4th inversion element, electric current successively flows into the
One inductance, load, the second inductance, diode in hexasomic, the 7th inversion element, the second capacitor, two poles in third inversion element
Pipe and the first inductance.
Further, it works in negative half-cycle, as VO < 0.5VI, the 6th inversion element is in normal open state, and third is inverse
Dependent element is in pulsewidth modulation state, including third inversion element ON or shutdown:
When third inversion element ON, electric current successively flows into the second capacitance cathode, the 7th internal diode, the 6th inversion
Element, the second inductance, load, the first inductance, third inversion element and capacitor cathode；
When third inversion element OFF, electric current successively flows into the second inductance, load, the first inductance, the 5th internal two pole
Pipe, the 6th inversion element and the second inductance.
Further, it works in negative half-cycle, as VO > 0.5VI, the second inversion element, third inversion element and the 7th
Inversion element is in pulsewidth modulation state, including turns off the 7th inversion element and open the second inversion element and third inversion member
Part, or open the 7th inversion element and the second inversion element of shutdown and third inversion element:
When turning off the 7th inversion element and opening the second inversion element and third inversion element, electric current successively flows into defeated
Enter the anode of voltage end, the second inversion element, the second inductance, load, the first inductance, third inversion element and Input voltage terminal
Negative terminal；
When opening the 7th inversion element and the second inversion element of shutdown and when third inversion element, electric current successively flows into the
Two inductance, load, the first inductance, the 5th internal diode, the 7th inversion element, the second capacitor, two in the 4th inversion element body
Pole pipe and the second inductance.
The beneficial effects of the present invention are: the present invention provides a kind of single-phase three-level inverter circuit, using three level designs,
Inverter output voltage in each switch periods only has zero level and a positive or negative level, compared with two level circuits,
Showed on output voltage and current harmonics performance it is more excellent, simultaneously because the variation of each switch periods inverter output voltage be two electricity
The half on ordinary telegram road, therefore the parameter of its output filter will be obviously reduced；Inversion element has multiple sub-units, can be perfect suitable
Driving of the Ying Yu under the normal duty cycle；Single phase design is used simultaneously, it is simpler, facilitate analysis to handle；First inductance
Play the role of reducing ripple current with the second inductance, ensure that the steady operation of entire inverter circuit.Therefore, the present invention has
Following advantages: design is simple, facilitates analysis, and the parameter of output filter is smaller, in terms of output voltage with harmonic wave aspect of performance
Performance preferably, can satisfy low EMI and low ripple electric current, interfere smaller.
Detailed description of the invention
Present pre-ferred embodiments are provided, with reference to the accompanying drawing with the embodiment that the present invention will be described in detail.
Fig. 1 is circuit diagram of the invention.
Specific embodiment
Referring to Fig.1, a kind of single-phase three-level inverter circuit of the invention, including inversion element 1, the first inductance L1, second
Inductance L2, first capacitor C1, the second capacitor C2 and Input voltage terminal；Inversion element 1 includes the first inversion element Q1, the second inversion
Element Q2, third inversion element Q3, the 4th inversion element Q4, the 5th inversion element Q5, the 6th inversion element Q6 and the 7th inversion
Element Q7；The emitter of 5th inversion element Q5 is arranged in the first inversion element Q1, third inversion element Q3 and the first inductance L1
Intersection node on, the collector of the 5th inversion element Q5 connects the collector and the 6th inversion element Q6 in the 7th inversion element Q7
Collector intersection node on；The emitter of 6th inversion element Q6 is arranged in the second inversion element Q2, the 4th inversion element
On the intersection node of Q4 and the second inductance L2, the collector of the 6th inversion element Q6 connect collector in the 7th inversion element Q7 with
On the intersection node of the collector of 5th inversion element Q5；First inversion element Q1 and third inversion element Q3 is connected in series and divides
It is not connect with the first inductance L1, the second inversion element Q2 and the 4th inversion element Q4 are connected in series and connect respectively with the second inductance L2
It connects；First capacitor C1 and the second capacitor C2 are connected in series, and the collector of the 7th inversion element Q7 is connected respectively to the 5th inversion member
The emitter of part Q5 and the 6th inversion element Q6, the 7th inversion element Q7 are connected to the intersection of first capacitor C1 and the second capacitor C2
Node；First inductance L1 is arranged on firewire and connects with the emitter of the 5th inversion element Q5, and the second inductance L2 is arranged zero
Connect on line and with the emitter of the 6th inversion element Q6；The anode of first capacitor C1 is connected to the anode of Input voltage terminal, and second
The cathode of capacitor C2 is connected to the negative terminal of Input voltage terminal.
Specifically, firewire is indicated with L in Fig. 1, and zero curve is indicated with N；Two level circuits refer under PWM modulation mode,
Inverter output voltage waveform in each switch periods only will appear the polar level of both positive and negative, and use three level designs,
Inverter output voltage in each switch periods has zero level and a positive or negative level, compared with two level circuits, defeated
Showed on voltage and current harmonic performance out it is more excellent, simultaneously because the variation of each switch periods inverter output voltage is two level
The half of circuit, therefore the parameter of its output filter will be obviously reduced；Inversion element 1 of the invention has multiple sub-units,
Perfect it can be adapted to the driving under positive half period and negative half-cycle；Single phase design is used simultaneously, it is simpler, facilitate at analysis
Reason；First inductance L1 and the second inductance L2 plays the role of reducing ripple current, ensure that the steady operation of entire inverter circuit.
Wherein, the first inversion element Q1 includes the first internal diode D1 of the first IGBT pipe S1 and reverse parallel connection, and second
Inversion element Q2 includes the second internal diode D2 of the 2nd IGBT pipe S2 and reverse parallel connection, and third inversion element Q3 includes third
Diode D3 in the third body of IGBT pipe S3 and reverse parallel connection, the 4th inversion element Q4 include the 4th IGBT pipe S4 and reverse parallel connection
The 4th internal diode D4, the 5th inversion element Q5 includes the 5th internal diode of the 5th IGBT pipe S5 and reverse parallel connection
D5, the 6th inversion element Q6 include diode D6 in the hexasomic of the 6th IGBT pipe S6 and reverse parallel connection, the 7th inversion element Q7
The 7th internal diode D7 including the 7th IGBT pipe S7 and reverse parallel connection；
The collector of first IGBT pipe S1 is connected to the collector of the 2nd IGBT pipe S2, the anode of the first internal diode D1
It is connected to the emitter of the 5th IGBT pipe S5 and the collector of the 3rd IGBT pipe S3, the anode of the second internal diode D2 is connected to
The emitter of 6th IGBT pipe S6 and the collector of the 4th IGBT pipe S4, the collector of the 7th IGBT pipe S7 are connected to the 5th in vivo
The cathode of diode D6 in the cathode and hexasomic of diode D5, the anode of the 7th internal diode D7 are connected to first capacitor C1
With the intersection node of the second capacitor C2, the anode of diode D3 is connected to the anode of the 4th internal diode D4 in third body.
Above-mentioned setting ensure that the overall operation of inverter circuit is stablized, but above-mentioned setting does not limit uniquely, therein
IGBT Guan Keyong metal-oxide-semiconductor replaces, and the pole D of metal-oxide-semiconductor is analogous to the collector of IGBT pipe in the present invention, and the pole S of metal-oxide-semiconductor is analogous to this
The emitter of IGBT pipe in invention；Internal diode can also be substituted using external diode, above-mentioned setting is for this field
Similar implementation can be carried out for technical staff.
Wherein, referring to Fig.1, the invention also includes filter capacitor C3, filter capacitor C3 be arranged between firewire and zero curve and
It is connected respectively to the first inductance L1 and the second inductance L2, the both ends access load of filter capacitor C3 guarantees that inverter circuit has and stablizes
Output.
Wherein, referring to Fig.1, when working under a duty cycle, including the following course of work, detect Input voltage terminal
The input voltage VI and load voltage VO for loading both ends:
It works in positive half period, as VO < 0.5VI, the 5th inversion element Q5 is in normal open state, the 4th inversion element
Q4 is in pulsewidth modulation state, and other inversion elements 1 are in off state；
It works in positive half period, as VO > 0.5VI, the first inversion element Q1, the 4th inversion element Q4 and the 7th inversion
Element Q7 is in pulsewidth modulation state, and other inversion elements 1 are in off state；
It works in negative half-cycle, as VO < 0.5VI, the 6th inversion element Q6 is in normal open state, third inversion element
Q3 is in pulsewidth modulation state, and other inversion elements 1 are in off state；
It works in negative half-cycle, as VO > 0.5VI, the second inversion element Q2, third inversion element Q3 and the 7th inversion
Element Q7 is in pulsewidth modulation state, and other inversion elements 1 are in off state.
It realizes that inverter circuit drives in the way of above-mentioned 4 kinds, it is small to can get stable output voltage and low EMI, interference
Current harmonics.
Wherein, referring to Fig.1, it works in positive half period, as VO < 0.5VI, the 5th inversion element Q5 is in normal open shape
State, the 4th inversion element Q4 are in pulsewidth modulation state, including the 4th inversion element Q4 is switched on or off:
When the 4th inversion element Q4 is opened, electric current successively flows into the second capacitor C2 anode, in the 7th inversion element Q7 body
Diode, the 5th inversion element Q5, the first inductance L1, load, the second inductance L2, the 4th inversion element Q4 and the second capacitor C2 are negative
Pole；
When the 4th inversion element Q4 shutdown, electric current successively flows into the first inductance L1, load, the second inductance L2, hexasomic
Interior diode D6, the 5th inversion element Q5 and the first inductance L1.
Wherein, referring to Fig.1, it works in positive half period, as VO > 0.5VI, the first inversion element Q1, the 4th inversion member
Part Q4 and the 7th inversion element Q7 is in pulsewidth modulation state, including turns off the 7th inversion element Q7 and open the first inversion member
Part Q1 and the 4th inversion element Q4, or open the 7th inversion element Q7 and the first inversion element Q1 of shutdown and the 4th inversion element
Q4:
When turning off the 7th inversion element Q7 and opening the first inversion element Q1 and the 4th inversion element Q4, electric current is successively
Flow into anode, the first inversion element Q1, the first inductance L1, load, the second inductance L2, the 4th inversion element Q4 of Input voltage terminal
With the negative terminal of Input voltage terminal；When open the 7th inversion element Q7 and shutdown the first inversion element Q1 and the 4th inversion element Q4
When, electric current successively flows into the first inductance L1, load, the second inductance L2, diode D6, the 7th inversion element Q7, in hexasomic
Diode and the first inductance L1 in two capacitor C2, third inversion element Q3 body.
Wherein, referring to Fig.1, it works in negative half-cycle, as VO < 0.5VI, the 6th inversion element Q5 is in normal open shape
State, third inversion element Q3 are in pulsewidth modulation state, including third inversion element Q3 is switched on or off:
When third inversion element Q3 is opened, electric current successively flows into the second capacitor C2 anode, the 7th internal diode D7,
Six inversion element Q6, the second inductance L2, load, the first inductance L1, third inversion element Q3 and the second capacitor C2 cathode；
When third inversion element Q3 shutdown, electric current successively flows into the second inductance L2, load, the first inductance L1, five body constituents
Interior diode D5, the 6th inversion element Q6 and the second inductance L2.
Wherein, referring to Fig.1, it works in negative half-cycle, as VO > 0.5VI, the second inversion element Q2, third inversion member
Part Q3 and the 7th inversion element Q7 is in pulsewidth modulation state, including turns off the 7th inversion element Q7 and open the second inversion member
Part Q2 and third inversion element Q3, or open the 7th inversion element Q7 and the second inversion element Q2 of shutdown and third inversion element
Q3:
When turning off the 7th inversion element Q7 and opening the second inversion element Q2 and third inversion element Q3, electric current is successively
Flow into anode, the second inversion element Q2, the second inductance L2, load, the first inductance L1, the third inversion element Q3 of Input voltage terminal
With the negative terminal of Input voltage terminal；
When opening the 7th inversion element Q7 and shutdown the second inversion element Q2 and third inversion element Q3, electric current is successively
Flow into the second inductance L2, load, the first inductance L1, the 5th internal diode D5, the 7th inversion element Q7, the second capacitor C2,
Diode and the second inductance L2 in four inversion element Q4 bodies.
Pulsewidth modulation makes certain components in inversion element 1 be periodically switched on or off, according to aforesaid way, often
Inverter output voltage in a switch periods has zero level and a positive or negative level, compared with two level circuits, exporting
It is showed on voltage and current harmonic performance more excellent.
Presently preferred embodiments of the present invention and basic principle is discussed in detail in the above content, but the invention is not limited to
Above embodiment, those skilled in the art should be recognized that also have on the premise of without prejudice to spirit of the invention it is various
Equivalent variations and replacement, these equivalent variations and replacement all fall within the protetion scope of the claimed invention.
Claims (6)
1. a kind of single-phase three-level inverter circuit, it is characterised in that:
Including inversion element (1), the first inductance (L1), the second inductance (L2), first capacitor (C1), the second capacitor (C2) and input
Voltage end；The inversion element (1) include the first inversion element (Q1), the second inversion element (Q2), third inversion element (Q3),
4th inversion element (Q4), the 5th inversion element (Q5), the 6th inversion element (Q6) and the 7th inversion element (Q7)；Described 5th
Phase of the emitter setting of inversion element (Q5) in the first inversion element (Q1), third inversion element (Q3) and the first inductance (L1)
On knot point, the collector of the 5th inversion element (Q5) connects the collector and the 6th inversion element in the 7th inversion element (Q7)
(Q6) on the intersection node of collector；The 6th inversion element (Q6) emitter setting the second inversion element (Q2),
On the intersection node of 4th inversion element (Q4) and the second inductance (L2)；The first inversion element (Q1) and third inversion element
(Q3) it is connected in series and is connect respectively with the first inductance (L1), the second inversion element (Q2) and the 4th inversion element (Q4) string
Connection connects and connect respectively with the second inductance (L2)；The first capacitor (C1) and the second capacitor (C2) are connected in series, and the 7th is inverse
The emitter of dependent element (Q7) is connected to the intersection node of first capacitor (C1) and the second capacitor (C2)；First inductance (L1)
Be arranged on firewire and connect with the emitter of the 5th inversion element (Q5), second inductance (L2) be arranged on zero curve and with
The emitter of 6th inversion element (Q6) connects；The anode of the first capacitor (C1) is connected to the anode of Input voltage terminal, described
The cathode of second capacitor (C2) is connected to the negative terminal of Input voltage terminal；
The first inversion element (Q1) includes the first internal diode (D1) of the first IGBT pipe (S1) and reverse parallel connection, described
Second inversion element (Q2) includes the second internal diode (D2) of the 2nd IGBT pipe (S2) and reverse parallel connection, the third inversion
Element (Q3) includes diode (D3) in the third body of the 3rd IGBT pipe (S3) and reverse parallel connection, the 4th inversion element (Q4)
The 4th internal diode (D4) including the 4th IGBT pipe (S4) and reverse parallel connection, the 5th inversion element (Q5) include the 5th
IGBT manages the 5th internal diode (D5) of (S5) and reverse parallel connection, and the 6th inversion element (Q6) is managed including the 6th IGBT
(S6) and in the hexasomic of reverse parallel connection diode (D6), the 7th inversion element (Q7) are managed (S7) and anti-including the 7th IGBT
To the 7th internal diode (D7) in parallel；
The collector of the first IGBT pipe (S1) is connected to the collector of the 2nd IGBT pipe (S2), the first internal diode
(D1) anode be connected to the 5th IGBT pipe (S5) emitter and the 3rd IGBT pipe (S3) collector, described second internal two
The anode of pole pipe (D2) be connected to the 6th IGBT pipe (S6) emitter and the 4th IGBT pipe (S4) collector, the described 7th
The collector of IGBT pipe (S7) is connected to the cathode of diode (D6) in the cathode and hexasomic of the 5th internal diode (D5), institute
The anode for stating the 7th internal diode (D7) is connected to the intersection node of first capacitor (C1) Yu the second capacitor (C2), the third
The anode of internal diode (D3) is connected to the anode of the 4th internal diode (D4)；
When single-phase three-level inverter circuit works under a duty cycle, including the following course of work, detect Input voltage terminal
Input voltage VI and load both ends load voltage VO:
It works in positive half period, as VO < 0.5VI, the 5th inversion element (Q5) is in normal open state, the 4th inversion element
(Q4) it is in pulsewidth modulation state, other inversion elements (1) are in off state；
It works in positive half period, as VO > 0.5VI, the first inversion element (Q1), the 4th inversion element (Q4) and the 7th inversion
Element (Q7) is in pulsewidth modulation state, and other inversion elements (1) are in off state；
It works in negative half-cycle, as VO < 0.5VI, the 6th inversion element (Q6) is in normal open state, third inversion element
(Q3) it is in pulsewidth modulation state, other inversion elements (1) are in off state；
It works in negative half-cycle, as VO > 0.5VI, the second inversion element (Q2), third inversion element (Q3) and the 7th inversion
Element (Q7) is in pulsewidth modulation state, and other inversion elements (1) are in off state.
2. a kind of single-phase three-level inverter circuit according to claim 1, it is characterised in that: further include filter capacitor
(C3), the filter capacitor (C3) is arranged between firewire and zero curve and is connected respectively to the first inductance (L1) and the second inductance
(L2), the both ends of the filter capacitor (C3) connect with load.
3. a kind of single-phase three-level inverter circuit according to claim 1, which is characterized in that it works in positive half period,
As VO < 0.5VI, the 4th inversion element (Q4) is in pulsewidth modulation state, including the 4th inversion element (Q4) is switched on or off,
5th inversion element (Q5) is in normal open state；
When the 4th inversion element (Q4) is opened, electric current successively flows into capacitor (C2) anode, the 7th internal diode (D7), the 5th
Inversion element (Q5), the first inductance (L1), load, the second inductance (L2), the 4th inversion element (Q4) and the second capacitor (C2) are negative
Pole；
When the shutdown of the 4th inversion element (Q4), electric current successively flows into the first inductance (L1), load, the second inductance (L2), the 6th
Internal diode (D6), the 5th inversion element (Q5) and the first inductance (L1).
4. a kind of single-phase three-level inverter circuit according to claim 1, which is characterized in that it works in positive half period,
As VO > 0.5VI, the first inversion element (Q1), the 4th inversion element (Q4) and the 7th inversion element (Q7) are in pulsewidth modulation
State, including turn off the 7th inversion element (Q7) and open the first inversion element (Q1) and the 4th inversion element (Q4), or open
Logical 7th inversion element (Q7) and the first inversion element (Q1) of shutdown and the 4th inversion element (Q4):
When turning off the 7th inversion element (Q7) and when opening the first inversion element (Q1) and the 4th inversion element (Q4), electric current according to
The secondary anode of Input voltage terminal, the first inversion element (Q1), the first inductance (L1), load, the second inductance (L2), the 4th inverse of flowing into
The negative terminal of dependent element (Q4) and Input voltage terminal；
When opening the 7th inversion element (Q7) and the first inversion element (Q1) of shutdown and when the 4th inversion element (Q4), electric current according to
The first inductance of secondary inflow (L1), load, the second inductance (L2), diode (D6), the 7th inversion element (Q7), second in hexasomic
Diode (D3) and the first inductance (L1) in capacitor (C2), third body.
5. a kind of single-phase three-level inverter circuit according to claim 1, which is characterized in that it works in negative half-cycle,
As VO < 0.5VI, third inversion element (Q3) is in pulsewidth modulation state, including third inversion element (Q3) is switched on or off,
6th inversion element (Q6) is in normal open state:
When third inversion element (Q3) is opened, electric current successively flow into the second capacitor (C2) anode, the 7th internal diode (D7),
6th inversion element (Q6), the second inductance (L2), load, the first inductance (L1), third inversion element (Q3) and the second capacitor
(C2) cathode；
When third inversion element (Q3) shutdown, electric current successively flows into the second inductance (L2), load, the first inductance (L1), the 5th
Internal diode (D5), the 6th inversion element (Q6) and the second inductance (L2).
6. a kind of single-phase three-level inverter circuit according to claim 1, which is characterized in that it works in negative half-cycle,
As VO > 0.5VI, the second inversion element (Q2), third inversion element (Q3) and the 7th inversion element (Q7) are in pulsewidth modulation
State, including turn off the 7th inversion element (Q7) and open the second inversion element (Q2) and third inversion element (Q3), or open
Logical 7th inversion element (Q7) and the second inversion element (Q2) of shutdown and third inversion element (Q3):
When turning off the 7th inversion element (Q7) and when opening the second inversion element (Q2) and third inversion element (Q3), electric current according to
The secondary anode for flowing into Input voltage terminal, the second inversion element (Q2), the second inductance (L2), load, the first inductance (L1), third are inverse
The negative terminal of dependent element (Q3) and Input voltage terminal；
When opening the 7th inversion element (Q7) and the second inversion element (Q2) of shutdown and when third inversion element (Q3), electric current according to
The second inductance of secondary inflow (L2), load, the first inductance (L1), the 5th internal diode (D5), the 7th inversion element (Q7), second
Diode (D4) and the second inductance (L2) in capacitor (C2), the 4th inversion element.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102185511A (en) * | 2011-05-09 | 2011-09-14 | 浙江金贝能源科技有限公司 | Noninsulated type converting circuit from direct-current voltage to alternating-current voltage |
| CN103956927A (en) * | 2014-04-28 | 2014-07-30 | 浙江大学 | Voltage-active-clamping non-transformer-type single-phase photovoltaic inverter |
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| JP6613883B2 (en) * | 2015-12-25 | 2019-12-04 | 富士電機株式会社 | 3-level power conversion circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102185511A (en) * | 2011-05-09 | 2011-09-14 | 浙江金贝能源科技有限公司 | Noninsulated type converting circuit from direct-current voltage to alternating-current voltage |
| CN103956927A (en) * | 2014-04-28 | 2014-07-30 | 浙江大学 | Voltage-active-clamping non-transformer-type single-phase photovoltaic inverter |
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