CN108305875B - 使用用于源极/漏极限域的间隔物的半导体器件的制作方法 - Google Patents
使用用于源极/漏极限域的间隔物的半导体器件的制作方法 Download PDFInfo
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Abstract
一种制作半导体器件的方法,包括:在第一半导体材料层上形成用于至少一个栅极堆叠的第一间隔物,以及与所述至少一个栅极相邻地形成用于源极和漏极区域中的每一个的相应第二间隔物。每个第二间隔物具有成对的相对的侧壁和与之耦合的端壁。该方法包括在第一间隔物和第二间隔物提供限域的同时,利用第二半导体材料填充源极和漏极区域。
Description
分案申请说明
本申请是于2014年4月8日提交的申请号为201410143386.1、名称为“使用用于源极/漏极限域的间隔物的半导体器件的制作方法”的中国发明专利申请的分案申请。
技术领域
本发明涉及电子器件,并且更具体地涉及制造半导体器件的方法。
背景技术
半导体器件技术持续演进,提供更高的芯片密度和工作频率。鳍式场效应晶体管(FinFET)是当前用于帮助提高期望器件缩小、同时保持适当功耗预算的一种晶体管技术。
该鳍式场效应晶体管(FinFET)是形成在材料鳍内的晶体管。鳍是具有相对窄的宽度、相对高的高度的结构,其从衬底的顶表面突出。特意将鳍宽度保持为小以限制短沟道效应。在许多FinFET中,鳍帽定位在鳍的顶部上并且沿着鳍长度延伸。鳍帽具有等于鳍宽度的鳍帽宽度和小于鳍高度的鳍帽高度。
在常规FinFET中,栅极导体定位在衬底的顶表面上和鳍的一部分之上。栅极导体与衬底的顶部并行并且与鳍长度垂直地延伸,从而栅极导体与鳍的一部分交叉。绝缘体(例如栅极氧化物)将栅极导体与鳍和鳍帽隔开。此外,定位在栅极导体下方的鳍的区域包括半导体沟道区域。FinFET结构可以包括多个鳍和鳍帽,在这种情况下栅极导体将环绕并填充这些鳍之间的空间。
在FinFET形成期间,形成源极和漏极凹陷(recess),并且源极和漏极凹陷通常需要附加的清洗以在源极和漏极区域处的鳍上方具有外延再生长。由该外延再生长形成的一些外延结受到应力。在制造期间,当使用多个鳍并且外延结受到应力时难以制作均匀的鳍凹陷尺寸。而且,在制造期间,在间隔物形成之后并且在原位掺杂外延期间,鳍剖面经常圆化并且鳍表面受到侵蚀性反应离子刻蚀(RIE)的损坏。这些因素会不利地影响晶体管的功能性。
发明内容
一种制作半导体器件的方法,包括:在第一半导体材料层上形成用于至少一个栅极堆叠的第一间隔物。该方法进一步包括:在第一半导体层中并且与至少一个栅极相邻地形成用于源极区域和漏极区域中的每一个的相应第二间隔物,其中每个第二间隔物包括成对的相对侧壁和与之耦合的端壁。该方法进一步包括:在第一间隔物和第二间隔物提供限域(confinement)的同时,利用第二半导体材料填充源极区域和漏极区域。
该方法可以包括在填充之前刻蚀与至少一个栅极堆叠相邻的源极和漏极凹陷。可以例如在同一处理腔室中执行刻蚀和填充。在另一示例中,该方法可以包括:使源极凹陷和漏极凹陷成形以具有与至少一个栅极堆叠相邻的倾斜延伸。第一间隔物和第二间隔物可以包括氮化物,例如SiN。
第一半导体材料和第二半导体材料可以由不同的半导体材料形成,使得应力传递到至少一个栅极堆叠下方的沟道区域。第一半导体材料可以包括硅,并且第二半导体材料可以包括硅和锗。第一半导体层包括绝缘体上硅(SOI)晶片。该方法可以进一步包括:形成多个鳍,以及在这些鳍的外表面上并且与至少一个栅极堆叠相邻地形成第二间隔物。在示例中,刻蚀这些鳍以形成源极凹陷和漏极凹陷。
附图说明
本发明的其它特征和优势将从下面结合附图给出的本发明的详细描述中变得显而易见,在附图中:
图1是示出现有技术中与鳍相邻的嵌入式外延区域的现有技术FinFET结构的局部图。
图2和图3是示出本发明的嵌入式外延源极区域和漏极区域的FinFET器件的局部图。
图4是示出现有技术中的示例性FinFET器件的鳍剖面的绘图。
图5是作为根据本发明非限域性示例的FinFET器件的半导体器件的透视图,并且示出了构图和刻蚀以形成硅鳍的第一处理步骤。
图6是类似于图5的另一透视图,并且示出了在每个半导体鳍的外表面上形成第一SiN间隔物和第二SiN间隔物的第二处理步骤,包括形成源极区域和漏极区域中的每一个。
图7是示出刻蚀硅鳍以在相应源极和漏极区域处形成源极凹陷和漏极凹陷的第三处理步骤的另一透视图。
图8是沿着图7的线8-8所取的截面图并且示出了刻蚀后的源极和漏极凹陷的剖面。
图9是由图8的虚线区域示出的倾斜延伸的截面图像并且示出了刻面(平面)剖面和相应的角度。
图10是类似于图8的另一截面图,但示出了旋转的衬底。
图11是示出第四处理步骤的另一透视图,其中源极和漏极凹陷填充有第二半导体材料并且在填充期间第一SiN间隔物和第二SiN间隔物提供限域。
图12是沿着图11的线12-12所取的截面图并且示出了在源极和漏极区域处的与至少一个栅极堆叠相邻的倾斜延伸。
图13是图示根据本发明非限域性示例的用于制造半导体器件的方法的流程图。
具体实施方式
现在将在下面参照附图更充分地描述不同实施例,在附图中示出了优选实施例。许多不同的形式不应认为是限于这里阐述的实施例。而且,提供这些实施例使得本公开内容将是透彻和完整的,并且这些实施例将向本领域技术人员充分传递范围。
图1是作为FinFET结构20的现有技术半导体器件的局部图,该FinFET结构20包括在鳍24之上的外延再生长22。这种器件可能在性能上受限。相比之下,图2和图3图示了修改的FinFET结构25,其中通过在沿着鳍30刻蚀之后将外延再生长26嵌入到鳍的源极和漏极区域28中,增强器件的功能性。当在间隔物形成之后通过部分各向异性反应离子束(RIE)刻蚀形成鳍时,随后是原位掺杂外延,嵌入的外延结会潜在地受到应力。外延材料可以为n型或p型掺杂硅、或锗硅(SiGe)、或碳化硅(SiC),用于赋予应力和增强的迁移率。SiGe用于沟道的压应力(pFET),而SiC用于nFET晶体管改进的拉应力。
图4示出了示例性FinFET器件的图像的截面图,示出了作为非限制性示例的FinFET剖面的间距到间距剖面和相对尺寸。图4所示的剖面是诸如由于侵蚀性反应离子束刻蚀工艺可能损坏了的圆化鳍剖面的现有技术示例,需要附加的表面清洗。
当由于侵蚀性反应离子束刻蚀工艺损坏了鳍表面并且鳍被圆化时可能难以具有均匀的鳍、间距到间距剖面,由此在外延再生长之前需要附加的处理和清洗以使表面更清洁。鳍在间隔物外部也可能凹陷,并且可能需要附加的注入物来构建结作为延伸。
根据本实施例的非限制性示例的方法克服了这些不利之处,并且提供外延的源极和漏极区域,通过至少一个硅鳍的原位HCL(盐酸)刻蚀、之后进行原位掺杂Si、SiGe或SiC的外延再生长来形成这些外延的源极和漏极区域。SiN间隔物可以限域应力体材料作为外延材料并且使后续掺杂剂剂量最小化。为此原因,可能不需要注入物。HCL刻蚀工艺更具各向同性,并且实现包含(111)面(平面)的良好剖面,达到应力和器件改进的最大化。
根据本实施例的非限制性示例的方法具有诸如限制在凹陷刻蚀期间鳍的损坏的优势。在一个非限制性示例中,可以在清洁环境下原位完成该处理并且可以使用诸如外延反应器的单一处理工具。在凹陷形成之后可能不需要附加的清洗。化学纯表面导致诸如任意SiGe或SiC层之类的生长层的良好晶体质量。不存在如图1的现有技术器件中所示的外延过生长22,因为材料在所有方向上都受到SiN间隔物材料限域,从而形成如图2和图3所示的方形配置。可以不需要将减少应力和损坏硅的附加注入物。而且,可以经由原位掺杂外延直接对结进行建造。取决于晶体管的类型(诸如nFET或pFET),掺杂剂可以是硼、磷、砷和其它类似掺杂剂。
图5至图13图示了根据非限制性示例形成的半导体器件(诸如FinFET)的方法,其中图5至图7和图11示出了不同处理阶段中的各种立体图,图8至图10和图12示出了不同处理阶段期间的截面图。
图5是第一处理阶段中总体以40图示的FinFET器件的半导体器件的立体图,并且示出了从作为衬底的第一半导体材料层43向上延伸并且沿着衬底间隔开的多个半导体鳍42。每个半导体鳍具有相对的第一端42a和第二端42b,并且形成相应的源极和漏极区域44以及它们之间的中间部分。在第一半导体材料层上的半导体鳍42的中间部分之上形成至少一个栅极堆叠46。在一个示例中,将第一半导体层形成为绝缘体上硅(SOI)晶片48,其中如所示那样SiO2层50在硅衬底52上方。硬掩膜54保护栅极堆叠46的顶表面并且包括氮化硅材料,在一个示例中为30nm(纳米)厚。
图6示出了施加用于在第一半导体材料层43上的至少一个栅极堆叠46的第一SiN间隔物60以及施加用于在第一半导体材料层43中并且与至少一个栅极相邻的源极和漏极区域44中每一个的第二相应SiN间隔物62的进一步的处理步骤,其中每个第二SiN间隔物包括成对的相对的侧壁64和与之耦合的图8所示的端壁66。
图7示出了进一步的处理步骤,其中在一个示例中利用气相HCL刻蚀硅鳍42,以在所示源极和漏极区域44中的每一个处与至少一个栅极堆叠46相邻地形成源极和漏极凹陷70。
图8是沿着图7的线8-8所取的截面图并且示出在HCL刻蚀以形成源极和漏极凹陷70之后的鳍剖面。源极和漏极凹陷70具有如图8所示的与至少一个栅极堆叠46相邻的倾斜延伸72,并且在图9的图像中示出了该剖面,而图10示出了旋转的衬底,其中呈现(110)面(平面),而不是图8和图9中的(111)面(平面)。
在HCL刻蚀之后,存在(100)-(111)面(平面)剖面。在与第一半导体材料层43的法线成30-60度范围中的角度处期望最大的应力并且形成倾斜延伸72。在一个示例中,(111)面(平面)与作为垂直面的(100)面(平面)形成54度角。可以使用温度和压力处理来调节各种面(平面)的刻蚀速率。在图8中,对于良好的外延再生长而言,TSI(顶表面成像)大于2nm(纳米)。图9示出了在500nm(纳米)处的尺寸比例。
图11是另一立体图,示出了填充有第二半导体材料74的源极和漏极凹陷70,使得在诸如外延材料填充之类的填充期间第一SiN间隔物60和第二SiN间隔物62提供限域。
图12是沿着图11的线12-12所取的截面图,并且示出了填充有第二半导体材料74的与至少一个栅极堆叠46相邻的源极和漏极区域44,在一个示例中第二半导体材料74为硼锗硅(SiGe)B。在一个非限制性示例中,在与外延反应器相同的处理腔室中执行刻蚀和外延生长。晶体(不管是SiGe还是SiC)的晶体质量提供纯表面,其中在一个示例中外延生长赋予由图12中的箭头所指示并且在所有方向由氮化物间隔物60、62限域的压应变。填充物外延材料形成可以由外延生长建造的延伸。在一个示例中,使用原位掺杂外延以用于利用SiGeC:B/SiGe:B的多层的结构造,这可能使应变最大化同时保持良好的晶体管静电性。
源极和漏极凹陷70的形状创建发生在相同的处理腔室(例如外延反应器)中。在一个非限制性示例中,加载晶片,并且针对深度和在650度到800度之间的刻蚀温度处理以及在5TORR至约500TORR的压力下设置外延反应器。在具有Si、SiGe、SiC和其它前驱体:硅二氯甲硅烷SiH2Cl2(作为硅前驱体)、锗烷(GeH4)和甲基硅烷(CH3-SiH3)的情形下发生沉积。掺杂可以伴有硼乙硼烷(B2H6)、磷化氢(PH3)和砷化三氢(ASH3)。
可以在具有从100SCCM(标准立方厘米每分钟)到20SLM(标准升每分钟)流量下的HCL(盐酸)的情形下产生刻蚀,以对源极和漏极凹陷70进行成形,并且形成诸如图8所示的与栅极堆叠46相邻的倾斜延伸72。
外延沉积层通常是锗硅,其中锗含量的范围从约25%到约60%,以赋予应力。相同范围的压力可以施加在与外延反应器相同的处理腔室中,其中压力的范围从约5TORR到约500TORR,并且温度范围从约500度到约800度。可以在具有前面提及的Si、SiGe前驱体的情形下产生沉积,并且可以在具有前面提及的相同掺杂剂的情形下产生掺杂。
图13图示了高级流程图,其示出了基本顺序步骤。工艺开始(框100),并且在第一半导体材料层上形成诸如用于至少一个栅极堆叠的第一SiN间隔物(框102)。在第一半导体层中并且与至少一个栅极相邻地形成诸如用于源极和漏极区域中每一个的相应第二SiN间隔物(框104)。第二SiN间隔物形成为成对的相对侧壁和与之耦合的端壁。利用第二半导体材料填充源极和漏极区域(框106),使得第一SiN间隔物和第二SiN间隔物在填充器件提供限域。工艺在框108结束。
本发明的许多修改和其它实施例对于受益于前面的描述和附图中呈现的教导的本领域技术人员来说将是显而易见的。因此,理解到,本发明不限于公开的特定实施例,而旨在于将这些修改和实施例包括在所附权利要求的范围内。
Claims (22)
1.一种半导体器件(40),包括:
半导体衬底(43),包括第一半导体材料,所述半导体衬底包括仅由所述第一半导体材料制成的第一表面;
多个半导体鳍(42),直接在所述半导体衬底的所述第一表面上,每个半导体鳍具有包括第二半导体材料的相应的源极区域和漏极区域(44)以及位于每个源极区域和漏极区域之间的中间部分,每个源极区域和每个漏极区域具有相对的第一侧表面和第二侧表面和端部表面,所述半导体衬底的第一表面在所述半导体鳍中的相邻半导体鳍之间延伸;
至少一个栅极堆叠(46),叠置在所述半导体鳍的中间部分之上;
多个第一间隔物,直接在所述半导体衬底的第一表面上,所述第一间隔物邻接所述源极区域和所述漏极区域中的每个的第一侧表面;
多个第二间隔物,直接在所述半导体衬底的第一表面上,所述第二间隔物邻接所述源极区域和所述漏极区域中的每个的第二侧表面;
多个第三间隔物(66),直接在所述半导体衬底的所述第一表面上,所述第三间隔物邻接所述源极区域和所述漏极区域中的每个的端部表面,以及
多个第四间隔物(60),直接在所述半导体衬底的所述第一表面上,并且邻接所述至少一个栅极堆叠,其中所述第一半导体材料和所述第二半导体材料是不同的半导体材料。
2.根据权利要求1所述的半导体器件,其中所述第一半导体材料包括硅。
3.根据权利要求1所述的半导体器件,其中所述第二半导体材料包括硅和锗。
4.根据权利要求1所述的半导体器件,其中所述第一间隔物和所述第二间隔物包括氮化物。
5.根据权利要求1所述的半导体器件,其中每个第一间隔物与至少一个栅极堆叠相邻。
6.根据权利要求1所述的半导体器件,其中所述半导体器件包括FinFET晶体管。
7.根据权利要求1所述的半导体器件,其中每个第四间隔物覆盖所述至少一个栅极堆叠的整个侧壁。
8.一种半导体器件(40),包括:
半导体衬底(43),具有仅由第一半导体材料制成的第一表面;
多个半导体鳍(42),从所述半导体衬底的所述第一表面延伸,每个半导体鳍具有源极区域和漏极区域(44)以及位于每个源极区域和漏极区域之间的中间部分,所述源极区域和所述漏极区域包括第一半导体材料,所述中间部分包括第二半导体材料,所述半导体衬底的第一表面在所述半导体鳍中的相邻半导体鳍之间延伸;
至少一个栅极堆叠(46),叠置在所述半导体鳍的中间部分之上;
多个第一间隔物,所述多个第一间隔物直接在所述半导体衬底的所述第一表面上,并且邻接所述源极区域和所述漏极区域中的每个的第一侧表面;
多个第二间隔物,所述多个第二间隔物直接在所述半导体衬底的所述第一表面上,并且邻接所述源极区域和所述漏极区域中的每个的第二侧表面,所述第二侧表面中的每个第二侧表面与所述第一侧表面中的相应第一侧表面相对;
多个第三间隔物(66),所述第三间隔物直接在所述半导体衬底的所述第一表面上,并且邻接所述源极区域和所述漏极区域中的每个的端部表面,所述端部表面与所述第一侧表面和所述第二侧表面以及所述半导体衬底横切;以及
多个第四间隔物(60),所述多个第四间隔物直接在所述半导体衬底的所述第一表面上,并且邻接所述至少一个栅极堆叠,其中所述源极区域和所述漏极区域至少部分地在所述至少一个栅极堆叠下方延伸,以及所述第一半导体材料和所述第二半导体材料是不同的半导体材料。
9.根据权利要求8所述的半导体器件,其中所述源极区域和所述漏极区域具有沿(111)面的剖面分布。
10.根据权利要求8所述的半导体器件,其中所述源极区域和所述漏极区域具有沿(110)面的剖面分布。
11.根据权利要求8所述的半导体器件,其中所述第二半导体材料包括硅。
12.根据权利要求8所述的半导体器件,其中所述第一半导体材料包括硅和锗。
13.根据权利要求8所述的半导体器件,其中所述第一间隔物和所述第二间隔物包括氮化物。
14.根据权利要求8所述的半导体器件,其中每个第一间隔物与至少一个栅极堆叠相邻。
15.根据权利要求8所述的半导体器件,其中所述半导体器件包括FinFET晶体管。
16.一种半导体器件(40),包括:
半导体衬底(43),包括第一半导体材料,所述半导体衬底包括仅由所述第一半导体材料制成的第一表面;
多个半导体鳍(42),在所述半导体衬底的所述第一表面上,每个半导体鳍具有源极区域和漏极区域以及位于每个源极区域和漏极区域之间的中间部分,所述源极区域和所述漏极区域包括第二半导体材料,所述半导体衬底的第一表面在所述半导体鳍中的相邻半导体鳍之间延伸;
至少一个栅极堆叠,叠置在所述半导体鳍的中间部分之上;
多个第一间隔物,直接在所述半导体衬底的所述第一表面上,所述第一间隔物邻接所述源极区域和所述漏极区域中的每个的第一侧表面;
多个第二间隔物,直接在所述半导体衬底的所述第一表面上,所述第二间隔物邻接所述源极区域和所述漏极区域中的每个的第二侧表面,所述第二侧表面中的每个第二侧表面与所述第一侧表面中的相应第一侧表面相对;以及
多个第三间隔物,直接在所述半导体衬底的所述第一表面上,并且邻接所述第三间隔物邻接所述源极区域和所述漏极区域中的每个的端部表面,所述端部表面与所述第一侧表面和所述第二侧表面横切;以及
多个第四间隔物(60),直接在所述半导体衬底的所述第一表面上,并且邻接所述至少一个栅极堆叠,其中所述源极区域和所述漏极区域包括与所述至少一个栅极堆叠相邻的倾斜延伸部,以及所述第一半导体材料和所述第二半导体材料是不同的半导体材料。
17.根据权利要求16所述的半导体器件,其中所述倾斜延伸部具有与所述半导体衬底法线在30至60度范围内的角度。
18.根据权利要求16所述的半导体器件,其中所述第一半导体材料包括硅。
19.根据权利要求16所述的半导体器件,其中所述第二半导体材料包括硅和锗。
20.根据权利要求16所述的半导体器件,其中所述第一间隔物和所述第二间隔物包括氮化物。
21.根据权利要求16所述的半导体器件,其中每个第一间隔物与至少一个栅极堆叠相邻。
22.根据权利要求16所述的半导体器件,其中所述半导体器件包括FinFET晶体管。
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