CN108305858B - Enhanced heat dissipation type package and preparation method thereof - Google Patents

Enhanced heat dissipation type package and preparation method thereof Download PDF

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Publication number
CN108305858B
CN108305858B CN201711382379.7A CN201711382379A CN108305858B CN 108305858 B CN108305858 B CN 108305858B CN 201711382379 A CN201711382379 A CN 201711382379A CN 108305858 B CN108305858 B CN 108305858B
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heat dissipation
chip
side wall
plastic package
package body
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CN108305858A (en
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谭小春
张光耀
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Hefei Silicon Microelectronics Technology Co ltd
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Hefei Silicon Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides a heat dissipation enhancement type package and a preparation method thereof. The packaging body comprises at least one chip and a plastic packaging body, the plastic packaging body is used for plastic packaging the chips, each chip is provided with an upper surface provided with a welding pad and a lower surface opposite to the upper surface, a bottom radiating plate is arranged at the bottom of the plastic packaging body, a side wall radiating plate is arranged on at least one side wall of the plastic packaging body, the lower surface of the chip is connected with the bottom radiating plate, and chip output pins arranged on the upper surface of the plastic packaging body penetrate through the plastic packaging body and are communicated with the welding pad on the upper surface of the chip. The invention has the advantages that the bottom surface and the side surface of the packaging body are both provided with the heat dissipation plates, so that the packaging body has excellent heat dissipation performance, and the structure is simple, the heat dissipation effect can be obviously improved for common IC packaging or high-power devices, the heat resistance of the chip packaging is reduced, the reliability and the stability of the chip are improved, and the functions and the practicability of the chip are improved.

Description

Enhanced heat dissipation type package and preparation method thereof
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a heat dissipation enhancement type packaging body and a preparation method thereof.
Background
In order to meet the demand of slim and small electronic products, semiconductor packages, which are core elements of the electronic products, are also being developed toward Miniaturization (Miniaturization). In recent years, a miniaturized semiconductor package (Chip ScalePackage, CSP) has been developed, wherein the size of the chip scale package is about equal to or slightly larger than the size of the chip. On the other hand, in addition to miniaturization in size, the semiconductor package needs to increase the integration and the number of Input/Output terminals (I/O) for electrically connecting with external electronic devices such as circuit boards, so as to meet the requirements of the electronic products on high performance and high processing speed.
The conventional chip size package is generally manufactured by coating a chip with a packaging colloid, forming a reconfiguration circuit layer on the packaging colloid and the active surface of the chip after coating, and electrically connecting input/output terminals (I/O) on the active surface of the chip with the reconfiguration circuit layer. Generally, the heat generated by the chip is mostly transferred to the outside through the reconfiguration circuit because of the low heat conduction coefficient and poor heat dissipation effect of the encapsulant, and the heat dissipation area or path is limited, so the heat dissipation efficiency is poor. In the case where heat cannot be quickly transferred to the outside and accumulated inside the size package, warpage (passage) of the package is easily caused.
Disclosure of Invention
The invention aims to solve the technical problem of providing a heat dissipation enhancement type package and a preparation method thereof.
In order to solve the above problems, the present invention provides an enhanced heat dissipation type package, which comprises at least one chip and a plastic package body, wherein the plastic package body is used for plastic packaging the chip, each chip is provided with an upper surface provided with a bonding pad and a lower surface opposite to the upper surface, a bottom heat dissipation plate is arranged at the bottom of the plastic package body, a side wall heat dissipation plate is arranged on at least one side wall of the plastic package body, the lower surface of the chip is connected with the bottom heat dissipation plate, and chip output pins arranged on the upper surface of the plastic package body penetrate through the plastic package body and are communicated with the bonding pad on the upper surface of the chip.
In an embodiment, a side wall heat dissipation plate is disposed on one side wall, two side walls, three side walls or four side walls of the plastic package body.
In an embodiment, the side wall heat sink is connected to the bottom heat sink.
In an embodiment, the plastic package body includes a base layer plastic package body and an insulating layer disposed on a surface of the base layer plastic package body, a redistribution layer is disposed on an upper surface of the base layer plastic package body, the redistribution layer has a plurality of metal pads respectively connected with the pads of the chip, the insulating layer covers the redistribution layer, the insulating layer exposes the metal pads, and the output pins of the chip pass through the insulating layer and are communicated with the metal pads of the redistribution layer.
The invention also provides a preparation method of the enhanced heat dissipation type packaging body, which comprises the following steps: providing a carrier; forming a bottom heat dissipation plate and at least one side wall heat dissipation plate perpendicular to the carrier on the upper surface of the carrier; adhering the lower surface of at least one chip to the upper surface of the bottom heat dissipation plate, wherein the upper surface of the chip provided with a welding pad is opposite to the lower surface of the chip; adopting plastic packaging material to plastic package the chip, the bottom radiating plate and the side wall radiating plate to form a plastic package body; removing the plastic package body corresponding to the welding pad of the chip, and exposing the welding pad; forming a chip output pin on the upper surface of the plastic package body, wherein the chip output pin is communicated with the exposed welding pad; and removing the plastic packaging material on the outer surface of the side wall heat dissipation plate, and removing the carrier to form the heat dissipation enhancement type packaging body.
In an embodiment, a metal layer is disposed on the upper surface of the carrier, and the bottom heat dissipation plate and the side wall heat dissipation plate are formed on the surface of the metal layer by electroplating.
In an embodiment, the side wall heat dissipation plates are one, two, three or four, and the side wall heat dissipation plates are connected with the bottom heat dissipation plate.
In an embodiment, in the step of removing the plastic packages corresponding to the bonding pads of the chip, the method further includes removing all plastic packages on a plane where the bonding pads are located, and exposing the upper surfaces of the bonding pads and the upper surfaces of the side wall heat dissipation plates.
In an embodiment, before the step of forming the output pins of the chip on the upper surface of the plastic package body, a step of forming a redistribution layer is further included, where a plastic package body formed by plastic packaging the chip, the bottom heat dissipation plate and the side wall heat dissipation plate with a plastic package material is defined as a base layer plastic package body: forming a rewiring layer on the upper surface of the base layer plastic package body, wherein the rewiring layer is provided with metal pads which are respectively communicated with the welding pads of the chip; forming an insulating layer on the surface of the rewiring layer, wherein the insulating layer covers the rewiring layer and the base layer plastic package body; removing the insulating layer corresponding to the metal pad of the re-wiring layer to expose the metal pad; and forming a chip output pin on the upper surface of the insulating layer, wherein the chip output pin is communicated with the exposed metal pad.
In one embodiment, the sidewall heat spreader is also raised during the step of forming the redistribution layer.
The invention has the advantages that the bottom surface and the side surface of the packaging body are both provided with the heat dissipation plates, so that the packaging body has excellent heat dissipation performance, and the structure is simple, the heat dissipation effect can be obviously improved for common IC packaging or high-power devices, the heat resistance of the chip packaging is reduced, the reliability and the stability of the chip are improved, and the functions and the practicability of the chip are improved.
Drawings
FIG. 1 is a schematic diagram showing steps of a first embodiment of a method for manufacturing a heat-dissipating enhancement type package;
FIGS. 2A-2G are process flow diagrams of a first embodiment of a method for fabricating a package with enhanced heat dissipation according to the present invention;
FIG. 3 is a schematic diagram showing steps of a second embodiment of a method for manufacturing a heat-dissipating enhancement type package;
fig. 4A to 4J are process flow diagrams of a second embodiment of a method for manufacturing a package with enhanced heat dissipation according to the present invention
FIG. 5 is a schematic view of a first embodiment of a heat dissipation enhancement type package according to the present invention;
fig. 6 is a schematic structural diagram of a second embodiment of the enhanced heat dissipation type package of the present invention.
Detailed Description
The following describes in detail specific embodiments of the enhanced heat dissipation type package and the method for manufacturing the same according to the present invention with reference to the accompanying drawings.
The invention provides a preparation method of a heat dissipation enhancement type package. The structural dimensions of the various components in the drawings are different from the actual components, and are merely used herein to illustrate the technical solution of the present invention, and the specific structure thereof is not limited.
Fig. 1 is a schematic step diagram of a first embodiment of a method for manufacturing a heat dissipation enhancement type package. Referring to fig. 1, in a first embodiment, the method for preparing the enhanced heat dissipation type package includes the following steps: step S10, providing a carrier; s11, forming a bottom radiating plate and at least one side wall radiating plate perpendicular to the carrier on the upper surface of the carrier; step S12, adhering the lower surface of at least one chip to the upper surface of the bottom heat dissipation plate, wherein the upper surface of the chip provided with the welding pad is opposite to the lower surface of the chip; step S13, adopting plastic packaging materials to plastic package the chip, the bottom radiating plate and the side wall radiating plate to form a plastic package body; step S14, removing the plastic package body corresponding to the welding pad of the chip, and exposing the welding pad; s15, forming a chip output pin on the upper surface of the plastic package body, wherein the chip output pin is communicated with the exposed welding pad; and S16, removing the plastic packaging material on the outer surface of the side wall heat dissipation plate, and removing the carrier to form the heat dissipation enhancement type packaging body.
Fig. 2A to 2G are process flow diagrams of a first embodiment of a method for manufacturing a heat dissipation enhancement type package according to the present invention.
Referring to step S10 and fig. 2A, a carrier 200 is provided. The carrier 200 may be a carrier conventional in the art, such as carbon steel or the like. If the carrier 200 is an insulating carrier, a metal layer (not shown in the drawing) may be covered on the upper surface of the carrier 200 to provide the conductive performance, and if the carrier 200 is a conductive carrier, the metal layer may not be formed on the surface of the carrier 200. The carrier 200 has electrical conductivity and can provide a basis for forming the bottom heat spreader and the sidewall heat spreader by a subsequent electroplating process.
Referring to step S11 and fig. 2B, a bottom heat spreader 201 and at least one side heat spreader 202 perpendicular to the carrier 200 are formed on the upper surface of the carrier 200. In the present embodiment, the bottom heat sink 201 and the side wall heat sink 202 may be formed by electroplating. Further, the bottom heat sink 201 is connected to the side heat sink 202. The side wall heat dissipation plates 202 are one, two, three or four, and adjacent side wall heat dissipation plates 202 are connected to each other and the bottom heat dissipation plate 201. In this embodiment, two side wall heat dissipation plates 202 are disposed on the carrier 200, and the two side wall heat dissipation plates 202 and the bottom heat dissipation plate 201 form a U-shaped structure.
Referring to step S12 and fig. 2C, a lower surface of at least one chip 203 is adhered to an upper surface of the bottom heat spreader 201, and an upper surface of the chip 203 with bonding pads 2031 is opposite to the lower surface of the chip 203. The number of the chips 203 is not limited, and may be plural or one, and in this embodiment, one chip 203 is disposed on the upper surface of the bottom heat sink 201. The chip 203 is adhered to the upper surface of the bottom heat sink 201 by using a conductive or non-conductive adhesive 210. The adhesive may include conductive paste, non-conductive paste, solder paste, metallic material, or the like. The chip 203 may be of the type of a functional chip.
Referring to step S13 and fig. 2D, the chip 203, the bottom heat dissipation plate 201 and the side wall heat dissipation plate 202 are encapsulated by a molding compound to form an encapsulated body 204. The plastic packaging method is a conventional plastic packaging method in the field. Wherein, the lower surface of the bottom heat dissipation plate 201 is in contact with the upper surface of the carrier 200, such that the lower surface of the bottom heat dissipation plate 201 is not encapsulated by the encapsulation body 204, i.e., the lower surface thereof is exposed to the lower surface of the bottom heat dissipation plate 201.
Referring to step S14 and fig. 2E, the plastic package corresponding to the bonding pad 2031 of the chip 203 is removed, and the bonding pad 2031 is exposed. In this step, there are many methods for exposing the bonding pad 2031, for example, removing the plastic package body at the corresponding position of the bonding pad 2031 by drilling or the like, exposing the bonding pad 2031, or removing all the plastic package body above the layer where the bonding pad 2031 is located by grinding or the like, exposing the bonding pad 2031. In this embodiment, the whole plastic package body above the layer where the bonding pad 2031 is located is removed by grinding or the like, so that the bonding pad 2031 is exposed. In this step, the bonding pad 2031 is exposed, and the upper surface of the side heat spreader 202 is also exposed.
Referring to step S15 and fig. 2F, a chip output pin 205 is formed on the upper surface of the plastic package 204, and the chip output pin 205 is in communication with the exposed bonding pad 2031. If in step S14, the plastic package body at the position corresponding to the bonding pad 2031 is removed by drilling or the like, and the bonding pad 2031 is exposed, in this step, a metal layer is formed, and the metal layer passes through the hole of the plastic package body to be communicated with the bonding pad 2031, and the metal layer is patterned to form the chip output pin 205; if in step S14, the plastic package body above the layer where the bonding pad 2031 is located is removed by polishing or the like, and the bonding pad 2031 is exposed, then in this step, a metal layer is formed, and the metal layer covers the exposed bonding pad 2031 and the plastic package body 204, and the metal layer is patterned to form the chip output pins 205. In this step, a metal block 206 is also formed on the upper surface of the side wall heat dissipation plate 202, and the metal block 206 increases the height of the side wall heat dissipation plate 202. The thickness of the metal block 206 is less than or equal to the thickness of the chip output pins 205, so as to avoid the side wall heat dissipation plate 202 from affecting the connection between the package and external components.
Referring to step S16 and fig. 2G, the plastic molding compound on the outer surface of the side wall heat spreader 202 is removed, and the carrier 200 is removed, so as to form a heat dissipation enhancement type package. In this step, the plastic package material on the outer surface of the side wall heat dissipation plate 202 is removed, so that the side wall heat dissipation plate 202 is exposed, and the heat dissipation function of the side wall heat dissipation plate 202 is achieved; the carrier 200 is removed to expose the lower surface of the bottom heat dissipation plate 201, so as to implement the heat dissipation function of the bottom heat dissipation plate 201. If the surface of the carrier 200 has a metal layer, the metal layer may remain, which does not affect the heat dissipation performance of the bottom heat dissipation plate 201.
According to the preparation method of the enhanced heat dissipation type packaging body, the heat dissipation plates are arranged on the bottom surface and the side surface of the packaging body, so that the packaging body has excellent heat dissipation performance, is simple in structure, can remarkably improve the heat dissipation effect for common IC packaging or high-power devices, reduces the heat resistance of chip packaging, improves the reliability and stability of chips, and improves the functions and practicability of the chips.
Fig. 3 is a schematic step diagram of a second embodiment of a method for manufacturing a heat dissipation enhancement type package. Referring to fig. 3, in a second embodiment, the method for preparing the enhanced heat dissipation type package includes the following steps: step S30, providing a carrier; s31, forming a bottom radiating plate and at least one side wall radiating plate perpendicular to the carrier on the upper surface of the carrier; step S32, adhering the lower surface of at least one chip to the upper surface of the bottom heat dissipation plate, wherein the upper surface of the chip provided with the welding pad is opposite to the lower surface of the chip; step S33, adopting plastic packaging materials to plastic package the chip, the bottom radiating plate and the side wall radiating plate to form a base layer plastic package body; step S34, removing the base layer plastic package body corresponding to the welding pad of the chip, and exposing the welding pad; step S35, forming a rewiring layer on the upper surface of the base layer plastic package body, wherein the rewiring layer is provided with metal pads which are respectively communicated with the welding pads of the chip; step S36, forming an insulating layer on the surface of the rewiring layer, wherein the insulating layer covers the rewiring layer and the base layer plastic package body; step S37, removing the insulating layer corresponding to the metal pad of the re-wiring layer to expose the metal pad; s38, forming a chip output pin on the upper surface of the insulating layer, wherein the chip output pin is communicated with the exposed metal pad; and S39, removing the plastic packaging material on the outer surface of the side wall heat dissipation plate, and removing the carrier to form the heat dissipation enhancement type packaging body.
Fig. 4A to 4J are process flow diagrams of a second embodiment of a method for manufacturing a package with enhanced heat dissipation according to the present invention.
Referring to step S30 and fig. 4A, a carrier 400 is provided. The carrier 400 may be a carrier conventional in the art, such as carbon steel or the like. If the carrier 400 is an insulating carrier, a metal layer (not shown in the drawing) may be covered on the upper surface of the carrier 400 to provide the conductive performance, and if the carrier 400 is a conductive carrier, the metal layer may not be formed on the surface of the carrier 400. The carrier 400 has conductive properties and can provide a basis for forming the bottom heat spreader and the sidewall heat spreader by a subsequent electroplating process.
Referring to step S31 and fig. 4B, a bottom heat spreader 401 and at least one side heat spreader 402 perpendicular to the carrier 400 are formed on the upper surface of the carrier 400. In the present embodiment, the bottom heat sink 401 and the side wall heat sink 402 may be formed by electroplating. Further, the bottom heat sink 401 is connected to the side heat sink 402. The side wall heat dissipation plates 402 are one, two, three or four, and adjacent side wall heat dissipation plates 402 are connected with each other and the bottom heat dissipation plate 401. In this embodiment, two side wall heat dissipation plates 402 are disposed on the carrier 400, and the two side wall heat dissipation plates 402 and the bottom heat dissipation plate 401 form a U-shaped structure.
Referring to step S32 and fig. 4C, a lower surface of at least one chip 403 is adhered to an upper surface of the bottom heat spreader 401, and an upper surface of the chip 403 with bonding pads 4031 is disposed opposite to the lower surface of the chip 403. The number of the chips 403 is not limited, and may be plural or one, and in this embodiment, one chip 403 is disposed on the upper surface of the bottom heat spreader 401. The chip 403 is adhered to the upper surface of the bottom heat sink 401 by using a conductive or non-conductive adhesive. The adhesive may include conductive paste, non-conductive paste, solder paste, metallic material, or the like. The chip 403 may be of the type a functional chip.
Referring to step S33 and fig. 4D, the chip 403, the bottom heat spreader 401 and the side wall heat spreader 402 are encapsulated by a molding compound to form a base layer encapsulated body 404. The plastic packaging method is a conventional plastic packaging method in the field. Wherein, the lower surface of the bottom heat dissipation plate 401 is in contact with the upper surface of the carrier 400, such that the lower surface of the bottom heat dissipation plate 401 is not encapsulated by the base layer encapsulation body 404, i.e., the lower surface thereof is exposed to the lower surface of the bottom heat dissipation plate 401.
Referring to step S34 and fig. 4E, the plastic package corresponding to the bonding pad 4031 of the chip 403 is removed, and the bonding pad 4031 is exposed. In this step, there are many methods for exposing the bonding pad 4031, for example, removing the plastic package body at the corresponding position of the bonding pad 4031 by drilling or the like, exposing the bonding pad 4031, or removing all plastic package bodies above the layer where the bonding pad 4031 is located by grinding or the like, exposing the bonding pad 4031. In this embodiment, the whole plastic package body above the layer where the bonding pad 4031 is located is removed by grinding, etc. to expose the bonding pad 4031. In this step, the upper surface of the side heat spreader 402 is exposed at the same time as the bonding pad 4031 is exposed.
Referring to step S35 and fig. 4F, a redistribution layer is formed on the upper surface of the base layer molding compound 404, and the redistribution layer has metal pads 407 respectively connected to the bonding pads 4031 of the chip 403. If in step S34, the plastic package body at the corresponding position of the bonding pad 4031 is removed by drilling or the like to expose the bonding pad 4031, then in this step, a metal layer is formed, and the metal layer passes through the hole of the base plastic package body 404 to be communicated with the bonding pad 4031, and the metal layer is patterned to form a rewiring layer; if in step S34, the whole plastic package body above the layer where the bonding pad 4031 is located is removed by polishing or the like to expose the bonding pad 4031, then in this step, a metal layer is formed, and the metal layer covers the exposed bonding pad 4031 and the base plastic package body 404, and the metal layer and the rewiring layer are patterned. In this step, a metal pad 407 of a redistribution layer is also formed on the upper surface of the side-wall heat sink 402, which increases the height of the side-wall heat sink 202. The redistribution layer can expand the range of the pads 4031 of the chip 403 to form a fan-out structure.
Referring to step S36 and fig. 4G, an insulating layer 408 is formed on the surface of the redistribution layer, and the insulating layer 408 covers the redistribution layer and the base layer plastic package 404. The insulating layer 408 may be formed by encapsulating the same plastic as the base layer plastic package 404, or may be formed by brushing or pasting a film. In this embodiment, the insulating layer 408 is formed by encapsulating the same molding compound as the base layer molding compound 404.
Referring to step S37 and fig. 4H, the insulating layer 408 corresponding to the metal pad 407 of the redistribution layer is removed, exposing the metal pad 407. In this step, there are many methods for exposing the metal pad 407, for example, removing the insulating layer 408 at the corresponding position of the metal pad 407 by drilling or the like, exposing the metal pad 407, or removing all the insulating layer 408 above the redistribution layer by grinding or the like, exposing the metal pad 407. In this embodiment, the insulating layer 408 at the corresponding position of the metal pad 407 is removed by drilling, etc., so as to expose the metal pad 407. In this step, the upper surface of the metal pad 407 of the sidewall heat spreader 402 is exposed at the same time as the corresponding metal pad 407 of the bonding pad 4031 is exposed.
Referring to step S38 and fig. 4I, a chip output pin 405 is formed on the upper surface of the insulating layer 408, and the chip output pin 405 is in communication with the exposed metal pad 407. If in step S37, the insulating layer 408 at the corresponding position of the metal pad 407 is removed by drilling or the like to expose the metal pad 407, then in this step, a metal layer is formed, and the metal layer is connected to the metal pad 407 through the hole of the insulating layer 408, and the metal layer is patterned to form the chip output pin 405; if in step S37, the entire insulating layer 408 above the redistribution layer is removed by polishing or the like to expose the metal pad 407, then in this step, a metal layer is formed, and the metal layer covers the exposed metal pad 407 and the insulating layer 408, and the metal layer is patterned to form the chip output pins 405. In this step, a metal block 406 is also formed on the upper surface of the metal pad 407 corresponding to the side wall heat dissipation plate 402, and the metal block 406 increases the height of the side wall heat dissipation plate 402. The thickness of the metal block 406 is less than or equal to the thickness of the chip output pins 405, so as to avoid the side wall heat dissipation plate 402 from affecting the connection between the package body and external components. The metal pad 407 and the metal block 406 connected to the side wall heat dissipation plate 402 may both play a role in heat dissipation, and may be collectively referred to as a side wall heat dissipation plate of the package.
Referring to step S39 and fig. 4J, the plastic molding compound on the outer surface of the side wall heat dissipation plate is removed, and the carrier 200 is removed, so as to form a heat dissipation enhancement type package. In the step, the plastic packaging material on the outer surface of the side wall heat dissipation plate is removed, so that the side wall heat dissipation plate is exposed, and the heat dissipation function of the side wall heat dissipation plate is realized; the carrier 200 is removed to expose the lower surface of the bottom heat dissipation plate 201, so as to implement the heat dissipation function of the bottom heat dissipation plate 201. If the surface of the carrier 400 has a metal layer, the metal layer may remain, which does not affect the heat dissipation performance of the bottom heat dissipation plate 401.
The invention also provides the enhanced heat dissipation type packaging body prepared by adopting the preparation method. Fig. 5 is a schematic structural diagram of a first embodiment of the enhanced heat dissipation type package of the present invention. Referring to fig. 5, the heat dissipation enhanced package of the present invention includes at least one chip 503 and a plastic package 504, wherein the plastic package 504 is shown by a dashed line. In this embodiment, one chip 503 is schematically illustrated. The molding body 504 encapsulates the chip 503. Each of the chips 503 has an upper surface provided with bonding pads 5031 and a lower surface disposed opposite to the upper surface. A bottom heat dissipation plate 501 is disposed at the bottom of the plastic package 504. A side wall heat dissipation plate 502 is disposed on at least one side wall of the plastic package 504. For example, the side wall heat dissipation plates 502 are disposed on one side wall, two side walls, three side walls, or four side walls of the plastic package 504, and in this embodiment, the side wall heat dissipation plates 502 are disposed on two side walls of the plastic package 504. The side wall heat dissipation plate 502 is connected to the bottom heat dissipation plate 501, and in this embodiment, the side wall heat dissipation plate 502 and the bottom heat dissipation plate 501 form a U-shaped structure. The lower surface of the chip 503 is connected to the bottom heat sink 501 by an adhesive 510. The side wall heat dissipation plate 502 and the bottom heat dissipation plate 501 are used for dissipating heat of the plastic package 504. The chip output pins 505 disposed on the upper surface of the plastic package 504 are connected to the bonding pads 5031 on the upper surface of the chip through the plastic package 504.
Fig. 6 is a schematic structural diagram of a second embodiment of the enhanced heat dissipation type package of the present invention. Referring to fig. 6, the difference between the second embodiment of the present invention and the first embodiment is that the plastic package 504 includes a base plastic package 5041 and an insulating layer 508 disposed on the surface of the base plastic package 5041, a redistribution layer is disposed on the upper surface of the base plastic package 5041, the redistribution layer has a plurality of metal pads 507 respectively connected to the pads 5031 of the chip 503, the insulating layer 508 covers the redistribution layer, the insulating layer 508 exposes the metal pads 507, and the chip output pins 505 are connected to the metal pads 507 of the redistribution layer through the insulating layer 508. The redistribution layer can expand the range of the pads 5031 of the die 503 to form a fan-out structure. Wherein the base molding compound 504 and the insulating layer 50 are shown by dashed lines.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (10)

1. A package for enhancing heat dissipation is characterized in that,
the chip packaging structure comprises at least one chip and a plastic package body, wherein the plastic package body is used for plastic packaging the chips, each chip is provided with an upper surface provided with a welding pad and a lower surface opposite to the upper surface, a bottom radiating plate is arranged at the bottom of the plastic package body, a side wall radiating plate is arranged on at least one side wall of the plastic package body, the lower surface of the chip is connected with the bottom radiating plate, and chip output pins arranged on the upper surface of the plastic package body penetrate through the plastic package body and are communicated with the welding pad on the upper surface of the chip;
and a metal block is formed on the upper surface of the side wall heat dissipation plate, the height of the side wall heat dissipation plate is increased by the metal block, and the thickness of the metal block is smaller than or equal to the thickness of the chip output pins.
2. The package of claim 1, wherein the heat dissipation enhancing type is a semiconductor device,
and a side wall heat dissipation plate is arranged on one side wall, two side walls, three side walls or four side walls of the plastic package body.
3. The package of claim 1, wherein the heat dissipation enhancing type is a semiconductor device,
the side wall heat dissipation plate is connected with the bottom heat dissipation plate.
4. The package of claim 1, wherein the heat dissipation enhancing type is a semiconductor device,
the plastic package body comprises a base layer plastic package body and an insulating layer arranged on the surface of the base layer plastic package body, wherein a rewiring layer is arranged on the upper surface of the base layer plastic package body and is provided with a plurality of metal pads respectively connected with the welding pads of the chip, the insulating layer covers the rewiring layer, the insulating layer exposes out of the metal pads, and the chip output pins penetrate through the insulating layer and are communicated with the metal pads of the rewiring layer.
5. A preparation method of a package body for enhancing heat dissipation is characterized in that,
the method comprises the following steps:
providing a carrier;
forming a bottom heat dissipation plate and at least one side wall heat dissipation plate perpendicular to the carrier on the upper surface of the carrier;
adhering the lower surface of at least one chip to the upper surface of the bottom heat dissipation plate, wherein the upper surface of the chip provided with a welding pad is opposite to the lower surface of the chip;
adopting plastic packaging material to plastic package the chip, the bottom radiating plate and the side wall radiating plate to form a plastic package body;
removing the plastic package body corresponding to the welding pad of the chip, and exposing the welding pad;
forming a chip output pin on the upper surface of the plastic package body, wherein the chip output pin is communicated with the exposed welding pad;
removing the plastic packaging material on the outer surface of the side wall heat dissipation plate, and removing the carrier to form a heat dissipation enhancement type packaging body;
the step of forming a chip output pin on the upper surface of the plastic package body, wherein the chip output pin is communicated with the exposed welding pad comprises the following steps: a metal block is formed on the upper surface of the side wall heat dissipation plate; the metal block increases the height of the side wall heat dissipation plate, and the thickness of the metal block is smaller than or equal to the thickness of the chip output pins.
6. The method of manufacturing a package for enhanced heat dissipation according to claim 5, wherein,
the upper surface of the carrier is provided with a metal layer, and the bottom radiating plate and the side wall radiating plate are formed on the surface of the metal layer in an electroplating mode.
7. The method of manufacturing a package for enhanced heat dissipation according to claim 5, wherein,
the side wall cooling plates are one, two, three or four, and the side wall cooling plates are connected with the bottom cooling plate.
8. The method of manufacturing a package for enhanced heat dissipation according to claim 5, wherein,
in the step of removing the plastic package bodies corresponding to the bonding pads of the chip, the method further comprises removing all the plastic package bodies on the plane where the bonding pads are located, and exposing the upper surfaces of the bonding pads and the upper surfaces of the side wall heat dissipation plates.
9. The method of manufacturing a package for enhanced heat dissipation according to claim 5, wherein,
the method further comprises a step of forming a rewiring layer before the step of forming the chip output pins on the upper surface of the plastic package body, wherein the plastic package body formed by adopting plastic package materials to plastic package the chip, the bottom heat dissipation plate and the side wall heat dissipation plate is defined as a base layer plastic package body:
forming a rewiring layer on the upper surface of the base layer plastic package body, wherein the rewiring layer is provided with metal pads which are respectively communicated with the welding pads of the chip;
forming an insulating layer on the surface of the rewiring layer, wherein the insulating layer covers the rewiring layer and the base layer plastic package body;
removing the insulating layer corresponding to the metal pad of the re-wiring layer to expose the metal pad;
and forming a chip output pin on the upper surface of the insulating layer, wherein the chip output pin is communicated with the exposed metal pad.
10. The method of manufacturing a package for enhanced heat dissipation according to claim 9,
in the step of forming the rewiring layer, the side wall heat dissipation plate is also raised.
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Publication number Priority date Publication date Assignee Title
CN1391274A (en) * 2002-07-01 2003-01-15 威盛电子股份有限公司 Chip package structure and its preparing process
CN207800591U (en) * 2017-12-20 2018-08-31 合肥矽迈微电子科技有限公司 Enhance heat radiating type packaging body

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TWI246760B (en) * 2004-12-22 2006-01-01 Siliconware Precision Industries Co Ltd Heat dissipating semiconductor package and fabrication method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1391274A (en) * 2002-07-01 2003-01-15 威盛电子股份有限公司 Chip package structure and its preparing process
CN207800591U (en) * 2017-12-20 2018-08-31 合肥矽迈微电子科技有限公司 Enhance heat radiating type packaging body

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