CN108292610B - 使用富含铋的焊料的电子组合件 - Google Patents

使用富含铋的焊料的电子组合件 Download PDF

Info

Publication number
CN108292610B
CN108292610B CN201580083334.2A CN201580083334A CN108292610B CN 108292610 B CN108292610 B CN 108292610B CN 201580083334 A CN201580083334 A CN 201580083334A CN 108292610 B CN108292610 B CN 108292610B
Authority
CN
China
Prior art keywords
bismuth
solder
substrate
copper
electronic assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201580083334.2A
Other languages
English (en)
Other versions
CN108292610A (zh
Inventor
刘丕林
P.K.穆图尔斯里纳
D.戈亚尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN108292610A publication Critical patent/CN108292610A/zh
Application granted granted Critical
Publication of CN108292610B publication Critical patent/CN108292610B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0233—Sheets, foils
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0233—Sheets, foils
    • B23K35/0238—Sheets, foils layered
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/264—Bi as the principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Abstract

一些形式涉及电子组合件，包含第一衬底，所述第一衬底具有安装在第一衬底的铜衬垫。电子组合件进一步包含第二衬底，所述第二衬底包含安装在第二衬底上的铜重分布层。电子组合件进一步包含富含铋的焊料，所述富含铋的焊料包含10‑40 w.t.%的锡。富含铋的焊料与铜衬垫和铜重分布层电接合。在一些形式中，铜重分布层是另一铜衬垫。第一衬底可包含存储器管芯以及第二衬底可包含逻辑管芯。在其它形式中，第一和第二衬底可以是各种不同的电子组件的部分。与第一和第二衬底关联的电子组件的类型将部分地取决于在其中电子组合件（连同其它因素一道）被利用的应用。

Description

使用富含铋的焊料的电子组合件
背景技术
焊点典型地包含一个衬底上的镍凸起和另一衬底上的铜衬垫的顶部上的电镀的阻挡层。电镀的阻挡层通常用于保护铜衬垫。
在跨越铜衬垫的阻挡层中典型地缺乏均匀性。这种均匀性的缺乏消极地影响阻挡层的有效性。这些阻挡层也通常要求不需要的额外的处理步骤和增加的成本。
此外，阻挡层在创建适当的焊点中可不是特别有效的。在焊点的形成期间，铜衬垫经常被完全消耗。如果在焊点的形成期间消耗太多铜衬垫，则焊点可形成不可靠的电连接。
附图说明
图1是在电子组件装配到一起之前的电子组合件中的电子组件的示意性侧视图。
图2示出在电子组件装配到一起以形成电子组合件之后的图1的电子组合件。
图3是在电子组件装配到一起之前的示例电子组合件中的电子组件的示意性侧视图。
图4是在电子组件装配到一起之前的另一示例电子组合件中的电子组件的示意性侧视图。
图5示出在电子组件装配到一起以形成电子组合件之后的图3或4的示例电子组合件。
图6是图示制作电子组合件的示例方法的流程图。
图7是电子装置的框图，所述电子装置包含本文描述的电子组合件和/或方法。
具体实施方式
以下描述和附图充分地图示具体的实施例以使本领域技术人员能够实践它们。其它实施例可包含结构、逻辑、电、工艺以及其它改变。一些实施例的部分和特征可包含在其它实施例的那些部分和特征中或替代它们。权利要求中阐述的实施例包含那些权利要求的所有可用的等同物。
如在本应用中使用的定向术语（诸如“水平”）关于与晶片或衬底的常规平面或表面平行的平面来定义，而不管晶片或衬底的定向。术语“垂直”指的是与如上面定义的水平正交的方向。诸如“在……上”、“侧”（如在“侧壁”中）、“更高”、“更低”、“在……上方”以及“在……下面”的介词关于在晶片或衬底的顶部表面上的常规平面或表面来定义，而不管晶片或衬底的定向。
本文描述的电子组合件和方法使用富含铋的焊料以形成具有最优化的锡含量的焊点。在焊点内最优化锡含量可解决在装配工艺期间由铜重分布层到金属间化合物的完全转换导致的重分布层铜衬垫打开问题。
在常规电子组合件和方法中的铜重分布层的这种完全转换是有问题的，因为理想的是将铜迹线的厚度最小化。在常规工艺中，在在通常使用的装配工艺期间发生的多个回流期间，可以迅速消耗薄的铜迹线。尤其当使用常规焊料时，这些多个回流可以导致形成为打开的焊点。
图1是在电子组件1、2装配到一起之前的常规电子组合件10中的电子组件1、2的示意性侧视图。图2示出在电子组件1、2装配到一起以形成电子组合件10之后的图1的电子组合件10。
焊点包含一个衬底4上的镍凸起3并且进一步包含另一衬底7上的铜衬垫6的顶部上的电镀的阻挡层5。电镀的阻挡层5通常用于保护铜衬垫6。
电子组合件10中的焊点遭受若干缺点的影响。一个缺点涉及在阻挡层5内维持质量。
另一缺点涉及跨越铜衬垫6的阻挡层5中均匀性的缺乏。这种均匀性的缺乏消极地影响阻挡层5的有效性。
电子组合件10和关联的制作工艺包含不需要的额外的处理步骤和增加的成本。这些不需要的额外的处理步骤和增加的成本最通常与将阻挡层5镀在铜衬垫6上关联。
此外，阻挡层5在创建适当的焊点中可不是特别有效的。最主导的顾虑涉及在焊点的形成期间铜衬垫6（或连接到铜衬垫6的导电迹线）被完全消耗。如果在焊点的形成期间消耗太多铜衬垫6，则焊点可形成不可靠的电连接。
本文所描述的电子组合件和方法利用仅提供用于与铜衬垫反应的限量的锡的富含铋的焊点。因为焊点包含适量的锡，所以焊点被最优化以在不使用任何阻挡层的情况下而消除铜重分布层消耗问题。本文所描述的电子组合件和方法是对于典型地要求阻挡层来保护铜重分布层的常规途径的改进。
图3是在电子组件装配到一起之前的示例电子组合件30中的电子组件的示意性侧视图。图4是图3中所示的电子组件的示意性侧视图，其中在电子组件装配到一起之前，富含铋的焊料包含共晶的锡-铋焊料。图5示出在电子组件装配到一起以形成电子组合件30之后的图3或4的示例电子组合件30。
如图3和5所示，电子组合件30包含第一衬底31，所述第一衬底31具有安装在第一衬底31的铜衬垫32。电子组合件进一步包含第二衬底33，所述第二衬底33包含安装在第二衬底33上的铜重分布层34。
电子组合件进一步包含富含铋的焊料35，所述富含铋的焊料35包含10-40 w.t. %的锡。富含铋的焊料35与铜衬垫32和铜重分布层34电接合。
作为一个示例，富含铋的焊料35可包含10-40 w.t. %的锡，并且富含铋的焊料35的剩余部分为铋。作为另一示例，富含铋的焊料35可包含10-40 w.t. %的锡，并且富含铋的焊料35的大部分（即大于50 w.t. %）可为铋。作为另一示例，富含铋的焊料35可包含10-40w.t. %的锡以及60-90 w.t. %的铋。
应注意的是富含铋的焊料35可具有170和260摄氏度之间的回流温度。更具体地，富含铋的焊料35可具有180和220摄氏度之间的回流温度。
在一些形式中，铜重分布层34是另一铜衬垫。应注意的是，取决于在其中电子组合件要被使用的应用以及用于制作电子组合件30的制造工艺，铜重分布层34可采用各种形式并且可以是各种不同的材料。
作为示例，第一衬底31可包含存储器管芯以及第二衬底33可包含逻辑管芯。其它形式中，第一和第二衬底31、33可以是各种不同的电子组件的部分。与第一和第二衬底31、33关联的电子组件的类型将部分地取决于在其中电子组合件30（连同其它因素一道）被利用的应用。
如图4所示，富含铋的焊料35可包含接合铜重分布层34的共晶的锡-铋焊料36。作为示例，即使预期将共晶的锡-铋焊料36附接到富含铋的焊料35的其它形式，共晶的锡-铋焊料36可被电镀到富含铋的焊料35。
在一些形式中，在将第一衬底31附接到第二衬底33之前，共晶的锡-铋焊料36为1-3微米厚。此外，在将第一衬底31附接到第二衬底33之前，富含铋的焊料35可具有10-15微米的z高度。
可向富含铋的焊料35添加共晶的富含铋的焊料36以改进富含铋的焊料的可湿性。改进富含铋的焊料35的可湿性可改进焊点的形成。
图3-5示出电子组合件30可进一步包含第二衬底33上的钝化层37。钝化层37可包含开口38使得铜重分布层34通过开口38暴露。
应注意的是，在制造工艺期间，只有锡将与铜重分布层34反应。铋将不与铜重分布层34反应。最优化锡的量以便在回流操作期间，铜重分布层34将不被完全消耗。
图6是图示制作电子组合件的示例方法[600]的流程图。方法[600]包含[610]使用包含10-40 w.t. %的锡的富含铋的焊料35，将第一衬底31上的铜衬垫32附接到第二衬底33上的铜重分布层34。富含铋的焊料35与铜衬垫32和铜重分布层34电接合（见图5）。
将第一衬底上的铜衬垫32附接到第二衬底33上的铜重分布层34可包含将逻辑管芯附接到存储器管芯。第一和第二衬底31、33可以是其它类型的电子组件的部分。在方法[600]中使用的电子组件的类型将部分地取决于在其中要使用电子组合件30的应用。
方法[600]可进一步包含[620]在将第一衬底31附接到第二衬底33之前，将共晶的锡-铋焊料36（见图4）电镀到富含铋的焊料35。共晶的锡-铋焊料36可采用现在已知或在未来发现的任何方式来附接到富含铋的焊料35。
共晶的锡-铋焊料36可改进富含铋的焊料35的可湿性。在一些形式中，将共晶的锡-铋焊料36电镀到富含铋的焊料35包含将1-3微米的共晶的锡-铋焊料36电镀到富含铋的焊料35。
在一些形式中，[610]将第一衬底31上的铜衬垫32附接到第二衬底33上的铜重分布层34可包含（i）将第一衬底31上的铜衬垫32附接到第二衬底33上的另一铜衬垫；（ii）在170和260℃之间的温度，将铜衬垫32焊接到铜重分布层34；和/或（iii）将富含铋的焊料35置于第二衬底33上的钝化层37中的开口38内。在将第一衬底31焊接到第二衬底33时，富含铋的焊料35的使用可提供使用各种温度的灵活性。
本文所描述的电子组合件30和方法[600]可提供改进的焊点，因为在装配工艺期间，常规焊点经常完全消耗铜重分布层中的铜。此外，本文所描述的电子组合件30和方法[600]可消除对于阻挡层的需要，因而简化制作工艺并且潜在地降低总制作成本。
图7是合并本文所描述的电子组合件30和/或方法[600]中的至少一个的电子装置700的框图。电子装置700只是电子装置的一个示例，在所述电子装置700中，可使用本文所描述的方法[600]和/或电子组合件30的形式。电子装置700的示例包含（但不限于）个人计算机、平板计算机、移动电话、游戏设备、MP3或其它数字媒体播放器等。
在本示例中，电子装置700包括数据处理系统，所述数据处理系统包含系统总线702以耦合电子装置700的各种组件。系统总线702提供在电子装置700的各种组件之中的通信链路，并且可实现为单个总线、总线的组合或采用任何其它适合的方式来实现。
如本文所描述的电子装置700可耦合到系统总线702。电子装置700可包含任何电路或电路的组合。在一个实施例中，电子装置700包含可以是任何类型的处理器712。如本文所使用的“处理器”意思是任何类型的计算电路，诸如但不限于：微处理器、微控制器、复杂指令集计算（CISC）微处理器、精简指令集计算（RISC）微处理器、超长指令字（VLIW）微处理器、图形处理器、数字信号处理器（DSP）、多核处理器或任何其它类型的处理器或处理电路。
可包含在电子装置700的其它类型的电路是定制电路、专用集成电路（ASIC）等等，诸如，例如供无线设备（像移动电话、平板计算机、膝上型计算机、双向无线电、以及类似的电子系统）使用的一个或多个电路（诸如通信电路714）。IC可以执行任何其它类型的功能。
电子装置700也可包含外部存储器720，所述外部存储器720可又包含适用于特定应用的一个或多个存储器元件，诸如采用随机存取存储器（RAM）形式的主存储器722、一个或多个硬盘驱动器724、和/或处理诸如压缩盘（CD）、闪速存储器卡、数字视频盘（DVD）等等的可移除媒体726的一个或多个驱动器。
电子装置700也可包含显示设备716、一个或多个扬声器718以及键盘和/或控制器730，其可以包含鼠标、跟踪球、触控板、声音识别设备或允许系统用户向电子装置700中输入信息以及从电子装置700接收信息的任何其它设备。
为了更好地图示本文所公开的电子组合件和/或方法，本文提供了示例的非限制性列表：
示例1包含一种电子组合件，所述电子组合件具有第一衬底，其中铜衬垫安装在第一衬底；第二衬底，所述第二衬底包含安装在第二衬底上的铜重分布层；以及富含铋的焊料，所述富含铋的焊料包含10-40 w.t. %的锡，富含铋的焊料与铜衬垫和铜重分布层电接合。
示例2包含示例1的电子组合件，其中铜重分布层是另一铜衬垫。
示例3包含示例1到2中任一个的电子组合件，其中第一衬底包含存储器管芯。
示例4包含示例1到3中任一个的电子组合件，其中第二衬底包含逻辑管芯。
示例5包含示例1到4中任一个的电子组合件，其中富含铋的焊料包含接合铜重分布层的共晶的锡-铋焊料。
示例6包含示例1到5中任一个的电子组合件，其中共晶的锡-铋焊料被电镀到富含铋的焊料。
示例7包含示例1到6中任一个的电子组合件，其中在将第一衬底附接到第二衬底之前，共晶的锡-铋焊料为1-3微米厚。
示例8包含示例1到7中任一个的电子组合件，其中在将第一衬底附接到第二衬底之前，富含铋的焊料具有10-15微米的z高度。
示例9包含示例1到8中任一个的电子组合件，并且进一步包含铜重分布层上的钝化层。
示例10包含示例1到9中任一个的电子组合件，其中钝化层包含开口使得铜重分布层通过开口暴露。
示例11包含示例1到10中任一个的电子组合件，其中富含铋的焊料包含10-40w.t. %的锡，以及富含铋的焊料的剩余部分为铋。
示例12包含示例1到10中任一个的电子组合件，其中富含铋的焊料包含10-40w.t. %的锡，以及富含铋的焊料的大部分可为铋。
示例13包含示例1到10中任一个的电子组合件，其中富含铋的焊料包含10-40w.t. %的锡以及60-90 w.t. %的铋。
示例14包含示例1到13中任一个的电子组合件，其中富含铋的焊料具有170和260摄氏度之间的回流温度。
示例15包含一种制作电子组合件的方法，所述方法包括使用包含10-40 w.t. %的锡的富含铋的焊料，将第一衬底上的铜衬垫附接到第二衬底上的铜重分布层，富含铋的焊料与铜衬垫和铜重分布层电接合。
示例16包含示例15的方法，并且进一步包含在将第一衬底附接到第二衬底之前，将共晶的锡-铋焊料电镀到富含铋的焊料。
示例17包含示例15到16中任一个的方法，其中使用富含铋的焊料将第一衬底上的铜衬垫附接到第二衬底上的铜重分布层包含在170和260摄氏度之间的温度，将铜衬垫焊接到铜重分布层。
示例18是一种制作电子组合件的方法，所述方法包括将共晶的锡-铋焊料电镀到包含10-40 w.t. %的锡的富含铋的焊料；以及在170和260摄氏度之间的温度，使用富含铋的焊料将第一衬底上的第一铜衬垫焊接到第二衬底上的第二铜衬垫。
示例19包含示例18的计算机系统组合件，其中将第一衬底上的第一铜衬垫焊接到第二衬底上的第二铜衬垫包含将逻辑管芯上的第一铜衬垫焊接到存储器管芯上的第二铜衬垫。
示例20包含示例18到19中任一个的计算机系统组合件，并且进一步包含在将第一铜衬垫焊接到第二铜衬垫之前，将富含铋的焊料置于钝化层中的开口内。
本概述打算提供本主题的非限制性示例。不打算提供排他的或详尽的解释。详细的描述被包含以提供关于方法的另外的信息。
以上详细的描述包含对附图的参考，所述附图形成详细的描述的一部分。附图以图示的方式示出其中本发明可以被实践的具体实施例。这些实施例在本文中也称作“示例”。这种示例可以包含除了示出的或描述的那些元件以外的元件。然而，本发明人也预期其中只提供示出的或描述的那些元件的示例。此外，本发明人也预期使用关于特定的示例（或者其一个或多个方面）或关于本文所示出的或描述的其它示例（或者其一个或多个方面）而示出的或描述的那些元件（或者其一个或多个方面）的任何组合或排列的示例。
在本文件中，如专利文件中常见的，独立于“至少一个”或“一个或多个”的任何其它实例或使用，术语“a”或“an”被使用以包含一个或多于一个。在本文件中，术语“或”用于指非排他的或，使得“A或B”包含“A但不是B”、“B但不是A”以及“A和B”，除非另有指示。在本文件中，术语“包含”和“其中”被用作相应术语“包括”和“在其中”的易懂的英语的等同物。同样地，在以下权利要求中，术语“包含”和“包括”是开放的，即包含除了在权利要求中的这样的术语之后列出的那些元件以外的元件的系统、设备、物品、组成、形成或工艺，仍然被认为落入那个权利要求的范围内。此外，在以下权利要求中，术语“第一”、“第二”和“第三”等仅用作标签，并且不打算在它们的对象上强加数字的要求。
以上描述确定为说明性的，并且不是约束性的。例如，以上描述的实例（或者其一个或多个方面）可彼此组合使用。其它实施例可以例如由本领域内技术人员之一在回顾以上的描述时使用。
同样地，在上面的详细的描述中，各种特征可聚合到一起来简化本公开。这不应解释为意指未要求保护的公开特征对任何权利要求是必要的。相反，发明的主题可在于少于特定公开的实施例的所有特征。因此，以下权利要求据此并入详细的描述中，其中每个权利要求依赖它自己作为单独的实施例，并且预期这样的实施例可以采用各种组合或排列与彼此组合。应参考附的权利要求，连同这样的权利要求所授权的等同物的全部范围来确定本发明的范围。

Claims (18)

1.一种电子组合件，包括：
第一衬底，其中铜衬垫安装在所述第一衬底；
第二衬底，包含安装在所述第二衬底上的铜重分布层；以及
富含铋的焊料，包含10-40重量百分比的锡，所述富含铋的焊料与所述铜衬垫和所述铜重分布层电接合，其中，所述富含铋的焊料包括作为第一部分的共晶的锡-铋焊料，所述共晶的锡-铋焊料被接合到所述铜重分布层，其中，所述共晶的锡-铋焊料被电镀到所述富含铋的焊料的第二部分。
2.如权利要求1所述的电子组合件，其中所述铜重分布层是另一铜衬垫。
3.如权利要求1-2中任一项所述的电子组合件，其中所述第一衬底包含存储器管芯。
4.如权利要求1-2中任一项所述的电子组合件，其中所述第二衬底包含逻辑管芯。
5.如权利要求1所述的电子组合件，其中在将所述第一衬底附接到所述第二衬底之前，所述共晶的锡-铋焊料为1-3微米厚。
6.如权利要求1或5所述的电子组合件，其中在将所述第一衬底附接到所述第二衬底之前，所述富含铋的焊料具有10-15微米的z高度。
7.如权利要求1-2中任一项所述的电子组合件，进一步包括所述铜重分布层上的钝化层。
8.如权利要求7所述的电子组合件，其中所述钝化层包含开口使得所述铜重分布层通过所述开口暴露。
9.如权利要求1-2中任一项所述的电子组合件，其中所述富含铋的焊料包含10-40重量百分比的锡，以及所述富含铋的焊料的剩余部分为铋。
10.如权利要求1-2中任一项所述的电子组合件，其中所述富含铋的焊料包含10-40重量百分比的锡，以及所述富含铋的焊料的大部分为铋。
11.如权利要求1-2中任一项所述的电子组合件，其中所述富含铋的焊料包含10-40重量百分比的锡以及60-90重量百分比的铋。
12.如权利要求1-2中任一项所述的电子组合件，其中所述富含铋的焊料具有170和260摄氏度之间的回流温度。
13.一种制作电子组合件的方法，所述方法包括使用包含10-40重量百分比的锡的富含铋的焊料，将第一衬底上的铜衬垫附接到第二衬底上的铜重分布层，所述富含铋的焊料与所述铜衬垫和所述铜重分布层电接合，其中，所述富含铋的焊料包括作为第一部分的共晶的锡-铋焊料，所述共晶的锡-铋焊料被接合到所述铜重分布层，其中，所述共晶的锡-铋焊料被电镀到所述富含铋的焊料的第二部分。
14.如权利要求13所述的方法，进一步包括在将所述第一衬底附接到所述第二衬底之前，将共晶的锡-铋焊料电镀到所述富含铋的焊料。
15.如权利要求13-14中任一项所述的方法，其中使用富含铋的焊料将第一衬底上的铜衬垫附接到第二衬底上的铜重分布层包含在170和260摄氏度之间的温度，将所述铜衬垫焊接到所述铜重分布层。
16.一种制作电子组合件的方法，包括：
将作为富含铋的焊料的第一部分的共晶的锡-铋焊料电镀到所述富含铋的焊料的第二部分，所述富含铋的焊料包含10-40重量百分比的锡；以及
在170和260摄氏度之间的温度，使用所述富含铋的焊料将第一衬底上的第一铜衬垫焊接到第二衬底上的第二铜衬垫，其中，所述共晶的锡-铋焊料被接合到所述第二铜衬垫。
17.如权利要求16所述的方法，其中将第一衬底上的第一铜衬垫焊接到第二衬底上的第二铜衬垫包含将逻辑管芯上的所述第一铜衬垫焊接到存储器管芯上的所述第二铜衬垫。
18.如权利要求16-17中任一项所述的方法，进一步包括在将所述第一铜衬垫焊接到所述第二铜衬垫之前，将所述富含铋的焊料置于钝化层中的开口内。
CN201580083334.2A 2015-09-25 2015-09-25 使用富含铋的焊料的电子组合件 Active CN108292610B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/052443 WO2017052640A1 (en) 2015-09-25 2015-09-25 Electronic assembly using bismuth-rich solder

Publications (2)

Publication Number Publication Date
CN108292610A CN108292610A (zh) 2018-07-17
CN108292610B true CN108292610B (zh) 2023-02-28

Family

ID=58386971

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580083334.2A Active CN108292610B (zh) 2015-09-25 2015-09-25 使用富含铋的焊料的电子组合件

Country Status (3)

Country Link
US (1) US10361167B2 (zh)
CN (1) CN108292610B (zh)
WO (1) WO2017052640A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10361167B2 (en) 2015-09-25 2019-07-23 Intel Corporation Electronic assembly using bismuth-rich solder
US10784203B2 (en) * 2017-11-15 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
CN111354686B (zh) * 2018-12-21 2022-11-08 矽品精密工业股份有限公司 电子封装件及其制法暨封装用基板及其制法
US11276659B2 (en) 2020-02-28 2022-03-15 Micron Technology, Inc. Methods for forming elements for microelectronic components, related conductive elements, and microelectronic components, assemblies and electronic systems incorporating such conductive elements

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1927525A (zh) * 2006-08-11 2007-03-14 北京有色金属研究总院 一种无银的锡铋铜系无铅焊料及其制备方法
CN101348875A (zh) * 2008-06-04 2009-01-21 厦门市及时雨焊料有限公司 一种锡铋铜型低温无铅焊料合金
CN101716707A (zh) * 2009-11-26 2010-06-02 深圳市亿铖达工业有限公司 纳米增强无铅复合钎料
CN101869982A (zh) * 2010-06-26 2010-10-27 上海交通大学 核壳型铝锡铋无铅焊料及其制备方法
CN102321829A (zh) * 2011-10-24 2012-01-18 南京信息工程大学 一种无银低熔点锡铋系无铅焊料合金及其制备方法
CN102528336A (zh) * 2011-12-13 2012-07-04 浙江亚通焊材有限公司 一种利用脆性锡铋系合金制备高塑性焊接丝材的方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050275096A1 (en) * 2004-06-11 2005-12-15 Kejun Zeng Pre-doped reflow interconnections for copper pads
US7267861B2 (en) 2005-05-31 2007-09-11 Texas Instruments Incorporated Solder joints for copper metallization having reduced interfacial voids
TWI267996B (en) * 2005-10-13 2006-12-01 Phoenix Prec Technology Corp Method for manufacturing semiconductor package circuit board
TWI275186B (en) * 2005-10-17 2007-03-01 Phoenix Prec Technology Corp Method for manufacturing semiconductor package
KR100719905B1 (ko) * 2005-12-29 2007-05-18 삼성전자주식회사 Ｓｎ-Ｂｉ계 솔더 합금 및 이를 이용한 반도체 소자
US7723225B2 (en) * 2006-02-07 2010-05-25 Stats Chippac Ltd. Solder bump confinement system for an integrated circuit package
JP5537119B2 (ja) * 2009-10-28 2014-07-02 京セラ株式会社 蓋体並びに蓋体の製造方法および電子装置の製造方法
US9272371B2 (en) * 2013-05-30 2016-03-01 Agc Automotive Americas R&D, Inc. Solder joint for an electrical conductor and a window pane including same
JP2015056605A (ja) * 2013-09-13 2015-03-23 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9941207B2 (en) * 2014-10-24 2018-04-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield
US10361167B2 (en) 2015-09-25 2019-07-23 Intel Corporation Electronic assembly using bismuth-rich solder

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1927525A (zh) * 2006-08-11 2007-03-14 北京有色金属研究总院 一种无银的锡铋铜系无铅焊料及其制备方法
CN101348875A (zh) * 2008-06-04 2009-01-21 厦门市及时雨焊料有限公司 一种锡铋铜型低温无铅焊料合金
CN101716707A (zh) * 2009-11-26 2010-06-02 深圳市亿铖达工业有限公司 纳米增强无铅复合钎料
CN101869982A (zh) * 2010-06-26 2010-10-27 上海交通大学 核壳型铝锡铋无铅焊料及其制备方法
CN102321829A (zh) * 2011-10-24 2012-01-18 南京信息工程大学 一种无银低熔点锡铋系无铅焊料合金及其制备方法
CN102528336A (zh) * 2011-12-13 2012-07-04 浙江亚通焊材有限公司 一种利用脆性锡铋系合金制备高塑性焊接丝材的方法

Also Published As

Publication number Publication date
US20180254256A1 (en) 2018-09-06
CN108292610A (zh) 2018-07-17
US10361167B2 (en) 2019-07-23
WO2017052640A1 (en) 2017-03-30

Similar Documents

Publication Publication Date Title
CN108292610B (zh) 使用富含铋的焊料的电子组合件
US9064971B2 (en) Methods of forming ultra thin package structures including low temperature solder and structures formed therby
WO2019245693A1 (en) Electrical interconnections with improved compliance
US10741515B2 (en) Grid array connection device and method
US11676900B2 (en) Electronic assembly that includes a bridge
US20150371962A1 (en) Terminal structure, semiconductor device, and terminal forming method
US20190006294A1 (en) Stiffener for a package substrate
US8421223B2 (en) Conductive structure for a semiconductor integrated circuit
US10192840B2 (en) Ball pad with a plurality of lobes
KR102510801B1 (ko) Cu 표면 마감 상의 zn 도핑된 솔더들을 가지는 반도체 디바이스 및 솔더 인터커넥트를 형성하는 방법
CN110233141B (zh) 用于微电子结构中的互连垫的表面末道层
US9324680B2 (en) Solder attach apparatus and method
US9721906B2 (en) Electronic package with corner supports
JP7015489B2 (ja) マイクロ電子構造体における相互接続パッドの表面仕上げ材
CN100521180C (zh) 具有强化层的半导体封装结构及其封装方法
US11417592B2 (en) Methods of utilizing low temperature solder assisted mounting techniques for package structures
US9947631B2 (en) Surface finishes for interconnection pads in microelectronic structures
US20150001706A1 (en) Systems and methods for avoiding protrusions in injection molded solder

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant