CN108287443B

CN108287443B - Display panel

Info

Publication number: CN108287443B
Application number: CN201810136186.1A
Authority: CN
Inventors: 曾胜煊; 纪志贤; 李美慧
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2017-12-05
Filing date: 2018-02-09
Publication date: 2021-01-01
Anticipated expiration: 2038-02-09
Also published as: CN108287443A; TW201925866A; TWI643001B

Abstract

A display panel comprises a substrate, at least two first signal lines, at least two second signal lines, at least two adjacent sub-pixels, a first color conversion layer and a second color conversion layer. The first signal lines and the second signal lines are staggered and arranged on the substrate. The two adjacent sub-pixels are arranged on the substrate and are respectively electrically connected with one of the corresponding first signal lines and one of the corresponding second signal lines. One of the first signal lines between two adjacent sub-pixels has a main body portion and at least two first protruding portions, a part of the main body portion and the first protruding portions define a space having an opening, and one of the second signal lines extends through the part of the space via the opening and crosses the part of the main body portion. The first color conversion layer and the second color conversion layer are respectively positioned on two adjacent sub-pixels.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a display panel having a signal line with a protrusion.

Background

The color filter is integrated on a thin film transistor array substrate (COA) technology, which can avoid the alignment problem between the color filter unit and the pixel unit, which is easily generated between the color filter substrate and the COA substrate, so as to improve the aperture ratio and increase the brightness of the display panel. However, due to the structure of the double metal layers (e.g., the first metal layer and the second metal layer stacked up and down) and the insulating layer sandwiched between the double metal layers, the boundaries between two adjacent color filters are prone to have uneven surfaces (e.g., raised ox horn (Tsuno)) at the boundaries, so that the quality of the display panel is poor.

Disclosure of Invention

The invention provides a display panel, which has a substantially flat surface at the boundary of two adjacent color filters.

The display panel comprises a substrate, at least two first signal lines, at least two second signal lines, at least two adjacent sub-pixels, a first color conversion layer and a second color conversion layer. The at least two first signal lines and the at least two second signal lines are arranged on the substrate, and the first signal lines and the second signal lines are staggered. At least two adjacent sub-pixels are arranged on the substrate, and the two adjacent sub-pixels are respectively and electrically connected with one of the corresponding first signal lines and one of the corresponding second signal lines. One of the first signal lines between two adjacent sub-pixels has a main body portion and at least two first protruding portions, a space with an opening is defined by part of the main body portion and the first protruding portions, and one of the second signal lines extends through part of the space via the opening and is staggered with part of the main body portion. The first color conversion layer and the second color conversion layer are respectively positioned on two adjacent sub-pixels, wherein the adjacent part boundaries of the first color conversion layer and the second color conversion layer are respectively overlapped on part of the main body part, the first color conversion layer is provided with a second protruding part which is overlapped on at least one part of the first protruding part and at least one part of the space, the second color conversion layer is provided with a concave part corresponding to the second protruding part, and the color of the first color conversion layer is different from the color of the second color conversion layer.

Based on the above, in the display panel according to the embodiment of the invention, since the main body portion and the first protruding portion of one of the first signal lines define a space having an opening, and one of the second signal lines extends through a part of the space via the opening and crosses a part of the main body portion, and the first color conversion layer thereon has the second protruding portion overlapping at least a part of the first protruding portion and at least a part of the space; and the second color conversion layer has a recess corresponding to the second protrusion. In this way, when the adjacent partial boundaries of the first color conversion layer and the second color conversion layer are respectively overlapped on partial main body portions, the boundaries of the first color conversion layer and the second color conversion layer do not cover the metal layers arranged on different film layers at the same time, so that the substantially flat surface is realized at the boundaries of the adjacent first color conversion layer and the adjacent second color conversion layer.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a top view of a portion of sub-pixels of a display panel according to an embodiment of the invention.

Fig. 2 is an enlarged view of an area surrounded by a dotted line B in fig. 1.

Fig. 3 is a schematic sectional view taken along line a-a' of fig. 2.

Description of reference numerals:

100: display panel

102: substrate

104: main body part

106: first protruding part

108: opening of the container

110: space(s)

112: second protrusion

114: concave part

BL: boundary of

GI: gate insulating layer

DL: data line

SL: scanning line

CL1, CL2, CL 3: common electrode wire

PX1, PX 2: sub-pixel

PE 1: a first pixel electrode

PE 2: second pixel electrode

TFT 1: a first switch element

TFT 2: second switch element

ST: sharing element

G1, G2, SG: grid electrode

SM1, SM2, SSM: semiconductor layer

S1, S2, SS: source electrode

D1, D2, SD: drain electrode

C1, C2: contact window

CF1, CF 2: color conversion layer

SLi: slit

MB1, MB 2: main body

Detailed Description

The present invention will now be described more fully hereinafter with reference to the accompanying drawings of the present embodiments. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numbers refer to the same or similar elements, and the following paragraphs will not be repeated. In addition, directional terms mentioned in the embodiments, for example: up, down, left, right, front or rear, etc., are directions with reference to the attached drawings only. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting.

In the drawings, the thickness of layers, films, panels, regions, etc. have been exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections (or, couplings). However, an electrical connection (or coupling) is one where there are other elements between the two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specified amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%. Further, as used herein, "about", "approximately" or "substantially" may be selected based on optical properties, etch properties, or other properties, with a more acceptable range of deviation or standard deviation, and not all properties may be applied with one standard deviation.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG. 1 is a top view of a portion of sub-pixels of a display panel according to an embodiment of the invention. In order to clearly show the relative positions and connection relationships of the components in the sub-pixels and the plurality of same or different signal lines, the color conversion layer is omitted in fig. 1, and only one of the two adjacent sub-pixels is shown. Fig. 2 is an enlarged view of an area surrounded by a dotted line B in fig. 1. Fig. 3 is a schematic sectional view taken along line a-a' of fig. 2.

Referring to fig. 1 and 2, the display panel 100 includes a substrate 102, at least two first signal lines (e.g., data lines DL), at least two second signal lines (e.g., scan lines SL or common electrode lines CL1, CL2, or at least one of common electrode lines CL1, CL2 and scan lines SL), at least two adjacent sub-pixels PX1, PX2, color conversion layers CF1, and CF 2. The present embodiment is described with two adjacent sub-pixels as an exemplary embodiment, but the present invention is not limited thereto, and the display panel 100 may include a plurality of sub-pixels. In some embodiments, the display panel 100 may be composed of a substrate, an opposite substrate, and a display medium layer therebetween.

The first signal lines and the second signal lines are disposed on the substrate 102, and at least one of the first signal lines may be interlaced (or crossed, for example, interclane) with at least one of the second signal lines. In some embodiments, the first signal line may include one of the data lines DL, and the second signal line may include one of the scan lines SL, one of the common electrode lines CL1 and CL2, or one of the common electrode lines CL1 and CL2 and the scan line SL, but is not limited thereto. In the present embodiment, preferably, the first signal line may include one of the data lines DL, and the second signal line may include one of the scan lines SL, but is not limited thereto. In addition, the display panel 100 may optionally further include a common electrode line CL3 disposed between two adjacent first signal lines (e.g., the data lines DL), but is not limited thereto. In some embodiments, the scan line SL and the common electrode lines CL1, CL2 may belong to the same film layer, which belongs to different film layers from the common electrode line CL3 and the data line DL. For example, the scan line SL and the common electrode lines CL1 and CL2 may be a first conductive layer, and the common electrode line CL3 and the data line DL may be a second conductive layer disposed on the first conductive layer, but the invention is not limited thereto.

Two adjacent sub-pixels PX1, PX2 are disposed on the substrate 102, and the two adjacent sub-pixels PX1, PX2 are respectively electrically connected to one of the corresponding first signal lines (e.g., the data line DL) and one of the corresponding second signal lines (e.g., the scan line SL or the common electrode lines CL1, CL 2). In addition, three different color sub-pixels (e.g., red sub-pixel R, green sub-pixel G, and blue sub-pixel B) can constitute a pixel unit capable of emitting white light. In some embodiments, each of the two adjacent sub-pixels PX1, PX2 may include the first pixel electrode PE1 or the second pixel electrode PE2, respectively, but is not limited thereto. In the present embodiment, each of the two adjacent sub-pixels PX1, PX2 may include the first pixel electrode PE1 and the second pixel electrode PE2, respectively, for example, and may be disposed on two opposite sides of the scan line SL, respectively, but not limited thereto. In other embodiments, each of the two adjacent sub-pixels PX1, PX2 may include the first pixel electrode PE1 and the second pixel electrode PE2, respectively, and may also be disposed on the same side of the scan line SL, respectively. In some embodiments, at least one of the first pixel electrode PE1 and the second pixel electrode PE2 may optionally further include a plurality of slits SLi having different extending directions or a plurality of slits SLi having substantially the same extending direction, but is not limited thereto. For example, in the present embodiment, the common electrode line CL3 substantially overlaps with the main body MB1 of the first pixel electrode PE1 and the second pixel electrode PE2, and divides the first pixel electrode PE1 and the second pixel electrode PE2 into at least a left region and a right region. The main body MB1 may be located at the intersection of the slits of the first and second pixel electrodes PE1 and PE2, respectively, in different extending directions, the common electrode line CL3 may be located at the intersection of the slits of the first and second pixel electrodes PE1 and PE2, in different extending directions, and the common electrode line CL3 may substantially extend along the extending direction of the main body MB1, but is not limited thereto. In other embodiments, the extending direction of the common electrode line CL3 may also be changed according to the needs and/or effects. The main body MB1 may include a stem (e.g., where a film layer of the pixel electrode PE1 or PE2 is present, as in fig. 1) or a main slit (e.g., where a film layer of the pixel electrode PE1 or PE2 is not present). In other embodiments, the first pixel electrode PE1 and the second pixel electrode PE2 may further include another body MB2 respectively, the first pixel electrode PE1 and the second pixel electrode PE2 may be divided into at least an upper region and a lower region, the another body MB2 and the body MB1 are interlaced (or crossed, for example, intercale), and the another body MB2 may be located at the boundary of the slits of the first pixel electrode PE1 and the second pixel electrode PE2 in different extending directions respectively. The other main body MB2 may include a stem (e.g., where there is a film layer of the pixel electrode PE1 or PE2, as in fig. 1) or a main slit (e.g., where there is no film layer of the pixel electrode PE1 or PE 2). In other embodiments, at least one of the first pixel electrode PE1 and the second pixel electrode PE2 may not include a plurality of slits SLi having different extending directions, but only include at least one of the body MB1 and the other body MB2 or neither of the slits SLi, the body MB1 and the other body MB 2.

In some embodiments, each sub-pixel PX1, PX2 may include a first switching element TFT1 or a second switching element TFT 2. The first switching element TFT1 is electrically connected to a corresponding one of the first signal lines (e.g., the data line DL) and a corresponding one of the pixel electrodes (e.g., the first pixel electrode PE 1). The first switching element TFT1 includes a gate electrode G1, a semiconductor layer SM1, a source electrode S1, and a drain electrode D1. In some embodiments, the gate G1 is electrically connected to a corresponding one of the second signal lines (e.g., the scan line SL), the source S1 is electrically connected to a corresponding one of the first signal lines (e.g., the data line DL), and the drain D1 is electrically connected to a corresponding one of the pixel electrodes (e.g., the first pixel electrode PE1) through the contact hole C1. At least a portion of the semiconductor layer SM1 is positioned between the gate electrode G1 and the source and drain electrodes S1 and D1.

The second switching element TFT2 is electrically connected to the other corresponding pixel electrode (e.g., the second pixel electrode PE 2). The second switching element TFT2 includes a gate electrode G2, a semiconductor layer SM2, a source electrode S2, and a drain electrode D2. In some embodiments, the gate G2 is electrically connected to a corresponding one of the second signal lines (e.g., the scan line SL), the source S2 is electrically connected to a corresponding one of the first signal lines (e.g., the data line DL), and the drain D2 is electrically connected to a corresponding one of the pixel electrodes (e.g., the second pixel electrode PE2) through the contact hole C2. At least a portion of the semiconductor layer SM2 is located between the gate G2 and the source S2 and the drain D2. Preferably, the source S1 of the first switching element TFT1 connected to the first pixel electrode PE1 and the source S2 of the second switching element TFT2 connected to the second pixel electrode PE2 are connected to one of the same first signal lines (e.g., the data line DL), and the gate G2 of the second switching element TFT2 connected to the gate G1 of the first switching element TFT1 connected to the first pixel electrode PE1 and the second pixel electrode PE2 are connected to one of the same second signal lines (e.g., the scan line SL), which can improve the aperture ratio and the related electrical property of the sub-pixels PX1 and PX2, but is not limited thereto. In other embodiments, the source S1 of the first switching element TFT1 connected to the first pixel electrode PE1 and the source S2 of the second switching element TFT2 connected to the second pixel electrode PE2 may be respectively connected to different first signal lines (e.g., the data line DL), and the gate G2 of the second switching element TFT2 connected to the first pixel electrode PE1 and the gate G1 of the first switching element TFT1 and the second pixel electrode PE2 may be respectively connected to the same second signal line (e.g., the scan line SL) or may be respectively connected to different second signal lines (e.g., the scan line SL), or the source S1 of the first switching element TFT1 connected to the first pixel electrode PE1 and the source S2 of the second switching element TFT2 connected to the second pixel electrode PE2 may be respectively connected to the same first signal line (e.g., the data line DL), and the gate S639 of the first switching element TFT 68628 and the second switching element TFT G1 connected to the second pixel electrode PE 8653 may be respectively connected to the gate G8653 of the first switching element TFT1 and the gate G2 Respectively connected to different second signal lines (e.g., scan lines SL). In some embodiments, if each of the sub-pixels PX1, PX2 may include a first switching element TFT1 and a second switching element TFT2, the first switching element TFT1 and the corresponding line and the second switching element TFT2 and the corresponding line may refer to the foregoing description. However, the source S2 of the second switching element TFT2 may be electrically connected with the source S1 of the first switching TFT 1; and the gate G2 of the second switching element TFT2 may be electrically connected to the gate G1 of the first switching TFT 1. For example, the gate G2 of the second switching element TFT2 and the gate G1 of the first switch are electrically connected to the corresponding second signal line (e.g., the scan line SL), and the source S1 of the first switching element TFT1 is electrically connected to the corresponding first signal line (e.g., the data line DL) through the source S2 of the second switching element TFT2, but not limited thereto.

In other embodiments, if each of the sub-pixels PX1 and PX2 optionally further includes a sharing element ST including a gate SG, a semiconductor layer SSM, a source SS and a drain SD. The source SS is electrically connected to the corresponding pixel electrode (e.g., the first pixel electrode PE1) through the contact window C1, and the source SS of the sharing element ST is electrically connected to the drain D1 of the first switching element TFT 1. The drain SD of the sharing element ST is electrically connected to the common electrode line CL 3. The gate SG of the sharing element ST is electrically connected to the corresponding scan line SL. At least a portion of the semiconductor layer SSM is located between the gate SG and the source SS and drain SD. In the present embodiment, the first pixel electrode PE1 is a sub-pixel electrode; the second pixel electrode PE2 is a main pixel electrode, but the invention is not limited thereto. In other embodiments, when the source SS of the sharing element ST is electrically connected to the second pixel electrode PE2, the first pixel electrode PE1 is a main pixel electrode, and the second pixel electrode PE2 is a sub-pixel electrode.

At least one of the first switching element TFT1, the second switching element TFT2, and the sharing element ST may be a bottom gate transistor, a top gate transistor, a stereo transistor, or other suitable transistors. The grid of the bottom grid transistor is positioned below the semiconductor layer, the grid of the top grid transistor is positioned above the semiconductor layer, and the channel of the semiconductor layer of the three-dimensional transistor is not extended and positioned on a plane. The semiconductor layer may be a single layer or a multi-layer structure, and the material thereof includes amorphous silicon, microcrystalline silicon, nanocrystalline silicon, polycrystalline silicon, single crystal silicon, an organic semiconductor material, an oxide semiconductor material, carbon nanotubes/rods, or other suitable materials, or a combination of the foregoing.

As shown in fig. 2, the color conversion layers CF1 and CF2 are respectively located on two adjacent sub-pixels PX1 and PX2, for example, the color conversion layer CF1 is located on the sub-pixel PX1, and the color conversion layer CF2 is located on the sub-pixel PX 2. In some embodiments, the color of the color conversion layer CF1 (alternatively referred to as the second color conversion layer) is different from the color of the color conversion layer CF2 (alternatively referred to as the first color conversion layer). In some embodiments, the color conversion layers CF1, CF2 may be color filters, such as color photoresists, organic layers mixed with quantum dots or quantum rods, or films mixed with quantum dots or quantum rods or other films suitable for color conversion. In some embodiments, the boundaries BL between the color conversion layer CF1 and the color conversion layer CF2 are in contact with each other and preferably do not overlap with each other, so that the display effect of the following sub-pixels (such as PX1 and PX2) can be improved, but not limited thereto.

Referring to fig. 1 and fig. 2, one of the first signal lines (e.g., the data line DL) between two adjacent sub-pixels PX1, PX2 has a main body 104 and at least two first protrusions 106, a portion of the main body 104 and the first protrusions 106 define a space 110 having an opening 108, and one of the second signal lines (e.g., the scan line SL) extends through the opening 108 and across the portion of the space 110 to intersect (or cross) with a portion of the main body 104. In the present embodiment, at least two first protrusions 106 are adjacent to a region where one of the second signal lines (e.g., the scan line SL) and one of the first signal lines (e.g., the data line DL) are crossed. In other embodiments, at least two first protrusions 106 may also be disposed in a region where one of the second signal lines (e.g., the common electrode line CL1 or the common electrode line CL2) crosses one of the first signal lines (e.g., the data line DL), so that one of the second signal lines (e.g., the common electrode line CL1 or the common electrode line CL2) may extend through the partial space 110 via the opening 108 to cross a portion of the main body portion 104 of one of the first signal lines (e.g., the data line DL).

As shown in FIG. 2, color conversion layer CF2 has second protrusions 112 that overlap at least a portion of first protrusions 106 and at least a portion of spaces 110, and color conversion layer CF1 has recesses 114 that correspond to second protrusions 112. As such, in the case where the color conversion layer CF1 and the color conversion layer CF2 are adjacent to each other and partially overlap with the main body 104, the boundary BL between the color conversion layer CF1 and the color conversion layer CF2 does not cover one of the second signal lines (e.g., the scan line SL) and one of the first signal lines (e.g., the data line DL) disposed in different layers (e.g., fig. 3), and the gate insulating layer GI may be disposed between one of the second signal lines (e.g., the scan line SL) and one of the first signal lines (e.g., the data line DL), so that the boundary BL between the adjacent color conversion layer CF1 and the color conversion layer CF2 can realize a substantially flat surface. Referring to fig. 2 and fig. 3, in the present embodiment, the boundary BL between two adjacent color conversion layers CF1 and CF2 covers only a single conductive layer, for example, the boundary BL between two adjacent color conversion layers CF1 and CF2 covers only one of the second signal lines (e.g., the scan line SL) or one of the first signal lines (e.g., the data line DL). In some embodiments, the first protrusion 106 of one of the first signal lines (e.g., the data line DL) supports a portion of the second protrusion 112 of the color conversion layer CF2, so that the surface of the color conversion layer CF2 located on a portion of the main body portion 104 and a portion of the first protrusion 106 can be more planar. In other embodiments, recess 114 of color conversion layer CF1 overlaps a portion of first protrusion 106 and at least a portion of opening 108, so that the surface of color conversion layer CF1 that is located over a portion of first protrusion 106 can be more planar.

In some embodiments, the first protrusion 106 of one of the first signal lines (e.g., the data line DL) does not overlap with one of the second signal lines (e.g., the scan line SL) extending over the space 110, but the invention is not limited thereto. In other embodiments, when the first protrusion 106 of one of the first signal lines (e.g., the data line DL) is disposed adjacent to a region where one of the second signal lines (e.g., the common electrode line CL1 or the common electrode line CL2) crosses over one of the first signal lines (e.g., the data line DL), the first protrusion 106 does not overlap with one of the second signal lines (e.g., the common electrode line CL1 or the common electrode line CL2) extending over the space 110. In other embodiments, the extending directions of the first signal line and the second signal line in the foregoing embodiments may be interchanged.

In summary, in the display panel of the above embodiment, the main body portion and the first protrusion portion of one of the first signal lines define an open space, and one of the second signal lines extends through a part of the open space and crosses a part of the main body portion, and one of the two adjacent color conversion layers has a second protrusion portion overlapping at least a part of the first protrusion portion and at least a part of the space; and the other of the two adjacent color conversion layers has a recess corresponding to the second protrusion. In this way, when the partial boundaries of the two adjacent color conversion layers are respectively overlapped on the partial main body portions, the boundaries of the two adjacent color conversion layers do not simultaneously cover the metal layers arranged on different film layers, so that the substantially flat surface is realized at the boundaries of the two adjacent color conversion layers.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A display panel, comprising:

a substrate;

at least two first signal lines and at least two second signal lines arranged on the substrate, wherein the first signal lines and the second signal lines are staggered;

at least two adjacent sub-pixels arranged on the substrate and electrically connected with one of the corresponding first signal lines and one of the corresponding second signal lines,

wherein one of the first signal lines between the two adjacent sub-pixels has a main body portion and at least two first protruding portions, a space having an opening is defined by a portion of the main body portion and the first protruding portions, and one of the second signal lines extends through the opening to partially cross the main body portion; and

a first color conversion layer and a second color conversion layer respectively located on the two adjacent sub-pixels, wherein the adjacent part of the boundary of the first color conversion layer and the second color conversion layer are respectively overlapped on part of the main body part, the first color conversion layer has a second protrusion overlapped on at least one part of the first protrusions and at least one part of the space, the second color conversion layer has a recess corresponding to the second protrusion, and the color of the first color conversion layer is different from the color of the second color conversion layer.

2. The display panel of claim 1, wherein the first protrusions support the second protrusions of the first color conversion layer such that a surface of the first color conversion layer on a portion of the main body and a portion of the first protrusions is flat.

3. The display panel of claim 1, wherein the first protruding portions do not overlap with one of the second signal lines extending across the space.

4. The display panel of claim 1, wherein the boundaries of the first color conversion layer adjacent to the second color conversion layer are touching and do not overlap.

5. The display panel of claim 1, wherein the first color conversion layer and the second color conversion layer are color filter layers respectively.

6. The display panel of claim 1, wherein the recess overlaps a portion of the first protrusions and at least a portion of the opening.

7. The display panel of claim 1, wherein the first signal lines comprise a data line.

8. The display panel of claim 1, wherein the second signal line comprises one of a scan line or a common electrode line.

9. The display panel of claim 8, wherein the two adjacent sub-pixels respectively have at least one main pixel and at least one sub-pixel.

10. The display panel of claim 9, wherein the sub-pixel is electrically connected to the main pixel and one of the first signal lines via at least one transistor.