CN108281348A - The root cavity wall angle adjusting method and T-type grid preparation method of T-type litho pattern - Google Patents
The root cavity wall angle adjusting method and T-type grid preparation method of T-type litho pattern Download PDFInfo
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- CN108281348A CN108281348A CN201810079573.6A CN201810079573A CN108281348A CN 108281348 A CN108281348 A CN 108281348A CN 201810079573 A CN201810079573 A CN 201810079573A CN 108281348 A CN108281348 A CN 108281348A
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- litho pattern
- grid
- type
- cavity wall
- wall angle
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000002360 preparation method Methods 0.000 title description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention relates to technical field of manufacturing semiconductors, and in particular to a kind of root cavity wall angle adjusting method of T-type litho pattern, T-type litho pattern includes grid foot litho pattern and grid cover litho pattern, which is characterized in that is included the following steps：The root cavity wall that grid foot litho pattern and/or grid cover litho pattern are bombarded using plasma degumming machine, it is 85~100 degree to make the root cavity wall angle of grid foot litho pattern and/or grid cover litho pattern.The application can effectively reduce the parasitic capacitance of T-type grid, to increase the working frequency of device.
Description
Technical field
The invention belongs to technical field of manufacturing semiconductors, and in particular to a kind of root cavity wall angle tune of T-type litho pattern
Adjusting method and T-type grid preparation method.
Background technology
HEMT device in MMICs, maximum operating frequency fmaxIt is the frequency that gain is reduced to 1, it is mainly long by grid
Degree, mutual conductance and tube core parasitic parameter (such as gate resistance Rg, capacitance C) determine.HEMT gate pole needed for the MMICs of common Ka wave bands
Length is 0.15 micron, which can lead to section severe decrease, quickly increase so as to cause gate resistance Rg, and gate resistance Rg's is fast
Speed increases the maximum operating frequency f for seriously limiting the transistormax, and grid is affected in high-output power, high leakage current
Under reliability.To ensure the high working frequency and high reliability of HEMT device, generally use grid length is short, section is big, resistance is low
T-type grid, but TXing Shan lower layers cavity can cause cavity wall angle between 60~80 degree in hot deformation step, which makes
It is big at the increased amplitudes of parasitic capacitance C, to reduce maximum operation frequency fmax。
Invention content
The purpose of the present invention is to provide a kind of root cavity wall angle adjusting method of T-type litho pattern, this method can be with
Root cavity wall angle is increased to 85~100 degree, makes to reduce using the T-type grid parasitic capacitance that this method is made, maximum work
Working frequency increases.
To reach above-mentioned requirements, the technical solution adopted by the present invention is that：A kind of root cavity wall angle of T-type litho pattern is provided
Method of adjustment is spent, T-type litho pattern includes grid foot litho pattern and grid cover litho pattern, is included the following steps：Utilize plasma
Resist remover bombards the root cavity wall of grid foot litho pattern and/or grid cover litho pattern, and it is 85~100 degree to make root cavity wall angle.
Preferably, the pressure of plasma degumming machine is 1~10Torr, and power is 50~250W, and bombardment time is 20~60
Second, in the cavity using oxygen and plasma rf from top to bottom by the way of carry out.
Compared with prior art, the present invention has the following advantages：
(1) the root cavity wall for using plasma degumming machine bombardment grid foot litho pattern and/or grid cover litho pattern, removes chamber
The part photoresist of wall makes root cavity wall angle increase to 85~100 degree, makes have arc using the T-type grid that this method is formed
Shape can effectively reduce the parasitic capacitance of T-type grid, to increase the working frequency of device；
(2) use low-voltage vacuum ion resist remover, compared to general high voltage vacuum (<600mTorr) plasma degumming machine,
The mean free path of low-voltage vacuum is smaller, increases the space between gas molecule, is conducive to the angle for adjusting root wall.
Description of the drawings
Attached drawing described herein is used for providing further understanding of the present application, constitutes part of this application, at this
Same or analogous part, the illustrative embodiments and their description of the application are indicated using identical reference label in a little attached drawings
For explaining the application, the improper restriction to the application is not constituted.In the accompanying drawings：
Fig. 1 (a) is the structure chart of existing T-type grid litho pattern；
Fig. 1 (b) is the structure chart that the application adjusts T-type grid litho pattern after cavity wall angle；
Fig. 2 (a) is the T-type grid structure figure formed using existing T-type grid litho pattern；
Fig. 2 (b) is the T-type grid structure figure formed using the T-type grid litho pattern after adjustment cavity wall angle.
Specific implementation mode
To keep the purpose, technical scheme and advantage of the application clearer, below in conjunction with drawings and the specific embodiments, to this
Application is described in further detail.For the sake of simplicity, it is omitted that well known to a person skilled in the art certain skills in being described below
Art feature.
The present embodiment provides a kind of root cavity wall angle adjusting methods of T-type litho pattern, before this method starts, first
Exposure, development form T-type litho pattern, and as shown in Figure 1a, T-type litho pattern includes grid foot litho pattern and grid cover photoetching figure
The root cavity wall angle of shape, grid foot litho pattern is A1, and after carrying out hot deformation step, A1 is usually 60~80 degree.This method
The root cavity wall of grid foot litho pattern and/or grid cover litho pattern, the pressure of plasma degumming machine are bombarded using plasma degumming machine
It is 1~10Torr by force, power is 50~250W, and bombardment time is 20~60 seconds, and uses oxygen and plasma in the cavity
The mode of radio frequency from top to bottom carries out.In this step, the part photoresist of plasma degumming machine removal root cavity wall, makes grid foot
The root of litho pattern and grid cover litho pattern is formed to be passed through as shown in Figure 1 b towards the arcuate structure of photoresist inner recess
Pressure, power and the bombardment time for controlling plasma degumming machine, it is 85~100 degree that can make the angle of root cavity wall；
Is evaporated by grid metal and is removed for T-type litho pattern after adjustment angle and forms T-type grid, as Fig. 2 b are formed for the application
T-type grid, it is seen that the root of its grid foot and grid cover all has arc protrusion, which can effectively reduce parasitic capacitance.
From working frequency FtIt is found that after parasitic capacitance Cgs reductions, the working frequency of device is carried=gm/ { * 2 π of rg* (Cgs+Cgd) }
It is high.Not carrying out wall angle, to adjust the T-type grid to be formed as shown in Figure 2 a, does not have arc and protrudes.
Above example only indicates the several embodiments of the present invention, the description thereof is more specific and detailed, but can not manage
Solution is limitation of the scope of the invention.It should be pointed out that for those of ordinary skill in the art, not departing from this hair
Under the premise of bright design, various modifications and improvements can be made, these belong to the scope of the present invention.Therefore the present invention
Protection domain should be subject to claim.
Claims (2)
1. a kind of root cavity wall angle adjusting method of T-type litho pattern, the T-type litho pattern include grid foot litho pattern and
Grid cover litho pattern, which is characterized in that include the following steps：Grid foot litho pattern and/or grid are bombarded using plasma degumming machine
The root cavity wall of cap litho pattern, it is 85~100 to make the root cavity wall angle of grid foot litho pattern and/or grid cover litho pattern
Degree.
2. the root cavity wall angle adjusting method of T-type litho pattern according to claim 1, which is characterized in that described etc.
The pressure of ion resist remover is 1~10Torr, and power is 50~250W, and bombardment time is 20~60 seconds, uses oxygen in the cavity
The mode of gas and plasma rf from top to bottom carries out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810079573.6A CN108281348A (en) | 2018-01-26 | 2018-01-26 | The root cavity wall angle adjusting method and T-type grid preparation method of T-type litho pattern |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810079573.6A CN108281348A (en) | 2018-01-26 | 2018-01-26 | The root cavity wall angle adjusting method and T-type grid preparation method of T-type litho pattern |
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| Publication Number | Publication Date |
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| CN108281348A true CN108281348A (en) | 2018-07-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810079573.6A Pending CN108281348A (en) | 2018-01-26 | 2018-01-26 | The root cavity wall angle adjusting method and T-type grid preparation method of T-type litho pattern |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103247526A (en) * | 2013-05-08 | 2013-08-14 | 中国电子科技集团公司第五十五研究所 | Method for gate dielectric etching suitable for submicro gate length semiconductor device production |
| US20140054598A1 (en) * | 2012-08-27 | 2014-02-27 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing semiconductor device |
| CN104882373A (en) * | 2015-04-24 | 2015-09-02 | 石以瑄 | Method for manufacturing transistor T-shaped gate |
-
2018
- 2018-01-26 CN CN201810079573.6A patent/CN108281348A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140054598A1 (en) * | 2012-08-27 | 2014-02-27 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing semiconductor device |
| CN103247526A (en) * | 2013-05-08 | 2013-08-14 | 中国电子科技集团公司第五十五研究所 | Method for gate dielectric etching suitable for submicro gate length semiconductor device production |
| CN104882373A (en) * | 2015-04-24 | 2015-09-02 | 石以瑄 | Method for manufacturing transistor T-shaped gate |
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Application publication date: 20180713 |
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