CN108269808A - SONOS devices and its manufacturing method - Google Patents
SONOS devices and its manufacturing method Download PDFInfo
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- CN108269808A CN108269808A CN201810024869.8A CN201810024869A CN108269808A CN 108269808 A CN108269808 A CN 108269808A CN 201810024869 A CN201810024869 A CN 201810024869A CN 108269808 A CN108269808 A CN 108269808A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The invention discloses a kind of SONOS devices, the first grid structure of the selecting pipe of storage unit is formed in shallow trench, and the second side of first grid structure is formed with the second grid structure of storage tube and the second channel region of bottom；Include only two source and drain injection regions in the both sides of the first and second gate structures, storage unit can be made in 1.5T type structures, so as to reduce the area of device.The first polysilicon gate and the second polysilicon gate of first grid structure no overlap in machine and transverse direction, the electric leakage between the first and second polysilicon gates can be reduced, reduce device power consumption, improve the reliability of device, the quality requirement of the insulating layer between the first and second polysilicon gates is reduced, interfering with each other between the first and second polysilicon gates can be prevented.The invention also discloses a kind of manufacturing methods of SONOS devices.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, more particularly to a kind of SONOS devices；The invention further relates to
A kind of SONOS devices and its manufacturing method.
Background technology
SONOS (Silicon-Oxide-Nitride- with low operating voltage, better COMS processing compatibilities
Oxide-Silicon) non-volatility memorizer is widely used in various embedded electronic products such as financial IC card, automotive electronics etc.
Using.At present close memory cellular construction by a complete storage tube and complete selecting pipe (select-gate,
SG) composition 2 transistor arrangements (2transistors, 2T) i.e. 2T types SONOS non-volatility memorizers, each transistor has had
Whole source electrode, drain and gate, and two transistors share one layer of polysilicon.It is deposited in depletion type SONOS non-volatility memorizers
The threshold voltage (Vt) of pipe is stored up less than 0, the Vt of selecting pipe is still greater than 0,2T depletion type SONOS non-volatility memorizers since its is low
Power consumption has obtained the favor of many low-power consumption applications.But 2T structures it is inherent the shortcomings that be exactly its larger chip area damage
Consumption.
As shown in Figure 1, be the memory cell structure figure of existing 2T depletion types SONOS non-volatility memorizers, including：
The storage tube 301 and selecting pipe 302 being formed on P-type semiconductor substrate such as silicon substrate 9；
The gate structure of storage tube 301 includes ONO layer and polysilicon gate 1, and ONO layer is by oxide layer (O) 6, nitration case (N) 5
It is formed with oxide layer (O) 4, composition oxide layer 6 is commonly referred to as tunnel oxide, and for storing charge tunnelling, nitration case 5 is conduct
Accumulation layer, oxide layer 4 are commonly referred to as barrier layer oxide layer.
The gate structure of selecting pipe 302 includes gate oxide 7 and polysilicon gate 1a.In general, polysilicon gate 1a and polysilicon
Grid 1 are formed simultaneously.Side wall, side wall generally use oxide layer or nitration case composition are also formed in the side of polysilicon gate 1 and 1a,
Side wall includes 3-tier architecture in Fig. 1, is followed successively by oxide layer 21, nitration case 22 and oxide layer 23.
The channel region of storage tube 301 includes N-type injection region 10, and N-type injection region 10 makes channel region for n-type doping, so as to make
It is depletion type structure to obtain storage tube 301.
In Fig. 1 the channel region of selecting pipe 302 doping directly using P-type semiconductor substrate 9 doping, can also individually into
Row p type impurity is modulated, the Enhanced Configuration that selecting pipe 302 is made to be more than 0V for threshold voltage.
N-type lightly-doped source drain region (LDD) 11 and N-type heavy doping are formed in the both sides autoregistration of polysilicon gate 1 and 1a
Source-drain area 8, in Fig. 1, LDD11 and source-drain area 8 between polysilicon gate 1 and 1a are shared as storage tube 301 and selecting pipe 302
Doped structure.
As shown in Figure 1 it is found that include between two polysilicon gates 1 and 1a in 2T structures shared doped region, that is, LDD11 and
Source-drain area 8, this causes there is larger spacing between polysilicon gate 1 and 1a, so as to occupy larger area, brings larger
Chip area is lost.Compared with 2T structures, chip area smaller that the structure of 1.5T occupies, existing 1.5T types SONOS is non-volatile
There are two types of property memory is general：
In the structure of the first, both greater than zero V of the Vt of storage tube and selecting pipe (select-gate (SG)), this feelings
Selecting pipe and storage tube are strictly that can share same raceway groove under condition, but since the Vt of storage tube is more than zero V, during read operation
A higher positive voltage must be terminated in the grid (gate) of storage tube, then its power consumption is higher.Low-power consumption 2T SONOS are non-
Volatile storage is as a result of 2T depletion type SONOS non-volatile memory structures, during read operation, the gate of storage tube
Zero potential i.e. readable data is connect, because the Vt of erase status is less than 0, the Vt of programming state is more than 0, i.e. Vte<0&Vtp>0,
Vte is the threshold voltage of erase status, and Vtp is the threshold voltage of programming state.
In second of structure, storage tube is less than the depletion type storage tube of 0V using Vt；Selecting pipe is using Vt more than 0V's
Enhanced selecting pipe, this 1.5T types SONOS non-volatility memorizers are SONOS devices.As shown in Fig. 2, it is existing SONOS devices
The memory cell structure figure of part；Difference part with structure shown in Fig. 1 is 1 He of polysilicon gate of the storage unit 201 in Fig. 2
It is isolated between 1a by side wall, the side wall in Fig. 2 between polysilicon gate 1 and 1a is made of oxide layer 24 and nitration case 25.Polycrystalline
The surface of P-type semiconductor substrate 9 between Si-gate 1 and 1a is no longer formed with LDD11 and source-drain area 8.At the top of polysilicon gate 1
It is formed with oxide layer 3.Nitration case 26 and oxide layer 27 are also formed in the two sides of polysilicon gate 1, in the remote of polysilicon gate 1a
The side of side from polysilicon gate 1 is formed with oxide layer 24a, silicon nitride 26 and oxide layer 27.In Fig. 2, a source is saved
Needed between the source-drain area 8 of drain region 8, polysilicon gate 1a and 1 both sides a part of raceway groove by being covered by polysilicon gate 1a and by
The raceway groove that a part of channels in series that polysilicon gate 1 covers is formed is connected, so do not need to again between polysilicon gate 1 and 1a
Additionally a source-drain area 8 is being set, structure shown in Fig. 2 is also known as 1.5T types.Saving a source-drain area 8 can be so that polysilicon
Spacing between grid 1 and 1a becomes very little.But from shown in Fig. 2 it is found that since polysilicon gate 1 carries out the channel region of bottom
It controls and the channel region of bottom is controlled in the threshold voltage and polysilicon gate 1a of surface formation raceway groove and is formed on surface
The threshold voltage of raceway groove is different, therefore the doped structure of the channel region corresponding with 1a bottoms of polysilicon gate 1 can be different, in Fig. 2, polycrystalline
The channel region of 1 bottom of Si-gate is made of N-type injection region 10, in this way can be so that the 1 corresponding threshold value of polysilicon gate of unprogrammed state
Voltage is less than 0V；And the channel region of polysilicon gate 1a bottoms is made of p type island region, is directly made of in Fig. 2 P-type semiconductor substrate 9,
Therefore the corresponding threshold voltages of polysilicon gate 1a are more than 0V.
As shown in figure 3, it is the array junctions composition of existing SONOS devices shown in Fig. 2；4 storage units are shown in Fig. 3
201, it is represented respectively with Cell A, Cell B, Cell C and Cell D, enables the source-drain area abutted with the polysilicon gate 1a of selecting pipe
8 be the first source-drain area, enables and the source-drain area 8 of the polysilicon gate 1 of storage tube adjoining is the second source-drain area, then as seen from Figure 3：
Second source-drain area of each storage unit 201 in same row is all connected to the bit line (BL) of respective column, is shown in Fig. 3
Two bit lines, are represented respectively with BL1 and BL2.
Polysilicon gate 1a with each storage unit 201 of a line is all connected to corresponding storage wordline (WLS) of mutually going together, figure
Two storage wordline WLS are shown in 3, are represented respectively with WLS1 and WLS2；With the polysilicon gate of each storage unit 201 of a line
1 is all connected to corresponding selection wordline (WL) of mutually going together, and two selection wordline are shown in Fig. 3, are represented respectively with WL1 and WL2；
The first source-drain area with each storage unit 201 of a line is all connected to the source line SL of corresponding row.
The P-type semiconductor substrate 9 of all storage units 201 is all connected to underlayer electrode line VBPW.
Table one
Being programmed (Program), wiping (Erase) and being read for for (Read) operation to the Cell A in Fig. 3
The voltage that bright memory cell structure shown in Fig. 2 is born in various working conditions, programming, erasing and read voltage value according to
The bias fashion of table one is configured, and for Cell A in programming, storage wordline WLS adds 7.2V, selects word it can be seen from table one
Line WL adds -4.5V, can finally form the voltage difference of 11.7V between polysilicon gate 1 and 1a in this way.And as shown in Figure 2 it is found that more
Crystal silicon grid 1 and 1a is adjacent in the horizontal and side is longitudinally overlapping and between polysilicon gate 1 and 1a by by oxide layer 24 and nitridation
The side wall isolation of 25 composition of layer, the spacer material that the voltage difference of 11.7V is isolated between composition polysilicon gate 1 and 1a propose very
High requirement, prolonged high voltage can degenerate the performance of device, influence the reliability of device.In addition, polysilicon shown in Fig. 2
The back to back structure of grid 1 and 1a compositions is also easy to so that easily generating electric leakage between polysilicon gate 1 and 1a and existing mutually relevant
The defects of disturbing, these can all influence the Performance And Reliability of device.
Invention content
The technical problems to be solved by the invention are to provide a kind of SONOS devices, can reduce the more of selecting pipe and storage tube
Electric leakage between crystal silicon grid avoids interfering with each other between selecting pipe and the polysilicon gate of storage tube, avoids selecting pipe and storage
The degeneration of insulating layer between the polysilicon gate of pipe improves the reliability of device.For this purpose, the present invention also provides a kind of SONOS devices
The manufacturing method of part.
In order to solve the above technical problems, the storage unit of the memory block of SONOS devices provided by the invention is deposited including one
Storage pipe and a selecting pipe.
The first grid structure of the selecting pipe includes：Be formed in the second conductive type semiconductor substrate surface first is shallow
Groove is formed in the first gate dielectric layer of the first shallow trench side and bottom surface, is filled in and is formed with the first grid
The first polysilicon gate in first shallow trench of dielectric layer is formed with first medium in first polycrystalline silicon gate surface
Layer.
First channel region of the selecting pipe is by being located at the side of first shallow trench and bottom surface and by described
The Semiconductor substrate composition of one polysilicon gate covering, first channel region are in enhancement type channel structure.
The semiconductor substrate surface in first the first side of shallow trench of the first grid structure is formed with by first
Second channel region of conduction type lightly doped district composition, second channel region are in deplection type channel structure.
The second grid structure of the storage tube, the second grid structure are formed at the top of second channel region
ONO layer and the second polysilicon gate including being sequentially formed in the second channel region surface, the ONO layer are by being sequentially formed in
The three-decker that second oxide layer, third nitration case and the 4th oxide layer on the second channel region surface form.
It is heavily doped that the first conduction type is formed in the semiconductor substrate surface of the second side of first polysilicon gate
The first miscellaneous source and drain injection region；The semiconductor substrate surface in the first side of second polysilicon gate is formed with first and leads
Second source and drain injection region of electric type heavy doping；The second side of the first source and drain injection region and first polysilicon gate is from right
It is accurate；The second source and drain injection region and the first side autoregistration of second polysilicon gate.
The first source and drain injection region and the second source and drain injection region pass through first channel region and second ditch
Road area is connected and the storage unit is made to be in 1.5T type structures.
The isolation of no overlap in machine and transverse direction is formed between first polysilicon gate and second polysilicon gate
Structure to reduce the electric leakage between first polysilicon gate and second polysilicon gate, reduces the power consumption of device and carries
The reliability of high device.
A further improvement is that each storage unit of the memory block of the SONOS devices is arranged in array structure, battle array
Array structure is：
The adjacent storage unit shares same first source and drain injection region in same row, adjacent institute in same row
That states storage unit shares same second source and drain injection region.
Second source and drain injection region of each storage unit in same row is all connected to identical bit line.
The first source and drain injection region with each storage unit in a line is all connected to identical source line.
The first polysilicon gate with each storage unit in a line is all connected to identical selection wordline.
The second polysilicon gate with each storage unit in a line is all connected to identical storage wordline.
A further improvement is that the SONOS devices further include logic area, CMOS logic is formed in the logic area
Pipe.
A further improvement is that it isolates to form the active of CMOS logic pipe by shallow trench field oxygen in the logic area
Area, shallow trench field oxygen are filled in the second shallow trench, the institute of the second shallow trench and the memory block in the logic area
The corresponding first shallow trench processes structure of first grid structure for stating selecting pipe is identical.
A further improvement is that CMOS logic pipe includes NMOS tube and PMOS tube, the third grid of the CMOS logic pipe
Structure includes the second gate dielectric layer and third polysilicon gate, and second polysilicon gate and the third polysilicon gate are using identical
Technique be formed simultaneously.
A further improvement is that the first conduction type lightly doped drain is also superimposed in the first source and drain injection region,
The first conduction type lightly doped drain is also superimposed in the second source and drain injection region.
A further improvement is that it is formed with side wall in the side of second polysilicon gate.
A further improvement is that the storage tube and the selecting pipe are all N-type device, the first conduction type is N-type, the
Two conduction types are p-type；Alternatively, the storage tube and the selecting pipe be all for P-type device, the first conduction type is p-type, second
Conduction type is N-type.
In order to solve the above technical problems, in the manufacturing method of SONOS devices provided by the invention SONOS devices memory block
Storage unit include a storage tube and a selecting pipe, manufacturing step and include：
Step 1: providing one second conductive type semiconductor substrate, the first shallow ridges is formed in the semiconductor substrate surface
Slot.
Step 2: form the first gate dielectric layer in the side of first shallow trench and bottom surface.
Step 3: polysilicon is filled in first shallow trench forms the first polysilicon gate, in first polysilicon
The surface of grid forms first medium layer；By first shallow trench, first gate dielectric layer and the first polysilicon gate group
Into the first grid structure of the selecting pipe；First channel region of the selecting pipe by be located at first shallow trench side and
Bottom surface and the Semiconductor substrate composition covered by first polysilicon gate, first channel region is in enhanced ditch
Road structure.
Step 4: carrying out the first conduction type is lightly doped first shallow trench the of the ion implanting in the first grid structure
The semiconductor substrate surface of side forms the second channel region, and second channel region is in deplection type channel structure.
It is laminated Step 5: being formed in the semiconductor substrate surface by the second oxide layer, third nitration case and the 4th oxidation
Add the ONO layer to be formed, carrying out chemical wet etching to the ONO layer makes the ONO layer be only remained in the memory block.
Step 6: deposit forms the second polysilicon layer, the second polysilicon layer described in the logic area is superimposed upon described
The surface of ONO layer.
Step 7: carrying out chemical wet etching to second polysilicon layer in the memory block and the ONO layer forms institute
State the second grid structure of storage tube；The second grid structure includes being sequentially formed in the ONO on the second channel region surface
Layer and the second polysilicon gate, second polysilicon gate are made of second polysilicon layer after etching.
Step 8: the source and drain injection for carrying out the first conduction type heavy doping is formed simultaneously the first source and drain injection region and the second source
Drain implant, the first source and drain injection region are formed in the Semiconductor substrate table of the second side of first polysilicon gate
Face；The second source and drain injection region is formed in the semiconductor substrate surface of the first side of second polysilicon gate；It is described
First source and drain injection region and the second side autoregistration of first polysilicon gate；The second source and drain injection region and described more than second
First side autoregistration of crystal silicon grid.
The first source and drain injection region and the second source and drain injection region pass through first channel region and second ditch
Road area is connected and the storage unit is made to be in 1.5T type structures.
The isolation of no overlap in machine and transverse direction is formed between first polysilicon gate and second polysilicon gate
Structure to reduce the electric leakage between first polysilicon gate and second polysilicon gate, reduces the power consumption of device and carries
The reliability of high device.
A further improvement is that each storage unit of the memory block of the SONOS devices is arranged in array structure, battle array
Array structure is：
The adjacent storage unit shares same first source and drain injection region in same row, adjacent institute in same row
That states storage unit shares same second source and drain injection region.
Second source and drain injection region of each storage unit in same row is all connected to identical bit line.
The first source and drain injection region with each storage unit in a line is all connected to identical source line.
The first polysilicon gate with each storage unit in a line is all connected to identical selection wordline.
The second polysilicon gate with each storage unit in a line is all connected to identical storage wordline.
A further improvement is that the SONOS devices further include logic area, CMOS logic is formed in the logic area
Pipe.
A further improvement is that second is formed in the logic area while first shallow trench is formed in step 1
Shallow trench；Filling oxide layer forms shallow trench field oxygen in second shallow trench later, by the shallow trench field oxygen isolation
Active area in the logic area.
A further improvement is that CMOS logic pipe includes NMOS tube and PMOS tube；
To by after the ONO layer removal outside the memory block, being additionally included in the logic area and carrying out in step 5
The step of CMOS logic pipe corresponding threshold voltage adjustment injection and the semiconductor lining for being formed in the logic area
Bottom surface forms the step of the second gate dielectric layer.
Later, the second polysilicon layer described in step 6 is formed simultaneously second gate dielectric layer in the logic area
Surface.
Later, photoetching is carried out to the second polysilicon layer in the logic area and the second dielectric layer simultaneously in step 7
Etching forms the third gate structure of the CMOS logic pipe；The third gate structure of the CMOS logic pipe is included by described the
The structure that two gate dielectric layers and the third polysilicon gate are formed by stacking.
The injection of the first conduction type lightly doped drain is carried out a further improvement is that being further included before the source and drain injection of step 8
The step of forming the first conduction type lightly doped drain.
Later side wall is formed in the side of second polysilicon gate；
Later in the source and drain injection for carrying out step 8.
A further improvement is that the storage tube and the selecting pipe are all N-type device, the first conduction type is N-type, the
Two conduction types are p-type；Alternatively, the storage tube and the selecting pipe be all for P-type device, the first conduction type is p-type, second
Conduction type is N-type.
The first grid structure setting of selecting pipe is the structure being formed in shallow trench by the present invention, first grid structure pair
Semiconductor substrate covers the first channel region to be formed and the second channel region of storage tube and can link together and finally so that storage
Unit is in 1.5T type structures, so as to reduce the area of device.
In addition, the first grid structure with shallow trench of the present invention can realize the of the first grid structure of selecting pipe
All no overlap in machine and transverse direction between second polysilicon gate of the second grid structure of one polysilicon gate and storage tube so that
First polysilicon gate and the second polysilicon gate form good physical isolation and in the prior art between selecting pipe and storage tubes
It is that back-to-back structure is compared between polysilicon gate, the present invention can greatly reduce between the first polysilicon gate and the second polysilicon gate
Electric leakage, so as to reduce the power consumption of device；In addition, due to being no overlap between the first polysilicon gate and the second polysilicon gate
Structure is physically isolated, therefore the first polysilicon caused by the high pressure between the first polysilicon gate and the second polysilicon gate can be avoided
The degeneration of isolated insulation layer between grid and the second polysilicon gate so as to improve the reliability of device, also reduces pair simultaneously
The quality requirement of isolated insulation layer between first polysilicon gate and the second polysilicon gate can simplify manufacturing process；In addition, first
Physical isolation structure between polysilicon gate and the second polysilicon gate for no overlap is also avoided that more than the first polysilicon gate and second
Interfering with each other between crystal silicon grid.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is the memory cell structure figure of existing 2T depletion types SONOS non-volatility memorizers；
Fig. 2 is the memory cell structure figure of existing SONOS devices；
Fig. 3 is the array junctions composition of existing SONOS devices shown in Fig. 2；
Fig. 4 is the memory cell structure figure of SONOS devices of the embodiment of the present invention；
Fig. 5 is the array junctions composition of the device of SONOS of the embodiment of the present invention shown in Fig. 4；
Fig. 6 A- Fig. 6 B are the memory cell structure figures in each step of the manufacturing method of SONOS devices of the embodiment of the present invention.
Specific embodiment
As shown in figure 4, it is 401 structure chart of storage unit of SONOS devices of the embodiment of the present invention；Fig. 5 is this hair shown in Fig. 4
The array junctions composition of bright embodiment SONOS devices；The storage unit 401 of the memory block of SONOS devices of the embodiment of the present invention includes
One storage tube and a selecting pipe.
The first grid structure of the selecting pipe includes：It is formed in the second conductive type semiconductor substrate such as silicon substrate 101
First shallow trench on surface is formed in the first gate dielectric layer such as gate oxide of the first shallow trench side and bottom surface
102, the first polysilicon gate 103 being filled in first shallow trench for being formed with first gate dielectric layer 102, described
First polysilicon gate, 103 surface is formed with first medium layer 104.First medium layer 104 can be used to first polysilicon gate
103 surface carries out the oxide layer of thermal oxide formation.
First channel region of the selecting pipe is by being located at the side of first shallow trench and bottom surface and by described
The Semiconductor substrate 101 of one polysilicon gate 103 covering forms, and first channel region is in enhancement type channel structure.
It is formed on 101 surface of the Semiconductor substrate of first the first side of shallow trench of the first grid structure by
Second channel region 105 of one conduction type lightly doped district composition, second channel region 105 are in deplection type channel structure.
The second grid structure of the storage tube, the second grid are formed at the top of second channel region 105
Structure includes being sequentially formed in the ONO layer on 105 surface of the second channel region and the second polysilicon gate 111, the ONO layer are served as reasons
It is sequentially formed in the second oxide layer 108,109 and the 4th 110 groups of the oxide layer of third nitration case on 105 surface of the second channel region
Into three-decker.
The first conductive-type is formed on 101 surface of the Semiconductor substrate of the second side of first polysilicon gate 103
First source and drain injection region 107a of type heavy doping；The Semiconductor substrate 101 in the first side of second polysilicon gate 111
Surface is formed with the second source and drain injection region 107b of the first conduction type heavy doping；The first source and drain injection region 107a and described
First side autoregistration of the first polysilicon gate 103；The of the second source and drain injection region 107b and second polysilicon gate 111
Side autoregistration.
The first source and drain injection region 107a and the second source and drain injection region 107b pass through first channel region and institute
The second channel region 105 is stated to be connected and the storage unit 401 is made to be in 1.5T type structures.
No overlap in machine and transverse direction is formed between first polysilicon gate 103 and second polysilicon gate 111
Isolation structure, to reduce the electric leakage between first polysilicon gate 103 and second polysilicon gate 111, reduce device
The power consumption of part and the reliability for improving device.
Each storage unit 401 of the memory block of the SONOS devices is arranged in array structure, as shown in figure 5, Fig. 5
In show 4 storage units 401, represent that array structure is with Cell A, Cell B, Cell C and Cell D respectively：
The adjacent storage unit 401 shares same first source and drain injection region 107a in same row, in same row
The adjacent storage unit 401 shares same second source and drain injection region 107b.
Second source and drain injection region 107b of each storage unit 401 in same row is all connected to identical bit line, Fig. 5
In show two bit lines, respectively BL1 and BL2.
The first source and drain injection region 107a with each storage unit 401 in a line is all connected to identical source line SL.
The first polysilicon gate 103 with each storage unit 401 in a line is all connected to identical selection wordline, figure
Two selection wordline are shown in 5, are represented respectively with WL1 and WL2.
The second polysilicon gate 111 with each storage unit 401 in a line is all connected to identical storage wordline, figure
Two storage wordline WLS are shown in 5, are represented respectively with WLS1 and WLS2.
The SONOS devices further include logic area, and CMOS logic pipe is formed in the logic area.
The active area to form CMOS logic pipe, shallow trench field oxygen are isolated in the logic area by shallow trench field oxygen
It is filled in the second shallow trench, the first grid of the selecting pipe of the second shallow trench and the memory block in the logic area
The corresponding first shallow trench processes structure of structure is identical.
CMOS logic pipe includes NMOS tube and PMOS tube, and the third gate structure of the CMOS logic pipe is situated between including second gate
Matter layer and third polysilicon gate, second polysilicon gate 111 and the third polysilicon gate are using identical technique while shape
Into.
The first conduction type lightly doped drain 106 is also superimposed in the first source and drain injection region 107a, described
The first conduction type lightly doped drain 106 is also superimposed in two source and drain injection region 107b.
It is formed with side wall in the side of second polysilicon gate 111, in Fig. 4, the side of second polysilicon gate 111
Side wall include oxide layer 112a, silicon nitride 112b and oxide layer 112c.
In the embodiment of the present invention, the storage tube and the selecting pipe are all N-type device, and the first conduction type is N-type, the
Two conduction types are p-type.Also can be in other embodiments：The storage tube and the selecting pipe are all P-type device, and first leads
Electric type is p-type, and the second conduction type is N-type.
The bias fashion of programming, erasing and the read operation of SONOS devices of the embodiment of the present invention can also be set according to table one
It puts, when storage unit 401 programs, the height of 11.7V can be also generated between the first polysilicon gate 103 and the second polysilicon gate 111
Voltage difference.But due between the first polysilicon gate 103 and the second polysilicon gate 111 of the embodiment of the present invention in longitudinal direction and horizontal
Upward all no overlaps so that the first polysilicon gate 103 and the second polysilicon gate 111 form good physical isolation and existing skill
It is that back-to-back structure is compared between polysilicon gate in art between selecting pipe and storage tube, the embodiment of the present invention can greatly reduce
Electric leakage between first polysilicon gate 103 and the second polysilicon gate 111, so as to reduce the power consumption of device；In addition, due to first
Between 103 and second polysilicon gate 111 of polysilicon gate it is the physical isolation structure of no overlap, therefore the first polysilicon gate can be avoided
103 and the second high pressure between polysilicon gate 111 caused by the first polysilicon gate 103 and the second polysilicon gate 111 between
The degeneration of isolated insulation layer so as to improve the reliability of device, is also reduced to the first polysilicon gate more than 103 and second simultaneously
The quality requirement of isolated insulation layer between crystal silicon grid 111 can simplify manufacturing process；In addition, the first polysilicon gate 103 and second
Physical isolation structure between polysilicon gate 111 for no overlap is also avoided that the first polysilicon gate 103 and the second polysilicon gate 111
Between interfere with each other.
As shown in Fig. 6 A to Fig. 6 B, be SONOS devices of the embodiment of the present invention manufacturing method each step in storage list
Meta structure figure, the storage unit 401 of the memory block of SONOS devices includes in the manufacturing method of SONOS devices of the embodiment of the present invention
One storage tube and a selecting pipe, manufacturing step include：
Step 1: as shown in Figure 6A, one second conductive type semiconductor substrate 101 is provided, in the Semiconductor substrate 101
Surface forms the first shallow trench.
Step 2: as shown in Figure 6A, the first gate dielectric layer is formed in the side of first shallow trench and bottom surface
102。
Step 3: as shown in Figure 6A, polysilicon the first polysilicon gate 103 of formation is filled in first shallow trench,
The surface of first polysilicon gate 103 forms first medium layer 104；By first shallow trench, first gate dielectric layer
102 and first polysilicon gate 103 form the first grid structure of the selecting pipe；First channel region of the selecting pipe by
Positioned at the side of first shallow trench and bottom surface and the Semiconductor substrate that is covered by first polysilicon gate 103
101 compositions, first channel region are in enhancement type channel structure.
Step 4: it as shown in Figure 6A, carries out the first conduction type and ion implanting is lightly doped in the first grid structure
101 surface of the Semiconductor substrate of first the first side of shallow trench forms the second channel region 105, and second channel region 105 is in
Deplection type channel structure.
Step 5: it as shown in Figure 6B, is formed on 101 surface of Semiconductor substrate and is nitrogenized by the second oxide layer 108, third
The ONO layer that 109 and the 4th superposition of oxide layer 110 of layer is formed, carrying out chemical wet etching to the ONO layer makes the ONO layer only retain
In the memory block.
Step 6: as shown in Figure 6B, deposit forms the second polysilicon layer, the second polysilicon layer described in the logic area
It is superimposed upon the surface of the ONO layer.
Step 7: as shown in Figure 6B, photoetching is carried out to second polysilicon layer in the memory block and the ONO layer
Etching forms the second grid structure of the storage tube；The second grid structure includes being sequentially formed in second channel region
The ONO layer on 105 surfaces and the second polysilicon gate 111, second polysilicon gate 111 is by second polysilicon layer after etching
Composition.
Step 8: as shown in figure 4, the source and drain injection for carrying out the first conduction type heavy doping is formed simultaneously the injection of the first source and drain
Area 107a and the second source and drain injection region 107b, the first source and drain injection region 107a are formed in first polysilicon gate 103
101 surface of the Semiconductor substrate of the second side；The second source and drain injection region 107b is formed in second polysilicon gate 111
The first side 101 surface of the Semiconductor substrate；The first source and drain injection region 107a and first polysilicon gate 103
First side autoregistration；The first side autoregistration of the second source and drain injection region 107b and second polysilicon gate 111.
The first source and drain injection region 107a and the second source and drain injection region 107b pass through first channel region and institute
The second channel region 105 is stated to be connected and the storage unit 401 is made to be in 1.5T type structures.
No overlap in machine and transverse direction is formed between first polysilicon gate 103 and second polysilicon gate 111
Isolation structure, to reduce the electric leakage between first polysilicon gate 103 and second polysilicon gate 111, reduce device
The power consumption of part and the reliability for improving device.
In present invention method, the SONOS devices further include logic area, and CMOS is formed in the logic area
Logic pipe.
The second shallow trench is formed while first shallow trench is formed in step 1 in the logic area；Later in institute
It states filling oxide layer in the second shallow trench and forms shallow trench field oxygen, by having in the shallow trench field oxygen isolation logic area
Source region.
CMOS logic pipe includes NMOS tube and PMOS tube；
To by after the ONO layer removal outside the memory block, being additionally included in the logic area and carrying out in step 5
The step of CMOS logic pipe corresponding threshold voltage adjustment injection and the semiconductor lining for being formed in the logic area
101 surface of bottom forms the step of the second gate dielectric layer.
Second polysilicon layer described in step 6 is formed simultaneously the table of second gate dielectric layer in the logic area
Face.
Later, photoetching is carried out to the second polysilicon layer in the logic area and the second dielectric layer simultaneously in step 7
Etching forms the third gate structure of the CMOS logic pipe；The third gate structure of the CMOS logic pipe is included by described the
The structure that two gate dielectric layers and the third polysilicon gate are formed by stacking.
The first conduction type lightly doped drain of progress is further included before the source and drain injection of step 8 to inject to form the first conductive-type
The step of type lightly doped drain 106.
Later side wall is formed in the side of second polysilicon gate 111；In Fig. 4, the side of second polysilicon gate 111
The side wall in face includes oxide layer 112a, silicon nitride 112b and oxide layer 112c.
Later in the source and drain injection for carrying out step 8.
In the embodiment of the present invention, the storage tube and the selecting pipe are all N-type device, and the first conduction type is N-type, the
Two conduction types are p-type.Also can be in other embodiments：The storage tube and the selecting pipe are all P-type device, and first leads
Electric type is p-type, and the second conduction type is N-type.
The present invention has been described in detail through specific embodiments, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these also should
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of SONOS devices, which is characterized in that the storage unit of the memory block of SONOS devices includes a storage tube and one
A selecting pipe；
The first grid structure of the selecting pipe includes：It is formed in the first shallow ridges of the second conductive type semiconductor substrate surface
Slot is formed in the first gate dielectric layer of the first shallow trench side and bottom surface, is filled in and is formed with first grid Jie
The first polysilicon gate in first shallow trench of matter layer is formed with first medium layer in first polycrystalline silicon gate surface；
First channel region of the selecting pipe is by being located at the side of first shallow trench and bottom surface and by more than described first
The Semiconductor substrate composition of crystal silicon grid covering, first channel region are in enhancement type channel structure；
The semiconductor substrate surface in first the first side of shallow trench of the first grid structure is formed with by the first conduction
Second channel region of type lightly doped district composition, second channel region are in deplection type channel structure；
The second grid structure of the storage tube is formed at the top of second channel region, the second grid structure includes
The ONO layer and the second polysilicon gate on the second channel region surface are sequentially formed in, the ONO layer is described by being sequentially formed in
The three-decker that second oxide layer, third nitration case and the 4th oxide layer on the second channel region surface form；
The first conduction type heavy doping is formed in the semiconductor substrate surface of the second side of first polysilicon gate
First source and drain injection region；The semiconductor substrate surface in the first side of second polysilicon gate is formed with the first conductive-type
Second source and drain injection region of type heavy doping；The first source and drain injection region and the second side autoregistration of first polysilicon gate；
The second source and drain injection region and the first side autoregistration of second polysilicon gate；
The first source and drain injection region and the second source and drain injection region pass through first channel region and second channel region
It is connected and the storage unit is made to be in 1.5T type structures；
The isolation structure of no overlap in machine and transverse direction is formed between first polysilicon gate and second polysilicon gate,
Reducing the electric leakage between first polysilicon gate and second polysilicon gate, reducing the power consumption of device and improving device
Reliability.
2. SONOS devices as described in claim 1, it is characterised in that：Each storage of the memory block of the SONOS devices
Unit is arranged in array structure, and array structure is：
The adjacent storage unit shares same first source and drain injection region in same row, adjacent in same row described to deposit
Storage unit shares same second source and drain injection region；
Second source and drain injection region of each storage unit in same row is all connected to identical bit line；
The first source and drain injection region with each storage unit in a line is all connected to identical source line；
The first polysilicon gate with each storage unit in a line is all connected to identical selection wordline；
The second polysilicon gate with each storage unit in a line is all connected to identical storage wordline.
3. SONOS devices as described in claim 1, it is characterised in that：The SONOS devices further include logic area, described
CMOS logic pipe is formed in logic area.
4. SONOS devices as claimed in claim 3, it is characterised in that：It is isolated in the logic area by shallow trench field oxygen
The active area of CMOS logic pipe is formed, shallow trench field oxygen is filled in the second shallow trench, and second in the logic area is shallow
Corresponding first shallow trench processes structure is identical with the first grid structure of the selecting pipe of the memory block for groove.
5. SONOS devices as claimed in claim 3, it is characterised in that：CMOS logic pipe includes NMOS tube and PMOS tube, described
The third gate structure of CMOS logic pipe includes the second gate dielectric layer and third polysilicon gate, second polysilicon gate and described
Third polysilicon gate is formed simultaneously using identical technique.
6. SONOS devices as described in claim 1, it is characterised in that：Is also superimposed in the first source and drain injection region
One conduction type lightly doped drain is also superimposed with the first conduction type lightly doped drain in the second source and drain injection region.
7. SONOS devices as described in claim 1, it is characterised in that：Side is formed in the side of second polysilicon gate
Wall.
8. the SONOS devices as described in claim 1 to 7 any claim, it is characterised in that：The storage tube and the choosing
Guan Douwei N-type devices are selected, the first conduction type is N-type, and the second conduction type is p-type；Alternatively, the storage tube and the selection
Guan Douwei P-type devices, the first conduction type are p-type, and the second conduction type is N-type.
9. a kind of manufacturing method of SONOS devices, which is characterized in that the storage unit of the memory block of SONOS devices includes one
Storage tube and a selecting pipe, manufacturing step include：
Step 1: providing one second conductive type semiconductor substrate, the first shallow trench is formed in the semiconductor substrate surface；
Step 2: form the first gate dielectric layer in the side of first shallow trench and bottom surface；
Step 3: polysilicon is filled in first shallow trench forms the first polysilicon gate, in first polysilicon gate
Surface forms first medium layer；Institute is formed by first shallow trench, first gate dielectric layer and first polysilicon gate
State the first grid structure of selecting pipe；First channel region of the selecting pipe is by being located at the side and bottom of first shallow trench
Surface and the Semiconductor substrate composition covered by first polysilicon gate, first channel region is in enhancement type channel knot
Structure；
Step 4: carrying out the first conduction type is lightly doped ion implanting in first the first side of shallow trench of the first grid structure
The semiconductor substrate surface formed the second channel region, second channel region be in deplection type channel structure；
Shape is superimposed by the second oxide layer, third nitration case and the 4th oxide layer Step 5: being formed in the semiconductor substrate surface
Into ONO layer, to the ONO layer carry out chemical wet etching the ONO layer is made to be only remained in the memory block；
Step 6: deposit forms the second polysilicon layer, the second polysilicon layer described in the logic area is superimposed upon the ONO layer
Surface；
Step 7: carrying out chemical wet etching to second polysilicon layer in the memory block and the ONO layer forms described deposit
Store up the second grid structure of pipe；The second grid structure include be sequentially formed in the second channel region surface ONO layer and
Second polysilicon gate, second polysilicon gate are made of second polysilicon layer after etching；
Step 8: the source and drain injection for carrying out the first conduction type heavy doping is formed simultaneously the first source and drain injection region and the second source and drain note
Enter area, the first source and drain injection region is formed in the semiconductor substrate surface of the second side of first polysilicon gate；Institute
State the semiconductor substrate surface that the second source and drain injection region is formed in the first side of second polysilicon gate；First source
The second side autoregistration of drain implant and first polysilicon gate；The second source and drain injection region and second polysilicon gate
The first side autoregistration；
The first source and drain injection region and the second source and drain injection region pass through first channel region and second channel region
It is connected and the storage unit is made to be in 1.5T type structures；
The isolation structure of no overlap in machine and transverse direction is formed between first polysilicon gate and second polysilicon gate,
Reducing the electric leakage between first polysilicon gate and second polysilicon gate, reducing the power consumption of device and improving device
Reliability.
10. the manufacturing method of SONOS devices as claimed in claim 9, it is characterised in that：The memory block of the SONOS devices
Each storage unit be arranged in array structure, array structure is：
The adjacent storage unit shares same first source and drain injection region in same row, adjacent in same row described to deposit
Storage unit shares same second source and drain injection region；
Second source and drain injection region of each storage unit in same row is all connected to identical bit line；
The first source and drain injection region with each storage unit in a line is all connected to identical source line；
The first polysilicon gate with each storage unit in a line is all connected to identical selection wordline；
The second polysilicon gate with each storage unit in a line is all connected to identical storage wordline.
11. the manufacturing method of SONOS devices as claimed in claim 9, it is characterised in that：The SONOS devices, which further include, patrols
Area is collected, CMOS logic pipe is formed in the logic area.
12. the manufacturing method of SONOS devices as claimed in claim 11, it is characterised in that：Described first is formed in step 1
The second shallow trench is formed while shallow trench in the logic area；Filling oxide layer is formed in second shallow trench later
Shallow trench field oxygen, by the active area in the shallow trench field oxygen isolation logic area.
13. the manufacturing method of SONOS devices as claimed in claim 12, it is characterised in that：CMOS logic pipe includes NMOS tube
And PMOS tube；
To by after the ONO layer removal outside the memory block, being additionally included in the logic area described in carrying out in step 5
The step of corresponding threshold voltage adjustment of CMOS logic pipe is injected and the Semiconductor substrate table for being formed in the logic area
Face forms the step of the second gate dielectric layer；
Later, the second polysilicon layer described in step 6 is formed simultaneously the table of second gate dielectric layer in the logic area
Face；
Later, chemical wet etching is carried out to the second polysilicon layer in the logic area and the second dielectric layer simultaneously in step 7
Form the third gate structure of the CMOS logic pipe；The third gate structure of the CMOS logic pipe is included by the second gate
The structure that dielectric layer and the third polysilicon gate are formed by stacking.
14. the manufacturing method of SONOS devices as claimed in claim 9, it is characterised in that：
It is further included before the source and drain injection of step 8 and carries out the first conduction type lightly doped drain and inject that form the first conduction type light
The step of doped drain；
Later side wall is formed in the side of second polysilicon gate；
Later in the source and drain injection for carrying out step 8.
15. the manufacturing method of the SONOS devices as described in claim 9 to 14 any claim, it is characterised in that：It is described to deposit
Selecting pipe described in Chu Guanhe is all N-type device, and the first conduction type is N-type, and the second conduction type is p-type；Alternatively, the storage
Pipe and the selecting pipe are all P-type device, and the first conduction type is p-type, and the second conduction type is N-type.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109119422A (en) * | 2018-08-28 | 2019-01-01 | 上海华虹宏力半导体制造有限公司 | 1.5-T SONOS device making technics method |
| TWI699876B (en) * | 2018-09-07 | 2020-07-21 | 日商東芝記憶體股份有限公司 | Semiconductor device and manufacturing method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040183124A1 (en) * | 2003-03-20 | 2004-09-23 | Powerchip Semiconductor Corp. | Flash memory device with selective gate within a substrate and method of fabricating the same |
| CN1540762A (en) * | 2003-01-02 | 2004-10-27 | ǰѶϵͳ�ɷ�����˾ | Flash memory possessing groove type selection grid and manufacturing method |
| US20080057647A1 (en) * | 2005-04-12 | 2008-03-06 | International Business Machines Corporation | Structure and method of fabricating high-density, trench-based non-volatile random access sonos memory cells for soc applications |
| CN103022041A (en) * | 2011-09-22 | 2013-04-03 | 上海华虹Nec电子有限公司 | SONOS (silicon-oxide-nitride-oxide-silicon) non-volatile memory |
| US20150311217A1 (en) * | 2014-04-28 | 2015-10-29 | Micron Technology, Inc. | Ferroelectric memory and methods of forming the same |
| US20160276354A1 (en) * | 2014-07-14 | 2016-09-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Salicided structure to integrate a flash memory device with a high k, metal gate logic device |
| CN107527917A (en) * | 2017-08-31 | 2017-12-29 | 上海华虹宏力半导体制造有限公司 | 1.5T depletion type SONOS non-volatility memorizers and its manufacture method |
-
2018
- 2018-01-11 CN CN201810024869.8A patent/CN108269808B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540762A (en) * | 2003-01-02 | 2004-10-27 | ǰѶϵͳ�ɷ�����˾ | Flash memory possessing groove type selection grid and manufacturing method |
| US20040183124A1 (en) * | 2003-03-20 | 2004-09-23 | Powerchip Semiconductor Corp. | Flash memory device with selective gate within a substrate and method of fabricating the same |
| US20080057647A1 (en) * | 2005-04-12 | 2008-03-06 | International Business Machines Corporation | Structure and method of fabricating high-density, trench-based non-volatile random access sonos memory cells for soc applications |
| CN103022041A (en) * | 2011-09-22 | 2013-04-03 | 上海华虹Nec电子有限公司 | SONOS (silicon-oxide-nitride-oxide-silicon) non-volatile memory |
| US20150311217A1 (en) * | 2014-04-28 | 2015-10-29 | Micron Technology, Inc. | Ferroelectric memory and methods of forming the same |
| US20160276354A1 (en) * | 2014-07-14 | 2016-09-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Salicided structure to integrate a flash memory device with a high k, metal gate logic device |
| CN107527917A (en) * | 2017-08-31 | 2017-12-29 | 上海华虹宏力半导体制造有限公司 | 1.5T depletion type SONOS non-volatility memorizers and its manufacture method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109119422A (en) * | 2018-08-28 | 2019-01-01 | 上海华虹宏力半导体制造有限公司 | 1.5-T SONOS device making technics method |
| CN109119422B (en) * | 2018-08-28 | 2020-08-07 | 上海华虹宏力半导体制造有限公司 | Manufacturing process method of 1.5-T SONOS device |
| TWI699876B (en) * | 2018-09-07 | 2020-07-21 | 日商東芝記憶體股份有限公司 | Semiconductor device and manufacturing method thereof |
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