CN108268693B - Method and system for dividing power-ground cell group - Google Patents
Method and system for dividing power-ground cell group Download PDFInfo
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- CN108268693B CN108268693B CN201711242514.8A CN201711242514A CN108268693B CN 108268693 B CN108268693 B CN 108268693B CN 201711242514 A CN201711242514 A CN 201711242514A CN 108268693 B CN108268693 B CN 108268693B
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Abstract
A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method comprises the following steps: forming a first split group by selecting at least one intra-boundary power-ground cell from a group of power-ground cells; adding at least one out-of-boundary power-ground cell of the power-ground cell group to the first split group; forming a second split group by selecting remaining intra-boundary power-ground cells and remaining extra-boundary power-ground cells in the power-ground cell group; calculating the total area of the power-ground cells in the boundary of the first division group; calculating the total area of the power-ground cells outside the boundary in the first partition group; calculating the total area of the power-ground cells in the boundary of the second division group; calculating the total area of the power-ground cells outside the boundary in the second partition group; and calculating a difference between a total area of power-ground cells within a boundary in a first split set and a total area of power-ground cells outside the boundary in the first split set.
Description
Technical Field
The embodiment of the invention relates to a block level design method of a heterogeneous power supply-ground cell.
Background
With the rapid development of mobile devices, internet of things (internet of things) ("IoT"), and system on a chip ("SoC"), the need for low power silicon chips has increased significantly. The internet of things is a network interconnection (internet) to physical devices, vehicles (also referred to as "connected devices" and "smart devices"), buildings and other items that are embedded with electronic equipment, software, sensors, actuators and network connections (network connectivity) that enable them to collect and exchange information. A system chip is an integrated circuit (integrated circuit) ("IC") that integrates all components of a computer or other electronic system into a single chip. The system-on-chip may contain digital functions (digital functions), analog functions (analog functions), mixed-signal functions (mixed-signal functions), and radio frequency functions (radio frequency function) all on a single chip substrate. System chips are widely implemented in mobile electronic devices and in the internet of things due to their low power consumption characteristics.
Advances in integrated circuit fabrication processes have resulted in system-on-chip designs having ever-increasing complexity and functionality that consume more power. In order to prolong battery life, reduce overall system cost, and increase market competitiveness, low power chip designs are required for mobile devices and internet of things devices.
This demand for low power chip design requires that the design tool communicate low power design parameters in a single standard format to achieve low power design efficiency. In the power domain of low power design parameters, power-ground ("PG") networks and connectivity are determinants of chip efficiency. As discussed herein, cells having power-ground bars are referred to as power-ground cells (PG cells).
Disclosure of Invention
A method of partitioning a group of power-ground (PG) cells, the method comprising: forming a first split group by selecting at least one intra-boundary power-ground cell from the group of power-ground cells; adding at least one out-of-boundary power-ground cell of the power-ground cell group into the first split group; and forming a second split group by selecting remaining intra-boundary power-ground cells and remaining out-of-boundary power-ground cells in the power-ground cell group.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not drawn to scale in accordance with standard practices in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 illustrates a layout design of two out-of-boundary power-ground cells and one in-boundary power-ground cell forming a heterogeneous power-ground cell structure, according to some embodiments.
FIG. 2 is a block diagram of a circuit design hierarchy in accordance with some embodiments.
FIG. 3 is a block diagram illustrating a design methodology for a heterogeneous power-ground cell structure in accordance with some embodiments.
Fig. 4 is a schematic diagram of a division of a heterogeneous power-ground cell structure, according to some embodiments.
Fig. 5 is a schematic diagram of the legalization of heterogeneous power-ground cell structures according to some embodiments.
Fig. 6 is a schematic diagram of an optimization process of a heterogeneous power-ground cell structure, according to some embodiments.
Fig. 7 is a schematic diagram of a process for placing heterogeneous power-ground cell structures in compliance with a front end rule (front end rule) in accordance with some embodiments.
Fig. 8 is a schematic diagram of a process for filler insertion for a heterogeneous power-ground cell structure based on a voltage threshold rule (VT-rule) in accordance with some embodiments.
Description of the reference numerals
100: cell/first-edge external power-ground cell
101: power bar/first power bar/VDD power bar
102: power bar/second power bar/VSS power bar
200: cell/second boundary external power-ground cell
201: power bar/first power bar/VSS power bar
202: power strip/second power strip
203: power strip/third power strip/VSS power strip
250. 350: cell boundary
300: cell/intra-boundary power-ground cell
301: VDD power strip
302: VSS power strip
400: substrate and method for manufacturing the same
401. 402, 403: power rail
1000: layout/layout design
2000: system design hierarchy
2101: system and method for controlling a system
2201. 2202, 2203: circuit arrangement
2301. 2302 and 2303: block block
3000: design system
3101: in-boundary power-ground cell kit
3102: out-of-boundary power-ground cell tool kit
3103: design tool set
3200: application programming interface
3201: unit/plan view unit
3202: placement unit
3203: clock tree synthesis unit
3204: wiring unit
3205: cell/post-wiring cell
3300: geometry design system
3400: application programming interface unit based on heterogeneous power-ground structure
4100. 7200, 7300: plan view of a computer
4200. 4300, 4400, 4500: plan view/division set
5100. 6100, 7100: plan/initial plan
5101. 5102, 5103, 5201, 5202, 5203, 6101, 6102, 6103, 7101, 7103, 7105, 7110, 7111, 7112: out-of-boundary power-ground cell
5104. 5105, 5204, 5205, 6104, 6105, 6202: in-boundary power-ground cells 5106, 5107: fragments
5200: legalized plan view
7102. 7104, 7109: out-of-boundary power-ground/voltage cells
7106. 7107: power-ground cell/voltage cell within boundary
7108: cell/out-of-boundary power-ground cell/ultra-low threshold voltage out-of-boundary power-ground cell 7208: cell unit
8221. 8222, 8223, 8224, 8225: filling body
VDD: first power supply level
VSS: second power supply level
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. Such reuse is for brevity and clarity purposes and does not represent a relationship between the various embodiments and/or configurations discussed per se.
Further, for ease of description, spatially relative terms such as "below", "lower", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.
Fig. 1 illustrates a layout 1000 of two out-of-boundary power-ground cells and one in-boundary power-ground cell, according to some embodiments. According to some embodiments, the layout 1000 includes a first off-boundary power-ground cell 100, the first off-boundary power-ground cell 100 having a first power bar 101 providing a first power level VDD to the cell 100 and a second power bar 102 providing a second power level VSS to the cell 100. The first off-boundary power-ground cell 100 is located on top of the substrate 400 with the power bar 101 aligned with the power rail 402 and the power bar 102 aligned with the power rail 403 to achieve the proper power configuration. According to some embodiments, layout design 1000 further includes a second boundary outer power-ground cell 200, the second boundary outer power-ground cell 200 having a height approximately twice the height of cell 100. The second out-of-boundary power-ground cell 200 includes a first power rail 201 that provides the cell 200 with a second power level VSS, a second power rail 202 that provides the cell 200 with a first power level VDD, and a third power rail 203 that provides the second power level VSS. The second out-of-boundary power-ground cell 200 is also located on top of the substrate 400 and the power rails 201, 202, and 203 are aligned with the corresponding power rails 401, 402, and 403 to achieve the proper power configuration. Layout 1000 further includes an intra-boundary power-ground cell 300, the intra-boundary power-ground cell 300 including a VDD power rail 301 and a VSS power rail 302, the VDD power rail 301 and the VSS power rail 302 being aligned with corresponding power rails 402 and 403, respectively, for power management.
Cell 100 is an "out-of-boundary power-ground cell" in that VDD power rail 101 and VSS power rail 102 are not enclosed within cell boundary 150 of cell 100 as shown in fig. 1. Similarly, cell 200 is an "out-of-boundary power-ground cell" in that VSS power rail 201 and VSS power rail 203 are not enclosed within cell boundary 250. In contrast, cell 300 is an "intra-boundary power-ground cell" in that VDD power rail 301 and VSS power rail 302 are both enclosed within cell boundary 350 of cell 300. As shown in fig. 1, VDD power rail 101 of cell 100 and VDD power rail 301 of cell 300 are both aligned to power rail 402; similarly, the VSS power rail 102 of cell 100 and the VSS power rail 302 of cell 300 are aligned with power rail 403. Due to the fact that cell 100 is an out-of-boundary power-ground cell and cell 300 is an in-boundary power-ground cell, the height of cell 300 is greater than the height of cell 100. According to some embodiments, the intra-boundary power-ground cells have a greater height than the corresponding extra-boundary power-ground cells. For this reason, conventional design approaches fail to handle both intra-boundary power-ground cells and out-of-boundary power-ground cells in the same design block, as will be discussed further below in connection with fig. 2. According to some embodiments, both the out-of-boundary power-ground cells and the in-boundary power-ground cells are implemented in the same design block, thereby reducing the area required by the cells on the substrate.
FIG. 2 is a block diagram of a system design hierarchy in accordance with some embodiments. According to some embodiments, system design hierarchy 2000 includes a system 2101, system 2101 further including a plurality of circuits 2201, 2202, 2203, and the like. Each circuit also includes a plurality of blocks 2301, 2302, 2303, etc. According to some embodiments, one or more of the plurality of blocks includes both an intra-boundary power-ground cell structure and an out-of-boundary power-ground cell structure that optimize overall power efficiency and performance. In addition, blocks that include both intra-boundary power-ground cell structures and out-of-boundary power-ground cell structures minimize chip area.
FIG. 3 is a block diagram illustrating a design methodology for a heterogeneous power-ground cell structure in accordance with some embodiments. According to some embodiments, design system 3000 includes an intra-boundary power-ground cell tool set (in-boundary PG cell tool Kit) ("IBPG tool set (IBPG Kit)") 3101, an out-of-boundary power-ground cell tool set (out-boundary PG cell tool Kit) ("OBPG tool set (OBPG Kit)") 3102, and a design tool set 3103 for processing intra-boundary power-ground cells. According to some embodiments, the design system is an electronic design automation (Electronic Design Automation) ("EDA") tool. According to some embodiments, the electronic design automation tool is provided by the electronic design automation software (Cadence EDA software). According to some embodiments, design system 3000 also includes an application programming interface (application programming interface) ("API") 3200 and a geometry design system (geometry design system) ("GDS") 3300. According to some embodiments, the application programming interface 3200 includes a planogram unit 3201, a placement unit 3202, a clock tree synthesis (clock tree synthesis) ("CTS") unit 3203, a routing unit 3204, a post-routing unit 3205, and an application programming interface unit 3400 based on a heterogeneous power-ground structure, which will be described in further detail below.
According to some embodiments, the in-boundary power-ground tool suite 3101, the out-of-boundary power-ground tool suite 3102, and the design tool suite 3103 provide design parameters as inputs to the application programming interface 3200. Upon receiving this input data, the planogram unit 3201 groups or partitions the received circuit blocks into functional modules. Next, the placement unit 3202 places the modules in the layout according to the design rule. Next, the clock tree synthesizing unit 3203 synthesizes the clock tree to achieve an appropriate timing (clock) and clock (clock). After properly arranging the timing and clock, the wiring unit 3204 appropriately arranges the circuit wirings. Finally, the post-wiring unit 3205 performs post-wiring processing to achieve timing optimization. When the post-routing processing is complete, the file is saved in GDS format for further processing.
According to another embodiment, the units 3201-3205 are based on heterogeneous power-ground structures, meaning that during the design process, a single block can include both intra-boundary power-ground cells and extra-boundary power-ground cells to achieve improved performance and power efficiency.
According to some embodiments, the design system 3000 creates a circuit layout based on input data using an in-boundary power-ground tool set 3101, an out-of-boundary power-ground tool set 3102, a design tool set 3103, an application programming interface 3200, and a geometry design system 3300. For example, the input data includes information about the out-of-boundary power-ground cells, the in-boundary power-ground cells, and such relationship information between the out-of-boundary power-ground cells and the in-boundary power-ground cells. By using the in-boundary power-ground tool kit 3101, the out-of-boundary power-ground tool kit 3102, the design tool kit 3103, the application programming interface 3200, and the geometry design system 3300, the deployment of out-of-boundary power-ground cells and/or in-boundary power-ground cells is optimized to achieve maximum efficiency of power and routing. According to some embodiments, an integrated circuit is then fabricated based on a circuit layout that has been optimized by the systems and methods discussed above. The integrated circuit fabricated will thus achieve maximum efficiency of power and routing.
Fig. 4 is a schematic diagram of a split process of a heterogeneous power-ground cell structure, according to some embodiments. As a non-limiting example, assume that there are 200 intra-boundary power-ground cells and 200 out-of-boundary power-ground structures in the plan view 4100 provided to the plan view unit 3201 in fig. 3. The heterogeneous power-ground architecture based application programming interface unit 3400 performs partitioning to optimize power and performance and minimize consumed area. According to some embodiments, design system 3000 performs the following optimizations:
wherein A (IBPG) i A (OBPG) i Respectively representing the power-ground layout design area inside the boundary and the power-ground layout design area outside the boundary.
According to some embodiments, system 3000 is designed to maximize the area difference between the intra-boundary power-ground cells and the out-of-boundary power-ground cells. For example, the plan view 4100 is partitioned into plan views 4200 and 4300, wherein the plan view 4200 includes 100 intra-boundary power-ground cells and 100 out-of-boundary power-ground cells, and the plan view 4300 includes 100 intra-boundary power-ground cells and 100 out-of-boundary power-ground cells. The division into the plan view 4200+4300 results in no maximization of the area difference between the power-ground cells inside the boundary and the power-ground cells outside the boundary. As another example, the plan view 4100 is partitioned into plan views 4400 and 4500, wherein the plan view 4400 includes 20 intra-boundary power-ground cells and 180 out-of-boundary power-ground cells, and the plan view 4500 includes 180 intra-boundary power-ground cells and 20 out-of-boundary power-ground cells. The division into the plan view 4400+4500 results in a maximized area difference between the power-ground cells inside the boundary and the power-ground cells outside the boundary. In the split group 4200 and the split group 4300 having 100 intra-boundary power-ground cells and 100 extra-boundary power-ground cells, the difference between the intra-boundary power-ground cells and the extra-boundary power-ground cells is zero. In the divided groups 4400 and 4500, the difference between the intra-boundary power-ground cells and the out-of-boundary power-ground cells is 160.
Fig. 5 is a schematic diagram of a process of legalization of a heterogeneous power-ground cell structure in which an initial plan view 5100 is rearranged into a legalized plan view 5200, according to some embodiments. According to some embodiments, the plan view 5100 includes out-of-boundary power-ground cells 5101, 5102, 5103, and in-boundary power-ground cells 5104 and 5105. Because of the size difference between the intra-boundary power-ground cells and the extra-boundary power-ground cells, segments 5106 and 5107 exist between the intra-boundary power-ground cells and the extra-boundary power-ground cells. According to some embodiments, the optimization process in the heterogeneous power-ground architecture based application programming interface unit 3400 performs cell legitimization by minimizing the cell segments 5106 and 5107. According to some embodiments, for example, as shown on the right side of fig. 5, the boundary outer power-ground cells 5201, 5202, and 5203 are packaged together, with the corresponding power bars of the boundary outer power-ground cells 5201, 5202, and 5203 properly aligned with the power rails on the substrate as illustrated in fig. 1. Similarly, as shown on the right side of fig. 5, the intra-boundary power-ground cells 5204 and 5205 are packaged together, with the corresponding power bars of the intra-boundary power-ground cells 5204 and 5205 properly aligned with the power rails on the substrate as illustrated in fig. 1. In rearranged plan view 5200, segments 5106 and 5107 are removed. According to some embodiments, it is desirable to minimize the displacement of the power-ground cells and reduce or minimize the area required for the power-ground cells when rearranging the power-ground cells.
Fig. 6 is a schematic diagram of an optimization process of a heterogeneous power-ground cell structure, according to some embodiments. According to some embodiments, initial plan view 6100 includes boundary outer power-ground cells 6101, 6102, and 6103, with corresponding power bars of boundary outer power-ground cells 6101, 6102, and 6103 properly aligned with corresponding power bars of a substrate. The plan view 6100 also includes intra-boundary power-ground cells 6104 and 6105. According to some embodiments, to optimize the timing of the plan view and because there is a constraint that there is no space for changing small drive out-of-boundary power-ground cells to large drive out-of-boundary power-ground cells, changing out-of-boundary power-ground cells 6102 to in-boundary power-ground cells 6202 without introducing a shift, properly aligning their original power bars to the corresponding power bars optimizes the power efficiency and timing of the plan view. According to some embodiments, a small driving cell implies a small area cell, and vice versa.
Fig. 7 is a schematic diagram of a process for placing a heterogeneous power-ground cell structure in compliance with front-end rules, in accordance with some embodiments. According to some embodiments, the initial plan view 7100 includes out-of-boundary power-ground cells 7101, 7102, 7103, 7104, 7105, 7108, 7109, 7110, 7111, and 7112. The plan view 7100 also includes intra-boundary power-ground cells 7106 and 7107. According to some embodiments, voltage cells 7102, 7106, and 7109 are standard threshold voltage cells, voltage cells 7104 and 7107 are low threshold voltage cells, and the remaining voltage cells are ultra-low threshold voltage cells. According to some embodiments, the front-end rule (also referred to as the voltage threshold rule (voltage threshold rule) ("VT rule")) requires that a single cell occupying at least three sites have a minimum width. There are some fabrication constraints for the ion implantation region, referred to as minimum implantation region constraints (minimum implant area constraint). Each ion implantation region must have a certain minimum width according to the constraints. In addition, two ion implantation regions of the same type must be separated by a certain minimum spacing (spacing). To meet the front end rule, the ultra-low threshold voltage out-of-boundary power-ground cell 7108 is shifted right to become cell 7208 in plan view 7200, so that half row fills can be inserted to meet the voltage threshold minimum region rule. Additional half row fills will be added to fill the hollow space left by this movement, which will be discussed in detail in fig. 8 below. The filler is a virtual block for occupying a hollow space in the layout. According to some embodiments, shifting the location of the cells to meet the voltage threshold rules as discussed above may improve the power consumption and time characteristics of the resulting circuit.
Fig. 8 is a schematic diagram of a process for filler insertion within a heterogeneous power-ground cell structure, according to some embodiments. According to some embodiments, as discussed in fig. 7, cell 7108 is shifted to become cell 7208 in plan view 7200. In plan view 7300, half row fills 8221, 8222, 8223, 8224, and 8225 are inserted to meet the voltage threshold rule as discussed above.
According to some embodiments, a method of partitioning a power-ground cell group having at least one intra-boundary power-ground cell and at least one extra-boundary power-ground cell is disclosed. The method comprises the following steps: forming a first split group by selecting at least one intra-boundary power-ground cell from a group of power-ground cells; adding at least one out-of-boundary power-ground cell of the power-ground cell group to the first split group; and forming a second split group by selecting the remaining intra-boundary power-ground cells and the remaining extra-boundary power-ground cells in the power-ground cell group.
According to some embodiments, the method further comprises the steps of: the total area of the power-ground cells within the boundary in the first split set is calculated.
According to some embodiments, the method further comprises the steps of: the total area of the out-of-boundary power-ground cells in the first split set is calculated.
According to some embodiments, the method further comprises the steps of: the total area of the power-ground cells within the boundary in the second partition group is calculated.
According to some embodiments, the method further comprises the steps of: the total area of the out-of-boundary power-ground cells in the second split set is calculated.
According to some embodiments, the method further comprises the steps of: a difference between a total area of power-ground cells within a boundary in a first split set and a total area of power-ground cells outside the boundary in the first split set is calculated.
According to some embodiments, the method further comprises the steps of: the difference between the total area of the power-ground cells within the boundary in the second split set and the total area of the power-ground cells outside the boundary in the second split set is calculated.
According to some embodiments, the method further comprises the steps of: the difference between the total area of the intra-boundary power-ground cells in a first split set and the total area of the extra-boundary power-ground cells in the first split set is maximized by adjusting the number of intra-boundary power-ground cells in the first split set and the number of extra-boundary power-ground cells in the first split set.
According to some embodiments, the method further comprises the steps of: the difference between the total area of the intra-boundary power-ground cells in the second split set and the total area of the extra-boundary power-ground cells in the second split set is maximized by adjusting the number of intra-boundary power-ground cells in the second split set and the number of extra-boundary power-ground cells in the second split set.
According to some embodiments, a method of partitioning a power-ground cell group having at least one intra-boundary power-ground cell and at least one extra-boundary power-ground cell is disclosed. The method comprises the following steps: placing at least one out-of-boundary power-ground cell on a substrate, wherein a power rail of the at least one out-of-boundary power-ground cell is aligned with a corresponding power rail on the substrate; and placing at least one intra-border power-ground cell on a substrate, wherein a power rail of the at least one intra-border power-ground cell is aligned with a corresponding power rail on the substrate.
According to some embodiments, the method further comprises the steps of: the at least one out-of-boundary power-ground cell is maintained in its original position.
According to some embodiments, the method further comprises the steps of: the at least one intra-boundary power-ground cell is maintained in its original position.
According to some embodiments, the method further comprises the steps of: the at least one out-of-boundary power-ground cell is changed into an in-boundary power-ground cell by increasing the size of the at least one out-of-boundary power-ground cell to match the size of the in-boundary power-ground cell to form a new plan view.
According to some embodiments, the method further comprises the steps of: the timing of the new plan is optimized.
According to some embodiments, a circuit for partitioning a power-ground cell group having at least one intra-boundary power-ground (PG) cell and at least one extra-boundary power-ground cell is disclosed. The circuit comprises: an intra-boundary power-ground cell tool unit for processing intra-boundary power-ground cells; an off-boundary power-ground cell tool kit for processing off-boundary power-ground cells; a design unit for processing the ID design information; an application programming interface unit for interfacing with an application programming; and a geometry design unit for designing the geometry of the integrated circuit.
According to some embodiments, the application programming interface unit further comprises: a plan view unit for dividing the plurality of received circuit blocks into functional modules; a placement unit for processing integrated circuit placement according to design rules; a clock tree synthesis unit for synthesizing a clock tree to realize proper time sequence and clock; a wiring unit for arranging wirings; and a post-wiring unit for post-wiring processing to achieve timing optimization.
According to some embodiments, a system for partitioning a power-ground cell group of an Integrated Circuit (IC) having at least one intra-boundary power-ground (PG) cell and at least one out-of-boundary power-ground cell is disclosed, the system comprising: an intra-boundary power-ground cell tool unit configured to determine a location of at least one intra-boundary power-ground cell within the integrated circuit; an off-boundary power-ground cell kit configured to determine a location of at least one off-boundary power-ground cell within the integrated circuit; a design unit configured to determine whether the location of the at least one intra-boundary power-ground cell and the location of the at least one external-boundary power-ground cell satisfy a predetermined design rule; an application programming interface unit configured to accept input from a user; and a geometry design unit configured to determine a geometry feature of the integrated circuit based on the input from the user.
According to some embodiments, the application programming interface unit further comprises: and the plane diagram unit is used for dividing the plurality of received circuit blocks into functional modules.
According to some embodiments, the application programming interface unit further comprises: a placement unit for adjusting the position of the at least one intra-boundary power-ground cell and the position of the at least one out-of-boundary power-ground cell according to the predetermined design rule to optimize wiring and timing of the integrated circuit.
According to some embodiments, the application programming interface unit further comprises: and the clock tree synthesis unit is used for synthesizing a clock tree to provide optimized time sequence and clock for the integrated circuit.
According to some embodiments, the application programming interface unit further comprises: a wiring unit configured to arrange wirings of the integrated circuit according to the predetermined design rule.
According to some embodiments, the application programming interface unit further comprises: a post-routing unit for determining the integrated circuit component locations and any further adjustments of the routing to achieve timing optimization.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. A method of partitioning a group of power-ground cells, the method comprising:
forming a first split group by selecting at least one intra-boundary power-ground cell from the group of power-ground cells;
adding at least one out-of-boundary power-ground cell of the power-ground cell group into the first split group; and
a second split set is formed by selecting the remaining intra-boundary power-ground cells and the remaining extra-boundary power-ground cells in the power-ground cell group,
wherein the power-ground cells in the power-ground cell group are cells having a power bar and a ground bar, the at least one intra-boundary power-ground cell is a corresponding cell in which the power bar and the ground bar are both enclosed within the cell boundary of the corresponding cell, and the at least one out-of-boundary power-ground cell is a corresponding cell in which the power bar and the ground bar are not enclosed within the cell boundary of the corresponding cell.
2. The method as recited in claim 1, further comprising:
a total area of power-ground cells within the boundary in the first split set is calculated.
3. The method as recited in claim 2, further comprising:
the total area of the out-of-boundary power-ground cells in the first split set is calculated.
4. A method according to claim 3, further comprising:
and calculating the total area of the power-ground cells in the boundary in the second partition group.
5. The method as recited in claim 4, further comprising:
and calculating the total area of the power-ground cells outside the boundary in the second partition group.
6. The method as recited in claim 5, further comprising:
the difference between the total area of the intra-boundary power-ground cells in the first split set and the total area of the out-of-boundary power-ground cells in the first split set is calculated.
7. The method as recited in claim 6, further comprising:
the difference between the total area of the intra-boundary power-ground cells in the second split set and the total area of the out-of-boundary power-ground cells in the second split set is calculated.
8. The method as recited in claim 7, further comprising:
the difference between the total area of the intra-boundary power-ground cells in the first split set and the total area of the extra-boundary power-ground cells in the first split set is maximized by adjusting the number of intra-boundary power-ground cells in the first split set and the number of extra-boundary power-ground cells in the first split set.
9. The method as recited in claim 8, further comprising:
the difference between the total area of the intra-boundary power-ground cells in the second split set and the total area of the extra-boundary power-ground cells in the second split set is maximized by adjusting the number of intra-boundary power-ground cells in the second split set and the number of extra-boundary power-ground cells in the second split set.
10. A method of partitioning a power-ground cell group having at least one intra-boundary power-ground cell and at least one extra-boundary power-ground cell, the method comprising:
placing at least one out-of-boundary power-ground cell on a substrate, wherein a power rail of the at least one out-of-boundary power-ground cell is aligned with a corresponding power rail on the substrate; and
placing at least one intra-border power-ground cell on the substrate, wherein a power rail of the at least one intra-border power-ground cell is aligned with a corresponding power rail on the substrate,
wherein the power-ground cells in the power-ground cell group are cells having a power bar and a ground bar, the at least one intra-boundary power-ground cell is a corresponding cell in which the power bar and the ground bar are both enclosed within the cell boundary of the corresponding cell, and the at least one out-of-boundary power-ground cell is a corresponding cell in which the power bar and the ground bar are not enclosed within the cell boundary of the corresponding cell.
11. The method as recited in claim 10, further comprising:
the at least one out-of-boundary power-ground cell is maintained in its original position.
12. The method as recited in claim 11, further comprising:
the at least one intra-boundary power-ground cell is maintained in its original position.
13. The method as recited in claim 12, further comprising:
the at least one out-of-boundary power-ground cell is changed into an in-boundary power-ground cell by increasing the size of the at least one out-of-boundary power-ground cell to match the size of the in-boundary power-ground cell to form a new plan view.
14. The method as recited in claim 13, further comprising:
the timing of the new plan is optimized.
15. A system for partitioning a power-ground cell group of an integrated circuit having at least one intra-boundary power-ground cell and at least one extra-boundary power-ground cell, the system comprising:
an intra-boundary power-ground cell tool unit configured to determine a location of at least one intra-boundary power-ground cell within the integrated circuit;
an off-boundary power-ground cell kit configured to determine a location of at least one off-boundary power-ground cell within the integrated circuit;
a design unit configured to determine whether the location of the at least one intra-boundary power-ground cell and the location of the at least one external-boundary power-ground cell satisfy a predetermined design rule;
an application programming interface unit configured to accept input from a user; and
a geometry design unit configured to determine a geometry feature of the integrated circuit based on the input from the user,
wherein the power-ground cells in the power-ground cell group are cells having a power bar and a ground bar, the at least one intra-boundary power-ground cell is a corresponding cell in which the power bar and the ground bar are both enclosed within the cell boundary of the corresponding cell, and the at least one out-of-boundary power-ground cell is a corresponding cell in which the power bar and the ground bar are not enclosed within the cell boundary of the corresponding cell.
16. The system of claim 15, wherein the application programming interface unit further comprises:
and the plane diagram unit is used for dividing the plurality of received circuit blocks into functional modules.
17. The system of claim 15, wherein the application programming interface unit further comprises:
a placement unit for adjusting the position of the at least one intra-boundary power-ground cell and the position of the at least one out-of-boundary power-ground cell according to the predetermined design rule to optimize wiring and timing of the integrated circuit.
18. The system of claim 15, wherein the application programming interface unit further comprises:
and the clock tree synthesis unit is used for synthesizing a clock tree to provide optimized time sequence and clock for the integrated circuit.
19. The system of claim 15, wherein the application programming interface unit further comprises:
a wiring unit configured to arrange wirings of the integrated circuit according to the predetermined design rule.
20. The system of claim 15, wherein the application programming interface unit further comprises:
a post-routing unit for determining the integrated circuit component locations and any further adjustments of the routing to achieve timing optimization.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662434693P | 2016-12-15 | 2016-12-15 | |
| US62/434,693 | 2016-12-15 | ||
| US15/723,308 US10515175B2 (en) | 2016-12-15 | 2017-10-03 | Block-level design method for heterogeneous PG-structure cells |
| US15/723,308 | 2017-10-03 |
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| Publication Number | Publication Date |
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| CN108268693A CN108268693A (en) | 2018-07-10 |
| CN108268693B true CN108268693B (en) | 2023-09-01 |
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| CN201711242514.8A Active CN108268693B (en) | 2016-12-15 | 2017-11-30 | Method and system for dividing power-ground cell group |
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| TW201638812A (en) * | 2015-04-16 | 2016-11-01 | 台灣積體電路製造股份有限公司 | Method for cell placement in semiconductor layout and system thereof |
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| JPH0786405A (en) * | 1993-09-17 | 1995-03-31 | Fujitsu Ltd | Wiring method in semiconductor chip |
| CN1514482A (en) * | 2003-02-25 | 2004-07-21 | 智权第一公司 | Automatic allocation and allocation method of spare element in wiring module |
| CN1585110A (en) * | 2003-08-21 | 2005-02-23 | 川崎微电子股份有限公司 | Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure |
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