CN108233919A - Fire alarm double rail logic circuit and implementation method based on strand displacement - Google Patents
Fire alarm double rail logic circuit and implementation method based on strand displacement Download PDFInfo
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Abstract
本发明提出了一种基于链置换的火灾报警双轨逻辑电路及实现方法,基于DNA链置换的反应机制构建了四输入的火灾报警电路系统,搭建了烟感、温感、光感、手报装置四输入的火灾报警电路操作运算的数字逻辑电路,利用双轨逻辑思想将数字逻辑电路转化成双轨逻辑电路,通过双轨逻辑电路再转化成跷跷板生化逻辑电路,最后通过Visual DSD仿真软件验证其输出结果,并分析判断是否有火情发生。本发明的电路设计是有效的,且具有很高的准确性以及灵敏度;对于大规模的智能化报警装置系统设计的运算操作提供了基本的理论基础,提高生物计算机逻辑电路的可靠性,促进了生物计算机的发展。
The present invention proposes a dual-track logic circuit for fire alarm based on chain replacement and its implementation method, constructs a four-input fire alarm circuit system based on the reaction mechanism of DNA chain replacement, and builds smoke, temperature, light, and alarm devices The digital logic circuit of the four-input fire alarm circuit operation operation uses the dual-rail logic idea to convert the digital logic circuit into a dual-rail logic circuit, and then converts it into a seesaw biochemical logic circuit through the dual-rail logic circuit, and finally verifies its output through the Visual DSD simulation software. And analyze and judge whether there is a fire. The circuit design of the present invention is effective, and has very high accuracy and sensitivity; Provides a basic theoretical basis for the operation of large-scale intelligent alarm system design, improves the reliability of biological computer logic circuits, and promotes The development of biological computers.
Description
技术领域technical field
本发明涉及逻辑电路的技术领域,尤其涉及一种基于链置换的火灾报警双轨逻辑电路及实现方法。The invention relates to the technical field of logic circuits, in particular to a fire alarm dual-track logic circuit based on chain replacement and an implementation method.
背景技术Background technique
在当前快速发展的计算机时代,传统的逻辑电路设计已经不能满足人们正常安全生活中的需要,例如设备电路因复杂的运算导致线路老化,报警装置系统对火灾判断不准确等等,火灾问题是目前我国比较重视的一个大问题,怎样才能及时准确地判断是否有隐患存在将是研究的方向。结合科学计算机和分子生物学科的DNA计算是一个新的研究领域。DNA作为一种新的计算工具已经解决了很多问题,比如哈密顿路径以及最大团问题等。DNA自组装是DNA纳米技术的一个重要支撑技术,具有可预测性和可编程性的特点,在应用领域这两种特点在自组装方面都具有很好的发展前景。DNA链置换技术在生物计算领域也扮演着一种动态的DNA纳米技术。DNA链置换技术由于其本身具有一系列自发性、灵敏性及准确性的特点,已经在纳米机器、分子逻辑电路、纳米药物及其他方面被广泛应用。近年来,生物计算机已被许多来自不同领域的科学家广泛关注,而且分子逻辑电路又是生物计算机的重要组成部分。因此,逻辑电路的构建方法在生物计算机中起着重要的作用。In the current rapidly developing computer age, traditional logic circuit design can no longer meet the needs of people in normal and safe life. A big problem that our country attaches great importance to, how to judge whether there are hidden dangers in a timely and accurate manner will be the direction of research. DNA computing combining scientific computing and molecular biology disciplines is a new field of research. As a new computing tool, DNA has solved many problems, such as Hamiltonian path and maximum clique problem. DNA self-assembly is an important supporting technology of DNA nanotechnology, which has the characteristics of predictability and programmability, both of which have good development prospects in self-assembly in the application field. DNA strand displacement technology also plays a dynamic role in DNA nanotechnology in the field of biocomputing. Due to its own series of characteristics of spontaneity, sensitivity and accuracy, DNA strand replacement technology has been widely used in nanomachines, molecular logic circuits, nanomedicine and other fields. In recent years, biological computers have been widely concerned by many scientists from different fields, and molecular logic circuits are an important part of biological computers. Therefore, the method of constructing logic circuits plays an important role in biological computers.
DNA计算已经处理了大量如自组装、荧光标记、链置换和探针机等分子操作。DNA链置换技术是在DNA自组装技术的基础上发展起来,所以,DNA自组装技术和DNA链置换技术是研究DNA纳米技术的两大重要支撑技术。而且DNA链置换技术非常适合于构建分子逻辑电路,在传统的电子逻辑电路中,高电平和低电平通常表示为布尔逻辑的“真”和“假”。基于链置换技术的级联反应已经实现了相邻逻辑模块的动态连接,并为研究人员构建大规模、复杂的逻辑电路成为可能。此外,DNA链置换技术凭借高容量信息积累、高性能并行计算、编程以及仿真的优势,已经在分子计算、纳米机器、诊断和疾病治疗领域得到了深入的研究。DNA链置换技术在解决数学问题、管理纳米机器和讨论生命历程方面也具有很大的研究意义。另外,基于DNA链置换的生物化学逻辑电路的构建对设计程序的掌握也具有重要的研究意义。基于DNA链置换技术的策略在智能刺激响应材料、纳米电子电路和器件、生物传感器和纳米医学等领域具有很大的应用前景。DNA computing has handled a large number of molecular operations such as self-assembly, fluorescent labeling, strand displacement, and probe machines. DNA strand replacement technology is developed on the basis of DNA self-assembly technology, so DNA self-assembly technology and DNA strand replacement technology are two important supporting technologies for the study of DNA nanotechnology. Moreover, DNA strand replacement technology is very suitable for building molecular logic circuits. In traditional electronic logic circuits, high and low levels are usually expressed as "true" and "false" of Boolean logic. The cascade reaction based on chain displacement technology has realized the dynamic connection of adjacent logic modules and made it possible for researchers to construct large-scale and complex logic circuits. In addition, with the advantages of high-capacity information accumulation, high-performance parallel computing, programming and simulation, DNA strand replacement technology has been deeply researched in the fields of molecular computing, nanomachines, diagnosis and disease treatment. DNA strand replacement technology is also of great research interest in solving mathematical problems, managing nanomachines, and discussing the course of life. In addition, the construction of biochemical logic circuits based on DNA strand replacement also has important research significance for the mastery of design procedures. Strategies based on DNA strand displacement technology have great application prospects in the fields of smart stimuli-responsive materials, nanoelectronic circuits and devices, biosensors, and nanomedicine.
发明内容Contents of the invention
为了推进生物计算机的发展,本发明提出一种基于DNA链置换的火灾报警双轨逻辑电路及实现方法,先设计出火灾报警双轨逻辑的数字电路,然后将数字逻辑电路用双轨的逻辑思想构建火灾报警双轨逻辑电路,最后将双轨逻辑电路转化为生化逻辑电路,并用Visual DSD仿真软件分析了火灾报警双轨逻辑电路的正确性,具有很高的灵敏度和可靠性。In order to promote the development of biological computers, the present invention proposes a dual-track logic circuit for fire alarm based on DNA strand replacement and its implementation method. First, a digital circuit with dual-track logic for fire alarm is designed, and then the digital logic circuit is used to construct a fire alarm with dual-track logic. Dual-track logic circuit, and finally convert the dual-track logic circuit into a biochemical logic circuit, and use Visual DSD simulation software to analyze the correctness of the fire alarm dual-track logic circuit, which has high sensitivity and reliability.
为了达到上述目的,本发明的技术方案是这样实现的:一种基于链置换的火灾报警双轨逻辑电路,包括四个输入链、放大门、集成门、第一DNA阈值门、第二DNA阈值门和输出链,每个输入链都具有两种状态:表示逻辑开的状态为A1、B1、C1和D1,表示逻辑关的状态为A0、B0、C0和D0;输出链包括两种状态分别为Y1和Y0;放大门具有一个输入和三个输出,放大门中的阈值浓度小于1n mol/L,集成门包括三个输入一个输出的三输入集成门和四个输入一个输出的四输入集成门;第一DNA阈值门的阈值浓度小于1n mol/L,第二DNA阈值门的阈值浓度大于1;所述输入链的状态A1、B1、C1、D1、A0、B0、C0和D0作为输入信号分别与一个放大门相连接,放大门的输出端分别通过DNA信号与不同的三输入集成门相连接,四个三输入集成门分别通过一个第一DNA阈值门与一个四输入集成门相连接,四输入集成门通过第二DNA阈值门得到输出信号Y0;四个三输入集成门分别通过一个第二DNA阈值门与另一个四输入集成门相连接,另一个四输入集成门通过第一DNA阈值门得到输出信号Y1。In order to achieve the above object, the technical solution of the present invention is achieved in this way: a double-track logic circuit for fire alarm based on chain replacement, including four input chains, amplification gates, integrated gates, the first DNA threshold gate, and the second DNA threshold gate and output chains, each of which has two states: A 1 , B 1 , C 1 , and D 1 for logic-on states, and A 0 , B 0 , C 0 , and D 0 for logic-off states; The output chain includes two states Y 1 and Y 0 respectively; the amplification gate has one input and three outputs, the threshold concentration in the amplification gate is less than 1n mol/L, and the integration gate includes a three-input integration gate with three inputs and one output and A four-input integrated gate with four inputs and one output; the threshold concentration of the first DNA threshold gate is less than 1nmol/L, and the threshold concentration of the second DNA threshold gate is greater than 1; the state of the input chain is A 1 , B 1 , C 1 , D 1 , A 0 , B 0 , C 0 and D 0 are respectively connected to an amplification gate as input signals, and the output terminals of the amplification gates are respectively connected to different three-input integrated gates through DNA signals, and four three-input integrated gates The gates are respectively connected to a four-input integrated gate through a first DNA threshold gate, and the four-input integrated gate obtains an output signal Y 0 through a second DNA threshold gate; the four three-input integrated gates are respectively connected to the other through a second DNA threshold gate. One four-input integration gate is connected, and the other four-input integration gate passes through the first DNA threshold gate to obtain an output signal Y 1 .
所述输入链A0与放大门Ⅰ相连接,输入链A1与放大门Ⅱ相连接,输入链B0与放大门Ⅲ相连接,输入链B1与放大门Ⅳ相连接,输入链C0与放大门Ⅴ相连接,输入链C1与放大门Ⅵ相连接,输入链D0与放大门Ⅶ相连接,输入链D1与放大门Ⅷ相连接;放大门Ⅰ的第一输出端、放大门Ⅲ的第一输出端、放大门Ⅴ的第一输出端均与三输入集成门Ⅰ相连接,放大门Ⅱ的第一输出端、放大门Ⅳ的第一输出端、放大门Ⅵ的第一输出端均与三输入集成门Ⅱ相连接,放大门Ⅰ的第二输出端、放大门Ⅲ的第二输出端、放大门Ⅶ的第一输出端均与三输入集成门Ⅲ相连接,放大门Ⅱ的第二输出端、放大门Ⅳ的第二输出端、放大门Ⅷ的第一输出端均三输入集成门Ⅳ相连接,放大门Ⅰ的第三输出端、放大门Ⅴ的第二输出端、放大门Ⅶ的第二输出端均三输入集成门Ⅴ相连接,放大门Ⅱ的第三输出端、放大门Ⅵ的第二输出端、放大门Ⅷ的第二输出端均三输入集成门Ⅵ相连接,放大门Ⅲ的第三输出端、放大门Ⅴ的第三输出端、放大门Ⅶ的第三输出端均三输入集成门Ⅶ相连接,放大门Ⅳ的第三输出端、放大门Ⅵ的第三输出端、放大门Ⅷ的第三输出端均三输入集成门Ⅷ相连接;最后,三输入集成门Ⅰ、三输入集成门Ⅲ、三输入集成门Ⅴ、三输入集成门Ⅶ分别通过一个第一DNA阈值门与四输入集成门Ⅱ相连接,四输入集成门Ⅱ与一个第二DNA阈值门相连接,从而获得输出信号Y0;三输入集成门Ⅱ、三输入集成门Ⅳ、三输入集成门Ⅵ分别通过一个第二DNA阈值门与四输入集成门Ⅰ相连接,四输入集成门Ⅰ与一个第一DNA阈值门相连接,从而获得输出信号Y1。The input chain A 0 is connected to the amplification gate I, the input chain A 1 is connected to the amplification gate II, the input chain B 0 is connected to the amplification gate III, the input chain B 1 is connected to the amplification gate IV, and the input chain C 0 It is connected with the amplifier gate V, the input chain C1 is connected with the amplifier gate VI, the input chain D0 is connected with the amplifier gate VII, and the input chain D1 is connected with the amplifier gate VIII; the first output terminal of the amplifier gate I, the amplifier The first output end of the gate III and the first output end of the amplifying gate V are connected with the three-input integrated gate I, the first output end of the amplifying gate II, the first output end of the amplifying gate IV, and the first output end of the amplifying gate VI The output ends are all connected to the three-input integrated gate II, the second output end of the amplifying gate I, the second output end of the amplifying gate III, and the first output end of the amplifying gate VII are all connected to the three-input integrated gate III, and the amplifying gate The second output terminal of II, the second output terminal of amplifier gate IV, and the first output terminal of amplifier gate VIII are connected with the three-input integration gate IV, the third output terminal of amplifier gate I, the second output terminal of amplifier gate V , the second output end of the amplifier gate VII are connected to the three-input integrated gate V, the third output end of the amplifier gate II, the second output end of the amplifier gate VI, and the second output end of the amplifier gate VIII are all three-input integrated gate VI The third output terminal of the amplifier gate III, the third output terminal of the amplifier gate V, and the third output terminal of the amplifier gate VII are connected with the three-input integrated gate VII, the third output terminal of the amplifier gate IV, the third output terminal of the amplifier gate VII The third output terminal of the amplifier gate VIII and the third output terminal of the amplification gate VIII are connected to the three-input integrated gate VIII; finally, the three-input integrated gate I, the three-input integrated gate III, the three-input integrated gate V, and the three-input integrated gate VII respectively pass through A first DNA threshold gate is connected with four-input integration gate II, and four-input integration gate II is connected with a second DNA threshold gate, so as to obtain output signal Y 0 ; three-input integration gate II, three-input integration gate IV, three-input integration gate II The input integration gate VI is respectively connected to the four-input integration gate I through a second DNA threshold gate, and the four-input integration gate I is connected to a first DNA threshold gate to obtain an output signal Y 1 .
所述放大门中燃料的初始浓度为输出信号绑定浓度的两倍;放大门的阈值浓度设定为0.2 n mol/L,放大门的燃料浓度设定为6 n mol/L;当输入链的浓度为1.2 n mol/L时,放大门的输出端的输出浓度为1 n mol/L;所述第一DNA阈值门的阈值浓度为0.6 nmol/L,第二DNA阈值门的阈值浓度为2.4 n mol/L。The initial concentration of fuel in the amplification gate is twice the binding concentration of the output signal; the threshold concentration of the amplification gate is set to 0.2 nmol/L, and the fuel concentration of the amplification gate is set to 6 nmol/L; when the input chain When the concentration is 1.2 nmol/L, the output concentration of the output terminal of the amplification gate is 1 nmol/L; the threshold concentration of the first DNA threshold gate is 0.6 nmol/L, and the threshold concentration of the second DNA threshold gate is 2.4 n mol/L.
其实现方法的步骤为:The steps of its realization method are:
步骤一:DNA链置换反应中没有酶或转录机制的常温下实现,将输入链的末端结构域与部分信号链反应并进行分支迁移,直到下一次双链中的单链被外界的单链取代,最终形成新的单链为输出链;Step 1: In the DNA strand displacement reaction, it is realized at room temperature without enzymes or transcription mechanisms. The terminal domain of the input strand reacts with part of the signal chain and undergoes branch migration until the single strand in the next double strand is replaced by the external single strand. , and finally form a new single chain as the output chain;
步骤二:利用基本的DNA链置换的反应机制构建四种探测信号输入的火灾报警系统双轨逻辑电路输出信号为Y的数字逻辑电路,数字逻辑电路中的逻辑运算状态分别用二进制数值0和1表示;Step 2: Use the basic reaction mechanism of DNA strand replacement to construct a fire alarm system with four types of detection signal input. A digital logic circuit with a dual-track logic circuit whose output signal is Y. The logic operation states in the digital logic circuit are represented by binary values 0 and 1, respectively. ;
步骤三:每个输入信号都转换成两个状态相反的输入信号A0和A1、B0和B1、C0和C1、D0和D1,输出信号Y输出运算结果有Y0和Y1两种状态,利用双轨逻辑思想将数字逻辑电路转化为使用没有低电平借位的四种探测信号输入操作运算的双轨逻辑电路,从而根据所设计的双轨逻辑电路计算两个不同的二进制数操作,确定是否有火灾报警信号产生;Step 3: Each input signal is converted into two opposite input signals A 0 and A 1 , B 0 and B 1 , C 0 and C 1 , D 0 and D 1 , and the output signal Y is Y 0 and Y 1 two states, using the dual-rail logic idea to transform the digital logic circuit into a dual-rail logic circuit that uses four kinds of detection signal input operations without low-level borrowing, so as to calculate two different according to the designed dual-rail logic circuit Binary number operation to determine whether there is a fire alarm signal;
步骤四:采用跷跷板电路作为分子逻辑电路单元的基本组成部分,将双轨逻辑电路中的逻辑门转化为均有输入信号链、输出信号链、阈值链和燃料链的跷跷板逻辑门,得到跷跷板逻辑电路;Step 4: Use the seesaw circuit as the basic component of the molecular logic circuit unit, convert the logic gates in the dual-rail logic circuit into seesaw logic gates with input signal chain, output signal chain, threshold value chain and fuel chain, and obtain the seesaw logic circuit ;
步骤五:基于DNA链置换反应将输入信号A0、A1、B0、B1、C0、C1、D0和D1分别作为不同放大门的输入链,在跷跷板逻辑门前增加相匹配的集成门,将跷跷板逻辑电路转化为跷跷板生化逻辑电。Step 5: Based on the DNA strand replacement reaction, the input signals A 0 , A 1 , B 0 , B 1 , C 0 , C 1 , D 0 and D 1 are respectively used as the input chains of different amplification gates, and phases are added in front of the seesaw logic gates. Matching integrated gates to convert seesaw logic circuits into seesaw biochemical logic circuits.
所述步骤一中如果双链中产生新的结构域,则发生与反应相似的反应,并将达到动态平衡;如果没有产生新的目标域,则反应结束。In the first step, if a new structural domain is generated in the double chain, a reaction similar to the reaction will occur and a dynamic equilibrium will be reached; if no new target domain is generated, the reaction will end.
所述数字逻辑电路包括五个与门、A、B、C和D四个输入信号,一个输出信号Y;首先输入信号A、B和C进行与运算操作,运算结果值用R1表示;输入信号A、B和D进行与运算操作,运算结果值用R2表示;输入信号A、C和D进行与运算操作,运算结果值用R3表示;输入信号B、C和D进行与运算操作,运算结果值用R4表示;最后将前运算输出值R1、R2、R3、R4再进行下一级的与运算操作,运算结果值用Q表示,得到最终的逻辑运算输出结果Y,即Y=Q={R1 ∧R2 ∧R3 ∧ R4 }。The digital logic circuit comprises five AND gates, four input signals of A, B, C and D, and an output signal Y; first, the input signals A, B and C carry out an AND operation, and the operation result value is represented by R1 ; input Signals A, B, and D perform AND operation, and the operation result value is represented by R 2 ; input signals A, C, and D perform AND operation, and the operation result value is represented by R 3 ; input signals B, C, and D perform AND operation , the operation result value is represented by R 4 ; finally, the previous operation output values R 1 , R 2 , R 3 , R 4 are subjected to the next-level AND operation operation, and the operation result value is represented by Q to obtain the final logic operation output result Y, namely Y=Q={R 1 ∧ R 2 ∧ R 3 ∧ R 4 }.
在输入信号中,A、B、C和D分别是烟感、温感、光感和手报装置四种输入信号对应的二进制数输入,Y是判断是否有火灾发生的双轨逻辑电路的操作运算的输出结果,也用二进制数0和1表示,输出结果Y的值若为1则有火灾发生,否则没有火灾发生。In the input signal, A, B, C and D are the binary number input corresponding to the four input signals of smoke sensor, temperature sensor, light sensor and hand signal device respectively, and Y is the operation calculation of the double-track logic circuit for judging whether there is a fire The output result of is also represented by binary numbers 0 and 1. If the value of the output result Y is 1, there is a fire, otherwise there is no fire.
所述双轨逻辑电路包括五个逻辑与门和五个逻辑或门,输入信号包括A0、A1、B0、B1、C0、C1、D0和D1,输出信号为Y0和Y1;输入信号A0、B0、C0均与逻辑或门K1相连接,输入信号A1、B1、C1均与逻辑与门K2相连接,输入信号A0、B0、D0均与逻辑或门K3相连接,输入信号A1、B1、D1均与逻辑与门K4相连接,输入信号A0、C0、D0均与逻辑或门K5相连接,输入信号A1、C1、D1均与逻辑与门K6相连接,输入信号B0、C0和D0均与逻辑或门K7相连接,输入信号B1、C1和D1均与逻辑与门K8相连接;逻辑或门K1、K3、K5、K7的输出结果均与逻辑四输入信号的与门K9相连接,得到输出信号Y0;逻辑或门K2、K4、K6、K8的输出结果均与四输入信号的逻辑或门K10相连接,得到输出信号Y1。The dual-rail logic circuit includes five logic AND gates and five logic OR gates, the input signal includes A 0 , A 1 , B 0 , B 1 , C 0 , C 1 , D 0 and D 1 , and the output signal is Y 0 and Y 1 ; input signals A 0 , B 0 , C 0 are all connected to logic OR gate K 1 , input signals A 1 , B 1 , C 1 are all connected to logic AND gate K 2 , input signals A 0 , B 0 and D 0 are connected with logic OR gate K 3 , input signals A 1 , B 1 , D 1 are connected with logic AND gate K 4 , input signals A 0 , C 0 , D 0 are all connected with logic OR gate K 5- phase connection, input signals A 1 , C 1 , D 1 are all connected to logic AND gate K 6 , input signals B 0 , C 0 and D 0 are all connected to logic OR gate K 7 , input signals B 1 , C Both 1 and D1 are connected to the logical AND gate K8 ; the output results of the logical OR gates K1 , K3 , K5 , and K7 are all connected to the logical four-input signal AND gate K9 to obtain the output signal Y0 ; The output results of the logical OR gates K 2 , K 4 , K 6 , and K 8 are all connected to the logical OR gate K 10 of four input signals to obtain the output signal Y 1 .
本发明的有益效果:基于链置换构建了四种探测信号输入的火灾报警系统的数字逻辑电路,利用双轨逻辑思想将数字逻辑电路运算操作转化成四种探测信号输入的火灾报警系统的双轨逻辑电路,通过双轨逻辑电路再转化成跷跷板生化逻辑电路,最后通过Visual DSD仿真软件验证其输出结果,并根据仿真结果分析判断当四种探测信号随机输入时是否有火情发生。仿真结果显示,本发明实现四种探测信号输入的火灾报警系统的双轨逻辑电路是有效的,且具有很高的准确灵敏度和可靠性。本发明对将来设计更复杂、大规模逻辑电路运算操作提供了基本的理论基础,提高了生物计算机逻辑电路的可靠性,促进了生物计算机的发展。Beneficial effects of the present invention: the digital logic circuit of the fire alarm system with four kinds of detection signal input is constructed based on the chain replacement, and the operation operation of the digital logic circuit is converted into the dual-rail logic circuit of the fire alarm system with four kinds of detection signal input by using the dual-track logic idea , and then transformed into a seesaw biochemical logic circuit through a dual-track logic circuit, and finally verified its output results through Visual DSD simulation software, and analyzed and judged whether there was a fire when the four detection signals were randomly input according to the simulation results. The simulation results show that the dual-rail logic circuit of the fire alarm system that realizes the input of four kinds of detection signals is effective, and has high accuracy, sensitivity and reliability. The invention provides a basic theoretical basis for future design of more complex and large-scale logic circuit operations, improves the reliability of the logic circuit of the biological computer, and promotes the development of the biological computer.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.
图1为本发明基于链置换的火灾报警系统的数字逻辑电路数。Fig. 1 is the number of digital logic circuits of the fire alarm system based on chain replacement in the present invention.
图2为本发明基于链置换的火灾报警系统的双轨逻辑电路。Fig. 2 is the dual-rail logic circuit of the fire alarm system based on chain replacement in the present invention.
图3为本发明跷跷板逻辑门转化的抽象图。Fig. 3 is an abstract diagram of the transformation of the seesaw logic gate of the present invention.
图4为本发明基于链置换的火灾报警系统的跷跷板生化逻辑电路。Fig. 4 is the seesaw biochemical logic circuit of the chain replacement-based fire alarm system of the present invention.
图5为本发明Visual DSD Software输出结果仿真图。Fig. 5 is a simulation diagram of the output result of the Visual DSD Software of the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
一种基于链置换的火灾报警双轨逻辑电路的实现方法的步骤为:The steps of a method for implementing a fire alarm dual-track logic circuit based on chain replacement are as follows:
步骤一:DNA链置换反应在没有酶或转录机制的常温下实现,将输入链的末端结构域与部分信号链反应,并进行分支迁移,直到下一次双链中的单链被外界的单链取代,最终形成新的单链为输出链。Step 1: The DNA strand displacement reaction is realized at room temperature without enzymes or transcription mechanisms, reacts the terminal domain of the input strand with part of the signal chain, and performs branch migration until the next single strand in the double strand is replaced by the external single strand Instead, a new single chain is finally formed as the output chain.
DNA自组装技术在生物工程逻辑电路中的应用越来越广泛,而DNA链置换技术源自DNA自组装技术,由于基本双螺旋结构互补配对规则,多条DNA单链自发有序的进行多维组装。基于DNA链置换的反应机制设计了一种新的逻辑电路,包括烟感、温感、光感、手报装置四种输入信号的火灾报警逻辑电路,对应DNA链置换的输入输出逻辑关系,将四种探测信号作为输入端,用输出端来表示是否有火灾情况产生。这种基于DNA链置换的反应机制电路的设计思想被应用于具体的生活电路设计中,其具有的准确性和高度灵敏性具有很好的应用价值,能够及时准确的确保人们生活的安全。DNA self-assembly technology is more and more widely used in bioengineering logic circuits, and DNA strand replacement technology is derived from DNA self-assembly technology. Due to the complementary pairing rules of the basic double helix structure, multiple DNA single strands are spontaneously and orderly assembled in multiple dimensions. . Based on the reaction mechanism of DNA strand replacement, a new logic circuit is designed, including fire alarm logic circuit with four input signals of smoke sensor, temperature sensor, light sensor and hand alarm device. Corresponding to the input and output logic relationship of DNA strand replacement, the Four detection signals are used as input terminals, and the output terminals are used to indicate whether there is a fire situation. The design idea of this reaction mechanism circuit based on DNA strand replacement is applied to the design of specific life circuits. Its accuracy and high sensitivity have good application value, and can ensure the safety of people's lives in a timely and accurate manner.
步骤二:利用基本的DNA链置换的反应机制构建四种探测信号输入的火灾报警系统双轨逻辑电路输出信号为Y的数字逻辑电路,数字逻辑电路中的逻辑运算状态分别用二进制数值0和1表示。Step 2: Use the basic reaction mechanism of DNA strand replacement to construct a fire alarm system with four types of detection signal input. A digital logic circuit with a dual-track logic circuit whose output signal is Y. The logic operation states in the digital logic circuit are represented by binary values 0 and 1, respectively. .
在数字逻辑电路中,逻辑运算状态分别用0和1表示。如果两个输入状态的值都为0,逻辑或门的值为0,否则为1。如果两个输入状态的值都为1,则逻辑或门的值为1,否则为0。通过使用没有低电平借位的四种探测信号输入的火灾报警系统操作运算的双轨逻辑电路来计算两个不同的二进制数。根据不同的输入信号,输出信号可能相同。在这些输入信号中,A、B、C和D分别是火灾报警系统数字逻辑电路对应的烟感、温感、光感和手报装置四种探测信号的输入,Y是基于DNA链置换的四种探测信号输入的火灾报警系统数字逻辑电路的输出结果,输出结果值若为1则有火灾发生,否则是没有火情出现。即该数字逻辑电路具有判定是否有火情发生的效果。In digital logic circuits, logic operation states are represented by 0 and 1, respectively. The logical OR gate evaluates to 0 if both input states have a value of 0, and 1 otherwise. A logical OR gate evaluates to 1 if both input states have a value of 1, otherwise it is 0. Two different binary numbers are calculated by the dual-rail logic circuit of the operation operation of the fire alarm system using the four detection signal inputs without a low level borrow. Depending on the input signal, the output signal may be the same. Among these input signals, A, B, C, and D are the inputs of the four detection signals of smoke, temperature, light, and alarm devices corresponding to the digital logic circuit of the fire alarm system, and Y is the four detection signals based on DNA strand replacement. The output result of the digital logic circuit of the fire alarm system input by the detection signal, if the output result value is 1, there is a fire, otherwise there is no fire. That is, the digital logic circuit has the effect of judging whether there is a fire.
如图1所示,数字逻辑电路包括四个具有三输入的与逻辑门和一个四输入信号的与逻辑门,四个输入信号分别为A、B、C和D,一个输出信号为Y;首先输入信号A、B、C进行与操作运算,运算结果用R1表示;然后输入信号A、B、D进行与运算操作,运算输出结果值用R2表示;输入信号A、C、D进行与操作运算,,运算结果用R3表示;接着输入信号B、C和D进行与操作运算,其输出结果值用R4表示;最后将前面的与运算的输出结果值R1、R2、R3和R4进行与运算操作,得到最终的逻辑运算输出结果即Y={R1 与 R2 与 R3 与 R4}。As shown in Figure 1, the digital logic circuit includes four AND logic gates with three inputs and one AND logic gate with four input signals, the four input signals are A, B, C and D, and one output signal is Y; first Input signals A, B, C perform AND operation, and the operation result is represented by R1 ; then input signals A, B, D perform AND operation, and the operation output value is represented by R2 ; input signals A, C, D are ANDed The operation operation, the operation result is represented by R 3 ; then the input signal B, C and D are AND operation operation, and the output result value is represented by R 4 ; finally, the output result value of the previous AND operation is R 1 , R 2 , R 3 and R 4 perform an AND operation to obtain the final logic operation output, namely Y={R 1 and R 2 and R 3 and R 4 }.
步骤三:每个输入信号都转换成两个状态相反的输入信号A0和A1、B0和B1、C0和C1、D0和D1,输出信号Y输出运算结果有Y0和Y1两种状态,利用双轨逻辑思想将数字逻辑电路转化为使用没有低电平借位的四种探测信号输入操作运算的双轨逻辑电路,从而进行双轨逻辑电路操作运算,根据所输出的二进制数的仿真结果来确定是否有火灾产生。Step 3: Each input signal is converted into two opposite input signals A 0 and A 1 , B 0 and B 1 , C 0 and C 1 , D 0 and D 1 , and the output signal Y is Y 0 and Y 1 two states, use the dual-rail logic idea to transform the digital logic circuit into a dual-rail logic circuit that uses four kinds of detection signal input operations without low-level borrowing, so as to perform dual-rail logic circuit operation operations, according to the output binary The results of several simulations are used to determine whether there is a fire.
在基于DNA链置换的四种探测信号输入的火灾报警系统操作运算的双轨逻辑电路中,使用双轨方法设计了DNA链置换的四种探测信号输入的火灾报警系统操作运算的双轨逻辑电路设计及实现的双层逻辑电路,双轨逻辑算法的采用能够避免错误的输出信号,在输入信号不完全存在的情况下可以获得确定的运算结果。结合数字电路图构建双轨逻辑电路,如图2所示。在双轨逻辑电路中,为了确保所有情况的输入信号都能被识别,每个原始输入信号都能被转换成两个输入信号,其中每一个均可以表示为逻辑“开”或“关”的状态。如果输入信号A不能参与反应,则A1和A0的状态在双轨逻辑电路中分别显示为逻辑“开”和逻辑“关”。另外,在双轨逻辑电路中的与门和或门的逻辑功能都应通过一对“与”逻辑门和“或”逻辑门来实现。根据不同状态的输入信号,输出信号的状态也不同。其输出信号Y的输出结果总共有两种情况,即输出运算结果为Y1和Y1 0。具体的反应过程为:输入信号A0、B0、C0、D0、A1、B1、C1、D1经过K2、K4、K6、K8四个与门和K1、K3、K5、K7四个或门进行逻辑运算操作,四个与门的输出结果用Q2、Q4、Q6、Q8表示,四个或门的输出结果用Q1、Q3、Q5、Q7表示,然后输出结果Q1、Q3、Q5、Q7再经过与门K9进行与运算,最后得出输出结果Y0。输出结果K2、K4、K6、K8再经过或门K10进行或运算,最后得出输出结果Y1。In the dual-track logic circuit for the operation and operation of the fire alarm system based on the four types of detection signals input by DNA strand replacement, the design and implementation of the dual-track logic circuit for the operation and operation of the fire alarm system with four types of detection signal input by DNA strand replacement is designed using the dual-track method The double-layer logic circuit and the double-track logic algorithm can avoid wrong output signals, and can obtain definite operation results when the input signals do not exist completely. Combined with the digital circuit diagram to build a dual-rail logic circuit, as shown in Figure 2. In dual-rail logic circuits, to ensure that all cases of input signals can be identified, each raw input signal can be converted into two input signals, each of which can be represented as a logical "on" or "off" state . If the input signal A cannot participate in the reaction, the states of A 1 and A 0 are shown as logic "on" and logic "off" respectively in the dual-rail logic circuit. In addition, the logic functions of the AND gate and the OR gate in the dual-rail logic circuit should be realized by a pair of "AND" logic gate and "OR" logic gate. According to the input signal of different state, the state of the output signal is also different. The output result of the output signal Y has two cases in total, that is, the output operation results are Y 1 and Y 1 0 . The specific reaction process is: the input signal A 0 , B 0 , C 0 , D 0 , A 1 , B 1 , C 1 , D 1 passes through the four AND gates K 2 , K 4 , K 6 , K 8 and K 1 The four OR gates of , K 3 , K 5 , and K 7 carry out logical operations, the output results of the four AND gates are represented by Q 2 , Q 4 , Q 6 , and Q 8 , and the output results of the four OR gates are represented by Q 1 , Q 3 , Q 5 , and Q 7 represent, and then output results Q 1 , Q 3 , Q 5 , and Q 7 and perform an AND operation through an AND gate K 9 , and finally obtain an output result Y 0 . The output results K 2 , K 4 , K 6 , and K 8 are ORed through the OR gate K 10 to finally obtain the output result Y 1 .
如图2所示,双轨逻辑电路包括五个逻辑与门和五个逻辑或门,输入信号包括A0、A1、B0、B1、C0、C1、D0和D1,输出信号为Y0和Y1;根据双轨逻辑电路从上到下、由左至右的顺序,输入信号A0、B0、C0均与逻辑或门K1相连接,输入信号A1、B1、C1均与逻辑与门K2相连接,输入信号A0、B0、D0均与逻辑或门K3相连接,输入信号A1、B1、D1均与逻辑与门K4相连接,输入信号A0、C0、D0均与逻辑或门K5相连接,输入信号A1、C1、D1均与逻辑与门K6相连接,输入信号B0、C0和D0均与逻辑或门K7相连接,输入信号B1、C1和D1均与逻辑与门K8相连接;逻辑或门K1的输出结果Q1、逻辑或门K3的输出结果Q3、逻辑或门K5的输出结果Q5和逻辑或门K7的输出结果Q7均与逻辑四输入信号的与门K9相连接,得到输出信号Y0;逻辑或门K2的输出结果Q2、逻辑或门K4的输出结果Q4、逻辑或门K6的输出结果Q6和逻辑或门K8的输出结果Q8均与四输入信号的逻辑或门K10相连接,得到输出信号Y1。As shown in Figure 2, the dual-rail logic circuit includes five logic AND gates and five logic OR gates, the input signals include A 0 , A 1 , B 0 , B 1 , C 0 , C 1 , D 0 and D 1 , and the output The signals are Y 0 and Y 1 ; according to the order of the double-track logic circuit from top to bottom and from left to right, the input signals A 0 , B 0 , and C 0 are all connected to the logical OR gate K 1 , and the input signals A 1 , B 1. C 1 is connected with logic AND gate K 2 , input signals A 0 , B 0 , D 0 are connected with logic OR gate K 3 , input signals A 1 , B 1 , D 1 are all connected with logic AND gate K 4- phase connection, input signals A 0 , C 0 , D 0 are all connected to logic OR gate K 5 , input signals A 1 , C 1 , D 1 are all connected to logic AND gate K 6 , input signals B 0 , C Both 0 and D 0 are connected to the logical OR gate K 7 , and the input signals B 1 , C 1 and D 1 are all connected to the logical AND gate K 8 ; the output result Q 1 of the logical OR gate K 1 and the logical OR gate K 3 The output result Q 3 of the logic OR gate K 5 , the output result Q 5 of the logic OR gate K 7 , and the output result Q 7 of the logic OR gate K 7 are all connected with the AND gate K 9 of the logic four-input signal to obtain the output signal Y 0 ; the logic OR gate The output result Q 2 of K 2 , the output result Q 4 of the logical OR gate K 4 , the output result Q 6 of the logical OR gate K 6 and the output result Q 8 of the logical OR gate K 8 are all combined with the logical OR gate K of four input signals 10 are connected to get the output signal Y 1 .
实例说明:Example description:
1)当ABCD为0101,即A0=1、B1=1、C0=1、D1=1、A1=0、B0=0、C1=0、D0=0时,A0=1、B0=0、C0=1经过第一个逻辑或门K1进行或运算,输出结果用Q1表示,即Q1=[(A0=1)∨(B0=0)∨(C0=1)]=1,A1=0、B1=1、C1=0经过第一个逻辑与门K2进行与运算,输出结果用Q2表示,即Q2=[(A1=0)∧(B1=1)∧(C1=0)]=0,A0=1、B0=0、D0=0经过第二个逻辑或门K3进行或运算,输出结果用Q3表示,即Q3=[(A0=1)∨(B0=0)∨(D0=0)]=1;A1=0、B1=1、D1=1经过第二个逻辑与门K4进行与运算,输出结果用Q4表示,即Q4=[(A1=0)∧(B1=1)∧(D1=1)]=0;A0=1、C0=1、D0=0经过第三个逻辑或门K5进行或运算,输出结果用Q5表示,即Q5=[(A0=1)∨(C0=1)∨(D0=0)]=1;A1=0、C1=0、D1=1经过第三个逻辑与门K6进行与运算,输出结果用Q6表示,即Q6=[(A1=0)∧(C1=0)∧(D1=1)]=0;B0=0、C0=1、D0=0经过第四个逻辑或门K7进行或运算,输出结果用Q7表示,即Q7=[(B0=0)∨(C0=1)∨(D0=0)]=1;B1=1、C1=0、D1=1经过第四个逻辑与门K8进行与运算,输出结果用Q8表示,即Q8=[(B1=1)∧(C1=0)∧(D1=1)]=0。然后输出结果Q1、Q3、Q5和Q7进行下一级逻辑与门K9进行与操作运算,其输出结果用Q9表示,即Q9=[(Q1=1)∧(Q3=1)∧(Q5=1)∧(Q7=1)]=1,因此最后的输出结果Y0=1。然后输出结果Q2、Q4、Q6和Q8进行下一级逻辑或门K10进行或操作运算,其输出结果用Q10表示,即Q10=[(P2=0)∨(P4=0)∨(P6=0)∨(P8=0)]=0,因此最后的输出结果Y1=0。由结果Y值可知,四种探测信号输入的火灾报警系统火情出现的概率比较低。1) When ABCD is 0101, namely A 0 =1, B 1 =1, C 0 =1, D 1 =1, A 1 =0, B 0 =0, C 1 = 0, D 0 =0, A 0 =1, B 0 =0, C 0 =1, through the first logical OR gate K 1 to carry out OR operation, the output result is represented by Q 1 , that is, Q 1 =[(A 0 =1)∨(B 0 =0 )∨(C 0 =1)]=1, A 1 =0, B 1 =1, C 1 =0 and operation through the first logical AND gate K 2 , and the output result is represented by Q 2 , that is, Q 2 = [(A 1 =0)∧(B 1 =1)∧(C 1 =0)]=0, A 0 =1, B 0 =0, D 0 =0 are ORed through the second logical OR gate K 3 Operation, the output result is represented by Q 3 , that is, Q 3 =[(A 0 =1)∨(B 0 =0)∨(D 0 =0)]=1; A 1 =0, B 1 =1, D 1 =1 and operation through the second logical AND gate K 4 , the output result is represented by Q 4 , that is, Q 4 =[(A 1 =0)∧(B 1 =1)∧(D 1 =1)]=0 ; A 0 =1, C 0 =1, D 0 =0 are ORed through the third logical OR gate K 5 , and the output result is represented by Q 5 , that is, Q 5 =[(A 0 =1)∨(C 0 =1)∨(D 0 =0)]=1; A 1 =0, C 1 =0, D 1 =1 are ANDed through the third logical AND gate K 6 , and the output result is represented by Q 6 , that is, Q 6 =[(A 1 =0)∧(C 1 =0)∧(D 1 =1)]=0; B 0 =0, C 0 =1, D 0 =0 through the fourth logic OR gate K 7 Perform an OR operation, and the output result is represented by Q 7 , that is, Q 7 =[(B 0 =0)∨(C 0 =1)∨(D 0 =0)]=1; B 1 =1, C 1 =0, D 1 =1 performs an AND operation through the fourth logic AND gate K 8 , and the output result is represented by Q 8 , that is, Q 8 =[(B 1 =1)∧(C 1 =0)∧(D 1 =1)] =0. Then the output results Q 1 , Q 3 , Q 5 and Q 7 are carried out to the next level logic AND gate K 9 for AND operation, and the output result is represented by Q 9 , that is, Q 9 =[(Q 1 =1)∧(Q 3 =1)∧(Q 5 =1)∧(Q 7 =1)]=1, so the final output Y 0 =1. Then the output results Q 2 , Q 4 , Q 6 and Q 8 are carried out to the next logical OR gate K 10 for OR operation, and the output result is represented by Q 10 , that is, Q 10 =[(P 2 =0)∨(P 4 =0)∨(P 6 =0)∨(P 8 =0)]=0, so the final output result Y 1 =0. It can be seen from the Y value of the result that the probability of fire occurrence in the fire alarm system input by the four kinds of detection signals is relatively low.
2)当ABCD为1101,即A1=1、B1=1、C0=1、D1=1、A0=0、B0=0、C1=0、D0=0时,A0=0、B0=0、C0=1经过第一个门逻辑或门K1进行或运算,输出结果用Q1表示,即Q1=[(A0=0)∨(B0=0)∨(C0=1)]=1;A1=1、B1=1、C1=0经过第二个门逻辑与门K2进行与运算,输出结果用Q2表示,即Q2=[(A1=1)∧(B1=1)∧(C1=0)]=0; A0=0、B0=0、D0=0经过第三个门逻辑或门K3进行或运算,输出结果用Q3表示,即Q3=[(A0=0)∨(B0=0)∨(D0=0)]=0;A1=1、B1=1、D1=1经过第四个门逻辑与门K4进行与运算,输出结果用Q4表示,即Q4=[(A1=1)∧(B1=1)∧(D1=1)]=1;A0=0、C0=1、D0=0经过第五个门逻辑或门K5进行或运算,输出结果用Q5表示,即Q5=[(A0=0)∨(C0=1)∨(D0=0)]=1;A1=1、C1=0、D1=1经过第六个门逻辑与门K6进行与运算,输出结果用Q6表示,即Q6=[(A1=1)∧(C1=0)∧(D1=1)]=0;B0=0、C0=1、D0=0经过第七个门逻辑或门K7进行或运算,输出结果用Q7表示,即Q7=[(B0=0)∨(C0=1)∨(D0=0)]=1;B1=1、C1=0、D1=1经过第八个门逻辑与门K8进行与运算,输出结果用Q8表示,即Q8=[(B1=1)∧(C1=0)∧(D1=1)]=0。然后输出结果Q1、Q3、Q5和Q7进行下一级逻辑与门K9进行与操作运算,其输出结果用Q9表示,即Q9=[(Q1=1)∧(Q3=0)∧(Q5=1)∧(Q7=1)]=0,因此最后的输出结果Y0=0。然后输出结果Q2、Q4、Q6和Q8进行下一级逻辑或门K10进行或操作运算,其输出结果用Q10表示,即Q10=[(P2=0)∨(P4=1)∨(P6=0)∨(P8=0)]=1,因此最后的输出结果Y1=1。由结果Y值可知,四种探测信号输入的火灾报警系统火情出现的概率比较高。2) When ABCD is 1101, namely A 1 =1, B 1 =1, C 0 =1, D 1 =1, A 0 =0, B 0 =0, C 1 =0, D 0 =0, A 0 =0, B 0 =0, C 0 =1, through the first gate logic OR gate K 1 to perform OR operation, the output result is represented by Q 1 , that is, Q 1 =[(A 0 =0)∨(B 0 = 0)∨(C 0 =1)]=1; A 1 =1, B 1 =1, C 1 =0 and the second gate logic AND gate K 2 , and the output result is represented by Q 2 , that is, Q 2 =[(A 1 =1)∧(B 1 =1)∧(C 1 =0)]=0; A 0 =0, B 0 =0, D 0 =0 through the third logic OR gate K 3 Carry out the OR operation, and the output result is represented by Q 3 , that is, Q 3 =[(A 0 =0)∨(B 0 =0)∨(D 0 =0)]=0; A 1 =1, B 1 =1 , D 1 =1 and operation through the fourth gate logic AND gate K 4 , and the output result is represented by Q 4 , that is, Q 4 =[(A 1 =1)∧(B 1 =1)∧(D 1 =1 )]=1; A 0 =0, C 0 =1, D 0 =0 are ORed through the fifth gate logic OR gate K 5 , and the output result is represented by Q 5 , that is, Q 5 =[(A 0 =0 )∨(C 0 =1)∨(D 0 =0)]=1; A 1 =1, C 1 =0, D 1 =1 perform AND operation through the sixth gate logic AND gate K 6 , and output the result with Q 6 means that Q 6 =[(A 1 =1)∧(C 1 =0)∧(D 1 =1)]=0; B 0 =0, C 0 =1, D 0 =0 after the seventh A logical OR gate K 7 performs an OR operation, and the output result is represented by Q 7 , that is, Q 7 =[(B 0 =0)∨(C 0 =1)∨(D 0 =0)]=1; B 1 = 1. C 1 =0, D 1 =1 and operation through the eighth gate logic AND gate K 8 , and the output result is represented by Q 8 , that is, Q 8 =[(B 1 =1)∧(C 1 =0) ∧(D 1 =1)]=0. Then the output results Q 1 , Q 3 , Q 5 and Q 7 are carried out to the next level logic AND gate K 9 for AND operation, and the output result is represented by Q 9 , that is, Q 9 =[(Q 1 =1)∧(Q 3 =0)∧(Q 5 =1)∧(Q 7 =1)]=0, so the final output Y 0 =0. Then the output results Q 2 , Q 4 , Q 6 and Q 8 are carried out to the next logical OR gate K 10 for OR operation, and the output result is represented by Q 10 , that is, Q 10 =[(P 2 =0)∨(P 4 =1)∨(P 6 =0)∨(P 8 =0)]=1, so the final output result Y 1 =1. It can be seen from the Y value of the result that the probability of fire occurrence in the fire alarm system input by the four kinds of detection signals is relatively high.
(3)当ABCD为0010,即A0=1、B0=1、C1=1、D0=1、A1=0、B1=0、C0=0、D1=0时,A0=1、B0=1、C0=0经过第一个门逻辑或门K1进行或运算,输出结果用Q1表示,即Q1=[(A0=1)∨(B0=1)∨(C0=0)]=1;A1=0、B1=0、C1=1经过第二个门逻辑与门K2进行与运算,输出结果用Q2表示,即Q2=[(A1=0)∧(B1=0)∧(C1=1)]=0;A0=1、B0=1、D0=1经过第三个门逻辑或门K3进行或运算,输出结果用Q3表示,即Q3=[(A0=1)∨(B0=1)∨(D0=1)]=1;A1=0、B1=0、D1=0经过第四个门逻辑与门K4进行与运算,输出结果用Q4表示,即Q4=[(A1=0)∧(B1=0)∧(D1=0)]=0;A0=1、C0=0、D0=1经过第五个门逻辑或门K5进行或运算,输出结果用Q5表示,即Q5=[(A0=1)∨(C0=0)∨(D0=1)]=1;A1=0、C1=1、D1=0经过第六个门逻辑与门K6进行与运算,输出结果用Q6表示,即Q6=[(A1=0)∧(C1=1)∧(D1=0)]=0;B0=1、C0=0、D0=1经过第七个门逻辑或门K7进行或运算,输出结果用Q7表示,即Q7=[(B0=1)∨(C0=0)∨(D0=1)]=1;B1=0、C1=1、D1=0经过第八个门逻辑与门K8进行与运算,输出结果用Q8表示,即Q8=[(B1=0)∧(C1=1)∧(D1=0)]=0。然后输出结果Q1、Q3、Q5和Q7进行下一级逻辑与门K9进行与操作运算,其输出结果用Q9表示,即Q9=[(Q1=1)∧(Q3=1)∧(Q5=1)∧(Q7=1)]=1,因此最后的输出结果Y0=1。然后Q2、Q4、Q6和Q8进行下一级逻辑或门K10进行或操作运算,其输出结果用Q10表示,即Q10=[(P2=0)∨(P4=0)∨(P6=0)∨(P8=0)]=0,因此最后的输出结果Y1=0。由结果Y值可知,四种探测信号输入的火灾报警系统火情出现的概率比较低。(3) When ABCD is 0010, namely A 0 =1, B 0 =1, C 1 =1, D 0 =1, A 1 =0, B 1 =0, C 0 =0, D 1 =0, A 0 =1, B 0 =1, C 0 =0 are ORed through the first logical OR gate K 1 , and the output result is represented by Q 1 , that is, Q 1 =[(A 0 =1)∨(B 0 =1)∨(C 0 =0)]=1; A 1 =0, B 1 =0, C 1 =1 are ANDed by the second gate logic AND gate K 2 , and the output result is represented by Q 2 , that is Q 2 =[(A 1 =0)∧(B 1 =0)∧(C 1 =1)]=0; A 0 =1, B 0 =1, D 0 =1 through the third logic OR gate K 3 performs an OR operation, and the output result is represented by Q 3 , that is, Q 3 =[(A 0 =1)∨(B 0 =1)∨(D 0 =1)]=1; A 1 =0, B 1 = 0. D 1 =0 performs an AND operation through the fourth gate logic AND gate K 4 , and the output result is represented by Q 4 , that is, Q 4 =[(A 1 =0)∧(B 1 =0)∧(D 1 = 0)]=0; A 0 =1, C 0 =0, D 0 =1 are ORed through the fifth gate logic OR gate K 5 , and the output result is represented by Q 5 , that is, Q 5 =[(A 0 = 1) ∨ (C 0 =0) ∨ (D 0 =1)] = 1; A 1 = 0, C 1 = 1, D 1 = 0 and the sixth gate logic AND gate K 6 , and output the result Expressed by Q 6 , that is, Q 6 =[(A 1 =0)∧(C 1 =1)∧(D 1 =0)]=0; B 0 =1, C 0 =0, D 0 =1 after the first The seven gate logic OR gate K 7 performs OR operation, and the output result is represented by Q 7 , that is, Q 7 =[(B 0 =1)∨(C 0 =0)∨(D 0 =1)]=1; B 1 =0, C 1 =1, D 1 =0 and operation through the eighth gate logic AND gate K 8 , and the output result is represented by Q 8 , that is, Q 8 =[(B 1 =0)∧(C 1 =1 )∧(D 1 =0)]=0. Then the output results Q 1 , Q 3 , Q 5 and Q 7 are carried out to the next level logic AND gate K 9 for AND operation, and the output result is represented by Q 9 , that is, Q 9 =[(Q 1 =1)∧(Q 3 =1)∧(Q 5 =1)∧(Q 7 =1)]=1, so the final output Y 0 =1. Then Q 2 , Q 4 , Q 6 and Q 8 perform an OR operation on the next logical OR gate K 10 , and the output result is represented by Q 10 , that is, Q 10 =[(P 2 =0)∨(P 4 = 0)∨(P 6 =0)∨(P 8 =0)]=0, so the final output result Y 1 =0. It can be seen from the Y value of the result that the probability of fire occurrence in the fire alarm system input by the four kinds of detection signals is relatively low.
(4)当ABCD为0111,即A0=1、B1=1、C1=1、D1=1、A1=0、B0=0、C0=0、D0=0时,A0=1、B0=0、C0=0经过第一个门逻辑或门K1进行或运算,输出结果用Q1表示,即Q1=[(A0=1)∨(B0=0)∨(C0=0)]=0;A1=0、B1=1、C1=1经过第二个门逻辑与门K2进行与运算,输出结果用Q2表示,即Q2=[(A1=0)∧(B1=1)∧(C1=1)]=0;A0=1、B0=0、D0=0经过第三个门逻辑或门K3进行或运算,输出结果用Q3表示,即Q3=[(A0=1)∨(B0=0)∨(D0=0)]=1;A1=0、B1=1、D1=1经过第四个门逻辑与门K4进行与运算,输出结果用Q4表示,即Q4=[(A1=0)∧(B1=1)∧(D1=1)]=0;A0=1、C0=0、D0=0经过第五个门逻辑或门K5进行或运算,输出结果用Q5表示,即Q5=[(A0=1)∨(C0=0)∨(D0=0)]=1;A1=0、C1=1、D1=1经过第六个门逻辑与门K6进行与运算,输出结果用Q6表示,即Q6=[(A1=0)∧(C1=1)∧(D1=1)]=0;B0=0、C0=0、D0=0经过第七个门逻辑或门K7进行或运算,输出结果用Q7表示,即Q7=[(B0=0)∨(C0=0)∨(D0=0)]=0;B1=1、C1=1、D1=1经过第八个门逻辑与门K8进行与运算,输出结果用Q8表示,即Q8=[(B1=1)∧(C1=1)∧(D1=1)]=1。然后输出结果Q1、Q3、Q5和Q7进行下一级逻辑与门K9进行与操作运算,其输出结果用Q9表示,即Q9=[(Q1=1)∧(Q3=1)∧(Q5=1)∧(Q7=0)]=0,因此最后的输出结果Y0=0。然后输出结果Q2、Q4、Q6和Q8进行下一级逻辑或门K10进行或操作运算,其输出结果用Q10表示,即Q10=[(P2=0)∨(P4=0)∨(P6=0)∨(P8=1)]=1,因此最后的输出结果Y1=1。由结果Y值可知,四种探测信号输入的火灾报警系统火情出现的概率比较高。(4) When ABCD is 0111, namely A 0 =1, B 1 =1, C 1 =1, D 1 =1, A 1 =0, B 0 =0, C 0 =0, D 0 =0, A 0 =1, B 0 =0, C 0 =0 are ORed through the first gate logic OR gate K 1 , and the output result is represented by Q 1 , that is, Q 1 =[(A 0 =1)∨(B 0 =0)∨(C 0 =0)]=0; A 1 =0, B 1 =1, C 1 =1 are ANDed through the second gate logic AND gate K 2 , and the output result is represented by Q 2 , that is Q 2 =[(A 1 =0)∧(B 1 =1)∧(C 1 =1)]=0; A 0 =1, B 0 =0, D 0 =0 through the third logic OR gate K 3 performs an OR operation, and the output result is represented by Q 3 , that is, Q 3 =[(A 0 =1)∨(B 0 =0)∨(D 0 =0)]=1; A 1 =0, B 1 = 1. D 1 =1 performs an AND operation through the fourth gate logic AND gate K 4 , and the output result is represented by Q 4 , that is, Q 4 =[(A 1 =0)∧(B 1 =1)∧(D 1 = 1)]=0; A 0 =1, C 0 =0, D 0 =0 conduct an OR operation through the fifth gate logic OR gate K 5 , and the output result is represented by Q 5 , that is, Q 5 =[(A 0 = 1) ∨ (C 0 =0) ∨ (D 0 =0)] = 1; A 1 = 0, C 1 = 1, D 1 = 1 perform AND operation through the sixth gate logic AND gate K 6 , and output the result Expressed by Q 6 , that is, Q 6 =[(A 1 =0)∧(C 1 =1)∧(D 1 =1)]=0; B 0 =0, C 0 =0, D 0 =0 after the first The seven logic gates K 7 perform an OR operation, and the output result is represented by Q 7 , that is, Q 7 =[(B 0 =0)∨(C 0 =0)∨(D 0 =0)]=0; B 1 =1, C 1 =1, D 1 =1 and operation through the eighth gate logic AND gate K 8 , and the output result is represented by Q 8 , that is, Q 8 =[(B 1 =1)∧(C 1 =1 )∧(D 1 =1)]=1. Then the output results Q 1 , Q 3 , Q 5 and Q 7 are carried out to the next level logic AND gate K 9 for AND operation, and the output result is represented by Q 9 , that is, Q 9 =[(Q 1 =1)∧(Q 3 =1)∧(Q 5 =1)∧(Q 7 =0)]=0, so the final output Y 0 =0. Then the output results Q 2 , Q 4 , Q 6 and Q 8 are carried out to the next logical OR gate K 10 for OR operation, and the output result is represented by Q 10 , that is, Q 10 =[(P 2 =0)∨(P 4 =0)∨(P 6 =0)∨(P 8 =1)]=1, so the final output result Y 1 =1. It can be seen from the Y value of the result that the probability of fire occurrence in the fire alarm system input by the four kinds of detection signals is relatively high.
步骤四:采用跷跷板电路作为分子逻辑电路单元的基本组成部分,将双轨逻辑电路中的逻辑门转化为均有输入信号链、输出信号链、阈值链和燃料链的跷跷板逻辑门,得到跷跷板逻辑电路。Step 4: Use the seesaw circuit as the basic component of the molecular logic circuit unit, convert the logic gates in the dual-rail logic circuit into seesaw logic gates with input signal chain, output signal chain, threshold value chain and fuel chain, and obtain the seesaw logic circuit .
采用跷跷板电路作为分子逻辑电路单元的基本组成部分,由六条DNA链组成:输入链,输出链、阈值链、燃料链、逻辑门链和链置换链。如图3所示,跷跷板逻辑门是由输入信号链、输出信号链、阈值链和燃料链共同转化而成。加黑数字表示节点或链置换中一些节点的接口的标识,节点内或线上的数字表示不同初始DNA种类的相对浓度。每个物种在门内起着特定的作用(例如,输入信号),并且在链置换内具有唯一的名称(例如,w2,5)。灰色线代表DNA链,箭头标记其3’端,深浅色表示不同的DNA序列。S2、S5和S6是对应于节点2,5和6的链长(15个核苷酸)识别域;S7不与链置换中的其他节点进行交互反应,而是保持信号链的一致性。T是短(5-核苷酸)支点结构域;T*是T的Watson-Crick补码等;S2*是3’末端的核苷酸。The seesaw circuit is adopted as the basic component of the molecular logic circuit unit, which consists of six DNA strands: input strand, output strand, threshold value strand, fuel strand, logic gate strand and strand displacement strand. As shown in Figure 3, the seesaw logic gate is jointly transformed from an input signal chain, an output signal chain, a threshold value chain and a fuel chain. Numbers in black indicate identification of nodes or interfaces of some nodes in strand permutation, and numbers within nodes or on lines indicate relative concentrations of different initial DNA species. Each species plays a specific role within the phylum (e.g., input signal) and has a unique name within the strand permutation (e.g., w2,5). The gray line represents the DNA strand, the arrow marks its 3' end, and the dark and light colors represent different DNA sequences. S2, S5, and S6 are chain-length (15 nucleotides) recognition domains corresponding to nodes 2, 5, and 6; S7 does not interact with other nodes in strand displacement, but maintains signal chain consistency. T is the short (5-nucleotide) pivot domain; T* is the Watson-Crick complement of T, etc.; S2* is the nucleotide at the 3' end.
为了更形象的描绘生化电路的表达,两部分的圆形节点分别表示每个DNA逻辑门,并且每条线分别用于代表每个DNA信号。双轨逻辑电路应转换为跷跷板逻辑电路,并处于反应的第一阶段。转换成了跷跷板逻辑电路,为了更清楚地看到不同逻辑门之间的关系,不同的线在整个跷跷板逻辑电路图分别表示不同的逻辑门操作。In order to describe the expression of the biochemical circuit more vividly, two circular nodes respectively represent each DNA logic gate, and each line is used to represent each DNA signal respectively. Dual-rail logic circuits should be converted to see-saw logic circuits and are in the first stage of reaction. It is converted into a seesaw logic circuit. In order to see the relationship between different logic gates more clearly, different lines represent different logic gate operations in the entire seesaw logic circuit diagram.
步骤五:基于DNA链置换反应将输入信号A0、A1、B0、B1、C0、C1、D0和D1分别作为不同放大门的输入链,在跷跷板逻辑门前增加相匹配的集成门,将跷跷板逻辑电路转化为跷跷板生化逻辑电路。Step 5: Based on the DNA strand replacement reaction, the input signals A 0 , A 1 , B 0 , B 1 , C 0 , C 1 , D 0 and D 1 are respectively used as the input chains of different amplification gates, and phases are added in front of the seesaw logic gates. Matched integrated gates to convert seesaw logic circuits into seesaw biochemical logic circuits.
如图4所示,一种基于DNA链置换的火灾报警双轨逻辑电路,包括输入链A0、A1、B0、B1、C0、C1、D0和D1,以及与输入链相匹配的放大门、集成门、第一DNA阈值门、第二DNA阈值门和输出链。每个输入链A、B、C、D都具有两种状态,表示逻辑开的状态为A1、B1、C1和D1,表示逻辑关的状态为A0、B0、C0和D0;输出链包括两种状态分别为Y0和Y1;放大门具有一个输入和三个输出,放大门中设有阈值并有多个燃料输出,放大门的阈值浓度小于1 n mol/L。输入信号的总浓度大于阈值浓度,则获得输出信号浓度为1n mol/L,否则输出浓度为0 n mol/L。集成门包括三个输入一个输出的三输入集成门和四个输入一个输出的四输入集成门,最后通过第一DNA阈值门和第二DNA阈值门的表达关系,输出结果值Y1和Y0。第一DNA阈值门的阈值浓度小于1 n mol/L,第二DNA阈值门的阈值浓度大于1 n mol/L。所述输入链A、B、C、D的状态A0、A1、B0、B1、C0、C1、D0和D1作为输入信号分别与放大门相连接,放大门的输出端分别通过DNA信号与不同的三输入集成门相连接,四个三输入集成门分别通过一个第一DNA阈值门与一个四输入集成门相连接,四输入集成门通过第二DNA阈值门得到输出信号Y0;四个三输入集成门分别通过一个第二DNA阈值门与一个四输入集成门相连接,四输入集成门通过第一DNA阈值门得到输出信号Y1。As shown in Figure 4, a dual-rail logic circuit for fire alarm based on DNA strand replacement, including input chains A 0 , A 1 , B 0 , B 1 , C 0 , C 1 , D 0 and D 1 , and input chains Matched amplification gate, integration gate, first DNA threshold gate, second DNA threshold gate and output strand. Each input chain A, B, C, D has two states, the state of logic open is A 1 , B 1 , C 1 and D 1 , and the state of logic off is A 0 , B 0 , C 0 and D 0 ; the output chain includes two states respectively Y 0 and Y 1 ; the amplification gate has one input and three outputs, a threshold is set in the amplification gate and there are multiple fuel outputs, and the threshold concentration of the amplification gate is less than 1 nmol/ L. If the total concentration of the input signal is greater than the threshold concentration, then the output signal concentration is 1nmol/L, otherwise the output concentration is 0nmol/L. The integrated gate includes a three-input integrated gate with three inputs and one output and a four-input integrated gate with four inputs and one output, and finally through the expression relationship between the first DNA threshold gate and the second DNA threshold gate, the output result values Y 1 and Y 0 . The threshold concentration of the first DNA threshold gate is less than 1 nmol/L, and the threshold concentration of the second DNA threshold gate is greater than 1 nmol/L. The states A 0 , A 1 , B 0 , B 1 , C 0 , C 1 , D 0 , and D 1 of the input chains A, B, C, and D are respectively connected to the amplification gate as input signals, and the output of the amplification gate is The terminals are respectively connected to different three-input integrated gates through DNA signals, and the four three-input integrated gates are respectively connected to a four-input integrated gate through a first DNA threshold gate, and the four-input integrated gate is output through the second DNA threshold gate Signal Y 0 ; the four three-input integration gates are respectively connected to one four-input integration gate through a second DNA threshold gate, and the four-input integration gate obtains an output signal Y 1 through the first DNA threshold gate.
放大门用于接收一个输入信号,并在反应后集成到三个输出信号。放大门中输入信号的总浓度大于阈值浓度,则可以获得输出信号,否则输出浓度为0 n mol/L,为了促使输出信号完全释放,燃料的初始浓度为输出信号绑定浓度的两倍。放大门的阈值浓度为0.2n mol/L,放大门的燃料浓度为6 n mol/L;输入链的信号为1时,放大门的输出端的输出浓度为1 n mol/L。具有输入1、输入2和输入3三个信号的集成门的功能与放大门是相反的,集成门用于接收多个输入信号,并在反应后集成到一个输出信号中。在跷跷板生化逻辑电路这个过程可以通过阈值门来执行与和或逻辑运算操作。阈值门的功能可通过浓度的幅度调节对输入信号进行调节。如果输入信号的总浓度大于阈值浓度,则可以产生输出信号,否则输出浓度为0 n mol/L。在本发明中,为了促使输出信号完全释放,根据实验的理论设计要求,第一DNA阈值门的阈值浓度为0.6 n mol/L,第二DNA阈值门的阈值浓度为2.4 n mol/L。由于集成门的输出信号浓度为1 n mol/L,因此,第一DNA阈值门的作用为逻辑或的作用,第二DNA阈值门的作用为逻辑与的作用。Amplifying gates are used to take one input signal and react to integrate three output signals. If the total concentration of the input signal in the amplification gate is greater than the threshold concentration, the output signal can be obtained, otherwise the output concentration is 0 nmol/L. In order to promote the complete release of the output signal, the initial concentration of the fuel is twice the binding concentration of the output signal. The threshold concentration of the amplification gate is 0.2nmol/L, and the fuel concentration of the amplification gate is 6nmol/L; when the signal of the input chain is 1, the output concentration of the output terminal of the amplification gate is 1nmol/L. The function of the integration gate with three signals of input 1, input 2 and input 3 is opposite to that of the amplification gate. The integration gate is used to receive multiple input signals and integrate them into one output signal after reaction. In the seesaw biochemical logic circuit, this process can perform AND and OR logic operations through threshold gates. The function of the threshold gate can adjust the input signal through the amplitude adjustment of the concentration. An output signal can be generated if the total concentration of the input signal is greater than a threshold concentration, otherwise the output concentration is 0 nmol/L. In the present invention, in order to promote the complete release of the output signal, according to the theoretical design requirements of the experiment, the threshold concentration of the first DNA threshold gate is 0.6 nmol/L, and the threshold concentration of the second DNA threshold gate is 2.4 nmol/L. Since the output signal concentration of the integrated gate is 1 nmol/L, the function of the first DNA threshold gate is logic OR, and the role of the second DNA threshold gate is logic AND.
优选地,放大门包括放大门Ⅰ、放大门Ⅱ、放大门Ⅲ、放大门Ⅳ、放大门Ⅴ、放大门Ⅵ、放大门Ⅶ和放大门Ⅷ,每个放大门均包含一个输入端和三个输出端。四输入集成门包括四输入集成门Ⅰ和四输入集成门Ⅱ。三输入集成门包括三输入集成门Ⅰ、三输入集成门Ⅱ、三输入集成门Ⅲ、三输入集成门Ⅳ、三输入集成门Ⅴ、三输入集成门Ⅵ、三输入集成门Ⅶ和三输入集成门Ⅷ。输入链A0与放大门Ⅰ相连接,输入链A1与放大门Ⅱ相连接,输入链B0与放大门Ⅲ相连接,输入链B1与放大门Ⅳ相连接,输入链C0与放大门Ⅴ相连接,输入链C1与放大门Ⅵ相连接,输入链D0与放大门Ⅶ相连接,输入链D1与放大门Ⅷ相连接;放大门Ⅰ的第一输出端、放大门Ⅲ的第一输出端、放大门Ⅴ的第一输出端均与三输入集成门Ⅰ相连接,放大门Ⅱ的第一输出端、放大门Ⅳ的第一输出端、放大门Ⅵ的第一输出端均与三输入集成门Ⅱ相连接,放大门Ⅰ的第二输出端、放大门Ⅲ的第二输出端、放大门Ⅶ的第一输出端均与三输入集成门Ⅲ相连接,放大门Ⅱ的第二输出端、放大门Ⅳ的第二输出端、放大门Ⅷ的第一输出端均三输入集成门Ⅳ相连接,放大门Ⅰ的第三输出端、放大门Ⅴ的第二输出端、放大门Ⅶ的第二输出端均三输入集成门Ⅴ相连接,放大门Ⅱ的第三输出端、放大门Ⅵ的第二输出端、放大门Ⅷ的第二输出端均三输入集成门Ⅵ相连接,放大门Ⅲ的第三输出端、放大门Ⅴ的第三输出端、放大门Ⅶ的第三输出端均三输入集成门Ⅶ相连接,放大门Ⅳ的第三输出端、放大门Ⅵ的第三输出端、放大门Ⅷ的第三输出端均三输入集成门Ⅷ相连接。最后,三输入集成门Ⅰ、三输入集成门Ⅲ、三输入集成门Ⅴ、三输入集成门Ⅶ分别通过一个第一DNA阈值门与四输入集成门Ⅱ相连接,四输入集成门Ⅱ与一个第二DNA阈值门相连接,从而获得输出信号Y0;三输入集成门Ⅱ、三输入集成门Ⅳ、三输入集成门Ⅵ和三输入集成门Ⅷ分别通过一个第二DNA阈值门与四输入集成门Ⅰ相连接,四输入集成门Ⅰ与一个第一DNA阈值门相连接,从而获得输出信号Y1。Preferably, the amplifying gates include amplifying gate I, amplifying gate II, amplifying gate III, amplifying gate IV, amplifying gate V, amplifying gate VI, amplifying gate VII and amplifying gate VIII, and each amplifying gate includes an input terminal and three output. Four-input integrated gates include four-input integrated gate I and four-input integrated gate II. Three-input integrated gates include three-input integrated gate I, three-input integrated gate II, three-input integrated gate III, three-input integrated gate IV, three-input integrated gate V, three-input integrated gate VI, three-input integrated gate VII and three-input integrated Gate VIII. The input chain A 0 is connected with the amplification gate Ⅰ, the input chain A 1 is connected with the amplification gate Ⅱ, the input chain B 0 is connected with the amplification gate Ⅲ, the input chain B 1 is connected with the amplification gate Ⅳ, the input chain C 0 is connected with the amplification gate The gate V is connected, the input chain C1 is connected with the amplification gate VI, the input chain D0 is connected with the amplification gate VII, the input chain D1 is connected with the amplification gate VIII; the first output terminal of the amplification gate I, the amplification gate III The first output end of the amplifying gate V and the first output end of the amplifying gate V are connected to the three-input integrated gate I, the first output end of the amplifying gate II, the first output end of the amplifying gate IV, and the first output end of the amplifying gate VI They are all connected to the three-input integrated gate II, the second output end of the amplifying gate I, the second output end of the amplifying gate III, and the first output end of the amplifying gate VII are all connected to the three-input integrated gate III, and the amplifying gate II’s The second output terminal, the second output terminal of the amplifier gate IV, and the first output terminal of the amplifier gate VIII are connected to the three-input integrated gate IV, the third output terminal of the amplifier gate I, the second output terminal of the amplifier gate V, and the amplifier The second output terminal of the gate VII is connected with the three-input integration gate V, and the third output terminal of the amplification gate II, the second output terminal of the amplification gate VI, and the second output terminal of the amplification gate VIII are connected with the three-input integration gate VI , the third output terminal of the amplifier gate III, the third output terminal of the amplifier gate V, and the third output terminal of the amplifier gate VII are connected with the three-input integration gate VII, the third output terminal of the amplifier gate IV, the third output terminal of the amplifier gate VI The three output terminals and the third output terminal of the amplification gate VIII are connected to the three-input integrated gate VIII. Finally, the three-input integrated gate I, the three-input integrated gate III, the three-input integrated gate V, and the three-input integrated gate VII are respectively connected to the four-input integrated gate II through a first DNA threshold gate, and the four-input integrated gate II is connected to a first The two DNA threshold gates are connected to obtain the output signal Y 0 ; the three-input integrated gate II, the three-input integrated gate IV, the three-input integrated gate VI and the three-input integrated gate VIII respectively pass through a second DNA threshold gate and a four-input integrated gate I is connected, and the four-input integration gate I is connected with a first DNA threshold gate to obtain an output signal Y 1 .
跷跷板生化逻辑电路的逻辑功能与双轨逻辑电路相同,当输入链信号为1时,放大门的三个输出端均可以获得输出信号,当四输入集成门的输入端为4 n mol/L时表示有生化反应,输出信号为1。第一DNA阈值门的输入端为3 n mol/L可以获得输出信号,反应继续进行。第二DNA阈值门的各输入端浓度均为1n mol/L,输出浓度为0 n mol/L,反应终止。The logic function of the seesaw biochemical logic circuit is the same as that of the dual-rail logic circuit. When the input chain signal is 1, the output signals can be obtained from the three output terminals of the amplifying gate. When the input terminal of the four-input integrated gate is 4 nmol/L, it means There is a biochemical reaction, and the output signal is 1. The input of the first DNA threshold gate is 3 nmol/L to obtain the output signal, and the reaction continues. The concentration of each input end of the second DNA threshold gate is 1nmol/L, the output concentration is 0nmol/L, and the reaction is terminated.
本发明运用双轨思想将DNA链置换的四种探测信号输入的火灾报警系统数字逻辑电路首先转化为双轨逻辑电路,再由双轨逻辑电路转化为跷跷板生化逻辑电路,最后得到输出信号的两种结果Y0和Y1,并运用Visual DSD仿真软件进行验证,如图5所示,验证的结果符合火灾发生的判断需求,可以应用到分析判断是否有火情发生。因此,本发明基于烟感、温感、光感、手报装置四输入的火灾报警系统双轨逻辑电路设计是有效的,且具有很高的准确性以及灵敏度。The present invention uses the double-track idea to convert the digital logic circuit of the fire alarm system input by the four kinds of detection signals replaced by the DNA chain into a dual-track logic circuit, and then converts the dual-track logic circuit into a seesaw biochemical logic circuit, and finally obtains two kinds of results of the output signal Y 0 and Y 1 , and use the Visual DSD simulation software to verify, as shown in Figure 5, the verification results meet the judgment requirements of fire occurrence, and can be applied to analyze and judge whether there is a fire. Therefore, the dual-track logic circuit design of the fire alarm system based on the four inputs of the smoke sensor, temperature sensor, light sensor and hand alarm device in the present invention is effective and has high accuracy and sensitivity.
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of the present invention. within the scope of protection.
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